2 * Procedures for creating, accessing and interpreting the device tree.
4 * Paul Mackerras August 1996.
5 * Copyright (C) 1996-2005 Paul Mackerras.
7 * Adapted for 64bit PowerPC by Dave Engebretsen and Peter Bergner.
8 * {engebret|bergner}@us.ibm.com
10 * Adapted for sparc64 by David S. Miller davem@davemloft.net
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version
15 * 2 of the License, or (at your option) any later version.
18 #include <linux/kernel.h>
19 #include <linux/types.h>
20 #include <linux/string.h>
22 #include <linux/bootmem.h>
23 #include <linux/module.h>
26 #include <asm/of_device.h>
27 #include <asm/oplib.h>
33 extern struct device_node *allnodes; /* temporary while merging */
35 extern rwlock_t devtree_lock; /* temporary while merging */
37 struct device_node *of_find_node_by_phandle(phandle handle)
39 struct device_node *np;
41 for (np = allnodes; np != 0; np = np->allnext)
42 if (np->node == handle)
47 EXPORT_SYMBOL(of_find_node_by_phandle);
49 int of_getintprop_default(struct device_node *np, const char *name, int def)
51 struct property *prop;
54 prop = of_find_property(np, name, &len);
55 if (!prop || len != 4)
58 return *(int *) prop->value;
60 EXPORT_SYMBOL(of_getintprop_default);
62 int of_set_property(struct device_node *dp, const char *name, void *val, int len)
64 struct property **prevp;
68 new_val = kmalloc(len, GFP_KERNEL);
72 memcpy(new_val, val, len);
76 write_lock(&devtree_lock);
77 prevp = &dp->properties;
79 struct property *prop = *prevp;
81 if (!strcasecmp(prop->name, name)) {
82 void *old_val = prop->value;
85 ret = prom_setprop(dp->node, name, val, len);
88 prop->value = new_val;
91 if (OF_IS_DYNAMIC(prop))
94 OF_MARK_DYNAMIC(prop);
100 prevp = &(*prevp)->next;
102 write_unlock(&devtree_lock);
104 /* XXX Upate procfs if necessary... */
108 EXPORT_SYMBOL(of_set_property);
110 static unsigned int prom_early_allocated;
112 static void * __init prom_early_alloc(unsigned long size)
116 ret = __alloc_bootmem(size, SMP_CACHE_BYTES, 0UL);
118 memset(ret, 0, size);
120 prom_early_allocated += size;
126 /* PSYCHO interrupt mapping support. */
127 #define PSYCHO_IMAP_A_SLOT0 0x0c00UL
128 #define PSYCHO_IMAP_B_SLOT0 0x0c20UL
129 static unsigned long psycho_pcislot_imap_offset(unsigned long ino)
131 unsigned int bus = (ino & 0x10) >> 4;
132 unsigned int slot = (ino & 0x0c) >> 2;
135 return PSYCHO_IMAP_A_SLOT0 + (slot * 8);
137 return PSYCHO_IMAP_B_SLOT0 + (slot * 8);
140 #define PSYCHO_IMAP_SCSI 0x1000UL
141 #define PSYCHO_IMAP_ETH 0x1008UL
142 #define PSYCHO_IMAP_BPP 0x1010UL
143 #define PSYCHO_IMAP_AU_REC 0x1018UL
144 #define PSYCHO_IMAP_AU_PLAY 0x1020UL
145 #define PSYCHO_IMAP_PFAIL 0x1028UL
146 #define PSYCHO_IMAP_KMS 0x1030UL
147 #define PSYCHO_IMAP_FLPY 0x1038UL
148 #define PSYCHO_IMAP_SHW 0x1040UL
149 #define PSYCHO_IMAP_KBD 0x1048UL
150 #define PSYCHO_IMAP_MS 0x1050UL
151 #define PSYCHO_IMAP_SER 0x1058UL
152 #define PSYCHO_IMAP_TIM0 0x1060UL
153 #define PSYCHO_IMAP_TIM1 0x1068UL
154 #define PSYCHO_IMAP_UE 0x1070UL
155 #define PSYCHO_IMAP_CE 0x1078UL
156 #define PSYCHO_IMAP_A_ERR 0x1080UL
157 #define PSYCHO_IMAP_B_ERR 0x1088UL
158 #define PSYCHO_IMAP_PMGMT 0x1090UL
159 #define PSYCHO_IMAP_GFX 0x1098UL
160 #define PSYCHO_IMAP_EUPA 0x10a0UL
162 static unsigned long __psycho_onboard_imap_off[] = {
163 /*0x20*/ PSYCHO_IMAP_SCSI,
164 /*0x21*/ PSYCHO_IMAP_ETH,
165 /*0x22*/ PSYCHO_IMAP_BPP,
166 /*0x23*/ PSYCHO_IMAP_AU_REC,
167 /*0x24*/ PSYCHO_IMAP_AU_PLAY,
168 /*0x25*/ PSYCHO_IMAP_PFAIL,
169 /*0x26*/ PSYCHO_IMAP_KMS,
170 /*0x27*/ PSYCHO_IMAP_FLPY,
171 /*0x28*/ PSYCHO_IMAP_SHW,
172 /*0x29*/ PSYCHO_IMAP_KBD,
173 /*0x2a*/ PSYCHO_IMAP_MS,
174 /*0x2b*/ PSYCHO_IMAP_SER,
175 /*0x2c*/ PSYCHO_IMAP_TIM0,
176 /*0x2d*/ PSYCHO_IMAP_TIM1,
177 /*0x2e*/ PSYCHO_IMAP_UE,
178 /*0x2f*/ PSYCHO_IMAP_CE,
179 /*0x30*/ PSYCHO_IMAP_A_ERR,
180 /*0x31*/ PSYCHO_IMAP_B_ERR,
181 /*0x32*/ PSYCHO_IMAP_PMGMT,
182 /*0x33*/ PSYCHO_IMAP_GFX,
183 /*0x34*/ PSYCHO_IMAP_EUPA,
185 #define PSYCHO_ONBOARD_IRQ_BASE 0x20
186 #define PSYCHO_ONBOARD_IRQ_LAST 0x34
187 #define psycho_onboard_imap_offset(__ino) \
188 __psycho_onboard_imap_off[(__ino) - PSYCHO_ONBOARD_IRQ_BASE]
190 #define PSYCHO_ICLR_A_SLOT0 0x1400UL
191 #define PSYCHO_ICLR_SCSI 0x1800UL
193 #define psycho_iclr_offset(ino) \
194 ((ino & 0x20) ? (PSYCHO_ICLR_SCSI + (((ino) & 0x1f) << 3)) : \
195 (PSYCHO_ICLR_A_SLOT0 + (((ino) & 0x1f)<<3)))
197 static unsigned int psycho_irq_build(struct device_node *dp,
201 unsigned long controller_regs = (unsigned long) _data;
202 unsigned long imap, iclr;
203 unsigned long imap_off, iclr_off;
207 if (ino < PSYCHO_ONBOARD_IRQ_BASE) {
209 imap_off = psycho_pcislot_imap_offset(ino);
212 if (ino > PSYCHO_ONBOARD_IRQ_LAST) {
213 prom_printf("psycho_irq_build: Wacky INO [%x]\n", ino);
216 imap_off = psycho_onboard_imap_offset(ino);
219 /* Now build the IRQ bucket. */
220 imap = controller_regs + imap_off;
222 iclr_off = psycho_iclr_offset(ino);
223 iclr = controller_regs + iclr_off;
225 if ((ino & 0x20) == 0)
226 inofixup = ino & 0x03;
228 return build_irq(inofixup, iclr, imap);
231 static void __init psycho_irq_trans_init(struct device_node *dp)
233 const struct linux_prom64_registers *regs;
235 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
236 dp->irq_trans->irq_build = psycho_irq_build;
238 regs = of_get_property(dp, "reg", NULL);
239 dp->irq_trans->data = (void *) regs[2].phys_addr;
242 #define sabre_read(__reg) \
244 __asm__ __volatile__("ldxa [%1] %2, %0" \
246 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
251 struct sabre_irq_data {
252 unsigned long controller_regs;
253 unsigned int pci_first_busno;
255 #define SABRE_CONFIGSPACE 0x001000000UL
256 #define SABRE_WRSYNC 0x1c20UL
258 #define SABRE_CONFIG_BASE(CONFIG_SPACE) \
259 (CONFIG_SPACE | (1UL << 24))
260 #define SABRE_CONFIG_ENCODE(BUS, DEVFN, REG) \
261 (((unsigned long)(BUS) << 16) | \
262 ((unsigned long)(DEVFN) << 8) | \
263 ((unsigned long)(REG)))
265 /* When a device lives behind a bridge deeper in the PCI bus topology
266 * than APB, a special sequence must run to make sure all pending DMA
267 * transfers at the time of IRQ delivery are visible in the coherency
268 * domain by the cpu. This sequence is to perform a read on the far
269 * side of the non-APB bridge, then perform a read of Sabre's DMA
270 * write-sync register.
272 static void sabre_wsync_handler(unsigned int ino, void *_arg1, void *_arg2)
274 unsigned int phys_hi = (unsigned int) (unsigned long) _arg1;
275 struct sabre_irq_data *irq_data = _arg2;
276 unsigned long controller_regs = irq_data->controller_regs;
277 unsigned long sync_reg = controller_regs + SABRE_WRSYNC;
278 unsigned long config_space = controller_regs + SABRE_CONFIGSPACE;
279 unsigned int bus, devfn;
282 config_space = SABRE_CONFIG_BASE(config_space);
284 bus = (phys_hi >> 16) & 0xff;
285 devfn = (phys_hi >> 8) & 0xff;
287 config_space |= SABRE_CONFIG_ENCODE(bus, devfn, 0x00);
289 __asm__ __volatile__("membar #Sync\n\t"
290 "lduha [%1] %2, %0\n\t"
293 : "r" ((u16 *) config_space),
294 "i" (ASI_PHYS_BYPASS_EC_E_L)
297 sabre_read(sync_reg);
300 #define SABRE_IMAP_A_SLOT0 0x0c00UL
301 #define SABRE_IMAP_B_SLOT0 0x0c20UL
302 #define SABRE_IMAP_SCSI 0x1000UL
303 #define SABRE_IMAP_ETH 0x1008UL
304 #define SABRE_IMAP_BPP 0x1010UL
305 #define SABRE_IMAP_AU_REC 0x1018UL
306 #define SABRE_IMAP_AU_PLAY 0x1020UL
307 #define SABRE_IMAP_PFAIL 0x1028UL
308 #define SABRE_IMAP_KMS 0x1030UL
309 #define SABRE_IMAP_FLPY 0x1038UL
310 #define SABRE_IMAP_SHW 0x1040UL
311 #define SABRE_IMAP_KBD 0x1048UL
312 #define SABRE_IMAP_MS 0x1050UL
313 #define SABRE_IMAP_SER 0x1058UL
314 #define SABRE_IMAP_UE 0x1070UL
315 #define SABRE_IMAP_CE 0x1078UL
316 #define SABRE_IMAP_PCIERR 0x1080UL
317 #define SABRE_IMAP_GFX 0x1098UL
318 #define SABRE_IMAP_EUPA 0x10a0UL
319 #define SABRE_ICLR_A_SLOT0 0x1400UL
320 #define SABRE_ICLR_B_SLOT0 0x1480UL
321 #define SABRE_ICLR_SCSI 0x1800UL
322 #define SABRE_ICLR_ETH 0x1808UL
323 #define SABRE_ICLR_BPP 0x1810UL
324 #define SABRE_ICLR_AU_REC 0x1818UL
325 #define SABRE_ICLR_AU_PLAY 0x1820UL
326 #define SABRE_ICLR_PFAIL 0x1828UL
327 #define SABRE_ICLR_KMS 0x1830UL
328 #define SABRE_ICLR_FLPY 0x1838UL
329 #define SABRE_ICLR_SHW 0x1840UL
330 #define SABRE_ICLR_KBD 0x1848UL
331 #define SABRE_ICLR_MS 0x1850UL
332 #define SABRE_ICLR_SER 0x1858UL
333 #define SABRE_ICLR_UE 0x1870UL
334 #define SABRE_ICLR_CE 0x1878UL
335 #define SABRE_ICLR_PCIERR 0x1880UL
337 static unsigned long sabre_pcislot_imap_offset(unsigned long ino)
339 unsigned int bus = (ino & 0x10) >> 4;
340 unsigned int slot = (ino & 0x0c) >> 2;
343 return SABRE_IMAP_A_SLOT0 + (slot * 8);
345 return SABRE_IMAP_B_SLOT0 + (slot * 8);
348 static unsigned long __sabre_onboard_imap_off[] = {
349 /*0x20*/ SABRE_IMAP_SCSI,
350 /*0x21*/ SABRE_IMAP_ETH,
351 /*0x22*/ SABRE_IMAP_BPP,
352 /*0x23*/ SABRE_IMAP_AU_REC,
353 /*0x24*/ SABRE_IMAP_AU_PLAY,
354 /*0x25*/ SABRE_IMAP_PFAIL,
355 /*0x26*/ SABRE_IMAP_KMS,
356 /*0x27*/ SABRE_IMAP_FLPY,
357 /*0x28*/ SABRE_IMAP_SHW,
358 /*0x29*/ SABRE_IMAP_KBD,
359 /*0x2a*/ SABRE_IMAP_MS,
360 /*0x2b*/ SABRE_IMAP_SER,
361 /*0x2c*/ 0 /* reserved */,
362 /*0x2d*/ 0 /* reserved */,
363 /*0x2e*/ SABRE_IMAP_UE,
364 /*0x2f*/ SABRE_IMAP_CE,
365 /*0x30*/ SABRE_IMAP_PCIERR,
366 /*0x31*/ 0 /* reserved */,
367 /*0x32*/ 0 /* reserved */,
368 /*0x33*/ SABRE_IMAP_GFX,
369 /*0x34*/ SABRE_IMAP_EUPA,
371 #define SABRE_ONBOARD_IRQ_BASE 0x20
372 #define SABRE_ONBOARD_IRQ_LAST 0x30
373 #define sabre_onboard_imap_offset(__ino) \
374 __sabre_onboard_imap_off[(__ino) - SABRE_ONBOARD_IRQ_BASE]
376 #define sabre_iclr_offset(ino) \
377 ((ino & 0x20) ? (SABRE_ICLR_SCSI + (((ino) & 0x1f) << 3)) : \
378 (SABRE_ICLR_A_SLOT0 + (((ino) & 0x1f)<<3)))
380 static int sabre_device_needs_wsync(struct device_node *dp)
382 struct device_node *parent = dp->parent;
383 const char *parent_model, *parent_compat;
385 /* This traversal up towards the root is meant to
388 * 1) non-PCI bus sitting under PCI, such as 'ebus'
389 * 2) the PCI controller interrupts themselves, which
390 * will use the sabre_irq_build but do not need
391 * the DMA synchronization handling
394 if (!strcmp(parent->type, "pci"))
396 parent = parent->parent;
402 parent_model = of_get_property(parent,
405 (!strcmp(parent_model, "SUNW,sabre") ||
406 !strcmp(parent_model, "SUNW,simba")))
409 parent_compat = of_get_property(parent,
412 (!strcmp(parent_compat, "pci108e,a000") ||
413 !strcmp(parent_compat, "pci108e,a001")))
419 static unsigned int sabre_irq_build(struct device_node *dp,
423 struct sabre_irq_data *irq_data = _data;
424 unsigned long controller_regs = irq_data->controller_regs;
425 const struct linux_prom_pci_registers *regs;
426 unsigned long imap, iclr;
427 unsigned long imap_off, iclr_off;
432 if (ino < SABRE_ONBOARD_IRQ_BASE) {
434 imap_off = sabre_pcislot_imap_offset(ino);
437 if (ino > SABRE_ONBOARD_IRQ_LAST) {
438 prom_printf("sabre_irq_build: Wacky INO [%x]\n", ino);
441 imap_off = sabre_onboard_imap_offset(ino);
444 /* Now build the IRQ bucket. */
445 imap = controller_regs + imap_off;
447 iclr_off = sabre_iclr_offset(ino);
448 iclr = controller_regs + iclr_off;
450 if ((ino & 0x20) == 0)
451 inofixup = ino & 0x03;
453 virt_irq = build_irq(inofixup, iclr, imap);
455 /* If the parent device is a PCI<->PCI bridge other than
456 * APB, we have to install a pre-handler to ensure that
457 * all pending DMA is drained before the interrupt handler
460 regs = of_get_property(dp, "reg", NULL);
461 if (regs && sabre_device_needs_wsync(dp)) {
462 irq_install_pre_handler(virt_irq,
464 (void *) (long) regs->phys_hi,
471 static void __init sabre_irq_trans_init(struct device_node *dp)
473 const struct linux_prom64_registers *regs;
474 struct sabre_irq_data *irq_data;
477 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
478 dp->irq_trans->irq_build = sabre_irq_build;
480 irq_data = prom_early_alloc(sizeof(struct sabre_irq_data));
482 regs = of_get_property(dp, "reg", NULL);
483 irq_data->controller_regs = regs[0].phys_addr;
485 busrange = of_get_property(dp, "bus-range", NULL);
486 irq_data->pci_first_busno = busrange[0];
488 dp->irq_trans->data = irq_data;
491 /* SCHIZO interrupt mapping support. Unlike Psycho, for this controller the
492 * imap/iclr registers are per-PBM.
494 #define SCHIZO_IMAP_BASE 0x1000UL
495 #define SCHIZO_ICLR_BASE 0x1400UL
497 static unsigned long schizo_imap_offset(unsigned long ino)
499 return SCHIZO_IMAP_BASE + (ino * 8UL);
502 static unsigned long schizo_iclr_offset(unsigned long ino)
504 return SCHIZO_ICLR_BASE + (ino * 8UL);
507 static unsigned long schizo_ino_to_iclr(unsigned long pbm_regs,
511 return pbm_regs + schizo_iclr_offset(ino);
514 static unsigned long schizo_ino_to_imap(unsigned long pbm_regs,
517 return pbm_regs + schizo_imap_offset(ino);
520 #define schizo_read(__reg) \
522 __asm__ __volatile__("ldxa [%1] %2, %0" \
524 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
528 #define schizo_write(__reg, __val) \
529 __asm__ __volatile__("stxa %0, [%1] %2" \
531 : "r" (__val), "r" (__reg), \
532 "i" (ASI_PHYS_BYPASS_EC_E) \
535 static void tomatillo_wsync_handler(unsigned int ino, void *_arg1, void *_arg2)
537 unsigned long sync_reg = (unsigned long) _arg2;
538 u64 mask = 1UL << (ino & IMAP_INO);
542 schizo_write(sync_reg, mask);
547 val = schizo_read(sync_reg);
552 printk("tomatillo_wsync_handler: DMA won't sync [%lx:%lx]\n",
557 static unsigned char cacheline[64]
558 __attribute__ ((aligned (64)));
560 __asm__ __volatile__("rd %%fprs, %0\n\t"
562 "wr %1, 0x0, %%fprs\n\t"
563 "stda %%f0, [%5] %6\n\t"
564 "wr %0, 0x0, %%fprs\n\t"
566 : "=&r" (mask), "=&r" (val)
567 : "0" (mask), "1" (val),
568 "i" (FPRS_FEF), "r" (&cacheline[0]),
569 "i" (ASI_BLK_COMMIT_P));
573 struct schizo_irq_data {
574 unsigned long pbm_regs;
575 unsigned long sync_reg;
580 static unsigned int schizo_irq_build(struct device_node *dp,
584 struct schizo_irq_data *irq_data = _data;
585 unsigned long pbm_regs = irq_data->pbm_regs;
586 unsigned long imap, iclr;
593 /* Now build the IRQ bucket. */
594 imap = schizo_ino_to_imap(pbm_regs, ino);
595 iclr = schizo_ino_to_iclr(pbm_regs, ino);
597 /* On Schizo, no inofixup occurs. This is because each
598 * INO has it's own IMAP register. On Psycho and Sabre
599 * there is only one IMAP register for each PCI slot even
600 * though four different INOs can be generated by each
603 * But, for JBUS variants (essentially, Tomatillo), we have
604 * to fixup the lowest bit of the interrupt group number.
608 is_tomatillo = (irq_data->sync_reg != 0UL);
611 if (irq_data->portid & 1)
612 ign_fixup = (1 << 6);
615 virt_irq = build_irq(ign_fixup, iclr, imap);
618 irq_install_pre_handler(virt_irq,
619 tomatillo_wsync_handler,
620 ((irq_data->chip_version <= 4) ?
621 (void *) 1 : (void *) 0),
622 (void *) irq_data->sync_reg);
628 static void __init __schizo_irq_trans_init(struct device_node *dp,
631 const struct linux_prom64_registers *regs;
632 struct schizo_irq_data *irq_data;
634 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
635 dp->irq_trans->irq_build = schizo_irq_build;
637 irq_data = prom_early_alloc(sizeof(struct schizo_irq_data));
639 regs = of_get_property(dp, "reg", NULL);
640 dp->irq_trans->data = irq_data;
642 irq_data->pbm_regs = regs[0].phys_addr;
644 irq_data->sync_reg = regs[3].phys_addr + 0x1a18UL;
646 irq_data->sync_reg = 0UL;
647 irq_data->portid = of_getintprop_default(dp, "portid", 0);
648 irq_data->chip_version = of_getintprop_default(dp, "version#", 0);
651 static void __init schizo_irq_trans_init(struct device_node *dp)
653 __schizo_irq_trans_init(dp, 0);
656 static void __init tomatillo_irq_trans_init(struct device_node *dp)
658 __schizo_irq_trans_init(dp, 1);
661 static unsigned int pci_sun4v_irq_build(struct device_node *dp,
665 u32 devhandle = (u32) (unsigned long) _data;
667 return sun4v_build_irq(devhandle, devino);
670 static void __init pci_sun4v_irq_trans_init(struct device_node *dp)
672 const struct linux_prom64_registers *regs;
674 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
675 dp->irq_trans->irq_build = pci_sun4v_irq_build;
677 regs = of_get_property(dp, "reg", NULL);
678 dp->irq_trans->data = (void *) (unsigned long)
679 ((regs->phys_addr >> 32UL) & 0x0fffffff);
682 struct fire_irq_data {
683 unsigned long pbm_regs;
687 #define FIRE_IMAP_BASE 0x001000
688 #define FIRE_ICLR_BASE 0x001400
690 static unsigned long fire_imap_offset(unsigned long ino)
692 return FIRE_IMAP_BASE + (ino * 8UL);
695 static unsigned long fire_iclr_offset(unsigned long ino)
697 return FIRE_ICLR_BASE + (ino * 8UL);
700 static unsigned long fire_ino_to_iclr(unsigned long pbm_regs,
703 return pbm_regs + fire_iclr_offset(ino);
706 static unsigned long fire_ino_to_imap(unsigned long pbm_regs,
709 return pbm_regs + fire_imap_offset(ino);
712 static unsigned int fire_irq_build(struct device_node *dp,
716 struct fire_irq_data *irq_data = _data;
717 unsigned long pbm_regs = irq_data->pbm_regs;
718 unsigned long imap, iclr;
719 unsigned long int_ctrlr;
723 /* Now build the IRQ bucket. */
724 imap = fire_ino_to_imap(pbm_regs, ino);
725 iclr = fire_ino_to_iclr(pbm_regs, ino);
727 /* Set the interrupt controller number. */
729 upa_writeq(int_ctrlr, imap);
731 /* The interrupt map registers do not have an INO field
732 * like other chips do. They return zero in the INO
733 * field, and the interrupt controller number is controlled
734 * in bits 6 to 9. So in order for build_irq() to get
735 * the INO right we pass it in as part of the fixup
736 * which will get added to the map register zero value
737 * read by build_irq().
739 ino |= (irq_data->portid << 6);
741 return build_irq(ino, iclr, imap);
744 static void __init fire_irq_trans_init(struct device_node *dp)
746 const struct linux_prom64_registers *regs;
747 struct fire_irq_data *irq_data;
749 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
750 dp->irq_trans->irq_build = fire_irq_build;
752 irq_data = prom_early_alloc(sizeof(struct fire_irq_data));
754 regs = of_get_property(dp, "reg", NULL);
755 dp->irq_trans->data = irq_data;
757 irq_data->pbm_regs = regs[0].phys_addr;
758 irq_data->portid = of_getintprop_default(dp, "portid", 0);
760 #endif /* CONFIG_PCI */
763 /* INO number to IMAP register offset for SYSIO external IRQ's.
764 * This should conform to both Sunfire/Wildfire server and Fusion
767 #define SYSIO_IMAP_SLOT0 0x2c00UL
768 #define SYSIO_IMAP_SLOT1 0x2c08UL
769 #define SYSIO_IMAP_SLOT2 0x2c10UL
770 #define SYSIO_IMAP_SLOT3 0x2c18UL
771 #define SYSIO_IMAP_SCSI 0x3000UL
772 #define SYSIO_IMAP_ETH 0x3008UL
773 #define SYSIO_IMAP_BPP 0x3010UL
774 #define SYSIO_IMAP_AUDIO 0x3018UL
775 #define SYSIO_IMAP_PFAIL 0x3020UL
776 #define SYSIO_IMAP_KMS 0x3028UL
777 #define SYSIO_IMAP_FLPY 0x3030UL
778 #define SYSIO_IMAP_SHW 0x3038UL
779 #define SYSIO_IMAP_KBD 0x3040UL
780 #define SYSIO_IMAP_MS 0x3048UL
781 #define SYSIO_IMAP_SER 0x3050UL
782 #define SYSIO_IMAP_TIM0 0x3060UL
783 #define SYSIO_IMAP_TIM1 0x3068UL
784 #define SYSIO_IMAP_UE 0x3070UL
785 #define SYSIO_IMAP_CE 0x3078UL
786 #define SYSIO_IMAP_SBERR 0x3080UL
787 #define SYSIO_IMAP_PMGMT 0x3088UL
788 #define SYSIO_IMAP_GFX 0x3090UL
789 #define SYSIO_IMAP_EUPA 0x3098UL
791 #define bogon ((unsigned long) -1)
792 static unsigned long sysio_irq_offsets[] = {
793 /* SBUS Slot 0 --> 3, level 1 --> 7 */
794 SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0,
795 SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0,
796 SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1,
797 SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1,
798 SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2,
799 SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2,
800 SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3,
801 SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3,
803 /* Onboard devices (not relevant/used on SunFire). */
834 #define NUM_SYSIO_OFFSETS ARRAY_SIZE(sysio_irq_offsets)
836 /* Convert Interrupt Mapping register pointer to associated
837 * Interrupt Clear register pointer, SYSIO specific version.
839 #define SYSIO_ICLR_UNUSED0 0x3400UL
840 #define SYSIO_ICLR_SLOT0 0x3408UL
841 #define SYSIO_ICLR_SLOT1 0x3448UL
842 #define SYSIO_ICLR_SLOT2 0x3488UL
843 #define SYSIO_ICLR_SLOT3 0x34c8UL
844 static unsigned long sysio_imap_to_iclr(unsigned long imap)
846 unsigned long diff = SYSIO_ICLR_UNUSED0 - SYSIO_IMAP_SLOT0;
850 static unsigned int sbus_of_build_irq(struct device_node *dp,
854 unsigned long reg_base = (unsigned long) _data;
855 const struct linux_prom_registers *regs;
856 unsigned long imap, iclr;
862 regs = of_get_property(dp, "reg", NULL);
864 sbus_slot = regs->which_io;
867 ino += (sbus_slot * 8);
869 imap = sysio_irq_offsets[ino];
870 if (imap == ((unsigned long)-1)) {
871 prom_printf("get_irq_translations: Bad SYSIO INO[%x]\n",
877 /* SYSIO inconsistency. For external SLOTS, we have to select
878 * the right ICLR register based upon the lower SBUS irq level
882 iclr = sysio_imap_to_iclr(imap);
884 sbus_level = ino & 0x7;
888 iclr = reg_base + SYSIO_ICLR_SLOT0;
891 iclr = reg_base + SYSIO_ICLR_SLOT1;
894 iclr = reg_base + SYSIO_ICLR_SLOT2;
898 iclr = reg_base + SYSIO_ICLR_SLOT3;
902 iclr += ((unsigned long)sbus_level - 1UL) * 8UL;
904 return build_irq(sbus_level, iclr, imap);
907 static void __init sbus_irq_trans_init(struct device_node *dp)
909 const struct linux_prom64_registers *regs;
911 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
912 dp->irq_trans->irq_build = sbus_of_build_irq;
914 regs = of_get_property(dp, "reg", NULL);
915 dp->irq_trans->data = (void *) (unsigned long) regs->phys_addr;
917 #endif /* CONFIG_SBUS */
920 static unsigned int central_build_irq(struct device_node *dp,
924 struct device_node *central_dp = _data;
925 struct of_device *central_op = of_find_device_by_node(central_dp);
926 struct resource *res;
927 unsigned long imap, iclr;
930 if (!strcmp(dp->name, "eeprom")) {
931 res = ¢ral_op->resource[5];
932 } else if (!strcmp(dp->name, "zs")) {
933 res = ¢ral_op->resource[4];
934 } else if (!strcmp(dp->name, "clock-board")) {
935 res = ¢ral_op->resource[3];
940 imap = res->start + 0x00UL;
941 iclr = res->start + 0x10UL;
943 /* Set the INO state to idle, and disable. */
947 tmp = upa_readl(imap);
949 upa_writel(tmp, imap);
951 return build_irq(0, iclr, imap);
954 static void __init central_irq_trans_init(struct device_node *dp)
956 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
957 dp->irq_trans->irq_build = central_build_irq;
959 dp->irq_trans->data = dp;
964 void (*init)(struct device_node *);
968 static struct irq_trans __initdata pci_irq_trans_table[] = {
969 { "SUNW,sabre", sabre_irq_trans_init },
970 { "pci108e,a000", sabre_irq_trans_init },
971 { "pci108e,a001", sabre_irq_trans_init },
972 { "SUNW,psycho", psycho_irq_trans_init },
973 { "pci108e,8000", psycho_irq_trans_init },
974 { "SUNW,schizo", schizo_irq_trans_init },
975 { "pci108e,8001", schizo_irq_trans_init },
976 { "SUNW,schizo+", schizo_irq_trans_init },
977 { "pci108e,8002", schizo_irq_trans_init },
978 { "SUNW,tomatillo", tomatillo_irq_trans_init },
979 { "pci108e,a801", tomatillo_irq_trans_init },
980 { "SUNW,sun4v-pci", pci_sun4v_irq_trans_init },
981 { "pciex108e,80f0", fire_irq_trans_init },
985 static unsigned int sun4v_vdev_irq_build(struct device_node *dp,
989 u32 devhandle = (u32) (unsigned long) _data;
991 return sun4v_build_irq(devhandle, devino);
994 static void __init sun4v_vdev_irq_trans_init(struct device_node *dp)
996 const struct linux_prom64_registers *regs;
998 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
999 dp->irq_trans->irq_build = sun4v_vdev_irq_build;
1001 regs = of_get_property(dp, "reg", NULL);
1002 dp->irq_trans->data = (void *) (unsigned long)
1003 ((regs->phys_addr >> 32UL) & 0x0fffffff);
1006 static void __init irq_trans_init(struct device_node *dp)
1014 model = of_get_property(dp, "model", NULL);
1016 model = of_get_property(dp, "compatible", NULL);
1018 for (i = 0; i < ARRAY_SIZE(pci_irq_trans_table); i++) {
1019 struct irq_trans *t = &pci_irq_trans_table[i];
1021 if (!strcmp(model, t->name))
1027 if (!strcmp(dp->name, "sbus") ||
1028 !strcmp(dp->name, "sbi"))
1029 return sbus_irq_trans_init(dp);
1031 if (!strcmp(dp->name, "fhc") &&
1032 !strcmp(dp->parent->name, "central"))
1033 return central_irq_trans_init(dp);
1034 if (!strcmp(dp->name, "virtual-devices"))
1035 return sun4v_vdev_irq_trans_init(dp);
1038 static int is_root_node(const struct device_node *dp)
1043 return (dp->parent == NULL);
1046 /* The following routines deal with the black magic of fully naming a
1049 * Certain well known named nodes are just the simple name string.
1051 * Actual devices have an address specifier appended to the base name
1052 * string, like this "foo@addr". The "addr" can be in any number of
1053 * formats, and the platform plus the type of the node determine the
1054 * format and how it is constructed.
1056 * For children of the ROOT node, the naming convention is fixed and
1057 * determined by whether this is a sun4u or sun4v system.
1059 * For children of other nodes, it is bus type specific. So
1060 * we walk up the tree until we discover a "device_type" property
1061 * we recognize and we go from there.
1063 * As an example, the boot device on my workstation has a full path:
1065 * /pci@1e,600000/ide@d/disk@0,0:c
1067 static void __init sun4v_path_component(struct device_node *dp, char *tmp_buf)
1069 struct linux_prom64_registers *regs;
1070 struct property *rprop;
1071 u32 high_bits, low_bits, type;
1073 rprop = of_find_property(dp, "reg", NULL);
1077 regs = rprop->value;
1078 if (!is_root_node(dp->parent)) {
1079 sprintf(tmp_buf, "%s@%x,%x",
1081 (unsigned int) (regs->phys_addr >> 32UL),
1082 (unsigned int) (regs->phys_addr & 0xffffffffUL));
1086 type = regs->phys_addr >> 60UL;
1087 high_bits = (regs->phys_addr >> 32UL) & 0x0fffffffUL;
1088 low_bits = (regs->phys_addr & 0xffffffffUL);
1090 if (type == 0 || type == 8) {
1091 const char *prefix = (type == 0) ? "m" : "i";
1094 sprintf(tmp_buf, "%s@%s%x,%x",
1096 high_bits, low_bits);
1098 sprintf(tmp_buf, "%s@%s%x",
1102 } else if (type == 12) {
1103 sprintf(tmp_buf, "%s@%x",
1104 dp->name, high_bits);
1108 static void __init sun4u_path_component(struct device_node *dp, char *tmp_buf)
1110 struct linux_prom64_registers *regs;
1111 struct property *prop;
1113 prop = of_find_property(dp, "reg", NULL);
1118 if (!is_root_node(dp->parent)) {
1119 sprintf(tmp_buf, "%s@%x,%x",
1121 (unsigned int) (regs->phys_addr >> 32UL),
1122 (unsigned int) (regs->phys_addr & 0xffffffffUL));
1126 prop = of_find_property(dp, "upa-portid", NULL);
1128 prop = of_find_property(dp, "portid", NULL);
1130 unsigned long mask = 0xffffffffUL;
1132 if (tlb_type >= cheetah)
1135 sprintf(tmp_buf, "%s@%x,%x",
1137 *(u32 *)prop->value,
1138 (unsigned int) (regs->phys_addr & mask));
1142 /* "name@slot,offset" */
1143 static void __init sbus_path_component(struct device_node *dp, char *tmp_buf)
1145 struct linux_prom_registers *regs;
1146 struct property *prop;
1148 prop = of_find_property(dp, "reg", NULL);
1153 sprintf(tmp_buf, "%s@%x,%x",
1159 /* "name@devnum[,func]" */
1160 static void __init pci_path_component(struct device_node *dp, char *tmp_buf)
1162 struct linux_prom_pci_registers *regs;
1163 struct property *prop;
1166 prop = of_find_property(dp, "reg", NULL);
1171 devfn = (regs->phys_hi >> 8) & 0xff;
1173 sprintf(tmp_buf, "%s@%x,%x",
1178 sprintf(tmp_buf, "%s@%x",
1184 /* "name@UPA_PORTID,offset" */
1185 static void __init upa_path_component(struct device_node *dp, char *tmp_buf)
1187 struct linux_prom64_registers *regs;
1188 struct property *prop;
1190 prop = of_find_property(dp, "reg", NULL);
1196 prop = of_find_property(dp, "upa-portid", NULL);
1200 sprintf(tmp_buf, "%s@%x,%x",
1202 *(u32 *) prop->value,
1203 (unsigned int) (regs->phys_addr & 0xffffffffUL));
1207 static void __init vdev_path_component(struct device_node *dp, char *tmp_buf)
1209 struct property *prop;
1212 prop = of_find_property(dp, "reg", NULL);
1218 sprintf(tmp_buf, "%s@%x", dp->name, *regs);
1221 /* "name@addrhi,addrlo" */
1222 static void __init ebus_path_component(struct device_node *dp, char *tmp_buf)
1224 struct linux_prom64_registers *regs;
1225 struct property *prop;
1227 prop = of_find_property(dp, "reg", NULL);
1233 sprintf(tmp_buf, "%s@%x,%x",
1235 (unsigned int) (regs->phys_addr >> 32UL),
1236 (unsigned int) (regs->phys_addr & 0xffffffffUL));
1239 /* "name@bus,addr" */
1240 static void __init i2c_path_component(struct device_node *dp, char *tmp_buf)
1242 struct property *prop;
1245 prop = of_find_property(dp, "reg", NULL);
1251 /* This actually isn't right... should look at the #address-cells
1252 * property of the i2c bus node etc. etc.
1254 sprintf(tmp_buf, "%s@%x,%x",
1255 dp->name, regs[0], regs[1]);
1258 /* "name@reg0[,reg1]" */
1259 static void __init usb_path_component(struct device_node *dp, char *tmp_buf)
1261 struct property *prop;
1264 prop = of_find_property(dp, "reg", NULL);
1270 if (prop->length == sizeof(u32) || regs[1] == 1) {
1271 sprintf(tmp_buf, "%s@%x",
1274 sprintf(tmp_buf, "%s@%x,%x",
1275 dp->name, regs[0], regs[1]);
1279 /* "name@reg0reg1[,reg2reg3]" */
1280 static void __init ieee1394_path_component(struct device_node *dp, char *tmp_buf)
1282 struct property *prop;
1285 prop = of_find_property(dp, "reg", NULL);
1291 if (regs[2] || regs[3]) {
1292 sprintf(tmp_buf, "%s@%08x%08x,%04x%08x",
1293 dp->name, regs[0], regs[1], regs[2], regs[3]);
1295 sprintf(tmp_buf, "%s@%08x%08x",
1296 dp->name, regs[0], regs[1]);
1300 static void __init __build_path_component(struct device_node *dp, char *tmp_buf)
1302 struct device_node *parent = dp->parent;
1304 if (parent != NULL) {
1305 if (!strcmp(parent->type, "pci") ||
1306 !strcmp(parent->type, "pciex"))
1307 return pci_path_component(dp, tmp_buf);
1308 if (!strcmp(parent->type, "sbus"))
1309 return sbus_path_component(dp, tmp_buf);
1310 if (!strcmp(parent->type, "upa"))
1311 return upa_path_component(dp, tmp_buf);
1312 if (!strcmp(parent->type, "ebus"))
1313 return ebus_path_component(dp, tmp_buf);
1314 if (!strcmp(parent->name, "usb") ||
1315 !strcmp(parent->name, "hub"))
1316 return usb_path_component(dp, tmp_buf);
1317 if (!strcmp(parent->type, "i2c"))
1318 return i2c_path_component(dp, tmp_buf);
1319 if (!strcmp(parent->type, "firewire"))
1320 return ieee1394_path_component(dp, tmp_buf);
1321 if (!strcmp(parent->type, "virtual-devices"))
1322 return vdev_path_component(dp, tmp_buf);
1324 /* "isa" is handled with platform naming */
1327 /* Use platform naming convention. */
1328 if (tlb_type == hypervisor)
1329 return sun4v_path_component(dp, tmp_buf);
1331 return sun4u_path_component(dp, tmp_buf);
1334 static char * __init build_path_component(struct device_node *dp)
1336 char tmp_buf[64], *n;
1339 __build_path_component(dp, tmp_buf);
1340 if (tmp_buf[0] == '\0')
1341 strcpy(tmp_buf, dp->name);
1343 n = prom_early_alloc(strlen(tmp_buf) + 1);
1349 static char * __init build_full_name(struct device_node *dp)
1351 int len, ourlen, plen;
1354 plen = strlen(dp->parent->full_name);
1355 ourlen = strlen(dp->path_component_name);
1356 len = ourlen + plen + 2;
1358 n = prom_early_alloc(len);
1359 strcpy(n, dp->parent->full_name);
1360 if (!is_root_node(dp->parent)) {
1361 strcpy(n + plen, "/");
1364 strcpy(n + plen, dp->path_component_name);
1369 static unsigned int unique_id;
1371 static struct property * __init build_one_prop(phandle node, char *prev, char *special_name, void *special_val, int special_len)
1373 static struct property *tmp = NULL;
1378 memset(p, 0, sizeof(*p) + 32);
1381 p = prom_early_alloc(sizeof(struct property) + 32);
1382 p->unique_id = unique_id++;
1385 p->name = (char *) (p + 1);
1387 strcpy(p->name, special_name);
1388 p->length = special_len;
1389 p->value = prom_early_alloc(special_len);
1390 memcpy(p->value, special_val, special_len);
1393 prom_firstprop(node, p->name);
1395 prom_nextprop(node, prev, p->name);
1397 if (strlen(p->name) == 0) {
1401 p->length = prom_getproplen(node, p->name);
1402 if (p->length <= 0) {
1405 p->value = prom_early_alloc(p->length + 1);
1406 prom_getproperty(node, p->name, p->value, p->length);
1407 ((unsigned char *)p->value)[p->length] = '\0';
1413 static struct property * __init build_prop_list(phandle node)
1415 struct property *head, *tail;
1417 head = tail = build_one_prop(node, NULL,
1418 ".node", &node, sizeof(node));
1420 tail->next = build_one_prop(node, NULL, NULL, NULL, 0);
1423 tail->next = build_one_prop(node, tail->name,
1431 static char * __init get_one_property(phandle node, const char *name)
1433 char *buf = "<NULL>";
1436 len = prom_getproplen(node, name);
1438 buf = prom_early_alloc(len);
1439 prom_getproperty(node, name, buf, len);
1445 static struct device_node * __init create_node(phandle node, struct device_node *parent)
1447 struct device_node *dp;
1452 dp = prom_early_alloc(sizeof(*dp));
1453 dp->unique_id = unique_id++;
1454 dp->parent = parent;
1456 kref_init(&dp->kref);
1458 dp->name = get_one_property(node, "name");
1459 dp->type = get_one_property(node, "device_type");
1462 dp->properties = build_prop_list(node);
1469 static struct device_node * __init build_tree(struct device_node *parent, phandle node, struct device_node ***nextp)
1471 struct device_node *ret = NULL, *prev_sibling = NULL;
1472 struct device_node *dp;
1475 dp = create_node(node, parent);
1480 prev_sibling->sibling = dp;
1487 *nextp = &dp->allnext;
1489 dp->path_component_name = build_path_component(dp);
1490 dp->full_name = build_full_name(dp);
1492 dp->child = build_tree(dp, prom_getchild(node), nextp);
1494 node = prom_getsibling(node);
1500 static const char *get_mid_prop(void)
1502 return (tlb_type == spitfire ? "upa-portid" : "portid");
1505 struct device_node *of_find_node_by_cpuid(int cpuid)
1507 struct device_node *dp;
1508 const char *mid_prop = get_mid_prop();
1510 for_each_node_by_type(dp, "cpu") {
1511 int id = of_getintprop_default(dp, mid_prop, -1);
1512 const char *this_mid_prop = mid_prop;
1515 this_mid_prop = "cpuid";
1516 id = of_getintprop_default(dp, this_mid_prop, -1);
1520 prom_printf("OF: Serious problem, cpu lacks "
1521 "%s property", this_mid_prop);
1530 static void __init of_fill_in_cpu_data(void)
1532 struct device_node *dp;
1533 const char *mid_prop = get_mid_prop();
1536 for_each_node_by_type(dp, "cpu") {
1537 int cpuid = of_getintprop_default(dp, mid_prop, -1);
1538 const char *this_mid_prop = mid_prop;
1539 struct device_node *portid_parent;
1542 portid_parent = NULL;
1544 this_mid_prop = "cpuid";
1545 cpuid = of_getintprop_default(dp, this_mid_prop, -1);
1551 portid_parent = portid_parent->parent;
1554 portid = of_getintprop_default(portid_parent,
1563 prom_printf("OF: Serious problem, cpu lacks "
1564 "%s property", this_mid_prop);
1571 if (cpuid >= NR_CPUS)
1574 /* On uniprocessor we only want the values for the
1575 * real physical cpu the kernel booted onto, however
1576 * cpu_data() only has one entry at index 0.
1578 if (cpuid != real_hard_smp_processor_id())
1583 cpu_data(cpuid).clock_tick =
1584 of_getintprop_default(dp, "clock-frequency", 0);
1586 if (portid_parent) {
1587 cpu_data(cpuid).dcache_size =
1588 of_getintprop_default(dp, "l1-dcache-size",
1590 cpu_data(cpuid).dcache_line_size =
1591 of_getintprop_default(dp, "l1-dcache-line-size",
1593 cpu_data(cpuid).icache_size =
1594 of_getintprop_default(dp, "l1-icache-size",
1596 cpu_data(cpuid).icache_line_size =
1597 of_getintprop_default(dp, "l1-icache-line-size",
1599 cpu_data(cpuid).ecache_size =
1600 of_getintprop_default(dp, "l2-cache-size", 0);
1601 cpu_data(cpuid).ecache_line_size =
1602 of_getintprop_default(dp, "l2-cache-line-size", 0);
1603 if (!cpu_data(cpuid).ecache_size ||
1604 !cpu_data(cpuid).ecache_line_size) {
1605 cpu_data(cpuid).ecache_size =
1606 of_getintprop_default(portid_parent,
1609 cpu_data(cpuid).ecache_line_size =
1610 of_getintprop_default(portid_parent,
1611 "l2-cache-line-size", 64);
1614 cpu_data(cpuid).core_id = portid + 1;
1615 cpu_data(cpuid).proc_id = portid;
1617 sparc64_multi_core = 1;
1620 cpu_data(cpuid).dcache_size =
1621 of_getintprop_default(dp, "dcache-size", 16 * 1024);
1622 cpu_data(cpuid).dcache_line_size =
1623 of_getintprop_default(dp, "dcache-line-size", 32);
1625 cpu_data(cpuid).icache_size =
1626 of_getintprop_default(dp, "icache-size", 16 * 1024);
1627 cpu_data(cpuid).icache_line_size =
1628 of_getintprop_default(dp, "icache-line-size", 32);
1630 cpu_data(cpuid).ecache_size =
1631 of_getintprop_default(dp, "ecache-size",
1633 cpu_data(cpuid).ecache_line_size =
1634 of_getintprop_default(dp, "ecache-line-size", 64);
1636 cpu_data(cpuid).core_id = 0;
1637 cpu_data(cpuid).proc_id = -1;
1641 cpu_set(cpuid, cpu_present_map);
1642 cpu_set(cpuid, cpu_possible_map);
1646 smp_fill_in_sib_core_maps();
1649 struct device_node *of_console_device;
1650 EXPORT_SYMBOL(of_console_device);
1652 char *of_console_path;
1653 EXPORT_SYMBOL(of_console_path);
1655 char *of_console_options;
1656 EXPORT_SYMBOL(of_console_options);
1658 static void __init of_console_init(void)
1660 char *msg = "OF stdout device is: %s\n";
1661 struct device_node *dp;
1665 of_console_path = prom_early_alloc(256);
1666 if (prom_ihandle2path(prom_stdout, of_console_path, 256) < 0) {
1667 prom_printf("Cannot obtain path of stdout.\n");
1670 of_console_options = strrchr(of_console_path, ':');
1671 if (of_console_options) {
1672 of_console_options++;
1673 if (*of_console_options == '\0')
1674 of_console_options = NULL;
1677 node = prom_inst2pkg(prom_stdout);
1679 prom_printf("Cannot resolve stdout node from "
1680 "instance %08x.\n", prom_stdout);
1684 dp = of_find_node_by_phandle(node);
1685 type = of_get_property(dp, "device_type", NULL);
1687 prom_printf("Console stdout lacks device_type property.\n");
1691 if (strcmp(type, "display") && strcmp(type, "serial")) {
1692 prom_printf("Console device_type is neither display "
1697 of_console_device = dp;
1699 prom_printf(msg, of_console_path);
1700 printk(msg, of_console_path);
1703 void __init prom_build_devicetree(void)
1705 struct device_node **nextp;
1707 allnodes = create_node(prom_root_node, NULL);
1708 allnodes->path_component_name = "";
1709 allnodes->full_name = "/";
1711 nextp = &allnodes->allnext;
1712 allnodes->child = build_tree(allnodes,
1713 prom_getchild(allnodes->node),
1717 printk("PROM: Built device tree with %u bytes of memory.\n",
1718 prom_early_allocated);
1720 if (tlb_type != hypervisor)
1721 of_fill_in_cpu_data();