git.oblomov.eu Git - linux-2.6/blob - drivers/net/wireless/ath9k/main.c

   1 /*
   2  * Copyright (c) 2008 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/nl80211.h>
  18 #include "core.h"
  19 #include "reg.h"
  20 #include "hw.h"
  21
  22 #define ATH_PCI_VERSION "0.1"
  23
  24 static char *dev_info = "ath9k";
  25
  26 MODULE_AUTHOR("Atheros Communications");
  27 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  28 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  29 MODULE_LICENSE("Dual BSD/GPL");
  30
  31 static struct pci_device_id ath_pci_id_table[] __devinitdata = {
  32         { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI   */
  33         { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
  34         { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI   */
  35         { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI   */
  36         { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
  37         { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
  38         { 0 }
  39 };
  40
  41 static void ath_detach(struct ath_softc *sc);
  42
  43 /* return bus cachesize in 4B word units */
  44
  45 static void bus_read_cachesize(struct ath_softc *sc, int *csz)
  46 {
  47         u8 u8tmp;
  48
  49         pci_read_config_byte(sc->pdev, PCI_CACHE_LINE_SIZE, (u8 *)&u8tmp);
  50         *csz = (int)u8tmp;
  51
  52         /*
  53          * This check was put in to avoid "unplesant" consequences if
  54          * the bootrom has not fully initialized all PCI devices.
  55          * Sometimes the cache line size register is not set
  56          */
  57
  58         if (*csz == 0)
  59                 *csz = DEFAULT_CACHELINE >> 2;   /* Use the default size */
  60 }
  61
  62 static void ath_setcurmode(struct ath_softc *sc, enum wireless_mode mode)
  63 {
  64         sc->cur_rate_table = sc->hw_rate_table[mode];
  65         /*
  66          * All protection frames are transmited at 2Mb/s for
  67          * 11g, otherwise at 1Mb/s.
  68          * XXX select protection rate index from rate table.
  69          */
  70         sc->sc_protrix = (mode == ATH9K_MODE_11G ? 1 : 0);
  71 }
  72
  73 static enum wireless_mode ath_chan2mode(struct ath9k_channel *chan)
  74 {
  75         if (chan->chanmode == CHANNEL_A)
  76                 return ATH9K_MODE_11A;
  77         else if (chan->chanmode == CHANNEL_G)
  78                 return ATH9K_MODE_11G;
  79         else if (chan->chanmode == CHANNEL_B)
  80                 return ATH9K_MODE_11B;
  81         else if (chan->chanmode == CHANNEL_A_HT20)
  82                 return ATH9K_MODE_11NA_HT20;
  83         else if (chan->chanmode == CHANNEL_G_HT20)
  84                 return ATH9K_MODE_11NG_HT20;
  85         else if (chan->chanmode == CHANNEL_A_HT40PLUS)
  86                 return ATH9K_MODE_11NA_HT40PLUS;
  87         else if (chan->chanmode == CHANNEL_A_HT40MINUS)
  88                 return ATH9K_MODE_11NA_HT40MINUS;
  89         else if (chan->chanmode == CHANNEL_G_HT40PLUS)
  90                 return ATH9K_MODE_11NG_HT40PLUS;
  91         else if (chan->chanmode == CHANNEL_G_HT40MINUS)
  92                 return ATH9K_MODE_11NG_HT40MINUS;
  93
  94         WARN_ON(1); /* should not get here */
  95
  96         return ATH9K_MODE_11B;
  97 }
  98
  99 static void ath_update_txpow(struct ath_softc *sc)
 100 {
 101         struct ath_hal *ah = sc->sc_ah;
 102         u32 txpow;
 103
 104         if (sc->sc_curtxpow != sc->sc_config.txpowlimit) {
 105                 ath9k_hw_set_txpowerlimit(ah, sc->sc_config.txpowlimit);
 106                 /* read back in case value is clamped */
 107                 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
 108                 sc->sc_curtxpow = txpow;
 109         }
 110 }
 111
 112 static u8 parse_mpdudensity(u8 mpdudensity)
 113 {
 114         /*
 115          * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
 116          *   0 for no restriction
 117          *   1 for 1/4 us
 118          *   2 for 1/2 us
 119          *   3 for 1 us
 120          *   4 for 2 us
 121          *   5 for 4 us
 122          *   6 for 8 us
 123          *   7 for 16 us
 124          */
 125         switch (mpdudensity) {
 126         case 0:
 127                 return 0;
 128         case 1:
 129         case 2:
 130         case 3:
 131                 /* Our lower layer calculations limit our precision to
 132                    1 microsecond */
 133                 return 1;
 134         case 4:
 135                 return 2;
 136         case 5:
 137                 return 4;
 138         case 6:
 139                 return 8;
 140         case 7:
 141                 return 16;
 142         default:
 143                 return 0;
 144         }
 145 }
 146
 147 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
 148 {
 149         struct ath_rate_table *rate_table = NULL;
 150         struct ieee80211_supported_band *sband;
 151         struct ieee80211_rate *rate;
 152         int i, maxrates;
 153
 154         switch (band) {
 155         case IEEE80211_BAND_2GHZ:
 156                 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
 157                 break;
 158         case IEEE80211_BAND_5GHZ:
 159                 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
 160                 break;
 161         default:
 162                 break;
 163         }
 164
 165         if (rate_table == NULL)
 166                 return;
 167
 168         sband = &sc->sbands[band];
 169         rate = sc->rates[band];
 170
 171         if (rate_table->rate_cnt > ATH_RATE_MAX)
 172                 maxrates = ATH_RATE_MAX;
 173         else
 174                 maxrates = rate_table->rate_cnt;
 175
 176         for (i = 0; i < maxrates; i++) {
 177                 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
 178                 rate[i].hw_value = rate_table->info[i].ratecode;
 179                 sband->n_bitrates++;
 180                 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
 181                         rate[i].bitrate / 10, rate[i].hw_value);
 182         }
 183 }
 184
 185 static int ath_setup_channels(struct ath_softc *sc)
 186 {
 187         struct ath_hal *ah = sc->sc_ah;
 188         int nchan, i, a = 0, b = 0;
 189         u8 regclassids[ATH_REGCLASSIDS_MAX];
 190         u32 nregclass = 0;
 191         struct ieee80211_supported_band *band_2ghz;
 192         struct ieee80211_supported_band *band_5ghz;
 193         struct ieee80211_channel *chan_2ghz;
 194         struct ieee80211_channel *chan_5ghz;
 195         struct ath9k_channel *c;
 196
 197         /* Fill in ah->ah_channels */
 198         if (!ath9k_regd_init_channels(ah, ATH_CHAN_MAX, (u32 *)&nchan,
 199                                       regclassids, ATH_REGCLASSIDS_MAX,
 200                                       &nregclass, CTRY_DEFAULT, false, 1)) {
 201                 u32 rd = ah->ah_currentRD;
 202                 DPRINTF(sc, ATH_DBG_FATAL,
 203                         "Unable to collect channel list; "
 204                         "regdomain likely %u country code %u\n",
 205                         rd, CTRY_DEFAULT);
 206                 return -EINVAL;
 207         }
 208
 209         band_2ghz = &sc->sbands[IEEE80211_BAND_2GHZ];
 210         band_5ghz = &sc->sbands[IEEE80211_BAND_5GHZ];
 211         chan_2ghz = sc->channels[IEEE80211_BAND_2GHZ];
 212         chan_5ghz = sc->channels[IEEE80211_BAND_5GHZ];
 213
 214         for (i = 0; i < nchan; i++) {
 215                 c = &ah->ah_channels[i];
 216                 if (IS_CHAN_2GHZ(c)) {
 217                         chan_2ghz[a].band = IEEE80211_BAND_2GHZ;
 218                         chan_2ghz[a].center_freq = c->channel;
 219                         chan_2ghz[a].max_power = c->maxTxPower;
 220
 221                         if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
 222                                 chan_2ghz[a].flags |= IEEE80211_CHAN_NO_IBSS;
 223                         if (c->channelFlags & CHANNEL_PASSIVE)
 224                                 chan_2ghz[a].flags |= IEEE80211_CHAN_PASSIVE_SCAN;
 225
 226                         band_2ghz->n_channels = ++a;
 227
 228                         DPRINTF(sc, ATH_DBG_CONFIG, "2MHz channel: %d, "
 229                                 "channelFlags: 0x%x\n",
 230                                 c->channel, c->channelFlags);
 231                 } else if (IS_CHAN_5GHZ(c)) {
 232                         chan_5ghz[b].band = IEEE80211_BAND_5GHZ;
 233                         chan_5ghz[b].center_freq = c->channel;
 234                         chan_5ghz[b].max_power = c->maxTxPower;
 235
 236                         if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
 237                                 chan_5ghz[b].flags |= IEEE80211_CHAN_NO_IBSS;
 238                         if (c->channelFlags & CHANNEL_PASSIVE)
 239                                 chan_5ghz[b].flags |= IEEE80211_CHAN_PASSIVE_SCAN;
 240
 241                         band_5ghz->n_channels = ++b;
 242
 243                         DPRINTF(sc, ATH_DBG_CONFIG, "5MHz channel: %d, "
 244                                 "channelFlags: 0x%x\n",
 245                                 c->channel, c->channelFlags);
 246                 }
 247         }
 248
 249         return 0;
 250 }
 251
 252 /*
 253  * Set/change channels.  If the channel is really being changed, it's done
 254  * by reseting the chip.  To accomplish this we must first cleanup any pending
 255  * DMA, then restart stuff.
 256 */
 257 static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
 258 {
 259         struct ath_hal *ah = sc->sc_ah;
 260         bool fastcc = true, stopped;
 261
 262         if (sc->sc_flags & SC_OP_INVALID)
 263                 return -EIO;
 264
 265         if (hchan->channel != sc->sc_ah->ah_curchan->channel ||
 266             hchan->channelFlags != sc->sc_ah->ah_curchan->channelFlags ||
 267             (sc->sc_flags & SC_OP_CHAINMASK_UPDATE) ||
 268             (sc->sc_flags & SC_OP_FULL_RESET)) {
 269                 int status;
 270                 /*
 271                  * This is only performed if the channel settings have
 272                  * actually changed.
 273                  *
 274                  * To switch channels clear any pending DMA operations;
 275                  * wait long enough for the RX fifo to drain, reset the
 276                  * hardware at the new frequency, and then re-enable
 277                  * the relevant bits of the h/w.
 278                  */
 279                 ath9k_hw_set_interrupts(ah, 0);
 280                 ath_draintxq(sc, false);
 281                 stopped = ath_stoprecv(sc);
 282
 283                 /* XXX: do not flush receive queue here. We don't want
 284                  * to flush data frames already in queue because of
 285                  * changing channel. */
 286
 287                 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
 288                         fastcc = false;
 289
 290                 DPRINTF(sc, ATH_DBG_CONFIG,
 291                         "(%u MHz) -> (%u MHz), cflags:%x, chanwidth: %d\n",
 292                         sc->sc_ah->ah_curchan->channel,
 293                         hchan->channel, hchan->channelFlags, sc->tx_chan_width);
 294
 295                 spin_lock_bh(&sc->sc_resetlock);
 296                 if (!ath9k_hw_reset(ah, hchan, sc->tx_chan_width,
 297                                     sc->sc_tx_chainmask, sc->sc_rx_chainmask,
 298                                     sc->sc_ht_extprotspacing, fastcc, &status)) {
 299                         DPRINTF(sc, ATH_DBG_FATAL,
 300                                 "Unable to reset channel %u (%uMhz) "
 301                                 "flags 0x%x hal status %u\n",
 302                                 ath9k_hw_mhz2ieee(ah, hchan->channel,
 303                                                   hchan->channelFlags),
 304                                 hchan->channel, hchan->channelFlags, status);
 305                         spin_unlock_bh(&sc->sc_resetlock);
 306                         return -EIO;
 307                 }
 308                 spin_unlock_bh(&sc->sc_resetlock);
 309
 310                 sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
 311                 sc->sc_flags &= ~SC_OP_FULL_RESET;
 312
 313                 if (ath_startrecv(sc) != 0) {
 314                         DPRINTF(sc, ATH_DBG_FATAL,
 315                                 "Unable to restart recv logic\n");
 316                         return -EIO;
 317                 }
 318
 319                 ath_setcurmode(sc, ath_chan2mode(hchan));
 320                 ath_update_txpow(sc);
 321                 ath9k_hw_set_interrupts(ah, sc->sc_imask);
 322         }
 323         return 0;
 324 }
 325
 326 /*
 327  *  This routine performs the periodic noise floor calibration function
 328  *  that is used to adjust and optimize the chip performance.  This
 329  *  takes environmental changes (location, temperature) into account.
 330  *  When the task is complete, it reschedules itself depending on the
 331  *  appropriate interval that was calculated.
 332  */
 333 static void ath_ani_calibrate(unsigned long data)
 334 {
 335         struct ath_softc *sc;
 336         struct ath_hal *ah;
 337         bool longcal = false;
 338         bool shortcal = false;
 339         bool aniflag = false;
 340         unsigned int timestamp = jiffies_to_msecs(jiffies);
 341         u32 cal_interval;
 342
 343         sc = (struct ath_softc *)data;
 344         ah = sc->sc_ah;
 345
 346         /*
 347         * don't calibrate when we're scanning.
 348         * we are most likely not on our home channel.
 349         */
 350         if (sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC)
 351                 return;
 352
 353         /* Long calibration runs independently of short calibration. */
 354         if ((timestamp - sc->sc_ani.sc_longcal_timer) >= ATH_LONG_CALINTERVAL) {
 355                 longcal = true;
 356                 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
 357                 sc->sc_ani.sc_longcal_timer = timestamp;
 358         }
 359
 360         /* Short calibration applies only while sc_caldone is false */
 361         if (!sc->sc_ani.sc_caldone) {
 362                 if ((timestamp - sc->sc_ani.sc_shortcal_timer) >=
 363                     ATH_SHORT_CALINTERVAL) {
 364                         shortcal = true;
 365                         DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
 366                         sc->sc_ani.sc_shortcal_timer = timestamp;
 367                         sc->sc_ani.sc_resetcal_timer = timestamp;
 368                 }
 369         } else {
 370                 if ((timestamp - sc->sc_ani.sc_resetcal_timer) >=
 371                     ATH_RESTART_CALINTERVAL) {
 372                         ath9k_hw_reset_calvalid(ah, ah->ah_curchan,
 373                                                 &sc->sc_ani.sc_caldone);
 374                         if (sc->sc_ani.sc_caldone)
 375                                 sc->sc_ani.sc_resetcal_timer = timestamp;
 376                 }
 377         }
 378
 379         /* Verify whether we must check ANI */
 380         if ((timestamp - sc->sc_ani.sc_checkani_timer) >=
 381            ATH_ANI_POLLINTERVAL) {
 382                 aniflag = true;
 383                 sc->sc_ani.sc_checkani_timer = timestamp;
 384         }
 385
 386         /* Skip all processing if there's nothing to do. */
 387         if (longcal || shortcal || aniflag) {
 388                 /* Call ANI routine if necessary */
 389                 if (aniflag)
 390                         ath9k_hw_ani_monitor(ah, &sc->sc_halstats,
 391                                              ah->ah_curchan);
 392
 393                 /* Perform calibration if necessary */
 394                 if (longcal || shortcal) {
 395                         bool iscaldone = false;
 396
 397                         if (ath9k_hw_calibrate(ah, ah->ah_curchan,
 398                                                sc->sc_rx_chainmask, longcal,
 399                                                &iscaldone)) {
 400                                 if (longcal)
 401                                         sc->sc_ani.sc_noise_floor =
 402                                                 ath9k_hw_getchan_noise(ah,
 403                                                                ah->ah_curchan);
 404
 405                                 DPRINTF(sc, ATH_DBG_ANI,
 406                                         "calibrate chan %u/%x nf: %d\n",
 407                                         ah->ah_curchan->channel,
 408                                         ah->ah_curchan->channelFlags,
 409                                         sc->sc_ani.sc_noise_floor);
 410                         } else {
 411                                 DPRINTF(sc, ATH_DBG_ANY,
 412                                         "calibrate chan %u/%x failed\n",
 413                                         ah->ah_curchan->channel,
 414                                         ah->ah_curchan->channelFlags);
 415                         }
 416                         sc->sc_ani.sc_caldone = iscaldone;
 417                 }
 418         }
 419
 420         /*
 421         * Set timer interval based on previous results.
 422         * The interval must be the shortest necessary to satisfy ANI,
 423         * short calibration and long calibration.
 424         */
 425         cal_interval = ATH_LONG_CALINTERVAL;
 426         if (sc->sc_ah->ah_config.enable_ani)
 427                 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
 428         if (!sc->sc_ani.sc_caldone)
 429                 cal_interval = min(cal_interval, (u32)ATH_SHORT_CALINTERVAL);
 430
 431         mod_timer(&sc->sc_ani.timer, jiffies + msecs_to_jiffies(cal_interval));
 432 }
 433
 434 /*
 435  * Update tx/rx chainmask. For legacy association,
 436  * hard code chainmask to 1x1, for 11n association, use
 437  * the chainmask configuration.
 438  */
 439 static void ath_update_chainmask(struct ath_softc *sc, int is_ht)
 440 {
 441         sc->sc_flags |= SC_OP_CHAINMASK_UPDATE;
 442         if (is_ht) {
 443                 sc->sc_tx_chainmask = sc->sc_ah->ah_caps.tx_chainmask;
 444                 sc->sc_rx_chainmask = sc->sc_ah->ah_caps.rx_chainmask;
 445         } else {
 446                 sc->sc_tx_chainmask = 1;
 447                 sc->sc_rx_chainmask = 1;
 448         }
 449
 450         DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
 451                 sc->sc_tx_chainmask, sc->sc_rx_chainmask);
 452 }
 453
 454 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
 455 {
 456         struct ath_node *an;
 457
 458         an = (struct ath_node *)sta->drv_priv;
 459
 460         if (sc->sc_flags & SC_OP_TXAGGR)
 461                 ath_tx_node_init(sc, an);
 462
 463         an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
 464                              sta->ht_cap.ampdu_factor);
 465         an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
 466 }
 467
 468 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
 469 {
 470         struct ath_node *an = (struct ath_node *)sta->drv_priv;
 471
 472         if (sc->sc_flags & SC_OP_TXAGGR)
 473                 ath_tx_node_cleanup(sc, an);
 474 }
 475
 476 static void ath9k_tasklet(unsigned long data)
 477 {
 478         struct ath_softc *sc = (struct ath_softc *)data;
 479         u32 status = sc->sc_intrstatus;
 480
 481         if (status & ATH9K_INT_FATAL) {
 482                 /* need a chip reset */
 483                 ath_reset(sc, false);
 484                 return;
 485         } else {
 486
 487                 if (status &
 488                     (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
 489                         spin_lock_bh(&sc->rx.rxflushlock);
 490                         ath_rx_tasklet(sc, 0);
 491                         spin_unlock_bh(&sc->rx.rxflushlock);
 492                 }
 493                 /* XXX: optimize this */
 494                 if (status & ATH9K_INT_TX)
 495                         ath_tx_tasklet(sc);
 496         }
 497
 498         /* re-enable hardware interrupt */
 499         ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
 500 }
 501
 502 static irqreturn_t ath_isr(int irq, void *dev)
 503 {
 504         struct ath_softc *sc = dev;
 505         struct ath_hal *ah = sc->sc_ah;
 506         enum ath9k_int status;
 507         bool sched = false;
 508
 509         do {
 510                 if (sc->sc_flags & SC_OP_INVALID) {
 511                         /*
 512                          * The hardware is not ready/present, don't
 513                          * touch anything. Note this can happen early
 514                          * on if the IRQ is shared.
 515                          */
 516                         return IRQ_NONE;
 517                 }
 518                 if (!ath9k_hw_intrpend(ah)) {   /* shared irq, not for us */
 519                         return IRQ_NONE;
 520                 }
 521
 522                 /*
 523                  * Figure out the reason(s) for the interrupt.  Note
 524                  * that the hal returns a pseudo-ISR that may include
 525                  * bits we haven't explicitly enabled so we mask the
 526                  * value to insure we only process bits we requested.
 527                  */
 528                 ath9k_hw_getisr(ah, &status);   /* NB: clears ISR too */
 529
 530                 status &= sc->sc_imask; /* discard unasked-for bits */
 531
 532                 /*
 533                  * If there are no status bits set, then this interrupt was not
 534                  * for me (should have been caught above).
 535                  */
 536                 if (!status)
 537                         return IRQ_NONE;
 538
 539                 sc->sc_intrstatus = status;
 540
 541                 if (status & ATH9K_INT_FATAL) {
 542                         /* need a chip reset */
 543                         sched = true;
 544                 } else if (status & ATH9K_INT_RXORN) {
 545                         /* need a chip reset */
 546                         sched = true;
 547                 } else {
 548                         if (status & ATH9K_INT_SWBA) {
 549                                 /* schedule a tasklet for beacon handling */
 550                                 tasklet_schedule(&sc->bcon_tasklet);
 551                         }
 552                         if (status & ATH9K_INT_RXEOL) {
 553                                 /*
 554                                  * NB: the hardware should re-read the link when
 555                                  *     RXE bit is written, but it doesn't work
 556                                  *     at least on older hardware revs.
 557                                  */
 558                                 sched = true;
 559                         }
 560
 561                         if (status & ATH9K_INT_TXURN)
 562                                 /* bump tx trigger level */
 563                                 ath9k_hw_updatetxtriglevel(ah, true);
 564                         /* XXX: optimize this */
 565                         if (status & ATH9K_INT_RX)
 566                                 sched = true;
 567                         if (status & ATH9K_INT_TX)
 568                                 sched = true;
 569                         if (status & ATH9K_INT_BMISS)
 570                                 sched = true;
 571                         /* carrier sense timeout */
 572                         if (status & ATH9K_INT_CST)
 573                                 sched = true;
 574                         if (status & ATH9K_INT_MIB) {
 575                                 /*
 576                                  * Disable interrupts until we service the MIB
 577                                  * interrupt; otherwise it will continue to
 578                                  * fire.
 579                                  */
 580                                 ath9k_hw_set_interrupts(ah, 0);
 581                                 /*
 582                                  * Let the hal handle the event. We assume
 583                                  * it will clear whatever condition caused
 584                                  * the interrupt.
 585                                  */
 586                                 ath9k_hw_procmibevent(ah, &sc->sc_halstats);
 587                                 ath9k_hw_set_interrupts(ah, sc->sc_imask);
 588                         }
 589                         if (status & ATH9K_INT_TIM_TIMER) {
 590                                 if (!(ah->ah_caps.hw_caps &
 591                                       ATH9K_HW_CAP_AUTOSLEEP)) {
 592                                         /* Clear RxAbort bit so that we can
 593                                          * receive frames */
 594                                         ath9k_hw_setrxabort(ah, 0);
 595                                         sched = true;
 596                                 }
 597                         }
 598                 }
 599         } while (0);
 600
 601         ath_debug_stat_interrupt(sc, status);
 602
 603         if (sched) {
 604                 /* turn off every interrupt except SWBA */
 605                 ath9k_hw_set_interrupts(ah, (sc->sc_imask & ATH9K_INT_SWBA));
 606                 tasklet_schedule(&sc->intr_tq);
 607         }
 608
 609         return IRQ_HANDLED;
 610 }
 611
 612 static int ath_get_channel(struct ath_softc *sc,
 613                            struct ieee80211_channel *chan)
 614 {
 615         int i;
 616
 617         for (i = 0; i < sc->sc_ah->ah_nchan; i++) {
 618                 if (sc->sc_ah->ah_channels[i].channel == chan->center_freq)
 619                         return i;
 620         }
 621
 622         return -1;
 623 }
 624
 625 static u32 ath_get_extchanmode(struct ath_softc *sc,
 626                                struct ieee80211_channel *chan,
 627                                enum nl80211_channel_type channel_type)
 628 {
 629         u32 chanmode = 0;
 630
 631         switch (chan->band) {
 632         case IEEE80211_BAND_2GHZ:
 633                 switch(channel_type) {
 634                 case NL80211_CHAN_NO_HT:
 635                 case NL80211_CHAN_HT20:
 636                         chanmode = CHANNEL_G_HT20;
 637                         break;
 638                 case NL80211_CHAN_HT40PLUS:
 639                         chanmode = CHANNEL_G_HT40PLUS;
 640                         break;
 641                 case NL80211_CHAN_HT40MINUS:
 642                         chanmode = CHANNEL_G_HT40MINUS;
 643                         break;
 644                 }
 645                 break;
 646         case IEEE80211_BAND_5GHZ:
 647                 switch(channel_type) {
 648                 case NL80211_CHAN_NO_HT:
 649                 case NL80211_CHAN_HT20:
 650                         chanmode = CHANNEL_A_HT20;
 651                         break;
 652                 case NL80211_CHAN_HT40PLUS:
 653                         chanmode = CHANNEL_A_HT40PLUS;
 654                         break;
 655                 case NL80211_CHAN_HT40MINUS:
 656                         chanmode = CHANNEL_A_HT40MINUS;
 657                         break;
 658                 }
 659                 break;
 660         default:
 661                 break;
 662         }
 663
 664         return chanmode;
 665 }
 666
 667 static void ath_key_reset(struct ath_softc *sc, u16 keyix, int freeslot)
 668 {
 669         ath9k_hw_keyreset(sc->sc_ah, keyix);
 670         if (freeslot)
 671                 clear_bit(keyix, sc->sc_keymap);
 672 }
 673
 674 static int ath_keyset(struct ath_softc *sc, u16 keyix,
 675                struct ath9k_keyval *hk, const u8 mac[ETH_ALEN])
 676 {
 677         bool status;
 678
 679         status = ath9k_hw_set_keycache_entry(sc->sc_ah,
 680                 keyix, hk, mac, false);
 681
 682         return status != false;
 683 }
 684
 685 static int ath_setkey_tkip(struct ath_softc *sc,
 686                            struct ieee80211_key_conf *key,
 687                            struct ath9k_keyval *hk,
 688                            const u8 *addr)
 689 {
 690         u8 *key_rxmic = NULL;
 691         u8 *key_txmic = NULL;
 692
 693         key_txmic = key->key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
 694         key_rxmic = key->key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
 695
 696         if (addr == NULL) {
 697                 /* Group key installation */
 698                 memcpy(hk->kv_mic,  key_rxmic, sizeof(hk->kv_mic));
 699                 return ath_keyset(sc, key->keyidx, hk, addr);
 700         }
 701         if (!sc->sc_splitmic) {
 702                 /*
 703                  * data key goes at first index,
 704                  * the hal handles the MIC keys at index+64.
 705                  */
 706                 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 707                 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
 708                 return ath_keyset(sc, key->keyidx, hk, addr);
 709         }
 710         /*
 711          * TX key goes at first index, RX key at +32.
 712          * The hal handles the MIC keys at index+64.
 713          */
 714         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
 715         if (!ath_keyset(sc, key->keyidx, hk, NULL)) {
 716                 /* Txmic entry failed. No need to proceed further */
 717                 DPRINTF(sc, ATH_DBG_KEYCACHE,
 718                         "Setting TX MIC Key Failed\n");
 719                 return 0;
 720         }
 721
 722         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 723         /* XXX delete tx key on failure? */
 724         return ath_keyset(sc, key->keyidx+32, hk, addr);
 725 }
 726
 727 static int ath_key_config(struct ath_softc *sc,
 728                           const u8 *addr,
 729                           struct ieee80211_key_conf *key)
 730 {
 731         struct ieee80211_vif *vif;
 732         struct ath9k_keyval hk;
 733         const u8 *mac = NULL;
 734         int ret = 0;
 735         enum nl80211_iftype opmode;
 736
 737         memset(&hk, 0, sizeof(hk));
 738
 739         switch (key->alg) {
 740         case ALG_WEP:
 741                 hk.kv_type = ATH9K_CIPHER_WEP;
 742                 break;
 743         case ALG_TKIP:
 744                 hk.kv_type = ATH9K_CIPHER_TKIP;
 745                 break;
 746         case ALG_CCMP:
 747                 hk.kv_type = ATH9K_CIPHER_AES_CCM;
 748                 break;
 749         default:
 750                 return -EINVAL;
 751         }
 752
 753         hk.kv_len  = key->keylen;
 754         memcpy(hk.kv_val, key->key, key->keylen);
 755
 756         if (!sc->sc_vaps[0])
 757                 return -EIO;
 758
 759         vif = sc->sc_vaps[0];
 760         opmode = vif->type;
 761
 762         /*
 763          *  Strategy:
 764          *   For STA mc tx, we will not setup a key at
 765          *   all since we never tx mc.
 766          *
 767          *   For STA mc rx, we will use the keyID.
 768          *
 769          *   For ADHOC mc tx, we will use the keyID, and no macaddr.
 770          *
 771          *   For ADHOC mc rx, we will alloc a slot and plumb the mac of
 772          *   the peer node.
 773          *   BUT we will plumb a cleartext key so that we can do
 774          *   per-Sta default key table lookup in software.
 775          */
 776         if (is_broadcast_ether_addr(addr)) {
 777                 switch (opmode) {
 778                 case NL80211_IFTYPE_STATION:
 779                         /* default key:  could be group WPA key
 780                          * or could be static WEP key */
 781                         mac = NULL;
 782                         break;
 783                 case NL80211_IFTYPE_ADHOC:
 784                         break;
 785                 case NL80211_IFTYPE_AP:
 786                         break;
 787                 default:
 788                         ASSERT(0);
 789                         break;
 790                 }
 791         } else {
 792                 mac = addr;
 793         }
 794
 795         if (key->alg == ALG_TKIP)
 796                 ret = ath_setkey_tkip(sc, key, &hk, mac);
 797         else
 798                 ret = ath_keyset(sc, key->keyidx, &hk, mac);
 799
 800         if (!ret)
 801                 return -EIO;
 802
 803         return 0;
 804 }
 805
 806 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
 807 {
 808         int freeslot;
 809
 810         freeslot = (key->keyidx >= 4) ? 1 : 0;
 811         ath_key_reset(sc, key->keyidx, freeslot);
 812 }
 813
 814 static void setup_ht_cap(struct ieee80211_sta_ht_cap *ht_info)
 815 {
 816 #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3       /* 2 ^ 16 */
 817 #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6          /* 8 usec */
 818
 819         ht_info->ht_supported = true;
 820         ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
 821                        IEEE80211_HT_CAP_SM_PS |
 822                        IEEE80211_HT_CAP_SGI_40 |
 823                        IEEE80211_HT_CAP_DSSSCCK40;
 824
 825         ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
 826         ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
 827         /* set up supported mcs set */
 828         memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
 829         ht_info->mcs.rx_mask[0] = 0xff;
 830         ht_info->mcs.rx_mask[1] = 0xff;
 831         ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
 832 }
 833
 834 static void ath9k_bss_assoc_info(struct ath_softc *sc,
 835                                  struct ieee80211_vif *vif,
 836                                  struct ieee80211_bss_conf *bss_conf)
 837 {
 838         struct ath_vap *avp = (void *)vif->drv_priv;
 839
 840         if (bss_conf->assoc) {
 841                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
 842                         bss_conf->aid, sc->sc_curbssid);
 843
 844                 /* New association, store aid */
 845                 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
 846                         sc->sc_curaid = bss_conf->aid;
 847                         ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
 848                                                sc->sc_curaid);
 849                 }
 850
 851                 /* Configure the beacon */
 852                 ath_beacon_config(sc, 0);
 853                 sc->sc_flags |= SC_OP_BEACONS;
 854
 855                 /* Reset rssi stats */
 856                 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
 857                 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
 858                 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
 859                 sc->sc_halstats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
 860
 861                 /* Start ANI */
 862                 mod_timer(&sc->sc_ani.timer,
 863                         jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
 864
 865         } else {
 866                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISSOC\n");
 867                 sc->sc_curaid = 0;
 868         }
 869 }
 870
 871 /********************************/
 872 /*       LED functions          */
 873 /********************************/
 874
 875 static void ath_led_brightness(struct led_classdev *led_cdev,
 876                                enum led_brightness brightness)
 877 {
 878         struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
 879         struct ath_softc *sc = led->sc;
 880
 881         switch (brightness) {
 882         case LED_OFF:
 883                 if (led->led_type == ATH_LED_ASSOC ||
 884                     led->led_type == ATH_LED_RADIO)
 885                         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
 886                 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
 887                                 (led->led_type == ATH_LED_RADIO) ? 1 :
 888                                 !!(sc->sc_flags & SC_OP_LED_ASSOCIATED));
 889                 break;
 890         case LED_FULL:
 891                 if (led->led_type == ATH_LED_ASSOC)
 892                         sc->sc_flags |= SC_OP_LED_ASSOCIATED;
 893                 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
 894                 break;
 895         default:
 896                 break;
 897         }
 898 }
 899
 900 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
 901                             char *trigger)
 902 {
 903         int ret;
 904
 905         led->sc = sc;
 906         led->led_cdev.name = led->name;
 907         led->led_cdev.default_trigger = trigger;
 908         led->led_cdev.brightness_set = ath_led_brightness;
 909
 910         ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
 911         if (ret)
 912                 DPRINTF(sc, ATH_DBG_FATAL,
 913                         "Failed to register led:%s", led->name);
 914         else
 915                 led->registered = 1;
 916         return ret;
 917 }
 918
 919 static void ath_unregister_led(struct ath_led *led)
 920 {
 921         if (led->registered) {
 922                 led_classdev_unregister(&led->led_cdev);
 923                 led->registered = 0;
 924         }
 925 }
 926
 927 static void ath_deinit_leds(struct ath_softc *sc)
 928 {
 929         ath_unregister_led(&sc->assoc_led);
 930         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
 931         ath_unregister_led(&sc->tx_led);
 932         ath_unregister_led(&sc->rx_led);
 933         ath_unregister_led(&sc->radio_led);
 934         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
 935 }
 936
 937 static void ath_init_leds(struct ath_softc *sc)
 938 {
 939         char *trigger;
 940         int ret;
 941
 942         /* Configure gpio 1 for output */
 943         ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
 944                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
 945         /* LED off, active low */
 946         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
 947
 948         trigger = ieee80211_get_radio_led_name(sc->hw);
 949         snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
 950                 "ath9k-%s:radio", wiphy_name(sc->hw->wiphy));
 951         ret = ath_register_led(sc, &sc->radio_led, trigger);
 952         sc->radio_led.led_type = ATH_LED_RADIO;
 953         if (ret)
 954                 goto fail;
 955
 956         trigger = ieee80211_get_assoc_led_name(sc->hw);
 957         snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
 958                 "ath9k-%s:assoc", wiphy_name(sc->hw->wiphy));
 959         ret = ath_register_led(sc, &sc->assoc_led, trigger);
 960         sc->assoc_led.led_type = ATH_LED_ASSOC;
 961         if (ret)
 962                 goto fail;
 963
 964         trigger = ieee80211_get_tx_led_name(sc->hw);
 965         snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
 966                 "ath9k-%s:tx", wiphy_name(sc->hw->wiphy));
 967         ret = ath_register_led(sc, &sc->tx_led, trigger);
 968         sc->tx_led.led_type = ATH_LED_TX;
 969         if (ret)
 970                 goto fail;
 971
 972         trigger = ieee80211_get_rx_led_name(sc->hw);
 973         snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
 974                 "ath9k-%s:rx", wiphy_name(sc->hw->wiphy));
 975         ret = ath_register_led(sc, &sc->rx_led, trigger);
 976         sc->rx_led.led_type = ATH_LED_RX;
 977         if (ret)
 978                 goto fail;
 979
 980         return;
 981
 982 fail:
 983         ath_deinit_leds(sc);
 984 }
 985
 986 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
 987
 988 /*******************/
 989 /*      Rfkill     */
 990 /*******************/
 991
 992 static void ath_radio_enable(struct ath_softc *sc)
 993 {
 994         struct ath_hal *ah = sc->sc_ah;
 995         int status;
 996
 997         spin_lock_bh(&sc->sc_resetlock);
 998         if (!ath9k_hw_reset(ah, ah->ah_curchan,
 999                             sc->tx_chan_width,
1000                             sc->sc_tx_chainmask,
1001                             sc->sc_rx_chainmask,
1002                             sc->sc_ht_extprotspacing,
1003                             false, &status)) {
1004                 DPRINTF(sc, ATH_DBG_FATAL,
1005                         "Unable to reset channel %u (%uMhz) "
1006                         "flags 0x%x hal status %u\n",
1007                         ath9k_hw_mhz2ieee(ah,
1008                                           ah->ah_curchan->channel,
1009                                           ah->ah_curchan->channelFlags),
1010                         ah->ah_curchan->channel,
1011                         ah->ah_curchan->channelFlags, status);
1012         }
1013         spin_unlock_bh(&sc->sc_resetlock);
1014
1015         ath_update_txpow(sc);
1016         if (ath_startrecv(sc) != 0) {
1017                 DPRINTF(sc, ATH_DBG_FATAL,
1018                         "Unable to restart recv logic\n");
1019                 return;
1020         }
1021
1022         if (sc->sc_flags & SC_OP_BEACONS)
1023                 ath_beacon_config(sc, ATH_IF_ID_ANY);   /* restart beacons */
1024
1025         /* Re-Enable  interrupts */
1026         ath9k_hw_set_interrupts(ah, sc->sc_imask);
1027
1028         /* Enable LED */
1029         ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1030                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1031         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1032
1033         ieee80211_wake_queues(sc->hw);
1034 }
1035
1036 static void ath_radio_disable(struct ath_softc *sc)
1037 {
1038         struct ath_hal *ah = sc->sc_ah;
1039         int status;
1040
1041
1042         ieee80211_stop_queues(sc->hw);
1043
1044         /* Disable LED */
1045         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1046         ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1047
1048         /* Disable interrupts */
1049         ath9k_hw_set_interrupts(ah, 0);
1050
1051         ath_draintxq(sc, false);        /* clear pending tx frames */
1052         ath_stoprecv(sc);               /* turn off frame recv */
1053         ath_flushrecv(sc);              /* flush recv queue */
1054
1055         spin_lock_bh(&sc->sc_resetlock);
1056         if (!ath9k_hw_reset(ah, ah->ah_curchan,
1057                             sc->tx_chan_width,
1058                             sc->sc_tx_chainmask,
1059                             sc->sc_rx_chainmask,
1060                             sc->sc_ht_extprotspacing,
1061                             false, &status)) {
1062                 DPRINTF(sc, ATH_DBG_FATAL,
1063                         "Unable to reset channel %u (%uMhz) "
1064                         "flags 0x%x hal status %u\n",
1065                         ath9k_hw_mhz2ieee(ah,
1066                                 ah->ah_curchan->channel,
1067                                 ah->ah_curchan->channelFlags),
1068                         ah->ah_curchan->channel,
1069                         ah->ah_curchan->channelFlags, status);
1070         }
1071         spin_unlock_bh(&sc->sc_resetlock);
1072
1073         ath9k_hw_phy_disable(ah);
1074         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1075 }
1076
1077 static bool ath_is_rfkill_set(struct ath_softc *sc)
1078 {
1079         struct ath_hal *ah = sc->sc_ah;
1080
1081         return ath9k_hw_gpio_get(ah, ah->ah_rfkill_gpio) ==
1082                                   ah->ah_rfkill_polarity;
1083 }
1084
1085 /* h/w rfkill poll function */
1086 static void ath_rfkill_poll(struct work_struct *work)
1087 {
1088         struct ath_softc *sc = container_of(work, struct ath_softc,
1089                                             rf_kill.rfkill_poll.work);
1090         bool radio_on;
1091
1092         if (sc->sc_flags & SC_OP_INVALID)
1093                 return;
1094
1095         radio_on = !ath_is_rfkill_set(sc);
1096
1097         /*
1098          * enable/disable radio only when there is a
1099          * state change in RF switch
1100          */
1101         if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1102                 enum rfkill_state state;
1103
1104                 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1105                         state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1106                                 : RFKILL_STATE_HARD_BLOCKED;
1107                 } else if (radio_on) {
1108                         ath_radio_enable(sc);
1109                         state = RFKILL_STATE_UNBLOCKED;
1110                 } else {
1111                         ath_radio_disable(sc);
1112                         state = RFKILL_STATE_HARD_BLOCKED;
1113                 }
1114
1115                 if (state == RFKILL_STATE_HARD_BLOCKED)
1116                         sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1117                 else
1118                         sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1119
1120                 rfkill_force_state(sc->rf_kill.rfkill, state);
1121         }
1122
1123         queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1124                            msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1125 }
1126
1127 /* s/w rfkill handler */
1128 static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1129 {
1130         struct ath_softc *sc = data;
1131
1132         switch (state) {
1133         case RFKILL_STATE_SOFT_BLOCKED:
1134                 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1135                     SC_OP_RFKILL_SW_BLOCKED)))
1136                         ath_radio_disable(sc);
1137                 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1138                 return 0;
1139         case RFKILL_STATE_UNBLOCKED:
1140                 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1141                         sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1142                         if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1143                                 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
1144                                         "radio as it is disabled by h/w\n");
1145                                 return -EPERM;
1146                         }
1147                         ath_radio_enable(sc);
1148                 }
1149                 return 0;
1150         default:
1151                 return -EINVAL;
1152         }
1153 }
1154
1155 /* Init s/w rfkill */
1156 static int ath_init_sw_rfkill(struct ath_softc *sc)
1157 {
1158         sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1159                                              RFKILL_TYPE_WLAN);
1160         if (!sc->rf_kill.rfkill) {
1161                 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1162                 return -ENOMEM;
1163         }
1164
1165         snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
1166                 "ath9k-%s:rfkill", wiphy_name(sc->hw->wiphy));
1167         sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1168         sc->rf_kill.rfkill->data = sc;
1169         sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1170         sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1171         sc->rf_kill.rfkill->user_claim_unsupported = 1;
1172
1173         return 0;
1174 }
1175
1176 /* Deinitialize rfkill */
1177 static void ath_deinit_rfkill(struct ath_softc *sc)
1178 {
1179         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1180                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1181
1182         if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1183                 rfkill_unregister(sc->rf_kill.rfkill);
1184                 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1185                 sc->rf_kill.rfkill = NULL;
1186         }
1187 }
1188
1189 static int ath_start_rfkill_poll(struct ath_softc *sc)
1190 {
1191         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1192                 queue_delayed_work(sc->hw->workqueue,
1193                                    &sc->rf_kill.rfkill_poll, 0);
1194
1195         if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1196                 if (rfkill_register(sc->rf_kill.rfkill)) {
1197                         DPRINTF(sc, ATH_DBG_FATAL,
1198                                 "Unable to register rfkill\n");
1199                         rfkill_free(sc->rf_kill.rfkill);
1200
1201                         /* Deinitialize the device */
1202                         ath_detach(sc);
1203                         if (sc->pdev->irq)
1204                                 free_irq(sc->pdev->irq, sc);
1205                         pci_iounmap(sc->pdev, sc->mem);
1206                         pci_release_region(sc->pdev, 0);
1207                         pci_disable_device(sc->pdev);
1208                         ieee80211_free_hw(sc->hw);
1209                         return -EIO;
1210                 } else {
1211                         sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1212                 }
1213         }
1214
1215         return 0;
1216 }
1217 #endif /* CONFIG_RFKILL */
1218
1219 static void ath_detach(struct ath_softc *sc)
1220 {
1221         struct ieee80211_hw *hw = sc->hw;
1222         int i = 0;
1223
1224         DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
1225
1226 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1227         ath_deinit_rfkill(sc);
1228 #endif
1229         ath_deinit_leds(sc);
1230
1231         ieee80211_unregister_hw(hw);
1232
1233         ath_rate_control_unregister();
1234
1235         ath_rx_cleanup(sc);
1236         ath_tx_cleanup(sc);
1237
1238         tasklet_kill(&sc->intr_tq);
1239         tasklet_kill(&sc->bcon_tasklet);
1240
1241         if (!(sc->sc_flags & SC_OP_INVALID))
1242                 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1243
1244         /* cleanup tx queues */
1245         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1246                 if (ATH_TXQ_SETUP(sc, i))
1247                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1248
1249         ath9k_hw_detach(sc->sc_ah);
1250         ath9k_exit_debug(sc);
1251 }
1252
1253 static int ath_init(u16 devid, struct ath_softc *sc)
1254 {
1255         struct ath_hal *ah = NULL;
1256         int status;
1257         int error = 0, i;
1258         int csz = 0;
1259
1260         /* XXX: hardware will not be ready until ath_open() being called */
1261         sc->sc_flags |= SC_OP_INVALID;
1262
1263         if (ath9k_init_debug(sc) < 0)
1264                 printk(KERN_ERR "Unable to create debugfs files\n");
1265
1266         spin_lock_init(&sc->sc_resetlock);
1267         tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1268         tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
1269                      (unsigned long)sc);
1270
1271         /*
1272          * Cache line size is used to size and align various
1273          * structures used to communicate with the hardware.
1274          */
1275         bus_read_cachesize(sc, &csz);
1276         /* XXX assert csz is non-zero */
1277         sc->sc_cachelsz = csz << 2;     /* convert to bytes */
1278
1279         ah = ath9k_hw_attach(devid, sc, sc->mem, &status);
1280         if (ah == NULL) {
1281                 DPRINTF(sc, ATH_DBG_FATAL,
1282                         "Unable to attach hardware; HAL status %u\n", status);
1283                 error = -ENXIO;
1284                 goto bad;
1285         }
1286         sc->sc_ah = ah;
1287
1288         /* Get the hardware key cache size. */
1289         sc->sc_keymax = ah->ah_caps.keycache_size;
1290         if (sc->sc_keymax > ATH_KEYMAX) {
1291                 DPRINTF(sc, ATH_DBG_KEYCACHE,
1292                         "Warning, using only %u entries in %u key cache\n",
1293                         ATH_KEYMAX, sc->sc_keymax);
1294                 sc->sc_keymax = ATH_KEYMAX;
1295         }
1296
1297         /*
1298          * Reset the key cache since some parts do not
1299          * reset the contents on initial power up.
1300          */
1301         for (i = 0; i < sc->sc_keymax; i++)
1302                 ath9k_hw_keyreset(ah, (u16) i);
1303         /*
1304          * Mark key cache slots associated with global keys
1305          * as in use.  If we knew TKIP was not to be used we
1306          * could leave the +32, +64, and +32+64 slots free.
1307          * XXX only for splitmic.
1308          */
1309         for (i = 0; i < IEEE80211_WEP_NKID; i++) {
1310                 set_bit(i, sc->sc_keymap);
1311                 set_bit(i + 32, sc->sc_keymap);
1312                 set_bit(i + 64, sc->sc_keymap);
1313                 set_bit(i + 32 + 64, sc->sc_keymap);
1314         }
1315
1316         /* Collect the channel list using the default country code */
1317
1318         error = ath_setup_channels(sc);
1319         if (error)
1320                 goto bad;
1321
1322         /* default to MONITOR mode */
1323         sc->sc_ah->ah_opmode = NL80211_IFTYPE_MONITOR;
1324
1325
1326         /* Setup rate tables */
1327
1328         ath_rate_attach(sc);
1329         ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1330         ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1331
1332         /*
1333          * Allocate hardware transmit queues: one queue for
1334          * beacon frames and one data queue for each QoS
1335          * priority.  Note that the hal handles reseting
1336          * these queues at the needed time.
1337          */
1338         sc->beacon.beaconq = ath_beaconq_setup(ah);
1339         if (sc->beacon.beaconq == -1) {
1340                 DPRINTF(sc, ATH_DBG_FATAL,
1341                         "Unable to setup a beacon xmit queue\n");
1342                 error = -EIO;
1343                 goto bad2;
1344         }
1345         sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1346         if (sc->beacon.cabq == NULL) {
1347                 DPRINTF(sc, ATH_DBG_FATAL,
1348                         "Unable to setup CAB xmit queue\n");
1349                 error = -EIO;
1350                 goto bad2;
1351         }
1352
1353         sc->sc_config.cabqReadytime = ATH_CABQ_READY_TIME;
1354         ath_cabq_update(sc);
1355
1356         for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1357                 sc->tx.hwq_map[i] = -1;
1358
1359         /* Setup data queues */
1360         /* NB: ensure BK queue is the lowest priority h/w queue */
1361         if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1362                 DPRINTF(sc, ATH_DBG_FATAL,
1363                         "Unable to setup xmit queue for BK traffic\n");
1364                 error = -EIO;
1365                 goto bad2;
1366         }
1367
1368         if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1369                 DPRINTF(sc, ATH_DBG_FATAL,
1370                         "Unable to setup xmit queue for BE traffic\n");
1371                 error = -EIO;
1372                 goto bad2;
1373         }
1374         if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1375                 DPRINTF(sc, ATH_DBG_FATAL,
1376                         "Unable to setup xmit queue for VI traffic\n");
1377                 error = -EIO;
1378                 goto bad2;
1379         }
1380         if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1381                 DPRINTF(sc, ATH_DBG_FATAL,
1382                         "Unable to setup xmit queue for VO traffic\n");
1383                 error = -EIO;
1384                 goto bad2;
1385         }
1386
1387         /* Initializes the noise floor to a reasonable default value.
1388          * Later on this will be updated during ANI processing. */
1389
1390         sc->sc_ani.sc_noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1391         setup_timer(&sc->sc_ani.timer, ath_ani_calibrate, (unsigned long)sc);
1392
1393         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1394                                    ATH9K_CIPHER_TKIP, NULL)) {
1395                 /*
1396                  * Whether we should enable h/w TKIP MIC.
1397                  * XXX: if we don't support WME TKIP MIC, then we wouldn't
1398                  * report WMM capable, so it's always safe to turn on
1399                  * TKIP MIC in this case.
1400                  */
1401                 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1402                                        0, 1, NULL);
1403         }
1404
1405         /*
1406          * Check whether the separate key cache entries
1407          * are required to handle both tx+rx MIC keys.
1408          * With split mic keys the number of stations is limited
1409          * to 27 otherwise 59.
1410          */
1411         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1412                                    ATH9K_CIPHER_TKIP, NULL)
1413             && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1414                                       ATH9K_CIPHER_MIC, NULL)
1415             && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1416                                       0, NULL))
1417                 sc->sc_splitmic = 1;
1418
1419         /* turn on mcast key search if possible */
1420         if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1421                 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1422                                              1, NULL);
1423
1424         sc->sc_config.txpowlimit = ATH_TXPOWER_MAX;
1425         sc->sc_config.txpowlimit_override = 0;
1426
1427         /* 11n Capabilities */
1428         if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1429                 sc->sc_flags |= SC_OP_TXAGGR;
1430                 sc->sc_flags |= SC_OP_RXAGGR;
1431         }
1432
1433         sc->sc_tx_chainmask = ah->ah_caps.tx_chainmask;
1434         sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask;
1435
1436         ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1437         sc->rx.defant = ath9k_hw_getdefantenna(ah);
1438
1439         ath9k_hw_getmac(ah, sc->sc_myaddr);
1440         if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) {
1441                 ath9k_hw_getbssidmask(ah, sc->sc_bssidmask);
1442                 ATH_SET_VAP_BSSID_MASK(sc->sc_bssidmask);
1443                 ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
1444         }
1445
1446         sc->beacon.slottime = ATH9K_SLOT_TIME_9;        /* default to short slot time */
1447
1448         /* initialize beacon slots */
1449         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
1450                 sc->beacon.bslot[i] = ATH_IF_ID_ANY;
1451
1452         /* save MISC configurations */
1453         sc->sc_config.swBeaconProcess = 1;
1454
1455         /* setup channels and rates */
1456
1457         sc->sbands[IEEE80211_BAND_2GHZ].channels =
1458                 sc->channels[IEEE80211_BAND_2GHZ];
1459         sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1460                 sc->rates[IEEE80211_BAND_2GHZ];
1461         sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1462
1463         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) {
1464                 sc->sbands[IEEE80211_BAND_5GHZ].channels =
1465                         sc->channels[IEEE80211_BAND_5GHZ];
1466                 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1467                         sc->rates[IEEE80211_BAND_5GHZ];
1468                 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1469         }
1470
1471         return 0;
1472 bad2:
1473         /* cleanup tx queues */
1474         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1475                 if (ATH_TXQ_SETUP(sc, i))
1476                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1477 bad:
1478         if (ah)
1479                 ath9k_hw_detach(ah);
1480
1481         return error;
1482 }
1483
1484 static int ath_attach(u16 devid, struct ath_softc *sc)
1485 {
1486         struct ieee80211_hw *hw = sc->hw;
1487         int error = 0;
1488
1489         DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1490
1491         error = ath_init(devid, sc);
1492         if (error != 0)
1493                 return error;
1494
1495         /* get mac address from hardware and set in mac80211 */
1496
1497         SET_IEEE80211_PERM_ADDR(hw, sc->sc_myaddr);
1498
1499         hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1500                 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1501                 IEEE80211_HW_SIGNAL_DBM |
1502                 IEEE80211_HW_AMPDU_AGGREGATION;
1503
1504         hw->wiphy->interface_modes =
1505                 BIT(NL80211_IFTYPE_AP) |
1506                 BIT(NL80211_IFTYPE_STATION) |
1507                 BIT(NL80211_IFTYPE_ADHOC);
1508
1509         hw->queues = 4;
1510         hw->max_rates = 4;
1511         hw->max_rate_tries = ATH_11N_TXMAXTRY;
1512         hw->sta_data_size = sizeof(struct ath_node);
1513         hw->vif_data_size = sizeof(struct ath_vap);
1514
1515         /* Register rate control */
1516         hw->rate_control_algorithm = "ath9k_rate_control";
1517         error = ath_rate_control_register();
1518         if (error != 0) {
1519                 DPRINTF(sc, ATH_DBG_FATAL,
1520                         "Unable to register rate control algorithm: %d\n", error);
1521                 ath_rate_control_unregister();
1522                 goto bad;
1523         }
1524
1525         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1526                 setup_ht_cap(&sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1527                 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1528                         setup_ht_cap(&sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1529         }
1530
1531         hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &sc->sbands[IEEE80211_BAND_2GHZ];
1532         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1533                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1534                         &sc->sbands[IEEE80211_BAND_5GHZ];
1535
1536         /* initialize tx/rx engine */
1537         error = ath_tx_init(sc, ATH_TXBUF);
1538         if (error != 0)
1539                 goto detach;
1540
1541         error = ath_rx_init(sc, ATH_RXBUF);
1542         if (error != 0)
1543                 goto detach;
1544
1545 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1546         /* Initialze h/w Rfkill */
1547         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1548                 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1549
1550         /* Initialize s/w rfkill */
1551         if (ath_init_sw_rfkill(sc))
1552                 goto detach;
1553 #endif
1554
1555         error = ieee80211_register_hw(hw);
1556         if (error != 0) {
1557                 ath_rate_control_unregister();
1558                 goto bad;
1559         }
1560
1561         /* Initialize LED control */
1562         ath_init_leds(sc);
1563
1564         return 0;
1565 detach:
1566         ath_detach(sc);
1567 bad:
1568         return error;
1569 }
1570
1571 int ath_reset(struct ath_softc *sc, bool retry_tx)
1572 {
1573         struct ath_hal *ah = sc->sc_ah;
1574         int status;
1575         int error = 0;
1576
1577         ath9k_hw_set_interrupts(ah, 0);
1578         ath_draintxq(sc, retry_tx);
1579         ath_stoprecv(sc);
1580         ath_flushrecv(sc);
1581
1582         spin_lock_bh(&sc->sc_resetlock);
1583         if (!ath9k_hw_reset(ah, sc->sc_ah->ah_curchan,
1584                             sc->tx_chan_width,
1585                             sc->sc_tx_chainmask, sc->sc_rx_chainmask,
1586                             sc->sc_ht_extprotspacing, false, &status)) {
1587                 DPRINTF(sc, ATH_DBG_FATAL,
1588                         "Unable to reset hardware; hal status %u\n", status);
1589                 error = -EIO;
1590         }
1591         spin_unlock_bh(&sc->sc_resetlock);
1592
1593         if (ath_startrecv(sc) != 0)
1594                 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1595
1596         /*
1597          * We may be doing a reset in response to a request
1598          * that changes the channel so update any state that
1599          * might change as a result.
1600          */
1601         ath_setcurmode(sc, ath_chan2mode(sc->sc_ah->ah_curchan));
1602
1603         ath_update_txpow(sc);
1604
1605         if (sc->sc_flags & SC_OP_BEACONS)
1606                 ath_beacon_config(sc, ATH_IF_ID_ANY);   /* restart beacons */
1607
1608         ath9k_hw_set_interrupts(ah, sc->sc_imask);
1609
1610         if (retry_tx) {
1611                 int i;
1612                 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1613                         if (ATH_TXQ_SETUP(sc, i)) {
1614                                 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1615                                 ath_txq_schedule(sc, &sc->tx.txq[i]);
1616                                 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
1617                         }
1618                 }
1619         }
1620
1621         return error;
1622 }
1623
1624 /*
1625  *  This function will allocate both the DMA descriptor structure, and the
1626  *  buffers it contains.  These are used to contain the descriptors used
1627  *  by the system.
1628 */
1629 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1630                       struct list_head *head, const char *name,
1631                       int nbuf, int ndesc)
1632 {
1633 #define DS2PHYS(_dd, _ds)                                               \
1634         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1635 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1636 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1637
1638         struct ath_desc *ds;
1639         struct ath_buf *bf;
1640         int i, bsize, error;
1641
1642         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1643                 name, nbuf, ndesc);
1644
1645         /* ath_desc must be a multiple of DWORDs */
1646         if ((sizeof(struct ath_desc) % 4) != 0) {
1647                 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
1648                 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1649                 error = -ENOMEM;
1650                 goto fail;
1651         }
1652
1653         dd->dd_name = name;
1654         dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1655
1656         /*
1657          * Need additional DMA memory because we can't use
1658          * descriptors that cross the 4K page boundary. Assume
1659          * one skipped descriptor per 4K page.
1660          */
1661         if (!(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1662                 u32 ndesc_skipped =
1663                         ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1664                 u32 dma_len;
1665
1666                 while (ndesc_skipped) {
1667                         dma_len = ndesc_skipped * sizeof(struct ath_desc);
1668                         dd->dd_desc_len += dma_len;
1669
1670                         ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1671                 };
1672         }
1673
1674         /* allocate descriptors */
1675         dd->dd_desc = pci_alloc_consistent(sc->pdev,
1676                               dd->dd_desc_len,
1677                               &dd->dd_desc_paddr);
1678         if (dd->dd_desc == NULL) {
1679                 error = -ENOMEM;
1680                 goto fail;
1681         }
1682         ds = dd->dd_desc;
1683         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1684                 dd->dd_name, ds, (u32) dd->dd_desc_len,
1685                 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1686
1687         /* allocate buffers */
1688         bsize = sizeof(struct ath_buf) * nbuf;
1689         bf = kmalloc(bsize, GFP_KERNEL);
1690         if (bf == NULL) {
1691                 error = -ENOMEM;
1692                 goto fail2;
1693         }
1694         memset(bf, 0, bsize);
1695         dd->dd_bufptr = bf;
1696
1697         INIT_LIST_HEAD(head);
1698         for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1699                 bf->bf_desc = ds;
1700                 bf->bf_daddr = DS2PHYS(dd, ds);
1701
1702                 if (!(sc->sc_ah->ah_caps.hw_caps &
1703                       ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1704                         /*
1705                          * Skip descriptor addresses which can cause 4KB
1706                          * boundary crossing (addr + length) with a 32 dword
1707                          * descriptor fetch.
1708                          */
1709                         while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1710                                 ASSERT((caddr_t) bf->bf_desc <
1711                                        ((caddr_t) dd->dd_desc +
1712                                         dd->dd_desc_len));
1713
1714                                 ds += ndesc;
1715                                 bf->bf_desc = ds;
1716                                 bf->bf_daddr = DS2PHYS(dd, ds);
1717                         }
1718                 }
1719                 list_add_tail(&bf->list, head);
1720         }
1721         return 0;
1722 fail2:
1723         pci_free_consistent(sc->pdev,
1724                 dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr);
1725 fail:
1726         memset(dd, 0, sizeof(*dd));
1727         return error;
1728 #undef ATH_DESC_4KB_BOUND_CHECK
1729 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1730 #undef DS2PHYS
1731 }
1732
1733 void ath_descdma_cleanup(struct ath_softc *sc,
1734                          struct ath_descdma *dd,
1735                          struct list_head *head)
1736 {
1737         pci_free_consistent(sc->pdev,
1738                 dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr);
1739
1740         INIT_LIST_HEAD(head);
1741         kfree(dd->dd_bufptr);
1742         memset(dd, 0, sizeof(*dd));
1743 }
1744
1745 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1746 {
1747         int qnum;
1748
1749         switch (queue) {
1750         case 0:
1751                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
1752                 break;
1753         case 1:
1754                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
1755                 break;
1756         case 2:
1757                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1758                 break;
1759         case 3:
1760                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
1761                 break;
1762         default:
1763                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1764                 break;
1765         }
1766
1767         return qnum;
1768 }
1769
1770 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1771 {
1772         int qnum;
1773
1774         switch (queue) {
1775         case ATH9K_WME_AC_VO:
1776                 qnum = 0;
1777                 break;
1778         case ATH9K_WME_AC_VI:
1779                 qnum = 1;
1780                 break;
1781         case ATH9K_WME_AC_BE:
1782                 qnum = 2;
1783                 break;
1784         case ATH9K_WME_AC_BK:
1785                 qnum = 3;
1786                 break;
1787         default:
1788                 qnum = -1;
1789                 break;
1790         }
1791
1792         return qnum;
1793 }
1794
1795 /**********************/
1796 /* mac80211 callbacks */
1797 /**********************/
1798
1799 static int ath9k_start(struct ieee80211_hw *hw)
1800 {
1801         struct ath_softc *sc = hw->priv;
1802         struct ieee80211_channel *curchan = hw->conf.channel;
1803         struct ath9k_channel *init_channel;
1804         int error = 0, pos, status;
1805
1806         DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1807                 "initial channel: %d MHz\n", curchan->center_freq);
1808
1809         /* setup initial channel */
1810
1811         pos = ath_get_channel(sc, curchan);
1812         if (pos == -1) {
1813                 DPRINTF(sc, ATH_DBG_FATAL, "Invalid channel: %d\n", curchan->center_freq);
1814                 error = -EINVAL;
1815                 goto error;
1816         }
1817
1818         sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1819         sc->sc_ah->ah_channels[pos].chanmode =
1820                 (curchan->band == IEEE80211_BAND_2GHZ) ? CHANNEL_G : CHANNEL_A;
1821         init_channel = &sc->sc_ah->ah_channels[pos];
1822
1823         /* Reset SERDES registers */
1824         ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1825
1826         /*
1827          * The basic interface to setting the hardware in a good
1828          * state is ``reset''.  On return the hardware is known to
1829          * be powered up and with interrupts disabled.  This must
1830          * be followed by initialization of the appropriate bits
1831          * and then setup of the interrupt mask.
1832          */
1833         spin_lock_bh(&sc->sc_resetlock);
1834         if (!ath9k_hw_reset(sc->sc_ah, init_channel,
1835                             sc->tx_chan_width,
1836                             sc->sc_tx_chainmask, sc->sc_rx_chainmask,
1837                             sc->sc_ht_extprotspacing, false, &status)) {
1838                 DPRINTF(sc, ATH_DBG_FATAL,
1839                         "Unable to reset hardware; hal status %u "
1840                         "(freq %u flags 0x%x)\n", status,
1841                         init_channel->channel, init_channel->channelFlags);
1842                 error = -EIO;
1843                 spin_unlock_bh(&sc->sc_resetlock);
1844                 goto error;
1845         }
1846         spin_unlock_bh(&sc->sc_resetlock);
1847
1848         /*
1849          * This is needed only to setup initial state
1850          * but it's best done after a reset.
1851          */
1852         ath_update_txpow(sc);
1853
1854         /*
1855          * Setup the hardware after reset:
1856          * The receive engine is set going.
1857          * Frame transmit is handled entirely
1858          * in the frame output path; there's nothing to do
1859          * here except setup the interrupt mask.
1860          */
1861         if (ath_startrecv(sc) != 0) {
1862                 DPRINTF(sc, ATH_DBG_FATAL,
1863                         "Unable to start recv logic\n");
1864                 error = -EIO;
1865                 goto error;
1866         }
1867
1868         /* Setup our intr mask. */
1869         sc->sc_imask = ATH9K_INT_RX | ATH9K_INT_TX
1870                 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1871                 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1872
1873         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_GTT)
1874                 sc->sc_imask |= ATH9K_INT_GTT;
1875
1876         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
1877                 sc->sc_imask |= ATH9K_INT_CST;
1878
1879         /*
1880          * Enable MIB interrupts when there are hardware phy counters.
1881          * Note we only do this (at the moment) for station mode.
1882          */
1883         if (ath9k_hw_phycounters(sc->sc_ah) &&
1884             ((sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) ||
1885              (sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC)))
1886                 sc->sc_imask |= ATH9K_INT_MIB;
1887         /*
1888          * Some hardware processes the TIM IE and fires an
1889          * interrupt when the TIM bit is set.  For hardware
1890          * that does, if not overridden by configuration,
1891          * enable the TIM interrupt when operating as station.
1892          */
1893         if ((sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
1894             (sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) &&
1895             !sc->sc_config.swBeaconProcess)
1896                 sc->sc_imask |= ATH9K_INT_TIM;
1897
1898         ath_setcurmode(sc, ath_chan2mode(init_channel));
1899
1900         sc->sc_flags &= ~SC_OP_INVALID;
1901
1902         /* Disable BMISS interrupt when we're not associated */
1903         sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1904         ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
1905
1906         ieee80211_wake_queues(sc->hw);
1907
1908 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1909         error = ath_start_rfkill_poll(sc);
1910 #endif
1911
1912 error:
1913         return error;
1914 }
1915
1916 static int ath9k_tx(struct ieee80211_hw *hw,
1917                     struct sk_buff *skb)
1918 {
1919         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1920         struct ath_softc *sc = hw->priv;
1921         struct ath_tx_control txctl;
1922         int hdrlen, padsize;
1923
1924         memset(&txctl, 0, sizeof(struct ath_tx_control));
1925
1926         /*
1927          * As a temporary workaround, assign seq# here; this will likely need
1928          * to be cleaned up to work better with Beacon transmission and virtual
1929          * BSSes.
1930          */
1931         if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1932                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1933                 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1934                         sc->tx.seq_no += 0x10;
1935                 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1936                 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1937         }
1938
1939         /* Add the padding after the header if this is not already done */
1940         hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1941         if (hdrlen & 3) {
1942                 padsize = hdrlen % 4;
1943                 if (skb_headroom(skb) < padsize)
1944                         return -1;
1945                 skb_push(skb, padsize);
1946                 memmove(skb->data, skb->data + padsize, hdrlen);
1947         }
1948
1949         /* Check if a tx queue is available */
1950
1951         txctl.txq = ath_test_get_txq(sc, skb);
1952         if (!txctl.txq)
1953                 goto exit;
1954
1955         DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
1956
1957         if (ath_tx_start(sc, skb, &txctl) != 0) {
1958                 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
1959                 goto exit;
1960         }
1961
1962         return 0;
1963 exit:
1964         dev_kfree_skb_any(skb);
1965         return 0;
1966 }
1967
1968 static void ath9k_stop(struct ieee80211_hw *hw)
1969 {
1970         struct ath_softc *sc = hw->priv;
1971
1972         if (sc->sc_flags & SC_OP_INVALID) {
1973                 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
1974                 return;
1975         }
1976
1977         DPRINTF(sc, ATH_DBG_CONFIG, "Cleaning up\n");
1978
1979         ieee80211_stop_queues(sc->hw);
1980
1981         /* make sure h/w will not generate any interrupt
1982          * before setting the invalid flag. */
1983         ath9k_hw_set_interrupts(sc->sc_ah, 0);
1984
1985         if (!(sc->sc_flags & SC_OP_INVALID)) {
1986                 ath_draintxq(sc, false);
1987                 ath_stoprecv(sc);
1988                 ath9k_hw_phy_disable(sc->sc_ah);
1989         } else
1990                 sc->rx.rxlink = NULL;
1991
1992 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1993         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1994                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1995 #endif
1996         /* disable HAL and put h/w to sleep */
1997         ath9k_hw_disable(sc->sc_ah);
1998         ath9k_hw_configpcipowersave(sc->sc_ah, 1);
1999
2000         sc->sc_flags |= SC_OP_INVALID;
2001
2002         DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
2003 }
2004
2005 static int ath9k_add_interface(struct ieee80211_hw *hw,
2006                                struct ieee80211_if_init_conf *conf)
2007 {
2008         struct ath_softc *sc = hw->priv;
2009         struct ath_vap *avp = (void *)conf->vif->drv_priv;
2010         enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2011
2012         /* Support only vap for now */
2013
2014         if (sc->sc_nvaps)
2015                 return -ENOBUFS;
2016
2017         switch (conf->type) {
2018         case NL80211_IFTYPE_STATION:
2019                 ic_opmode = NL80211_IFTYPE_STATION;
2020                 break;
2021         case NL80211_IFTYPE_ADHOC:
2022                 ic_opmode = NL80211_IFTYPE_ADHOC;
2023                 break;
2024         case NL80211_IFTYPE_AP:
2025                 ic_opmode = NL80211_IFTYPE_AP;
2026                 break;
2027         default:
2028                 DPRINTF(sc, ATH_DBG_FATAL,
2029                         "Interface type %d not yet supported\n", conf->type);
2030                 return -EOPNOTSUPP;
2031         }
2032
2033         DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VAP of type: %d\n", ic_opmode);
2034
2035         /* Set the VAP opmode */
2036         avp->av_opmode = ic_opmode;
2037         avp->av_bslot = -1;
2038
2039         if (ic_opmode == NL80211_IFTYPE_AP)
2040                 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2041
2042         sc->sc_vaps[0] = conf->vif;
2043         sc->sc_nvaps++;
2044
2045         /* Set the device opmode */
2046         sc->sc_ah->ah_opmode = ic_opmode;
2047
2048         if (conf->type == NL80211_IFTYPE_AP) {
2049                 /* TODO: is this a suitable place to start ANI for AP mode? */
2050                 /* Start ANI */
2051                 mod_timer(&sc->sc_ani.timer,
2052                           jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2053         }
2054
2055         return 0;
2056 }
2057
2058 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2059                                    struct ieee80211_if_init_conf *conf)
2060 {
2061         struct ath_softc *sc = hw->priv;
2062         struct ath_vap *avp = (void *)conf->vif->drv_priv;
2063
2064         DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
2065
2066         /* Stop ANI */
2067         del_timer_sync(&sc->sc_ani.timer);
2068
2069         /* Reclaim beacon resources */
2070         if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP ||
2071             sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC) {
2072                 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2073                 ath_beacon_return(sc, avp);
2074         }
2075
2076         sc->sc_flags &= ~SC_OP_BEACONS;
2077
2078         sc->sc_vaps[0] = NULL;
2079         sc->sc_nvaps--;
2080 }
2081
2082 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2083 {
2084         struct ath_softc *sc = hw->priv;
2085         struct ieee80211_conf *conf = &hw->conf;
2086
2087         if (changed & (IEEE80211_CONF_CHANGE_CHANNEL |
2088                        IEEE80211_CONF_CHANGE_HT)) {
2089                 struct ieee80211_channel *curchan = hw->conf.channel;
2090                 int pos;
2091
2092                 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2093                         curchan->center_freq);
2094
2095                 pos = ath_get_channel(sc, curchan);
2096                 if (pos == -1) {
2097                         DPRINTF(sc, ATH_DBG_FATAL, "Invalid channel: %d\n",
2098                                 curchan->center_freq);
2099                         return -EINVAL;
2100                 }
2101
2102                 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
2103                 sc->sc_ah->ah_channels[pos].chanmode =
2104                         (curchan->band == IEEE80211_BAND_2GHZ) ?
2105                         CHANNEL_G : CHANNEL_A;
2106
2107                 if (conf->ht.enabled) {
2108                         if (conf->ht.channel_type == NL80211_CHAN_HT40PLUS ||
2109                             conf->ht.channel_type == NL80211_CHAN_HT40MINUS)
2110                                 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
2111
2112                         sc->sc_ah->ah_channels[pos].chanmode =
2113                                 ath_get_extchanmode(sc, curchan,
2114                                                     conf->ht.channel_type);
2115                 }
2116
2117                 if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0) {
2118                         DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
2119                         return -EINVAL;
2120                 }
2121
2122                 ath_update_chainmask(sc, conf->ht.enabled);
2123         }
2124
2125         if (changed & IEEE80211_CONF_CHANGE_POWER)
2126                 sc->sc_config.txpowlimit = 2 * conf->power_level;
2127
2128         return 0;
2129 }
2130
2131 static int ath9k_config_interface(struct ieee80211_hw *hw,
2132                                   struct ieee80211_vif *vif,
2133                                   struct ieee80211_if_conf *conf)
2134 {
2135         struct ath_softc *sc = hw->priv;
2136         struct ath_hal *ah = sc->sc_ah;
2137         struct ath_vap *avp = (void *)vif->drv_priv;
2138         u32 rfilt = 0;
2139         int error, i;
2140
2141         /* TODO: Need to decide which hw opmode to use for multi-interface
2142          * cases */
2143         if (vif->type == NL80211_IFTYPE_AP &&
2144             ah->ah_opmode != NL80211_IFTYPE_AP) {
2145                 ah->ah_opmode = NL80211_IFTYPE_STATION;
2146                 ath9k_hw_setopmode(ah);
2147                 ath9k_hw_write_associd(ah, sc->sc_myaddr, 0);
2148                 /* Request full reset to get hw opmode changed properly */
2149                 sc->sc_flags |= SC_OP_FULL_RESET;
2150         }
2151
2152         if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2153             !is_zero_ether_addr(conf->bssid)) {
2154                 switch (vif->type) {
2155                 case NL80211_IFTYPE_STATION:
2156                 case NL80211_IFTYPE_ADHOC:
2157                         /* Set BSSID */
2158                         memcpy(sc->sc_curbssid, conf->bssid, ETH_ALEN);
2159                         sc->sc_curaid = 0;
2160                         ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
2161                                                sc->sc_curaid);
2162
2163                         /* Set aggregation protection mode parameters */
2164                         sc->sc_config.ath_aggr_prot = 0;
2165
2166                         DPRINTF(sc, ATH_DBG_CONFIG,
2167                                 "RX filter 0x%x bssid %pM aid 0x%x\n",
2168                                 rfilt, sc->sc_curbssid, sc->sc_curaid);
2169
2170                         /* need to reconfigure the beacon */
2171                         sc->sc_flags &= ~SC_OP_BEACONS ;
2172
2173                         break;
2174                 default:
2175                         break;
2176                 }
2177         }
2178
2179         if ((conf->changed & IEEE80211_IFCC_BEACON) &&
2180             ((vif->type == NL80211_IFTYPE_ADHOC) ||
2181              (vif->type == NL80211_IFTYPE_AP))) {
2182                 /*
2183                  * Allocate and setup the beacon frame.
2184                  *
2185                  * Stop any previous beacon DMA.  This may be
2186                  * necessary, for example, when an ibss merge
2187                  * causes reconfiguration; we may be called
2188                  * with beacon transmission active.
2189                  */
2190                 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2191
2192                 error = ath_beacon_alloc(sc, 0);
2193                 if (error != 0)
2194                         return error;
2195
2196                 ath_beacon_sync(sc, 0);
2197         }
2198
2199         /* Check for WLAN_CAPABILITY_PRIVACY ? */
2200         if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2201                 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2202                         if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2203                                 ath9k_hw_keysetmac(sc->sc_ah,
2204                                                    (u16)i,
2205                                                    sc->sc_curbssid);
2206         }
2207
2208         /* Only legacy IBSS for now */
2209         if (vif->type == NL80211_IFTYPE_ADHOC)
2210                 ath_update_chainmask(sc, 0);
2211
2212         return 0;
2213 }
2214
2215 #define SUPPORTED_FILTERS                       \
2216         (FIF_PROMISC_IN_BSS |                   \
2217         FIF_ALLMULTI |                          \
2218         FIF_CONTROL |                           \
2219         FIF_OTHER_BSS |                         \
2220         FIF_BCN_PRBRESP_PROMISC |               \
2221         FIF_FCSFAIL)
2222
2223 /* FIXME: sc->sc_full_reset ? */
2224 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2225                                    unsigned int changed_flags,
2226                                    unsigned int *total_flags,
2227                                    int mc_count,
2228                                    struct dev_mc_list *mclist)
2229 {
2230         struct ath_softc *sc = hw->priv;
2231         u32 rfilt;
2232
2233         changed_flags &= SUPPORTED_FILTERS;
2234         *total_flags &= SUPPORTED_FILTERS;
2235
2236         sc->rx.rxfilter = *total_flags;
2237         rfilt = ath_calcrxfilter(sc);
2238         ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2239
2240         if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
2241                 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
2242                         ath9k_hw_write_associd(sc->sc_ah, ath_bcast_mac, 0);
2243         }
2244
2245         DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
2246 }
2247
2248 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2249                              struct ieee80211_vif *vif,
2250                              enum sta_notify_cmd cmd,
2251                              struct ieee80211_sta *sta)
2252 {
2253         struct ath_softc *sc = hw->priv;
2254
2255         switch (cmd) {
2256         case STA_NOTIFY_ADD:
2257                 ath_node_attach(sc, sta);
2258                 break;
2259         case STA_NOTIFY_REMOVE:
2260                 ath_node_detach(sc, sta);
2261                 break;
2262         default:
2263                 break;
2264         }
2265 }
2266
2267 static int ath9k_conf_tx(struct ieee80211_hw *hw,
2268                          u16 queue,
2269                          const struct ieee80211_tx_queue_params *params)
2270 {
2271         struct ath_softc *sc = hw->priv;
2272         struct ath9k_tx_queue_info qi;
2273         int ret = 0, qnum;
2274
2275         if (queue >= WME_NUM_AC)
2276                 return 0;
2277
2278         qi.tqi_aifs = params->aifs;
2279         qi.tqi_cwmin = params->cw_min;
2280         qi.tqi_cwmax = params->cw_max;
2281         qi.tqi_burstTime = params->txop;
2282         qnum = ath_get_hal_qnum(queue, sc);
2283
2284         DPRINTF(sc, ATH_DBG_CONFIG,
2285                 "Configure tx [queue/halq] [%d/%d],  "
2286                 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2287                 queue, qnum, params->aifs, params->cw_min,
2288                 params->cw_max, params->txop);
2289
2290         ret = ath_txq_update(sc, qnum, &qi);
2291         if (ret)
2292                 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
2293
2294         return ret;
2295 }
2296
2297 static int ath9k_set_key(struct ieee80211_hw *hw,
2298                          enum set_key_cmd cmd,
2299                          const u8 *local_addr,
2300                          const u8 *addr,
2301                          struct ieee80211_key_conf *key)
2302 {
2303         struct ath_softc *sc = hw->priv;
2304         int ret = 0;
2305
2306         DPRINTF(sc, ATH_DBG_KEYCACHE, "Set HW Key\n");
2307
2308         switch (cmd) {
2309         case SET_KEY:
2310                 ret = ath_key_config(sc, addr, key);
2311                 if (!ret) {
2312                         set_bit(key->keyidx, sc->sc_keymap);
2313                         key->hw_key_idx = key->keyidx;
2314                         /* push IV and Michael MIC generation to stack */
2315                         key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2316                         if (key->alg == ALG_TKIP)
2317                                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2318                 }
2319                 break;
2320         case DISABLE_KEY:
2321                 ath_key_delete(sc, key);
2322                 clear_bit(key->keyidx, sc->sc_keymap);
2323                 break;
2324         default:
2325                 ret = -EINVAL;
2326         }
2327
2328         return ret;
2329 }
2330
2331 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2332                                    struct ieee80211_vif *vif,
2333                                    struct ieee80211_bss_conf *bss_conf,
2334                                    u32 changed)
2335 {
2336         struct ath_softc *sc = hw->priv;
2337
2338         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2339                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2340                         bss_conf->use_short_preamble);
2341                 if (bss_conf->use_short_preamble)
2342                         sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2343                 else
2344                         sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2345         }
2346
2347         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2348                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2349                         bss_conf->use_cts_prot);
2350                 if (bss_conf->use_cts_prot &&
2351                     hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2352                         sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2353                 else
2354                         sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2355         }
2356
2357         if (changed & BSS_CHANGED_ASSOC) {
2358                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2359                         bss_conf->assoc);
2360                 ath9k_bss_assoc_info(sc, vif, bss_conf);
2361         }
2362 }
2363
2364 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2365 {
2366         u64 tsf;
2367         struct ath_softc *sc = hw->priv;
2368         struct ath_hal *ah = sc->sc_ah;
2369
2370         tsf = ath9k_hw_gettsf64(ah);
2371
2372         return tsf;
2373 }
2374
2375 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2376 {
2377         struct ath_softc *sc = hw->priv;
2378         struct ath_hal *ah = sc->sc_ah;
2379
2380         ath9k_hw_reset_tsf(ah);
2381 }
2382
2383 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2384                        enum ieee80211_ampdu_mlme_action action,
2385                        struct ieee80211_sta *sta,
2386                        u16 tid, u16 *ssn)
2387 {
2388         struct ath_softc *sc = hw->priv;
2389         int ret = 0;
2390
2391         switch (action) {
2392         case IEEE80211_AMPDU_RX_START:
2393                 if (!(sc->sc_flags & SC_OP_RXAGGR))
2394                         ret = -ENOTSUPP;
2395                 break;
2396         case IEEE80211_AMPDU_RX_STOP:
2397                 break;
2398         case IEEE80211_AMPDU_TX_START:
2399                 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2400                 if (ret < 0)
2401                         DPRINTF(sc, ATH_DBG_FATAL,
2402                                 "Unable to start TX aggregation\n");
2403                 else
2404                         ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2405                 break;
2406         case IEEE80211_AMPDU_TX_STOP:
2407                 ret = ath_tx_aggr_stop(sc, sta, tid);
2408                 if (ret < 0)
2409                         DPRINTF(sc, ATH_DBG_FATAL,
2410                                 "Unable to stop TX aggregation\n");
2411
2412                 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2413                 break;
2414         case IEEE80211_AMPDU_TX_RESUME:
2415                 ath_tx_aggr_resume(sc, sta, tid);
2416                 break;
2417         default:
2418                 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
2419         }
2420
2421         return ret;
2422 }
2423
2424 static struct ieee80211_ops ath9k_ops = {
2425         .tx                 = ath9k_tx,
2426         .start              = ath9k_start,
2427         .stop               = ath9k_stop,
2428         .add_interface      = ath9k_add_interface,
2429         .remove_interface   = ath9k_remove_interface,
2430         .config             = ath9k_config,
2431         .config_interface   = ath9k_config_interface,
2432         .configure_filter   = ath9k_configure_filter,
2433         .sta_notify         = ath9k_sta_notify,
2434         .conf_tx            = ath9k_conf_tx,
2435         .bss_info_changed   = ath9k_bss_info_changed,
2436         .set_key            = ath9k_set_key,
2437         .get_tsf            = ath9k_get_tsf,
2438         .reset_tsf          = ath9k_reset_tsf,
2439         .ampdu_action       = ath9k_ampdu_action,
2440 };
2441
2442 static struct {
2443         u32 version;
2444         const char * name;
2445 } ath_mac_bb_names[] = {
2446         { AR_SREV_VERSION_5416_PCI,     "5416" },
2447         { AR_SREV_VERSION_5416_PCIE,    "5418" },
2448         { AR_SREV_VERSION_9100,         "9100" },
2449         { AR_SREV_VERSION_9160,         "9160" },
2450         { AR_SREV_VERSION_9280,         "9280" },
2451         { AR_SREV_VERSION_9285,         "9285" }
2452 };
2453
2454 static struct {
2455         u16 version;
2456         const char * name;
2457 } ath_rf_names[] = {
2458         { 0,                            "5133" },
2459         { AR_RAD5133_SREV_MAJOR,        "5133" },
2460         { AR_RAD5122_SREV_MAJOR,        "5122" },
2461         { AR_RAD2133_SREV_MAJOR,        "2133" },
2462         { AR_RAD2122_SREV_MAJOR,        "2122" }
2463 };
2464
2465 /*
2466  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2467  */
2468 static const char *
2469 ath_mac_bb_name(u32 mac_bb_version)
2470 {
2471         int i;
2472
2473         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2474                 if (ath_mac_bb_names[i].version == mac_bb_version) {
2475                         return ath_mac_bb_names[i].name;
2476                 }
2477         }
2478
2479         return "????";
2480 }
2481
2482 /*
2483  * Return the RF name. "????" is returned if the RF is unknown.
2484  */
2485 static const char *
2486 ath_rf_name(u16 rf_version)
2487 {
2488         int i;
2489
2490         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2491                 if (ath_rf_names[i].version == rf_version) {
2492                         return ath_rf_names[i].name;
2493                 }
2494         }
2495
2496         return "????";
2497 }
2498
2499 static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2500 {
2501         void __iomem *mem;
2502         struct ath_softc *sc;
2503         struct ieee80211_hw *hw;
2504         u8 csz;
2505         u32 val;
2506         int ret = 0;
2507         struct ath_hal *ah;
2508
2509         if (pci_enable_device(pdev))
2510                 return -EIO;
2511
2512         ret =  pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2513
2514         if (ret) {
2515                 printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
2516                 goto bad;
2517         }
2518
2519         ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2520
2521         if (ret) {
2522                 printk(KERN_ERR "ath9k: 32-bit DMA consistent "
2523                         "DMA enable failed\n");
2524                 goto bad;
2525         }
2526
2527         /*
2528          * Cache line size is used to size and align various
2529          * structures used to communicate with the hardware.
2530          */
2531         pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
2532         if (csz == 0) {
2533                 /*
2534                  * Linux 2.4.18 (at least) writes the cache line size
2535                  * register as a 16-bit wide register which is wrong.
2536                  * We must have this setup properly for rx buffer
2537                  * DMA to work so force a reasonable value here if it
2538                  * comes up zero.
2539                  */
2540                 csz = L1_CACHE_BYTES / sizeof(u32);
2541                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
2542         }
2543         /*
2544          * The default setting of latency timer yields poor results,
2545          * set it to the value used by other systems. It may be worth
2546          * tweaking this setting more.
2547          */
2548         pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
2549
2550         pci_set_master(pdev);
2551
2552         /*
2553          * Disable the RETRY_TIMEOUT register (0x41) to keep
2554          * PCI Tx retries from interfering with C3 CPU state.
2555          */
2556         pci_read_config_dword(pdev, 0x40, &val);
2557         if ((val & 0x0000ff00) != 0)
2558                 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2559
2560         ret = pci_request_region(pdev, 0, "ath9k");
2561         if (ret) {
2562                 dev_err(&pdev->dev, "PCI memory region reserve error\n");
2563                 ret = -ENODEV;
2564                 goto bad;
2565         }
2566
2567         mem = pci_iomap(pdev, 0, 0);
2568         if (!mem) {
2569                 printk(KERN_ERR "PCI memory map error\n") ;
2570                 ret = -EIO;
2571                 goto bad1;
2572         }
2573
2574         hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
2575         if (hw == NULL) {
2576                 printk(KERN_ERR "ath_pci: no memory for ieee80211_hw\n");
2577                 goto bad2;
2578         }
2579
2580         SET_IEEE80211_DEV(hw, &pdev->dev);
2581         pci_set_drvdata(pdev, hw);
2582
2583         sc = hw->priv;
2584         sc->hw = hw;
2585         sc->pdev = pdev;
2586         sc->mem = mem;
2587
2588         if (ath_attach(id->device, sc) != 0) {
2589                 ret = -ENODEV;
2590                 goto bad3;
2591         }
2592
2593         /* setup interrupt service routine */
2594
2595         if (request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath", sc)) {
2596                 printk(KERN_ERR "%s: request_irq failed\n",
2597                         wiphy_name(hw->wiphy));
2598                 ret = -EIO;
2599                 goto bad4;
2600         }
2601
2602         ah = sc->sc_ah;
2603         printk(KERN_INFO
2604                "%s: Atheros AR%s MAC/BB Rev:%x "
2605                "AR%s RF Rev:%x: mem=0x%lx, irq=%d\n",
2606                wiphy_name(hw->wiphy),
2607                ath_mac_bb_name(ah->ah_macVersion),
2608                ah->ah_macRev,
2609                ath_rf_name((ah->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR)),
2610                ah->ah_phyRev,
2611                (unsigned long)mem, pdev->irq);
2612
2613         return 0;
2614 bad4:
2615         ath_detach(sc);
2616 bad3:
2617         ieee80211_free_hw(hw);
2618 bad2:
2619         pci_iounmap(pdev, mem);
2620 bad1:
2621         pci_release_region(pdev, 0);
2622 bad:
2623         pci_disable_device(pdev);
2624         return ret;
2625 }
2626
2627 static void ath_pci_remove(struct pci_dev *pdev)
2628 {
2629         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2630         struct ath_softc *sc = hw->priv;
2631
2632         ath_detach(sc);
2633         if (pdev->irq)
2634                 free_irq(pdev->irq, sc);
2635         pci_iounmap(pdev, sc->mem);
2636         pci_release_region(pdev, 0);
2637         pci_disable_device(pdev);
2638         ieee80211_free_hw(hw);
2639 }
2640
2641 #ifdef CONFIG_PM
2642
2643 static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2644 {
2645         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2646         struct ath_softc *sc = hw->priv;
2647
2648         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
2649
2650 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2651         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2652                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2653 #endif
2654
2655         pci_save_state(pdev);
2656         pci_disable_device(pdev);
2657         pci_set_power_state(pdev, 3);
2658
2659         return 0;
2660 }
2661
2662 static int ath_pci_resume(struct pci_dev *pdev)
2663 {
2664         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2665         struct ath_softc *sc = hw->priv;
2666         u32 val;
2667         int err;
2668
2669         err = pci_enable_device(pdev);
2670         if (err)
2671                 return err;
2672         pci_restore_state(pdev);
2673         /*
2674          * Suspend/Resume resets the PCI configuration space, so we have to
2675          * re-disable the RETRY_TIMEOUT register (0x41) to keep
2676          * PCI Tx retries from interfering with C3 CPU state
2677          */
2678         pci_read_config_dword(pdev, 0x40, &val);
2679         if ((val & 0x0000ff00) != 0)
2680                 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2681
2682         /* Enable LED */
2683         ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
2684                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
2685         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
2686
2687 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2688         /*
2689          * check the h/w rfkill state on resume
2690          * and start the rfkill poll timer
2691          */
2692         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2693                 queue_delayed_work(sc->hw->workqueue,
2694                                    &sc->rf_kill.rfkill_poll, 0);
2695 #endif
2696
2697         return 0;
2698 }
2699
2700 #endif /* CONFIG_PM */
2701
2702 MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
2703
2704 static struct pci_driver ath_pci_driver = {
2705         .name       = "ath9k",
2706         .id_table   = ath_pci_id_table,
2707         .probe      = ath_pci_probe,
2708         .remove     = ath_pci_remove,
2709 #ifdef CONFIG_PM
2710         .suspend    = ath_pci_suspend,
2711         .resume     = ath_pci_resume,
2712 #endif /* CONFIG_PM */
2713 };
2714
2715 static int __init init_ath_pci(void)
2716 {
2717         printk(KERN_INFO "%s: %s\n", dev_info, ATH_PCI_VERSION);
2718
2719         if (pci_register_driver(&ath_pci_driver) < 0) {
2720                 printk(KERN_ERR
2721                         "ath_pci: No devices found, driver not installed.\n");
2722                 pci_unregister_driver(&ath_pci_driver);
2723                 return -ENODEV;
2724         }
2725
2726         return 0;
2727 }
2728 module_init(init_ath_pci);
2729
2730 static void __exit exit_ath_pci(void)
2731 {
2732         pci_unregister_driver(&ath_pci_driver);
2733         printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
2734 }
2735 module_exit(exit_ath_pci);