git.oblomov.eu Git - linux-2.6/blob - sound/pci/hda/hda_intel.c

   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base for Intel HD Audio.
   4  *
   5  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   6  *
   7  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   8  *                     PeiSen Hou <pshou@realtek.com.tw>
   9  *
  10  *  This program is free software; you can redistribute it and/or modify it
  11  *  under the terms of the GNU General Public License as published by the Free
  12  *  Software Foundation; either version 2 of the License, or (at your option)
  13  *  any later version.
  14  *
  15  *  This program is distributed in the hope that it will be useful, but WITHOUT
  16  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  17  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  18  *  more details.
  19  *
  20  *  You should have received a copy of the GNU General Public License along with
  21  *  this program; if not, write to the Free Software Foundation, Inc., 59
  22  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  23  *
  24  *  CONTACTS:
  25  *
  26  *  Matt Jared          matt.jared@intel.com
  27  *  Andy Kopp           andy.kopp@intel.com
  28  *  Dan Kogan           dan.d.kogan@intel.com
  29  *
  30  *  CHANGES:
  31  *
  32  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  33  *
  34  */
  35
  36 #include <sound/driver.h>
  37 #include <asm/io.h>
  38 #include <linux/delay.h>
  39 #include <linux/interrupt.h>
  40 #include <linux/module.h>
  41 #include <linux/moduleparam.h>
  42 #include <linux/init.h>
  43 #include <linux/slab.h>
  44 #include <linux/pci.h>
  45 #include <sound/core.h>
  46 #include <sound/initval.h>
  47 #include "hda_codec.h"
  48
  49
  50 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
  51 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  52 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
  53 static char *model[SNDRV_CARDS];
  54 static int position_fix[SNDRV_CARDS];
  55
  56 module_param_array(index, int, NULL, 0444);
  57 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
  58 module_param_array(id, charp, NULL, 0444);
  59 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
  60 module_param_array(enable, bool, NULL, 0444);
  61 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
  62 module_param_array(model, charp, NULL, 0444);
  63 MODULE_PARM_DESC(model, "Use the given board model.");
  64 module_param_array(position_fix, int, NULL, 0444);
  65 MODULE_PARM_DESC(position_fix, "Fix DMA pointer (0 = FIFO size, 1 = none, 2 = POSBUF).");
  66
  67 MODULE_LICENSE("GPL");
  68 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
  69                          "{Intel, ICH6M},"
  70                          "{Intel, ICH7},"
  71                          "{Intel, ESB2},"
  72                          "{ATI, SB450},"
  73                          "{VIA, VT8251},"
  74                          "{VIA, VT8237A}}");
  75 MODULE_DESCRIPTION("Intel HDA driver");
  76
  77 #define SFX     "hda-intel: "
  78
  79 /*
  80  * registers
  81  */
  82 #define ICH6_REG_GCAP                   0x00
  83 #define ICH6_REG_VMIN                   0x02
  84 #define ICH6_REG_VMAJ                   0x03
  85 #define ICH6_REG_OUTPAY                 0x04
  86 #define ICH6_REG_INPAY                  0x06
  87 #define ICH6_REG_GCTL                   0x08
  88 #define ICH6_REG_WAKEEN                 0x0c
  89 #define ICH6_REG_STATESTS               0x0e
  90 #define ICH6_REG_GSTS                   0x10
  91 #define ICH6_REG_INTCTL                 0x20
  92 #define ICH6_REG_INTSTS                 0x24
  93 #define ICH6_REG_WALCLK                 0x30
  94 #define ICH6_REG_SYNC                   0x34
  95 #define ICH6_REG_CORBLBASE              0x40
  96 #define ICH6_REG_CORBUBASE              0x44
  97 #define ICH6_REG_CORBWP                 0x48
  98 #define ICH6_REG_CORBRP                 0x4A
  99 #define ICH6_REG_CORBCTL                0x4c
 100 #define ICH6_REG_CORBSTS                0x4d
 101 #define ICH6_REG_CORBSIZE               0x4e
 102
 103 #define ICH6_REG_RIRBLBASE              0x50
 104 #define ICH6_REG_RIRBUBASE              0x54
 105 #define ICH6_REG_RIRBWP                 0x58
 106 #define ICH6_REG_RINTCNT                0x5a
 107 #define ICH6_REG_RIRBCTL                0x5c
 108 #define ICH6_REG_RIRBSTS                0x5d
 109 #define ICH6_REG_RIRBSIZE               0x5e
 110
 111 #define ICH6_REG_IC                     0x60
 112 #define ICH6_REG_IR                     0x64
 113 #define ICH6_REG_IRS                    0x68
 114 #define   ICH6_IRS_VALID        (1<<1)
 115 #define   ICH6_IRS_BUSY         (1<<0)
 116
 117 #define ICH6_REG_DPLBASE                0x70
 118 #define ICH6_REG_DPUBASE                0x74
 119 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
 120
 121 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
 122 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
 123
 124 /* stream register offsets from stream base */
 125 #define ICH6_REG_SD_CTL                 0x00
 126 #define ICH6_REG_SD_STS                 0x03
 127 #define ICH6_REG_SD_LPIB                0x04
 128 #define ICH6_REG_SD_CBL                 0x08
 129 #define ICH6_REG_SD_LVI                 0x0c
 130 #define ICH6_REG_SD_FIFOW               0x0e
 131 #define ICH6_REG_SD_FIFOSIZE            0x10
 132 #define ICH6_REG_SD_FORMAT              0x12
 133 #define ICH6_REG_SD_BDLPL               0x18
 134 #define ICH6_REG_SD_BDLPU               0x1c
 135
 136 /* PCI space */
 137 #define ICH6_PCIREG_TCSEL       0x44
 138
 139 /*
 140  * other constants
 141  */
 142
 143 /* max number of SDs */
 144 #define MAX_ICH6_DEV            8
 145 /* max number of fragments - we may use more if allocating more pages for BDL */
 146 #define AZX_MAX_FRAG            (PAGE_SIZE / (MAX_ICH6_DEV * 16))
 147 /* max buffer size - no h/w limit, you can increase as you like */
 148 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
 149 /* max number of PCM devics per card */
 150 #define AZX_MAX_PCMS            8
 151
 152 /* RIRB int mask: overrun[2], response[0] */
 153 #define RIRB_INT_RESPONSE       0x01
 154 #define RIRB_INT_OVERRUN        0x04
 155 #define RIRB_INT_MASK           0x05
 156
 157 /* STATESTS int mask: SD2,SD1,SD0 */
 158 #define STATESTS_INT_MASK       0x07
 159 #define AZX_MAX_CODECS          4
 160
 161 /* SD_CTL bits */
 162 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
 163 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
 164 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
 165 #define SD_CTL_STREAM_TAG_SHIFT 20
 166
 167 /* SD_CTL and SD_STS */
 168 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
 169 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
 170 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
 171 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|SD_INT_COMPLETE)
 172
 173 /* SD_STS */
 174 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
 175
 176 /* INTCTL and INTSTS */
 177 #define ICH6_INT_ALL_STREAM     0xff            /* all stream interrupts */
 178 #define ICH6_INT_CTRL_EN        0x40000000      /* controller interrupt enable bit */
 179 #define ICH6_INT_GLOBAL_EN      0x80000000      /* global interrupt enable bit */
 180
 181 /* GCTL reset bit */
 182 #define ICH6_GCTL_RESET         (1<<0)
 183
 184 /* CORB/RIRB control, read/write pointer */
 185 #define ICH6_RBCTL_DMA_EN       0x02    /* enable DMA */
 186 #define ICH6_RBCTL_IRQ_EN       0x01    /* enable IRQ */
 187 #define ICH6_RBRWP_CLR          0x8000  /* read/write pointer clear */
 188 /* below are so far hardcoded - should read registers in future */
 189 #define ICH6_MAX_CORB_ENTRIES   256
 190 #define ICH6_MAX_RIRB_ENTRIES   256
 191
 192 /* position fix mode */
 193 enum {
 194         POS_FIX_FIFO,
 195         POS_FIX_NONE,
 196         POS_FIX_POSBUF
 197 };
 198
 199 /* Defines for ATI HD Audio support in SB450 south bridge */
 200 #define ATI_SB450_HDAUDIO_PCI_DEVICE_ID     0x437b
 201 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
 202 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
 203
 204
 205 /*
 206  * Use CORB/RIRB for communication from/to codecs.
 207  * This is the way recommended by Intel (see below).
 208  */
 209 #define USE_CORB_RIRB
 210
 211 /*
 212  */
 213
 214 typedef struct snd_azx azx_t;
 215 typedef struct snd_azx_rb azx_rb_t;
 216 typedef struct snd_azx_dev azx_dev_t;
 217
 218 struct snd_azx_dev {
 219         u32 *bdl;                       /* virtual address of the BDL */
 220         dma_addr_t bdl_addr;            /* physical address of the BDL */
 221         volatile u32 *posbuf;                   /* position buffer pointer */
 222
 223         unsigned int bufsize;           /* size of the play buffer in bytes */
 224         unsigned int fragsize;          /* size of each period in bytes */
 225         unsigned int frags;             /* number for period in the play buffer */
 226         unsigned int fifo_size;         /* FIFO size */
 227
 228         void __iomem *sd_addr;          /* stream descriptor pointer */
 229
 230         u32 sd_int_sta_mask;            /* stream int status mask */
 231
 232         /* pcm support */
 233         snd_pcm_substream_t *substream; /* assigned substream, set in PCM open */
 234         unsigned int format_val;        /* format value to be set in the controller and the codec */
 235         unsigned char stream_tag;       /* assigned stream */
 236         unsigned char index;            /* stream index */
 237
 238         unsigned int opened: 1;
 239         unsigned int running: 1;
 240 };
 241
 242 /* CORB/RIRB */
 243 struct snd_azx_rb {
 244         u32 *buf;               /* CORB/RIRB buffer
 245                                  * Each CORB entry is 4byte, RIRB is 8byte
 246                                  */
 247         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
 248         /* for RIRB */
 249         unsigned short rp, wp;  /* read/write pointers */
 250         int cmds;               /* number of pending requests */
 251         u32 res;                /* last read value */
 252 };
 253
 254 struct snd_azx {
 255         snd_card_t *card;
 256         struct pci_dev *pci;
 257
 258         /* pci resources */
 259         unsigned long addr;
 260         void __iomem *remap_addr;
 261         int irq;
 262
 263         /* locks */
 264         spinlock_t reg_lock;
 265         struct semaphore open_mutex;
 266
 267         /* streams */
 268         azx_dev_t azx_dev[MAX_ICH6_DEV];
 269
 270         /* PCM */
 271         unsigned int pcm_devs;
 272         snd_pcm_t *pcm[AZX_MAX_PCMS];
 273
 274         /* HD codec */
 275         unsigned short codec_mask;
 276         struct hda_bus *bus;
 277
 278         /* CORB/RIRB */
 279         azx_rb_t corb;
 280         azx_rb_t rirb;
 281
 282         /* BDL, CORB/RIRB and position buffers */
 283         struct snd_dma_buffer bdl;
 284         struct snd_dma_buffer rb;
 285         struct snd_dma_buffer posbuf;
 286
 287         /* flags */
 288         int position_fix;
 289 };
 290
 291 /*
 292  * macros for easy use
 293  */
 294 #define azx_writel(chip,reg,value) \
 295         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
 296 #define azx_readl(chip,reg) \
 297         readl((chip)->remap_addr + ICH6_REG_##reg)
 298 #define azx_writew(chip,reg,value) \
 299         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
 300 #define azx_readw(chip,reg) \
 301         readw((chip)->remap_addr + ICH6_REG_##reg)
 302 #define azx_writeb(chip,reg,value) \
 303         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
 304 #define azx_readb(chip,reg) \
 305         readb((chip)->remap_addr + ICH6_REG_##reg)
 306
 307 #define azx_sd_writel(dev,reg,value) \
 308         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
 309 #define azx_sd_readl(dev,reg) \
 310         readl((dev)->sd_addr + ICH6_REG_##reg)
 311 #define azx_sd_writew(dev,reg,value) \
 312         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
 313 #define azx_sd_readw(dev,reg) \
 314         readw((dev)->sd_addr + ICH6_REG_##reg)
 315 #define azx_sd_writeb(dev,reg,value) \
 316         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
 317 #define azx_sd_readb(dev,reg) \
 318         readb((dev)->sd_addr + ICH6_REG_##reg)
 319
 320 /* for pcm support */
 321 #define get_azx_dev(substream) (azx_dev_t*)(substream->runtime->private_data)
 322
 323 /* Get the upper 32bit of the given dma_addr_t
 324  * Compiler should optimize and eliminate the code if dma_addr_t is 32bit
 325  */
 326 #define upper_32bit(addr) (sizeof(addr) > 4 ? (u32)((addr) >> 32) : (u32)0)
 327
 328
 329 /*
 330  * Interface for HD codec
 331  */
 332
 333 #ifdef USE_CORB_RIRB
 334 /*
 335  * CORB / RIRB interface
 336  */
 337 static int azx_alloc_cmd_io(azx_t *chip)
 338 {
 339         int err;
 340
 341         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
 342         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
 343                                   PAGE_SIZE, &chip->rb);
 344         if (err < 0) {
 345                 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
 346                 return err;
 347         }
 348         return 0;
 349 }
 350
 351 static void azx_init_cmd_io(azx_t *chip)
 352 {
 353         /* CORB set up */
 354         chip->corb.addr = chip->rb.addr;
 355         chip->corb.buf = (u32 *)chip->rb.area;
 356         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
 357         azx_writel(chip, CORBUBASE, upper_32bit(chip->corb.addr));
 358
 359         /* set the corb write pointer to 0 */
 360         azx_writew(chip, CORBWP, 0);
 361         /* reset the corb hw read pointer */
 362         azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
 363         /* enable corb dma */
 364         azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
 365
 366         /* RIRB set up */
 367         chip->rirb.addr = chip->rb.addr + 2048;
 368         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
 369         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
 370         azx_writel(chip, RIRBUBASE, upper_32bit(chip->rirb.addr));
 371
 372         /* reset the rirb hw write pointer */
 373         azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
 374         /* set N=1, get RIRB response interrupt for new entry */
 375         azx_writew(chip, RINTCNT, 1);
 376         /* enable rirb dma and response irq */
 377 #ifdef USE_CORB_RIRB
 378         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
 379 #else
 380         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN);
 381 #endif
 382         chip->rirb.rp = chip->rirb.cmds = 0;
 383 }
 384
 385 static void azx_free_cmd_io(azx_t *chip)
 386 {
 387         /* disable ringbuffer DMAs */
 388         azx_writeb(chip, RIRBCTL, 0);
 389         azx_writeb(chip, CORBCTL, 0);
 390 }
 391
 392 /* send a command */
 393 static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid, int direct,
 394                         unsigned int verb, unsigned int para)
 395 {
 396         azx_t *chip = codec->bus->private_data;
 397         unsigned int wp;
 398         u32 val;
 399
 400         val = (u32)(codec->addr & 0x0f) << 28;
 401         val |= (u32)direct << 27;
 402         val |= (u32)nid << 20;
 403         val |= verb << 8;
 404         val |= para;
 405
 406         /* add command to corb */
 407         wp = azx_readb(chip, CORBWP);
 408         wp++;
 409         wp %= ICH6_MAX_CORB_ENTRIES;
 410
 411         spin_lock_irq(&chip->reg_lock);
 412         chip->rirb.cmds++;
 413         chip->corb.buf[wp] = cpu_to_le32(val);
 414         azx_writel(chip, CORBWP, wp);
 415         spin_unlock_irq(&chip->reg_lock);
 416
 417         return 0;
 418 }
 419
 420 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
 421
 422 /* retrieve RIRB entry - called from interrupt handler */
 423 static void azx_update_rirb(azx_t *chip)
 424 {
 425         unsigned int rp, wp;
 426         u32 res, res_ex;
 427
 428         wp = azx_readb(chip, RIRBWP);
 429         if (wp == chip->rirb.wp)
 430                 return;
 431         chip->rirb.wp = wp;
 432
 433         while (chip->rirb.rp != wp) {
 434                 chip->rirb.rp++;
 435                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
 436
 437                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
 438                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
 439                 res = le32_to_cpu(chip->rirb.buf[rp]);
 440                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
 441                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
 442                 else if (chip->rirb.cmds) {
 443                         chip->rirb.cmds--;
 444                         chip->rirb.res = res;
 445                 }
 446         }
 447 }
 448
 449 /* receive a response */
 450 static unsigned int azx_get_response(struct hda_codec *codec)
 451 {
 452         azx_t *chip = codec->bus->private_data;
 453         int timeout = 50;
 454
 455         while (chip->rirb.cmds) {
 456                 if (! --timeout) {
 457                         snd_printk(KERN_ERR "azx_get_response timeout\n");
 458                         chip->rirb.rp = azx_readb(chip, RIRBWP);
 459                         chip->rirb.cmds = 0;
 460                         return -1;
 461                 }
 462                 msleep(1);
 463         }
 464         return chip->rirb.res; /* the last value */
 465 }
 466
 467 #else
 468 /*
 469  * Use the single immediate command instead of CORB/RIRB for simplicity
 470  *
 471  * Note: according to Intel, this is not preferred use.  The command was
 472  *       intended for the BIOS only, and may get confused with unsolicited
 473  *       responses.  So, we shouldn't use it for normal operation from the
 474  *       driver.
 475  *       I left the codes, however, for debugging/testing purposes.
 476  */
 477
 478 #define azx_alloc_cmd_io(chip)  0
 479 #define azx_init_cmd_io(chip)
 480 #define azx_free_cmd_io(chip)
 481
 482 /* send a command */
 483 static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid, int direct,
 484                         unsigned int verb, unsigned int para)
 485 {
 486         azx_t *chip = codec->bus->private_data;
 487         u32 val;
 488         int timeout = 50;
 489
 490         val = (u32)(codec->addr & 0x0f) << 28;
 491         val |= (u32)direct << 27;
 492         val |= (u32)nid << 20;
 493         val |= verb << 8;
 494         val |= para;
 495
 496         while (timeout--) {
 497                 /* check ICB busy bit */
 498                 if (! (azx_readw(chip, IRS) & ICH6_IRS_BUSY)) {
 499                         /* Clear IRV valid bit */
 500                         azx_writew(chip, IRS, azx_readw(chip, IRS) | ICH6_IRS_VALID);
 501                         azx_writel(chip, IC, val);
 502                         azx_writew(chip, IRS, azx_readw(chip, IRS) | ICH6_IRS_BUSY);
 503                         return 0;
 504                 }
 505                 udelay(1);
 506         }
 507         snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n", azx_readw(chip, IRS), val);
 508         return -EIO;
 509 }
 510
 511 /* receive a response */
 512 static unsigned int azx_get_response(struct hda_codec *codec)
 513 {
 514         azx_t *chip = codec->bus->private_data;
 515         int timeout = 50;
 516
 517         while (timeout--) {
 518                 /* check IRV busy bit */
 519                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
 520                         return azx_readl(chip, IR);
 521                 udelay(1);
 522         }
 523         snd_printd(SFX "get_response timeout: IRS=0x%x\n", azx_readw(chip, IRS));
 524         return (unsigned int)-1;
 525 }
 526
 527 #define azx_update_rirb(chip)
 528
 529 #endif /* USE_CORB_RIRB */
 530
 531 /* reset codec link */
 532 static int azx_reset(azx_t *chip)
 533 {
 534         int count;
 535
 536         /* reset controller */
 537         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
 538
 539         count = 50;
 540         while (azx_readb(chip, GCTL) && --count)
 541                 msleep(1);
 542
 543         /* delay for >= 100us for codec PLL to settle per spec
 544          * Rev 0.9 section 5.5.1
 545          */
 546         msleep(1);
 547
 548         /* Bring controller out of reset */
 549         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
 550
 551         count = 50;
 552         while (! azx_readb(chip, GCTL) && --count)
 553                 msleep(1);
 554
 555         /* Brent Chartrand said to wait >= 540us for codecs to intialize */
 556         msleep(1);
 557
 558         /* check to see if controller is ready */
 559         if (! azx_readb(chip, GCTL)) {
 560                 snd_printd("azx_reset: controller not ready!\n");
 561                 return -EBUSY;
 562         }
 563
 564         /* detect codecs */
 565         if (! chip->codec_mask) {
 566                 chip->codec_mask = azx_readw(chip, STATESTS);
 567                 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
 568         }
 569
 570         return 0;
 571 }
 572
 573
 574 /*
 575  * Lowlevel interface
 576  */
 577
 578 /* enable interrupts */
 579 static void azx_int_enable(azx_t *chip)
 580 {
 581         /* enable controller CIE and GIE */
 582         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
 583                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
 584 }
 585
 586 /* disable interrupts */
 587 static void azx_int_disable(azx_t *chip)
 588 {
 589         int i;
 590
 591         /* disable interrupts in stream descriptor */
 592         for (i = 0; i < MAX_ICH6_DEV; i++) {
 593                 azx_dev_t *azx_dev = &chip->azx_dev[i];
 594                 azx_sd_writeb(azx_dev, SD_CTL,
 595                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
 596         }
 597
 598         /* disable SIE for all streams */
 599         azx_writeb(chip, INTCTL, 0);
 600
 601         /* disable controller CIE and GIE */
 602         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
 603                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
 604 }
 605
 606 /* clear interrupts */
 607 static void azx_int_clear(azx_t *chip)
 608 {
 609         int i;
 610
 611         /* clear stream status */
 612         for (i = 0; i < MAX_ICH6_DEV; i++) {
 613                 azx_dev_t *azx_dev = &chip->azx_dev[i];
 614                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
 615         }
 616
 617         /* clear STATESTS */
 618         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 619
 620         /* clear rirb status */
 621         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
 622
 623         /* clear int status */
 624         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
 625 }
 626
 627 /* start a stream */
 628 static void azx_stream_start(azx_t *chip, azx_dev_t *azx_dev)
 629 {
 630         /* enable SIE */
 631         azx_writeb(chip, INTCTL,
 632                    azx_readb(chip, INTCTL) | (1 << azx_dev->index));
 633         /* set DMA start and interrupt mask */
 634         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
 635                       SD_CTL_DMA_START | SD_INT_MASK);
 636 }
 637
 638 /* stop a stream */
 639 static void azx_stream_stop(azx_t *chip, azx_dev_t *azx_dev)
 640 {
 641         /* stop DMA */
 642         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
 643                       ~(SD_CTL_DMA_START | SD_INT_MASK));
 644         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
 645         /* disable SIE */
 646         azx_writeb(chip, INTCTL,
 647                    azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
 648 }
 649
 650
 651 /*
 652  * initialize the chip
 653  */
 654 static void azx_init_chip(azx_t *chip)
 655 {
 656         unsigned char tcsel_reg, ati_misc_cntl2;
 657
 658         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 659          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 660          * Ensuring these bits are 0 clears playback static on some HD Audio codecs
 661          */
 662         pci_read_config_byte (chip->pci, ICH6_PCIREG_TCSEL, &tcsel_reg);
 663         pci_write_config_byte(chip->pci, ICH6_PCIREG_TCSEL, tcsel_reg & 0xf8);
 664
 665         /* reset controller */
 666         azx_reset(chip);
 667
 668         /* initialize interrupts */
 669         azx_int_clear(chip);
 670         azx_int_enable(chip);
 671
 672         /* initialize the codec command I/O */
 673         azx_init_cmd_io(chip);
 674
 675         if (chip->position_fix == POS_FIX_POSBUF) {
 676                 /* program the position buffer */
 677                 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
 678                 azx_writel(chip, DPUBASE, upper_32bit(chip->posbuf.addr));
 679         }
 680
 681         /* For ATI SB450 azalia HD audio, we need to enable snoop */
 682         if (chip->pci->vendor == PCI_VENDOR_ID_ATI &&
 683             chip->pci->device == ATI_SB450_HDAUDIO_PCI_DEVICE_ID) {
 684                 pci_read_config_byte(chip->pci, ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
 685                                      &ati_misc_cntl2);
 686                 pci_write_config_byte(chip->pci, ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
 687                                       (ati_misc_cntl2 & 0xf8) | ATI_SB450_HDAUDIO_ENABLE_SNOOP);
 688         }
 689 }
 690
 691
 692 /*
 693  * interrupt handler
 694  */
 695 static irqreturn_t azx_interrupt(int irq, void* dev_id, struct pt_regs *regs)
 696 {
 697         azx_t *chip = dev_id;
 698         azx_dev_t *azx_dev;
 699         u32 status;
 700         int i;
 701
 702         spin_lock(&chip->reg_lock);
 703
 704         status = azx_readl(chip, INTSTS);
 705         if (status == 0) {
 706                 spin_unlock(&chip->reg_lock);
 707                 return IRQ_NONE;
 708         }
 709
 710         for (i = 0; i < MAX_ICH6_DEV; i++) {
 711                 azx_dev = &chip->azx_dev[i];
 712                 if (status & azx_dev->sd_int_sta_mask) {
 713                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
 714                         if (azx_dev->substream && azx_dev->running) {
 715                                 spin_unlock(&chip->reg_lock);
 716                                 snd_pcm_period_elapsed(azx_dev->substream);
 717                                 spin_lock(&chip->reg_lock);
 718                         }
 719                 }
 720         }
 721
 722         /* clear rirb int */
 723         status = azx_readb(chip, RIRBSTS);
 724         if (status & RIRB_INT_MASK) {
 725                 if (status & RIRB_INT_RESPONSE)
 726                         azx_update_rirb(chip);
 727                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
 728         }
 729
 730 #if 0
 731         /* clear state status int */
 732         if (azx_readb(chip, STATESTS) & 0x04)
 733                 azx_writeb(chip, STATESTS, 0x04);
 734 #endif
 735         spin_unlock(&chip->reg_lock);
 736
 737         return IRQ_HANDLED;
 738 }
 739
 740
 741 /*
 742  * set up BDL entries
 743  */
 744 static void azx_setup_periods(azx_dev_t *azx_dev)
 745 {
 746         u32 *bdl = azx_dev->bdl;
 747         dma_addr_t dma_addr = azx_dev->substream->runtime->dma_addr;
 748         int idx;
 749
 750         /* reset BDL address */
 751         azx_sd_writel(azx_dev, SD_BDLPL, 0);
 752         azx_sd_writel(azx_dev, SD_BDLPU, 0);
 753
 754         /* program the initial BDL entries */
 755         for (idx = 0; idx < azx_dev->frags; idx++) {
 756                 unsigned int off = idx << 2; /* 4 dword step */
 757                 dma_addr_t addr = dma_addr + idx * azx_dev->fragsize;
 758                 /* program the address field of the BDL entry */
 759                 bdl[off] = cpu_to_le32((u32)addr);
 760                 bdl[off+1] = cpu_to_le32(upper_32bit(addr));
 761
 762                 /* program the size field of the BDL entry */
 763                 bdl[off+2] = cpu_to_le32(azx_dev->fragsize);
 764
 765                 /* program the IOC to enable interrupt when buffer completes */
 766                 bdl[off+3] = cpu_to_le32(0x01);
 767         }
 768 }
 769
 770 /*
 771  * set up the SD for streaming
 772  */
 773 static int azx_setup_controller(azx_t *chip, azx_dev_t *azx_dev)
 774 {
 775         unsigned char val;
 776         int timeout;
 777
 778         /* make sure the run bit is zero for SD */
 779         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) & ~SD_CTL_DMA_START);
 780         /* reset stream */
 781         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) | SD_CTL_STREAM_RESET);
 782         udelay(3);
 783         timeout = 300;
 784         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
 785                --timeout)
 786                 ;
 787         val &= ~SD_CTL_STREAM_RESET;
 788         azx_sd_writeb(azx_dev, SD_CTL, val);
 789         udelay(3);
 790
 791         timeout = 300;
 792         /* waiting for hardware to report that the stream is out of reset */
 793         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
 794                --timeout)
 795                 ;
 796
 797         /* program the stream_tag */
 798         azx_sd_writel(azx_dev, SD_CTL,
 799                       (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK) |
 800                       (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
 801
 802         /* program the length of samples in cyclic buffer */
 803         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
 804
 805         /* program the stream format */
 806         /* this value needs to be the same as the one programmed */
 807         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
 808
 809         /* program the stream LVI (last valid index) of the BDL */
 810         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
 811
 812         /* program the BDL address */
 813         /* lower BDL address */
 814         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl_addr);
 815         /* upper BDL address */
 816         azx_sd_writel(azx_dev, SD_BDLPU, upper_32bit(azx_dev->bdl_addr));
 817
 818         if (chip->position_fix == POS_FIX_POSBUF) {
 819                 /* enable the position buffer */
 820                 if (! (azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
 821                         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
 822         }
 823
 824         /* set the interrupt enable bits in the descriptor control register */
 825         azx_sd_writel(azx_dev, SD_CTL, azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
 826
 827         return 0;
 828 }
 829
 830
 831 /*
 832  * Codec initialization
 833  */
 834
 835 static int __devinit azx_codec_create(azx_t *chip, const char *model)
 836 {
 837         struct hda_bus_template bus_temp;
 838         int c, codecs, err;
 839
 840         memset(&bus_temp, 0, sizeof(bus_temp));
 841         bus_temp.private_data = chip;
 842         bus_temp.modelname = model;
 843         bus_temp.pci = chip->pci;
 844         bus_temp.ops.command = azx_send_cmd;
 845         bus_temp.ops.get_response = azx_get_response;
 846
 847         if ((err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus)) < 0)
 848                 return err;
 849
 850         codecs = 0;
 851         for (c = 0; c < AZX_MAX_CODECS; c++) {
 852                 if (chip->codec_mask & (1 << c)) {
 853                         err = snd_hda_codec_new(chip->bus, c, NULL);
 854                         if (err < 0)
 855                                 continue;
 856                         codecs++;
 857                 }
 858         }
 859         if (! codecs) {
 860                 snd_printk(KERN_ERR SFX "no codecs initialized\n");
 861                 return -ENXIO;
 862         }
 863
 864         return 0;
 865 }
 866
 867
 868 /*
 869  * PCM support
 870  */
 871
 872 /* assign a stream for the PCM */
 873 static inline azx_dev_t *azx_assign_device(azx_t *chip, int stream)
 874 {
 875         int dev, i;
 876         dev = stream == SNDRV_PCM_STREAM_PLAYBACK ? 4 : 0;
 877         for (i = 0; i < 4; i++, dev++)
 878                 if (! chip->azx_dev[dev].opened) {
 879                         chip->azx_dev[dev].opened = 1;
 880                         return &chip->azx_dev[dev];
 881                 }
 882         return NULL;
 883 }
 884
 885 /* release the assigned stream */
 886 static inline void azx_release_device(azx_dev_t *azx_dev)
 887 {
 888         azx_dev->opened = 0;
 889 }
 890
 891 static snd_pcm_hardware_t azx_pcm_hw = {
 892         .info =                 (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
 893                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
 894                                  SNDRV_PCM_INFO_MMAP_VALID |
 895                                  SNDRV_PCM_INFO_PAUSE |
 896                                  SNDRV_PCM_INFO_RESUME),
 897         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
 898         .rates =                SNDRV_PCM_RATE_48000,
 899         .rate_min =             48000,
 900         .rate_max =             48000,
 901         .channels_min =         2,
 902         .channels_max =         2,
 903         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
 904         .period_bytes_min =     128,
 905         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
 906         .periods_min =          2,
 907         .periods_max =          AZX_MAX_FRAG,
 908         .fifo_size =            0,
 909 };
 910
 911 struct azx_pcm {
 912         azx_t *chip;
 913         struct hda_codec *codec;
 914         struct hda_pcm_stream *hinfo[2];
 915 };
 916
 917 static int azx_pcm_open(snd_pcm_substream_t *substream)
 918 {
 919         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 920         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
 921         azx_t *chip = apcm->chip;
 922         azx_dev_t *azx_dev;
 923         snd_pcm_runtime_t *runtime = substream->runtime;
 924         unsigned long flags;
 925         int err;
 926
 927         down(&chip->open_mutex);
 928         azx_dev = azx_assign_device(chip, substream->stream);
 929         if (azx_dev == NULL) {
 930                 up(&chip->open_mutex);
 931                 return -EBUSY;
 932         }
 933         runtime->hw = azx_pcm_hw;
 934         runtime->hw.channels_min = hinfo->channels_min;
 935         runtime->hw.channels_max = hinfo->channels_max;
 936         runtime->hw.formats = hinfo->formats;
 937         runtime->hw.rates = hinfo->rates;
 938         snd_pcm_limit_hw_rates(runtime);
 939         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
 940         if ((err = hinfo->ops.open(hinfo, apcm->codec, substream)) < 0) {
 941                 azx_release_device(azx_dev);
 942                 up(&chip->open_mutex);
 943                 return err;
 944         }
 945         spin_lock_irqsave(&chip->reg_lock, flags);
 946         azx_dev->substream = substream;
 947         azx_dev->running = 0;
 948         spin_unlock_irqrestore(&chip->reg_lock, flags);
 949
 950         runtime->private_data = azx_dev;
 951         up(&chip->open_mutex);
 952         return 0;
 953 }
 954
 955 static int azx_pcm_close(snd_pcm_substream_t *substream)
 956 {
 957         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 958         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
 959         azx_t *chip = apcm->chip;
 960         azx_dev_t *azx_dev = get_azx_dev(substream);
 961         unsigned long flags;
 962
 963         down(&chip->open_mutex);
 964         spin_lock_irqsave(&chip->reg_lock, flags);
 965         azx_dev->substream = NULL;
 966         azx_dev->running = 0;
 967         spin_unlock_irqrestore(&chip->reg_lock, flags);
 968         azx_release_device(azx_dev);
 969         hinfo->ops.close(hinfo, apcm->codec, substream);
 970         up(&chip->open_mutex);
 971         return 0;
 972 }
 973
 974 static int azx_pcm_hw_params(snd_pcm_substream_t *substream, snd_pcm_hw_params_t *hw_params)
 975 {
 976         return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
 977 }
 978
 979 static int azx_pcm_hw_free(snd_pcm_substream_t *substream)
 980 {
 981         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 982         azx_dev_t *azx_dev = get_azx_dev(substream);
 983         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
 984
 985         /* reset BDL address */
 986         azx_sd_writel(azx_dev, SD_BDLPL, 0);
 987         azx_sd_writel(azx_dev, SD_BDLPU, 0);
 988         azx_sd_writel(azx_dev, SD_CTL, 0);
 989
 990         hinfo->ops.cleanup(hinfo, apcm->codec, substream);
 991
 992         return snd_pcm_lib_free_pages(substream);
 993 }
 994
 995 static int azx_pcm_prepare(snd_pcm_substream_t *substream)
 996 {
 997         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
 998         azx_t *chip = apcm->chip;
 999         azx_dev_t *azx_dev = get_azx_dev(substream);
1000         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1001         snd_pcm_runtime_t *runtime = substream->runtime;
1002
1003         azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream);
1004         azx_dev->fragsize = snd_pcm_lib_period_bytes(substream);
1005         azx_dev->frags = azx_dev->bufsize / azx_dev->fragsize;
1006         azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate,
1007                                                          runtime->channels,
1008                                                          runtime->format,
1009                                                          hinfo->maxbps);
1010         if (! azx_dev->format_val) {
1011                 snd_printk(KERN_ERR SFX "invalid format_val, rate=%d, ch=%d, format=%d\n",
1012                            runtime->rate, runtime->channels, runtime->format);
1013                 return -EINVAL;
1014         }
1015
1016         snd_printdd("azx_pcm_prepare: bufsize=0x%x, fragsize=0x%x, format=0x%x\n",
1017                     azx_dev->bufsize, azx_dev->fragsize, azx_dev->format_val);
1018         azx_setup_periods(azx_dev);
1019         azx_setup_controller(chip, azx_dev);
1020         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1021                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1022         else
1023                 azx_dev->fifo_size = 0;
1024
1025         return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1026                                   azx_dev->format_val, substream);
1027 }
1028
1029 static int azx_pcm_trigger(snd_pcm_substream_t *substream, int cmd)
1030 {
1031         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1032         azx_dev_t *azx_dev = get_azx_dev(substream);
1033         azx_t *chip = apcm->chip;
1034         int err = 0;
1035
1036         spin_lock(&chip->reg_lock);
1037         switch (cmd) {
1038         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1039         case SNDRV_PCM_TRIGGER_RESUME:
1040         case SNDRV_PCM_TRIGGER_START:
1041                 azx_stream_start(chip, azx_dev);
1042                 azx_dev->running = 1;
1043                 break;
1044         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1045         case SNDRV_PCM_TRIGGER_STOP:
1046                 azx_stream_stop(chip, azx_dev);
1047                 azx_dev->running = 0;
1048                 break;
1049         default:
1050                 err = -EINVAL;
1051         }
1052         spin_unlock(&chip->reg_lock);
1053         if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH ||
1054             cmd == SNDRV_PCM_TRIGGER_STOP) {
1055                 int timeout = 5000;
1056                 while (azx_sd_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START && --timeout)
1057                         ;
1058         }
1059         return err;
1060 }
1061
1062 static snd_pcm_uframes_t azx_pcm_pointer(snd_pcm_substream_t *substream)
1063 {
1064         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1065         azx_t *chip = apcm->chip;
1066         azx_dev_t *azx_dev = get_azx_dev(substream);
1067         unsigned int pos;
1068
1069         if (chip->position_fix == POS_FIX_POSBUF) {
1070                 /* use the position buffer */
1071                 pos = *azx_dev->posbuf;
1072         } else {
1073                 /* read LPIB */
1074                 pos = azx_sd_readl(azx_dev, SD_LPIB);
1075                 if (chip->position_fix == POS_FIX_FIFO)
1076                         pos += azx_dev->fifo_size;
1077         }
1078         if (pos >= azx_dev->bufsize)
1079                 pos = 0;
1080         return bytes_to_frames(substream->runtime, pos);
1081 }
1082
1083 static snd_pcm_ops_t azx_pcm_ops = {
1084         .open = azx_pcm_open,
1085         .close = azx_pcm_close,
1086         .ioctl = snd_pcm_lib_ioctl,
1087         .hw_params = azx_pcm_hw_params,
1088         .hw_free = azx_pcm_hw_free,
1089         .prepare = azx_pcm_prepare,
1090         .trigger = azx_pcm_trigger,
1091         .pointer = azx_pcm_pointer,
1092 };
1093
1094 static void azx_pcm_free(snd_pcm_t *pcm)
1095 {
1096         kfree(pcm->private_data);
1097 }
1098
1099 static int __devinit create_codec_pcm(azx_t *chip, struct hda_codec *codec,
1100                                       struct hda_pcm *cpcm, int pcm_dev)
1101 {
1102         int err;
1103         snd_pcm_t *pcm;
1104         struct azx_pcm *apcm;
1105
1106         snd_assert(cpcm->stream[0].substreams || cpcm->stream[1].substreams, return -EINVAL);
1107         snd_assert(cpcm->name, return -EINVAL);
1108
1109         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1110                           cpcm->stream[0].substreams, cpcm->stream[1].substreams,
1111                           &pcm);
1112         if (err < 0)
1113                 return err;
1114         strcpy(pcm->name, cpcm->name);
1115         apcm = kmalloc(sizeof(*apcm), GFP_KERNEL);
1116         if (apcm == NULL)
1117                 return -ENOMEM;
1118         apcm->chip = chip;
1119         apcm->codec = codec;
1120         apcm->hinfo[0] = &cpcm->stream[0];
1121         apcm->hinfo[1] = &cpcm->stream[1];
1122         pcm->private_data = apcm;
1123         pcm->private_free = azx_pcm_free;
1124         if (cpcm->stream[0].substreams)
1125                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &azx_pcm_ops);
1126         if (cpcm->stream[1].substreams)
1127                 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &azx_pcm_ops);
1128         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1129                                               snd_dma_pci_data(chip->pci),
1130                                               1024 * 64, 1024 * 128);
1131         chip->pcm[pcm_dev] = pcm;
1132
1133         return 0;
1134 }
1135
1136 static int __devinit azx_pcm_create(azx_t *chip)
1137 {
1138         struct list_head *p;
1139         struct hda_codec *codec;
1140         int c, err;
1141         int pcm_dev;
1142
1143         if ((err = snd_hda_build_pcms(chip->bus)) < 0)
1144                 return err;
1145
1146         pcm_dev = 0;
1147         list_for_each(p, &chip->bus->codec_list) {
1148                 codec = list_entry(p, struct hda_codec, list);
1149                 for (c = 0; c < codec->num_pcms; c++) {
1150                         if (pcm_dev >= AZX_MAX_PCMS) {
1151                                 snd_printk(KERN_ERR SFX "Too many PCMs\n");
1152                                 return -EINVAL;
1153                         }
1154                         err = create_codec_pcm(chip, codec, &codec->pcm_info[c], pcm_dev);
1155                         if (err < 0)
1156                                 return err;
1157                         pcm_dev++;
1158                 }
1159         }
1160         return 0;
1161 }
1162
1163 /*
1164  * mixer creation - all stuff is implemented in hda module
1165  */
1166 static int __devinit azx_mixer_create(azx_t *chip)
1167 {
1168         return snd_hda_build_controls(chip->bus);
1169 }
1170
1171
1172 /*
1173  * initialize SD streams
1174  */
1175 static int __devinit azx_init_stream(azx_t *chip)
1176 {
1177         int i;
1178
1179         /* initialize each stream (aka device)
1180          * assign the starting bdl address to each stream (device) and initialize
1181          */
1182         for (i = 0; i < MAX_ICH6_DEV; i++) {
1183                 unsigned int off = sizeof(u32) * (i * AZX_MAX_FRAG * 4);
1184                 azx_dev_t *azx_dev = &chip->azx_dev[i];
1185                 azx_dev->bdl = (u32 *)(chip->bdl.area + off);
1186                 azx_dev->bdl_addr = chip->bdl.addr + off;
1187                 if (chip->position_fix == POS_FIX_POSBUF)
1188                         azx_dev->posbuf = (volatile u32 *)(chip->posbuf.area + i * 8);
1189                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1190                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1191                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1192                 azx_dev->sd_int_sta_mask = 1 << i;
1193                 /* stream tag: must be non-zero and unique */
1194                 azx_dev->index = i;
1195                 azx_dev->stream_tag = i + 1;
1196         }
1197
1198         return 0;
1199 }
1200
1201
1202 #ifdef CONFIG_PM
1203 /*
1204  * power management
1205  */
1206 static int azx_suspend(snd_card_t *card, pm_message_t state)
1207 {
1208         azx_t *chip = card->pm_private_data;
1209         int i;
1210
1211         for (i = 0; i < chip->pcm_devs; i++)
1212                 if (chip->pcm[i])
1213                         snd_pcm_suspend_all(chip->pcm[i]);
1214         snd_hda_suspend(chip->bus, state);
1215         azx_free_cmd_io(chip);
1216         pci_disable_device(chip->pci);
1217         return 0;
1218 }
1219
1220 static int azx_resume(snd_card_t *card)
1221 {
1222         azx_t *chip = card->pm_private_data;
1223
1224         pci_enable_device(chip->pci);
1225         pci_set_master(chip->pci);
1226         azx_init_chip(chip);
1227         snd_hda_resume(chip->bus);
1228         return 0;
1229 }
1230 #endif /* CONFIG_PM */
1231
1232
1233 /*
1234  * destructor
1235  */
1236 static int azx_free(azx_t *chip)
1237 {
1238         if (chip->remap_addr) {
1239                 int i;
1240
1241                 for (i = 0; i < MAX_ICH6_DEV; i++)
1242                         azx_stream_stop(chip, &chip->azx_dev[i]);
1243
1244                 /* disable interrupts */
1245                 azx_int_disable(chip);
1246                 azx_int_clear(chip);
1247
1248                 /* disable CORB/RIRB */
1249                 azx_free_cmd_io(chip);
1250
1251                 /* disable position buffer */
1252                 azx_writel(chip, DPLBASE, 0);
1253                 azx_writel(chip, DPUBASE, 0);
1254
1255                 /* wait a little for interrupts to finish */
1256                 msleep(1);
1257
1258                 iounmap(chip->remap_addr);
1259         }
1260
1261         if (chip->irq >= 0)
1262                 free_irq(chip->irq, (void*)chip);
1263
1264         if (chip->bdl.area)
1265                 snd_dma_free_pages(&chip->bdl);
1266         if (chip->rb.area)
1267                 snd_dma_free_pages(&chip->rb);
1268         if (chip->posbuf.area)
1269                 snd_dma_free_pages(&chip->posbuf);
1270         pci_release_regions(chip->pci);
1271         pci_disable_device(chip->pci);
1272         kfree(chip);
1273
1274         return 0;
1275 }
1276
1277 static int azx_dev_free(snd_device_t *device)
1278 {
1279         return azx_free(device->device_data);
1280 }
1281
1282 /*
1283  * constructor
1284  */
1285 static int __devinit azx_create(snd_card_t *card, struct pci_dev *pci,
1286                                 int posfix, azx_t **rchip)
1287 {
1288         azx_t *chip;
1289         int err = 0;
1290         static snd_device_ops_t ops = {
1291                 .dev_free = azx_dev_free,
1292         };
1293
1294         *rchip = NULL;
1295
1296         if ((err = pci_enable_device(pci)) < 0)
1297                 return err;
1298
1299         chip = kcalloc(1, sizeof(*chip), GFP_KERNEL);
1300
1301         if (NULL == chip) {
1302                 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
1303                 pci_disable_device(pci);
1304                 return -ENOMEM;
1305         }
1306
1307         spin_lock_init(&chip->reg_lock);
1308         init_MUTEX(&chip->open_mutex);
1309         chip->card = card;
1310         chip->pci = pci;
1311         chip->irq = -1;
1312
1313         chip->position_fix = posfix;
1314
1315         if ((err = pci_request_regions(pci, "ICH HD audio")) < 0) {
1316                 kfree(chip);
1317                 pci_disable_device(pci);
1318                 return err;
1319         }
1320
1321         chip->addr = pci_resource_start(pci,0);
1322         chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0));
1323         if (chip->remap_addr == NULL) {
1324                 snd_printk(KERN_ERR SFX "ioremap error\n");
1325                 err = -ENXIO;
1326                 goto errout;
1327         }
1328
1329         if (request_irq(pci->irq, azx_interrupt, SA_INTERRUPT|SA_SHIRQ,
1330                         "HDA Intel", (void*)chip)) {
1331                 snd_printk(KERN_ERR SFX "unable to grab IRQ %d\n", pci->irq);
1332                 err = -EBUSY;
1333                 goto errout;
1334         }
1335         chip->irq = pci->irq;
1336
1337         pci_set_master(pci);
1338         synchronize_irq(chip->irq);
1339
1340         /* allocate memory for the BDL for each stream */
1341         if ((err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1342                                        PAGE_SIZE, &chip->bdl)) < 0) {
1343                 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
1344                 goto errout;
1345         }
1346         if (chip->position_fix == POS_FIX_POSBUF) {
1347                 /* allocate memory for the position buffer */
1348                 if ((err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
1349                                                MAX_ICH6_DEV * 8, &chip->posbuf)) < 0) {
1350                         snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
1351                         goto errout;
1352                 }
1353         }
1354         /* allocate CORB/RIRB */
1355         if ((err = azx_alloc_cmd_io(chip)) < 0)
1356                 goto errout;
1357
1358         /* initialize streams */
1359         azx_init_stream(chip);
1360
1361         /* initialize chip */
1362         azx_init_chip(chip);
1363
1364         /* codec detection */
1365         if (! chip->codec_mask) {
1366                 snd_printk(KERN_ERR SFX "no codecs found!\n");
1367                 err = -ENODEV;
1368                 goto errout;
1369         }
1370
1371         if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) <0) {
1372                 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
1373                 goto errout;
1374         }
1375
1376         *rchip = chip;
1377         return 0;
1378
1379  errout:
1380         azx_free(chip);
1381         return err;
1382 }
1383
1384 static int __devinit azx_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
1385 {
1386         static int dev;
1387         snd_card_t *card;
1388         azx_t *chip;
1389         int err = 0;
1390
1391         if (dev >= SNDRV_CARDS)
1392                 return -ENODEV;
1393         if (! enable[dev]) {
1394                 dev++;
1395                 return -ENOENT;
1396         }
1397
1398         card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
1399         if (NULL == card) {
1400                 snd_printk(KERN_ERR SFX "Error creating card!\n");
1401                 return -ENOMEM;
1402         }
1403
1404         if ((err = azx_create(card, pci, position_fix[dev], &chip)) < 0) {
1405                 snd_card_free(card);
1406                 return err;
1407         }
1408
1409         strcpy(card->driver, "HDA-Intel");
1410         strcpy(card->shortname, "HDA Intel");
1411         sprintf(card->longname, "%s at 0x%lx irq %i", card->shortname, chip->addr, chip->irq);
1412
1413         /* create codec instances */
1414         if ((err = azx_codec_create(chip, model[dev])) < 0) {
1415                 snd_card_free(card);
1416                 return err;
1417         }
1418
1419         /* create PCM streams */
1420         if ((err = azx_pcm_create(chip)) < 0) {
1421                 snd_card_free(card);
1422                 return err;
1423         }
1424
1425         /* create mixer controls */
1426         if ((err = azx_mixer_create(chip)) < 0) {
1427                 snd_card_free(card);
1428                 return err;
1429         }
1430
1431         snd_card_set_pm_callback(card, azx_suspend, azx_resume, chip);
1432         snd_card_set_dev(card, &pci->dev);
1433
1434         if ((err = snd_card_register(card)) < 0) {
1435                 snd_card_free(card);
1436                 return err;
1437         }
1438
1439         pci_set_drvdata(pci, card);
1440         dev++;
1441
1442         return err;
1443 }
1444
1445 static void __devexit azx_remove(struct pci_dev *pci)
1446 {
1447         snd_card_free(pci_get_drvdata(pci));
1448         pci_set_drvdata(pci, NULL);
1449 }
1450
1451 /* PCI IDs */
1452 static struct pci_device_id azx_ids[] = {
1453         { 0x8086, 0x2668, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ICH6 */
1454         { 0x8086, 0x27d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ICH7 */
1455         { 0x8086, 0x269a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ESB2 */
1456         { 0x1002, 0x437b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ATI SB450 */
1457         { 0x1106, 0x3288, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* VIA VT8251/VT8237A */
1458         { 0, }
1459 };
1460 MODULE_DEVICE_TABLE(pci, azx_ids);
1461
1462 /* pci_driver definition */
1463 static struct pci_driver driver = {
1464         .name = "HDA Intel",
1465         .id_table = azx_ids,
1466         .probe = azx_probe,
1467         .remove = __devexit_p(azx_remove),
1468         SND_PCI_PM_CALLBACKS
1469 };
1470
1471 static int __init alsa_card_azx_init(void)
1472 {
1473         return pci_register_driver(&driver);
1474 }
1475
1476 static void __exit alsa_card_azx_exit(void)
1477 {
1478         pci_unregister_driver(&driver);
1479 }
1480
1481 module_init(alsa_card_azx_init)
1482 module_exit(alsa_card_azx_exit)