1 /* ------------------------------------------------------------------------- */
2 /* i2c-iop3xx.c i2c driver algorithms for Intel XScale IOP3xx & IXP46x */
3 /* ------------------------------------------------------------------------- */
4 /* Copyright (C) 2003 Peter Milne, D-TACQ Solutions Ltd
5 * <Peter dot Milne at D hyphen TACQ dot com>
7 * With acknowledgements to i2c-algo-ibm_ocp.c by
8 * Ian DaSilva, MontaVista Software, Inc. idasilva@mvista.com
10 * And i2c-algo-pcf.c, which was created by Simon G. Vogl and Hans Berglund:
12 * Copyright (C) 1995-1997 Simon G. Vogl, 1998-2000 Hans Berglund
14 * And which acknowledged Kyösti Mälkki <kmalkki@cc.hut.fi>,
15 * Frodo Looijaard <frodol@dds.nl>, Martin Bailey<mbailey@littlefeet-inc.com>
17 * Major cleanup by Deepak Saxena <dsaxena@plexity.net>, 01/2005:
19 * - Use driver model to pass per-chip info instead of hardcoding and #ifdefs
20 * - Use ioremap/__raw_readl/__raw_writel instead of direct dereference
21 * - Make it work with IXP46x chips
22 * - Cleanup function names, coding style, etc
24 * This program is free software; you can redistribute it and/or modify
25 * it under the terms of the GNU General Public License as published by
26 * the Free Software Foundation, version 2.
29 #include <linux/config.h>
30 #include <linux/interrupt.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/delay.h>
34 #include <linux/slab.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/sched.h>
38 #include <linux/device.h>
39 #include <linux/i2c.h>
43 #include "i2c-iop3xx.h"
45 /* global unit counter */
46 static int i2c_id = 0;
48 static inline unsigned char
49 iic_cook_addr(struct i2c_msg *msg)
53 addr = (msg->addr << 1);
55 if (msg->flags & I2C_M_RD)
61 if (msg->flags & I2C_M_REV_DIR_ADDR)
68 iop3xx_i2c_reset(struct i2c_algo_iop3xx_data *iop3xx_adap)
70 /* Follows devman 9.3 */
71 __raw_writel(IOP3XX_ICR_UNIT_RESET, iop3xx_adap->ioaddr + CR_OFFSET);
72 __raw_writel(IOP3XX_ISR_CLEARBITS, iop3xx_adap->ioaddr + SR_OFFSET);
73 __raw_writel(0, iop3xx_adap->ioaddr + CR_OFFSET);
77 iop3xx_i2c_set_slave_addr(struct i2c_algo_iop3xx_data *iop3xx_adap)
79 __raw_writel(MYSAR, iop3xx_adap->ioaddr + SAR_OFFSET);
83 iop3xx_i2c_enable(struct i2c_algo_iop3xx_data *iop3xx_adap)
85 u32 cr = IOP3XX_ICR_GCD | IOP3XX_ICR_SCLEN | IOP3XX_ICR_UE;
88 * Every time unit enable is asserted, GPOD needs to be cleared
89 * on IOP321 to avoid data corruption on the bus.
91 #ifdef CONFIG_ARCH_IOP321
92 #define IOP321_GPOD_I2C0 0x00c0 /* clear these bits to enable ch0 */
93 #define IOP321_GPOD_I2C1 0x0030 /* clear these bits to enable ch1 */
95 *IOP321_GPOD &= (iop3xx_adap->id == 0) ? ~IOP321_GPOD_I2C0 :
98 /* NB SR bits not same position as CR IE bits :-( */
99 iop3xx_adap->SR_enabled =
100 IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD |
101 IOP3XX_ISR_RXFULL | IOP3XX_ISR_TXEMPTY;
103 cr |= IOP3XX_ICR_ALD_IE | IOP3XX_ICR_BERR_IE |
104 IOP3XX_ICR_RXFULL_IE | IOP3XX_ICR_TXEMPTY_IE;
106 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
110 iop3xx_i2c_transaction_cleanup(struct i2c_algo_iop3xx_data *iop3xx_adap)
112 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
114 cr &= ~(IOP3XX_ICR_MSTART | IOP3XX_ICR_TBYTE |
115 IOP3XX_ICR_MSTOP | IOP3XX_ICR_SCLEN);
117 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
121 * NB: the handler has to clear the source of the interrupt!
122 * Then it passes the SR flags of interest to BH via adap data
125 iop3xx_i2c_irq_handler(int this_irq, void *dev_id, struct pt_regs *regs)
127 struct i2c_algo_iop3xx_data *iop3xx_adap = dev_id;
128 u32 sr = __raw_readl(iop3xx_adap->ioaddr + SR_OFFSET);
130 if ((sr &= iop3xx_adap->SR_enabled)) {
131 __raw_writel(sr, iop3xx_adap->ioaddr + SR_OFFSET);
132 iop3xx_adap->SR_received |= sr;
133 wake_up_interruptible(&iop3xx_adap->waitq);
138 /* check all error conditions, clear them , report most important */
140 iop3xx_i2c_error(u32 sr)
144 if ((sr & IOP3XX_ISR_BERRD)) {
145 if ( !rc ) rc = -I2C_ERR_BERR;
147 if ((sr & IOP3XX_ISR_ALD)) {
148 if ( !rc ) rc = -I2C_ERR_ALD;
154 iop3xx_i2c_get_srstat(struct i2c_algo_iop3xx_data *iop3xx_adap)
159 spin_lock_irqsave(&iop3xx_adap->lock, flags);
160 sr = iop3xx_adap->SR_received;
161 iop3xx_adap->SR_received = 0;
162 spin_unlock_irqrestore(&iop3xx_adap->lock, flags);
168 * sleep until interrupted, then recover and analyse the SR
171 typedef int (* compare_func)(unsigned test, unsigned mask);
172 /* returns 1 on correct comparison */
175 iop3xx_i2c_wait_event(struct i2c_algo_iop3xx_data *iop3xx_adap,
176 unsigned flags, unsigned* status,
177 compare_func compare)
185 interrupted = wait_event_interruptible_timeout (
187 (done = compare( sr = iop3xx_i2c_get_srstat(iop3xx_adap) ,flags )),
190 if ((rc = iop3xx_i2c_error(sr)) < 0) {
193 } else if (!interrupted) {
205 * Concrete compare_funcs
208 all_bits_clear(unsigned test, unsigned mask)
210 return (test & mask) == 0;
214 any_bits_set(unsigned test, unsigned mask)
216 return (test & mask) != 0;
220 iop3xx_i2c_wait_tx_done(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status)
222 return iop3xx_i2c_wait_event(
224 IOP3XX_ISR_TXEMPTY | IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD,
225 status, any_bits_set);
229 iop3xx_i2c_wait_rx_done(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status)
231 return iop3xx_i2c_wait_event(
233 IOP3XX_ISR_RXFULL | IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD,
234 status, any_bits_set);
238 iop3xx_i2c_wait_idle(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status)
240 return iop3xx_i2c_wait_event(
241 iop3xx_adap, IOP3XX_ISR_UNITBUSY, status, all_bits_clear);
245 iop3xx_i2c_send_target_addr(struct i2c_algo_iop3xx_data *iop3xx_adap,
248 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
252 __raw_writel(iic_cook_addr(msg), iop3xx_adap->ioaddr + DBR_OFFSET);
254 cr &= ~(IOP3XX_ICR_MSTOP | IOP3XX_ICR_NACK);
255 cr |= IOP3XX_ICR_MSTART | IOP3XX_ICR_TBYTE;
257 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
258 rc = iop3xx_i2c_wait_tx_done(iop3xx_adap, &status);
264 iop3xx_i2c_write_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char byte,
267 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
271 __raw_writel(byte, iop3xx_adap->ioaddr + DBR_OFFSET);
272 cr &= ~IOP3XX_ICR_MSTART;
274 cr |= IOP3XX_ICR_MSTOP;
276 cr &= ~IOP3XX_ICR_MSTOP;
278 cr |= IOP3XX_ICR_TBYTE;
279 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
280 rc = iop3xx_i2c_wait_tx_done(iop3xx_adap, &status);
286 iop3xx_i2c_read_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char* byte,
289 unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
293 cr &= ~IOP3XX_ICR_MSTART;
296 cr |= IOP3XX_ICR_MSTOP | IOP3XX_ICR_NACK;
298 cr &= ~(IOP3XX_ICR_MSTOP | IOP3XX_ICR_NACK);
300 cr |= IOP3XX_ICR_TBYTE;
301 __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
303 rc = iop3xx_i2c_wait_rx_done(iop3xx_adap, &status);
305 *byte = __raw_readl(iop3xx_adap->ioaddr + DBR_OFFSET);
311 iop3xx_i2c_writebytes(struct i2c_adapter *i2c_adap, const char *buf, int count)
313 struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
317 for (ii = 0; rc == 0 && ii != count; ++ii)
318 rc = iop3xx_i2c_write_byte(iop3xx_adap, buf[ii], ii==count-1);
323 iop3xx_i2c_readbytes(struct i2c_adapter *i2c_adap, char *buf, int count)
325 struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
329 for (ii = 0; rc == 0 && ii != count; ++ii)
330 rc = iop3xx_i2c_read_byte(iop3xx_adap, &buf[ii], ii==count-1);
336 * Description: This function implements combined transactions. Combined
337 * transactions consist of combinations of reading and writing blocks of data.
338 * FROM THE SAME ADDRESS
339 * Each transfer (i.e. a read or a write) is separated by a repeated start
343 iop3xx_i2c_handle_msg(struct i2c_adapter *i2c_adap, struct i2c_msg* pmsg)
345 struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
348 rc = iop3xx_i2c_send_target_addr(iop3xx_adap, pmsg);
353 if ((pmsg->flags&I2C_M_RD)) {
354 return iop3xx_i2c_readbytes(i2c_adap, pmsg->buf, pmsg->len);
356 return iop3xx_i2c_writebytes(i2c_adap, pmsg->buf, pmsg->len);
361 * master_xfer() - main read/write entry
364 iop3xx_i2c_master_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
367 struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
372 iop3xx_i2c_wait_idle(iop3xx_adap, &status);
373 iop3xx_i2c_reset(iop3xx_adap);
374 iop3xx_i2c_enable(iop3xx_adap);
376 for (im = 0; ret == 0 && im != num; im++) {
377 ret = iop3xx_i2c_handle_msg(i2c_adap, &msgs[im]);
380 iop3xx_i2c_transaction_cleanup(iop3xx_adap);
389 iop3xx_i2c_algo_control(struct i2c_adapter *adapter, unsigned int cmd,
396 iop3xx_i2c_func(struct i2c_adapter *adap)
398 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
401 static struct i2c_algorithm iop3xx_i2c_algo = {
402 .name = "IOP3xx I2C algorithm",
403 .id = I2C_ALGO_IOP3XX,
404 .master_xfer = iop3xx_i2c_master_xfer,
405 .algo_control = iop3xx_i2c_algo_control,
406 .functionality = iop3xx_i2c_func,
410 iop3xx_i2c_remove(struct device *device)
412 struct platform_device *pdev = to_platform_device(device);
413 struct i2c_adapter *padapter = dev_get_drvdata(&pdev->dev);
414 struct i2c_algo_iop3xx_data *adapter_data =
415 (struct i2c_algo_iop3xx_data *)padapter->algo_data;
416 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
417 unsigned long cr = __raw_readl(adapter_data->ioaddr + CR_OFFSET);
420 * Disable the actual HW unit
422 cr &= ~(IOP3XX_ICR_ALD_IE | IOP3XX_ICR_BERR_IE |
423 IOP3XX_ICR_RXFULL_IE | IOP3XX_ICR_TXEMPTY_IE);
424 __raw_writel(cr, adapter_data->ioaddr + CR_OFFSET);
426 iounmap((void __iomem*)adapter_data->ioaddr);
427 release_mem_region(res->start, IOP3XX_I2C_IO_SIZE);
431 dev_set_drvdata(&pdev->dev, NULL);
437 iop3xx_i2c_probe(struct device *dev)
439 struct platform_device *pdev = to_platform_device(dev);
440 struct resource *res;
442 struct i2c_adapter *new_adapter;
443 struct i2c_algo_iop3xx_data *adapter_data;
445 new_adapter = kmalloc(sizeof(struct i2c_adapter), GFP_KERNEL);
450 memset((void*)new_adapter, 0, sizeof(*new_adapter));
452 adapter_data = kmalloc(sizeof(struct i2c_algo_iop3xx_data), GFP_KERNEL);
457 memset((void*)adapter_data, 0, sizeof(*adapter_data));
459 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
465 if (!request_mem_region(res->start, IOP3XX_I2C_IO_SIZE, pdev->name)) {
470 /* set the adapter enumeration # */
471 adapter_data->id = i2c_id++;
473 adapter_data->ioaddr = (u32)ioremap(res->start, IOP3XX_I2C_IO_SIZE);
474 if (!adapter_data->ioaddr) {
479 res = request_irq(platform_get_irq(pdev, 0), iop3xx_i2c_irq_handler, 0,
480 pdev->name, adapter_data);
486 memcpy(new_adapter->name, pdev->name, strlen(pdev->name));
487 new_adapter->id = I2C_HW_IOP3XX;
488 new_adapter->owner = THIS_MODULE;
489 new_adapter->dev.parent = &pdev->dev;
492 * Default values...should these come in from board code?
494 new_adapter->timeout = 100;
495 new_adapter->retries = 3;
496 new_adapter->algo = &iop3xx_i2c_algo;
498 init_waitqueue_head(&adapter_data->waitq);
499 spin_lock_init(&adapter_data->lock);
501 iop3xx_i2c_reset(adapter_data);
502 iop3xx_i2c_set_slave_addr(adapter_data);
503 iop3xx_i2c_enable(adapter_data);
505 dev_set_drvdata(&pdev->dev, new_adapter);
506 new_adapter->algo_data = adapter_data;
508 i2c_add_adapter(new_adapter);
513 iounmap((void __iomem*)adapter_data->ioaddr);
516 release_mem_region(res->start, IOP3XX_I2C_IO_SIZE);
529 static struct device_driver iop3xx_i2c_driver = {
530 .name = "IOP3xx-I2C",
531 .bus = &platform_bus_type,
532 .probe = iop3xx_i2c_probe,
533 .remove = iop3xx_i2c_remove
537 i2c_iop3xx_init (void)
539 return driver_register(&iop3xx_i2c_driver);
543 i2c_iop3xx_exit (void)
545 driver_unregister(&iop3xx_i2c_driver);
549 module_init (i2c_iop3xx_init);
550 module_exit (i2c_iop3xx_exit);
552 MODULE_AUTHOR("D-TACQ Solutions Ltd <www.d-tacq.com>");
553 MODULE_DESCRIPTION("IOP3xx iic algorithm and driver");
554 MODULE_LICENSE("GPL");