git.oblomov.eu Git - linux-2.6/blob - drivers/net/ixgbe/ixgbe_ethtool.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 /* ethtool support for ixgbe */
  29
  30 #include <linux/types.h>
  31 #include <linux/module.h>
  32 #include <linux/pci.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/ethtool.h>
  35 #include <linux/vmalloc.h>
  36 #include <linux/uaccess.h>
  37
  38 #include "ixgbe.h"
  39
  40
  41 #define IXGBE_ALL_RAR_ENTRIES 16
  42
  43 struct ixgbe_stats {
  44         char stat_string[ETH_GSTRING_LEN];
  45         int sizeof_stat;
  46         int stat_offset;
  47 };
  48
  49 #define IXGBE_STAT(m) sizeof(((struct ixgbe_adapter *)0)->m), \
  50                              offsetof(struct ixgbe_adapter, m)
  51 static struct ixgbe_stats ixgbe_gstrings_stats[] = {
  52         {"rx_packets", IXGBE_STAT(net_stats.rx_packets)},
  53         {"tx_packets", IXGBE_STAT(net_stats.tx_packets)},
  54         {"rx_bytes", IXGBE_STAT(net_stats.rx_bytes)},
  55         {"tx_bytes", IXGBE_STAT(net_stats.tx_bytes)},
  56         {"lsc_int", IXGBE_STAT(lsc_int)},
  57         {"tx_busy", IXGBE_STAT(tx_busy)},
  58         {"non_eop_descs", IXGBE_STAT(non_eop_descs)},
  59         {"rx_errors", IXGBE_STAT(net_stats.rx_errors)},
  60         {"tx_errors", IXGBE_STAT(net_stats.tx_errors)},
  61         {"rx_dropped", IXGBE_STAT(net_stats.rx_dropped)},
  62         {"tx_dropped", IXGBE_STAT(net_stats.tx_dropped)},
  63         {"multicast", IXGBE_STAT(net_stats.multicast)},
  64         {"broadcast", IXGBE_STAT(stats.bprc)},
  65         {"rx_no_buffer_count", IXGBE_STAT(stats.rnbc[0]) },
  66         {"collisions", IXGBE_STAT(net_stats.collisions)},
  67         {"rx_over_errors", IXGBE_STAT(net_stats.rx_over_errors)},
  68         {"rx_crc_errors", IXGBE_STAT(net_stats.rx_crc_errors)},
  69         {"rx_frame_errors", IXGBE_STAT(net_stats.rx_frame_errors)},
  70         {"hw_rsc_count", IXGBE_STAT(rsc_count)},
  71         {"rx_fifo_errors", IXGBE_STAT(net_stats.rx_fifo_errors)},
  72         {"rx_missed_errors", IXGBE_STAT(net_stats.rx_missed_errors)},
  73         {"tx_aborted_errors", IXGBE_STAT(net_stats.tx_aborted_errors)},
  74         {"tx_carrier_errors", IXGBE_STAT(net_stats.tx_carrier_errors)},
  75         {"tx_fifo_errors", IXGBE_STAT(net_stats.tx_fifo_errors)},
  76         {"tx_heartbeat_errors", IXGBE_STAT(net_stats.tx_heartbeat_errors)},
  77         {"tx_timeout_count", IXGBE_STAT(tx_timeout_count)},
  78         {"tx_restart_queue", IXGBE_STAT(restart_queue)},
  79         {"rx_long_length_errors", IXGBE_STAT(stats.roc)},
  80         {"rx_short_length_errors", IXGBE_STAT(stats.ruc)},
  81         {"tx_tcp4_seg_ctxt", IXGBE_STAT(hw_tso_ctxt)},
  82         {"tx_tcp6_seg_ctxt", IXGBE_STAT(hw_tso6_ctxt)},
  83         {"tx_flow_control_xon", IXGBE_STAT(stats.lxontxc)},
  84         {"rx_flow_control_xon", IXGBE_STAT(stats.lxonrxc)},
  85         {"tx_flow_control_xoff", IXGBE_STAT(stats.lxofftxc)},
  86         {"rx_flow_control_xoff", IXGBE_STAT(stats.lxoffrxc)},
  87         {"rx_csum_offload_good", IXGBE_STAT(hw_csum_rx_good)},
  88         {"rx_csum_offload_errors", IXGBE_STAT(hw_csum_rx_error)},
  89         {"tx_csum_offload_ctxt", IXGBE_STAT(hw_csum_tx_good)},
  90         {"rx_header_split", IXGBE_STAT(rx_hdr_split)},
  91         {"alloc_rx_page_failed", IXGBE_STAT(alloc_rx_page_failed)},
  92         {"alloc_rx_buff_failed", IXGBE_STAT(alloc_rx_buff_failed)},
  93         {"rx_no_dma_resources", IXGBE_STAT(hw_rx_no_dma_resources)},
  94 #ifdef IXGBE_FCOE
  95         {"fcoe_bad_fccrc", IXGBE_STAT(stats.fccrc)},
  96         {"rx_fcoe_dropped", IXGBE_STAT(stats.fcoerpdc)},
  97         {"rx_fcoe_packets", IXGBE_STAT(stats.fcoeprc)},
  98         {"rx_fcoe_dwords", IXGBE_STAT(stats.fcoedwrc)},
  99         {"tx_fcoe_packets", IXGBE_STAT(stats.fcoeptc)},
 100         {"tx_fcoe_dwords", IXGBE_STAT(stats.fcoedwtc)},
 101 #endif /* IXGBE_FCOE */
 102 };
 103
 104 #define IXGBE_QUEUE_STATS_LEN \
 105         ((((struct ixgbe_adapter *)netdev_priv(netdev))->num_tx_queues + \
 106         ((struct ixgbe_adapter *)netdev_priv(netdev))->num_rx_queues) * \
 107         (sizeof(struct ixgbe_queue_stats) / sizeof(u64)))
 108 #define IXGBE_GLOBAL_STATS_LEN ARRAY_SIZE(ixgbe_gstrings_stats)
 109 #define IXGBE_PB_STATS_LEN ( \
 110                  (((struct ixgbe_adapter *)netdev_priv(netdev))->flags & \
 111                  IXGBE_FLAG_DCB_ENABLED) ? \
 112                  (sizeof(((struct ixgbe_adapter *)0)->stats.pxonrxc) + \
 113                   sizeof(((struct ixgbe_adapter *)0)->stats.pxontxc) + \
 114                   sizeof(((struct ixgbe_adapter *)0)->stats.pxoffrxc) + \
 115                   sizeof(((struct ixgbe_adapter *)0)->stats.pxofftxc)) \
 116                   / sizeof(u64) : 0)
 117 #define IXGBE_STATS_LEN (IXGBE_GLOBAL_STATS_LEN + \
 118                          IXGBE_PB_STATS_LEN + \
 119                          IXGBE_QUEUE_STATS_LEN)
 120
 121 static const char ixgbe_gstrings_test[][ETH_GSTRING_LEN] = {
 122         "Register test  (offline)", "Eeprom test    (offline)",
 123         "Interrupt test (offline)", "Loopback test  (offline)",
 124         "Link test   (on/offline)"
 125 };
 126 #define IXGBE_TEST_LEN sizeof(ixgbe_gstrings_test) / ETH_GSTRING_LEN
 127
 128 static int ixgbe_get_settings(struct net_device *netdev,
 129                               struct ethtool_cmd *ecmd)
 130 {
 131         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 132         struct ixgbe_hw *hw = &adapter->hw;
 133         u32 link_speed = 0;
 134         bool link_up;
 135
 136         ecmd->supported = SUPPORTED_10000baseT_Full;
 137         ecmd->autoneg = AUTONEG_ENABLE;
 138         ecmd->transceiver = XCVR_EXTERNAL;
 139         if (hw->phy.media_type == ixgbe_media_type_copper) {
 140                 ecmd->supported |= (SUPPORTED_1000baseT_Full |
 141                                     SUPPORTED_TP | SUPPORTED_Autoneg);
 142
 143                 ecmd->advertising = (ADVERTISED_TP | ADVERTISED_Autoneg);
 144                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 145                         ecmd->advertising |= ADVERTISED_10000baseT_Full;
 146                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 147                         ecmd->advertising |= ADVERTISED_1000baseT_Full;
 148                 /*
 149                  * It's possible that phy.autoneg_advertised may not be
 150                  * set yet.  If so display what the default would be -
 151                  * both 1G and 10G supported.
 152                  */
 153                 if (!(ecmd->advertising & (ADVERTISED_1000baseT_Full |
 154                                            ADVERTISED_10000baseT_Full)))
 155                         ecmd->advertising |= (ADVERTISED_10000baseT_Full |
 156                                               ADVERTISED_1000baseT_Full);
 157
 158                 ecmd->port = PORT_TP;
 159         } else if (hw->phy.media_type == ixgbe_media_type_backplane) {
 160                 /* Set as FIBRE until SERDES defined in kernel */
 161                 switch (hw->device_id) {
 162                 case IXGBE_DEV_ID_82598:
 163                         ecmd->supported |= (SUPPORTED_1000baseT_Full |
 164                                 SUPPORTED_FIBRE);
 165                         ecmd->advertising = (ADVERTISED_10000baseT_Full |
 166                                 ADVERTISED_1000baseT_Full |
 167                                 ADVERTISED_FIBRE);
 168                         ecmd->port = PORT_FIBRE;
 169                         break;
 170                 case IXGBE_DEV_ID_82598_BX:
 171                         ecmd->supported = (SUPPORTED_1000baseT_Full |
 172                                            SUPPORTED_FIBRE);
 173                         ecmd->advertising = (ADVERTISED_1000baseT_Full |
 174                                              ADVERTISED_FIBRE);
 175                         ecmd->port = PORT_FIBRE;
 176                         ecmd->autoneg = AUTONEG_DISABLE;
 177                         break;
 178                 }
 179         } else {
 180                 ecmd->supported |= SUPPORTED_FIBRE;
 181                 ecmd->advertising = (ADVERTISED_10000baseT_Full |
 182                                      ADVERTISED_FIBRE);
 183                 ecmd->port = PORT_FIBRE;
 184                 ecmd->autoneg = AUTONEG_DISABLE;
 185         }
 186
 187         hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
 188         if (link_up) {
 189                 ecmd->speed = (link_speed == IXGBE_LINK_SPEED_10GB_FULL) ?
 190                                SPEED_10000 : SPEED_1000;
 191                 ecmd->duplex = DUPLEX_FULL;
 192         } else {
 193                 ecmd->speed = -1;
 194                 ecmd->duplex = -1;
 195         }
 196
 197         return 0;
 198 }
 199
 200 static int ixgbe_set_settings(struct net_device *netdev,
 201                               struct ethtool_cmd *ecmd)
 202 {
 203         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 204         struct ixgbe_hw *hw = &adapter->hw;
 205         u32 advertised, old;
 206         s32 err;
 207
 208         switch (hw->phy.media_type) {
 209         case ixgbe_media_type_fiber:
 210                 if ((ecmd->autoneg == AUTONEG_ENABLE) ||
 211                     (ecmd->speed + ecmd->duplex != SPEED_10000 + DUPLEX_FULL))
 212                         return -EINVAL;
 213                 /* in this case we currently only support 10Gb/FULL */
 214                 break;
 215         case ixgbe_media_type_copper:
 216                 /* 10000/copper and 1000/copper must autoneg
 217                  * this function does not support any duplex forcing, but can
 218                  * limit the advertising of the adapter to only 10000 or 1000 */
 219                 if (ecmd->autoneg == AUTONEG_DISABLE)
 220                         return -EINVAL;
 221
 222                 old = hw->phy.autoneg_advertised;
 223                 advertised = 0;
 224                 if (ecmd->advertising & ADVERTISED_10000baseT_Full)
 225                         advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 226
 227                 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
 228                         advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 229
 230                 if (old == advertised)
 231                         break;
 232                 /* this sets the link speed and restarts auto-neg */
 233                 err = hw->mac.ops.setup_link_speed(hw, advertised, true, true);
 234                 if (err) {
 235                         DPRINTK(PROBE, INFO,
 236                                 "setup link failed with code %d\n", err);
 237                         hw->mac.ops.setup_link_speed(hw, old, true, true);
 238                 }
 239                 break;
 240         default:
 241                 break;
 242         }
 243
 244         return 0;
 245 }
 246
 247 static void ixgbe_get_pauseparam(struct net_device *netdev,
 248                                  struct ethtool_pauseparam *pause)
 249 {
 250         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 251         struct ixgbe_hw *hw = &adapter->hw;
 252
 253         /*
 254          * Flow Control Autoneg isn't on if
 255          *  - we didn't ask for it OR
 256          *  - it failed, we know this by tx & rx being off
 257          */
 258         if (hw->fc.disable_fc_autoneg ||
 259             (hw->fc.current_mode == ixgbe_fc_none))
 260                 pause->autoneg = 0;
 261         else
 262                 pause->autoneg = 1;
 263
 264 #ifdef CONFIG_DCB
 265         if (hw->fc.current_mode == ixgbe_fc_pfc) {
 266                 pause->rx_pause = 0;
 267                 pause->tx_pause = 0;
 268         }
 269
 270 #endif
 271         if (hw->fc.current_mode == ixgbe_fc_rx_pause) {
 272                 pause->rx_pause = 1;
 273         } else if (hw->fc.current_mode == ixgbe_fc_tx_pause) {
 274                 pause->tx_pause = 1;
 275         } else if (hw->fc.current_mode == ixgbe_fc_full) {
 276                 pause->rx_pause = 1;
 277                 pause->tx_pause = 1;
 278         }
 279 }
 280
 281 static int ixgbe_set_pauseparam(struct net_device *netdev,
 282                                 struct ethtool_pauseparam *pause)
 283 {
 284         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 285         struct ixgbe_hw *hw = &adapter->hw;
 286
 287 #ifdef CONFIG_DCB
 288         if (adapter->dcb_cfg.pfc_mode_enable ||
 289                 ((hw->mac.type == ixgbe_mac_82598EB) &&
 290                 (adapter->flags & IXGBE_FLAG_DCB_ENABLED)))
 291                 return -EINVAL;
 292
 293 #endif
 294         if (pause->autoneg != AUTONEG_ENABLE)
 295                 hw->fc.disable_fc_autoneg = true;
 296         else
 297                 hw->fc.disable_fc_autoneg = false;
 298
 299         if (pause->rx_pause && pause->tx_pause)
 300                 hw->fc.requested_mode = ixgbe_fc_full;
 301         else if (pause->rx_pause && !pause->tx_pause)
 302                 hw->fc.requested_mode = ixgbe_fc_rx_pause;
 303         else if (!pause->rx_pause && pause->tx_pause)
 304                 hw->fc.requested_mode = ixgbe_fc_tx_pause;
 305         else if (!pause->rx_pause && !pause->tx_pause)
 306                 hw->fc.requested_mode = ixgbe_fc_none;
 307         else
 308                 return -EINVAL;
 309
 310 #ifdef CONFIG_DCB
 311         adapter->last_lfc_mode = hw->fc.requested_mode;
 312 #endif
 313         hw->mac.ops.setup_fc(hw, 0);
 314
 315         return 0;
 316 }
 317
 318 static u32 ixgbe_get_rx_csum(struct net_device *netdev)
 319 {
 320         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 321         return (adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED);
 322 }
 323
 324 static int ixgbe_set_rx_csum(struct net_device *netdev, u32 data)
 325 {
 326         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 327         if (data)
 328                 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
 329         else
 330                 adapter->flags &= ~IXGBE_FLAG_RX_CSUM_ENABLED;
 331
 332         if (netif_running(netdev))
 333                 ixgbe_reinit_locked(adapter);
 334         else
 335                 ixgbe_reset(adapter);
 336
 337         return 0;
 338 }
 339
 340 static u32 ixgbe_get_tx_csum(struct net_device *netdev)
 341 {
 342         return (netdev->features & NETIF_F_IP_CSUM) != 0;
 343 }
 344
 345 static int ixgbe_set_tx_csum(struct net_device *netdev, u32 data)
 346 {
 347         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 348
 349         if (data) {
 350                 netdev->features |= (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
 351                 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
 352                         netdev->features |= NETIF_F_SCTP_CSUM;
 353         } else {
 354                 netdev->features &= ~(NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM);
 355                 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
 356                         netdev->features &= ~NETIF_F_SCTP_CSUM;
 357         }
 358
 359         return 0;
 360 }
 361
 362 static int ixgbe_set_tso(struct net_device *netdev, u32 data)
 363 {
 364         if (data) {
 365                 netdev->features |= NETIF_F_TSO;
 366                 netdev->features |= NETIF_F_TSO6;
 367         } else {
 368                 netif_tx_stop_all_queues(netdev);
 369                 netdev->features &= ~NETIF_F_TSO;
 370                 netdev->features &= ~NETIF_F_TSO6;
 371                 netif_tx_start_all_queues(netdev);
 372         }
 373         return 0;
 374 }
 375
 376 static u32 ixgbe_get_msglevel(struct net_device *netdev)
 377 {
 378         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 379         return adapter->msg_enable;
 380 }
 381
 382 static void ixgbe_set_msglevel(struct net_device *netdev, u32 data)
 383 {
 384         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 385         adapter->msg_enable = data;
 386 }
 387
 388 static int ixgbe_get_regs_len(struct net_device *netdev)
 389 {
 390 #define IXGBE_REGS_LEN  1128
 391         return IXGBE_REGS_LEN * sizeof(u32);
 392 }
 393
 394 #define IXGBE_GET_STAT(_A_, _R_) _A_->stats._R_
 395
 396 static void ixgbe_get_regs(struct net_device *netdev,
 397                            struct ethtool_regs *regs, void *p)
 398 {
 399         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 400         struct ixgbe_hw *hw = &adapter->hw;
 401         u32 *regs_buff = p;
 402         u8 i;
 403
 404         memset(p, 0, IXGBE_REGS_LEN * sizeof(u32));
 405
 406         regs->version = (1 << 24) | hw->revision_id << 16 | hw->device_id;
 407
 408         /* General Registers */
 409         regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL);
 410         regs_buff[1] = IXGBE_READ_REG(hw, IXGBE_STATUS);
 411         regs_buff[2] = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 412         regs_buff[3] = IXGBE_READ_REG(hw, IXGBE_ESDP);
 413         regs_buff[4] = IXGBE_READ_REG(hw, IXGBE_EODSDP);
 414         regs_buff[5] = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
 415         regs_buff[6] = IXGBE_READ_REG(hw, IXGBE_FRTIMER);
 416         regs_buff[7] = IXGBE_READ_REG(hw, IXGBE_TCPTIMER);
 417
 418         /* NVM Register */
 419         regs_buff[8] = IXGBE_READ_REG(hw, IXGBE_EEC);
 420         regs_buff[9] = IXGBE_READ_REG(hw, IXGBE_EERD);
 421         regs_buff[10] = IXGBE_READ_REG(hw, IXGBE_FLA);
 422         regs_buff[11] = IXGBE_READ_REG(hw, IXGBE_EEMNGCTL);
 423         regs_buff[12] = IXGBE_READ_REG(hw, IXGBE_EEMNGDATA);
 424         regs_buff[13] = IXGBE_READ_REG(hw, IXGBE_FLMNGCTL);
 425         regs_buff[14] = IXGBE_READ_REG(hw, IXGBE_FLMNGDATA);
 426         regs_buff[15] = IXGBE_READ_REG(hw, IXGBE_FLMNGCNT);
 427         regs_buff[16] = IXGBE_READ_REG(hw, IXGBE_FLOP);
 428         regs_buff[17] = IXGBE_READ_REG(hw, IXGBE_GRC);
 429
 430         /* Interrupt */
 431         /* don't read EICR because it can clear interrupt causes, instead
 432          * read EICS which is a shadow but doesn't clear EICR */
 433         regs_buff[18] = IXGBE_READ_REG(hw, IXGBE_EICS);
 434         regs_buff[19] = IXGBE_READ_REG(hw, IXGBE_EICS);
 435         regs_buff[20] = IXGBE_READ_REG(hw, IXGBE_EIMS);
 436         regs_buff[21] = IXGBE_READ_REG(hw, IXGBE_EIMC);
 437         regs_buff[22] = IXGBE_READ_REG(hw, IXGBE_EIAC);
 438         regs_buff[23] = IXGBE_READ_REG(hw, IXGBE_EIAM);
 439         regs_buff[24] = IXGBE_READ_REG(hw, IXGBE_EITR(0));
 440         regs_buff[25] = IXGBE_READ_REG(hw, IXGBE_IVAR(0));
 441         regs_buff[26] = IXGBE_READ_REG(hw, IXGBE_MSIXT);
 442         regs_buff[27] = IXGBE_READ_REG(hw, IXGBE_MSIXPBA);
 443         regs_buff[28] = IXGBE_READ_REG(hw, IXGBE_PBACL(0));
 444         regs_buff[29] = IXGBE_READ_REG(hw, IXGBE_GPIE);
 445
 446         /* Flow Control */
 447         regs_buff[30] = IXGBE_READ_REG(hw, IXGBE_PFCTOP);
 448         regs_buff[31] = IXGBE_READ_REG(hw, IXGBE_FCTTV(0));
 449         regs_buff[32] = IXGBE_READ_REG(hw, IXGBE_FCTTV(1));
 450         regs_buff[33] = IXGBE_READ_REG(hw, IXGBE_FCTTV(2));
 451         regs_buff[34] = IXGBE_READ_REG(hw, IXGBE_FCTTV(3));
 452         for (i = 0; i < 8; i++)
 453                 regs_buff[35 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTL(i));
 454         for (i = 0; i < 8; i++)
 455                 regs_buff[43 + i] = IXGBE_READ_REG(hw, IXGBE_FCRTH(i));
 456         regs_buff[51] = IXGBE_READ_REG(hw, IXGBE_FCRTV);
 457         regs_buff[52] = IXGBE_READ_REG(hw, IXGBE_TFCS);
 458
 459         /* Receive DMA */
 460         for (i = 0; i < 64; i++)
 461                 regs_buff[53 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
 462         for (i = 0; i < 64; i++)
 463                 regs_buff[117 + i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
 464         for (i = 0; i < 64; i++)
 465                 regs_buff[181 + i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
 466         for (i = 0; i < 64; i++)
 467                 regs_buff[245 + i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
 468         for (i = 0; i < 64; i++)
 469                 regs_buff[309 + i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
 470         for (i = 0; i < 64; i++)
 471                 regs_buff[373 + i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
 472         for (i = 0; i < 16; i++)
 473                 regs_buff[437 + i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
 474         for (i = 0; i < 16; i++)
 475                 regs_buff[453 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
 476         regs_buff[469] = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
 477         for (i = 0; i < 8; i++)
 478                 regs_buff[470 + i] = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i));
 479         regs_buff[478] = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
 480         regs_buff[479] = IXGBE_READ_REG(hw, IXGBE_DROPEN);
 481
 482         /* Receive */
 483         regs_buff[480] = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
 484         regs_buff[481] = IXGBE_READ_REG(hw, IXGBE_RFCTL);
 485         for (i = 0; i < 16; i++)
 486                 regs_buff[482 + i] = IXGBE_READ_REG(hw, IXGBE_RAL(i));
 487         for (i = 0; i < 16; i++)
 488                 regs_buff[498 + i] = IXGBE_READ_REG(hw, IXGBE_RAH(i));
 489         regs_buff[514] = IXGBE_READ_REG(hw, IXGBE_PSRTYPE(0));
 490         regs_buff[515] = IXGBE_READ_REG(hw, IXGBE_FCTRL);
 491         regs_buff[516] = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
 492         regs_buff[517] = IXGBE_READ_REG(hw, IXGBE_MCSTCTRL);
 493         regs_buff[518] = IXGBE_READ_REG(hw, IXGBE_MRQC);
 494         regs_buff[519] = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
 495         for (i = 0; i < 8; i++)
 496                 regs_buff[520 + i] = IXGBE_READ_REG(hw, IXGBE_IMIR(i));
 497         for (i = 0; i < 8; i++)
 498                 regs_buff[528 + i] = IXGBE_READ_REG(hw, IXGBE_IMIREXT(i));
 499         regs_buff[536] = IXGBE_READ_REG(hw, IXGBE_IMIRVP);
 500
 501         /* Transmit */
 502         for (i = 0; i < 32; i++)
 503                 regs_buff[537 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
 504         for (i = 0; i < 32; i++)
 505                 regs_buff[569 + i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
 506         for (i = 0; i < 32; i++)
 507                 regs_buff[601 + i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
 508         for (i = 0; i < 32; i++)
 509                 regs_buff[633 + i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
 510         for (i = 0; i < 32; i++)
 511                 regs_buff[665 + i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
 512         for (i = 0; i < 32; i++)
 513                 regs_buff[697 + i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
 514         for (i = 0; i < 32; i++)
 515                 regs_buff[729 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAL(i));
 516         for (i = 0; i < 32; i++)
 517                 regs_buff[761 + i] = IXGBE_READ_REG(hw, IXGBE_TDWBAH(i));
 518         regs_buff[793] = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
 519         for (i = 0; i < 16; i++)
 520                 regs_buff[794 + i] = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
 521         regs_buff[810] = IXGBE_READ_REG(hw, IXGBE_TIPG);
 522         for (i = 0; i < 8; i++)
 523                 regs_buff[811 + i] = IXGBE_READ_REG(hw, IXGBE_TXPBSIZE(i));
 524         regs_buff[819] = IXGBE_READ_REG(hw, IXGBE_MNGTXMAP);
 525
 526         /* Wake Up */
 527         regs_buff[820] = IXGBE_READ_REG(hw, IXGBE_WUC);
 528         regs_buff[821] = IXGBE_READ_REG(hw, IXGBE_WUFC);
 529         regs_buff[822] = IXGBE_READ_REG(hw, IXGBE_WUS);
 530         regs_buff[823] = IXGBE_READ_REG(hw, IXGBE_IPAV);
 531         regs_buff[824] = IXGBE_READ_REG(hw, IXGBE_IP4AT);
 532         regs_buff[825] = IXGBE_READ_REG(hw, IXGBE_IP6AT);
 533         regs_buff[826] = IXGBE_READ_REG(hw, IXGBE_WUPL);
 534         regs_buff[827] = IXGBE_READ_REG(hw, IXGBE_WUPM);
 535         regs_buff[828] = IXGBE_READ_REG(hw, IXGBE_FHFT(0));
 536
 537         regs_buff[829] = IXGBE_READ_REG(hw, IXGBE_RMCS);
 538         regs_buff[830] = IXGBE_READ_REG(hw, IXGBE_DPMCS);
 539         regs_buff[831] = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
 540         regs_buff[832] = IXGBE_READ_REG(hw, IXGBE_RUPPBMR);
 541         for (i = 0; i < 8; i++)
 542                 regs_buff[833 + i] = IXGBE_READ_REG(hw, IXGBE_RT2CR(i));
 543         for (i = 0; i < 8; i++)
 544                 regs_buff[841 + i] = IXGBE_READ_REG(hw, IXGBE_RT2SR(i));
 545         for (i = 0; i < 8; i++)
 546                 regs_buff[849 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCCR(i));
 547         for (i = 0; i < 8; i++)
 548                 regs_buff[857 + i] = IXGBE_READ_REG(hw, IXGBE_TDTQ2TCSR(i));
 549         for (i = 0; i < 8; i++)
 550                 regs_buff[865 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCCR(i));
 551         for (i = 0; i < 8; i++)
 552                 regs_buff[873 + i] = IXGBE_READ_REG(hw, IXGBE_TDPT2TCSR(i));
 553
 554         /* Statistics */
 555         regs_buff[881] = IXGBE_GET_STAT(adapter, crcerrs);
 556         regs_buff[882] = IXGBE_GET_STAT(adapter, illerrc);
 557         regs_buff[883] = IXGBE_GET_STAT(adapter, errbc);
 558         regs_buff[884] = IXGBE_GET_STAT(adapter, mspdc);
 559         for (i = 0; i < 8; i++)
 560                 regs_buff[885 + i] = IXGBE_GET_STAT(adapter, mpc[i]);
 561         regs_buff[893] = IXGBE_GET_STAT(adapter, mlfc);
 562         regs_buff[894] = IXGBE_GET_STAT(adapter, mrfc);
 563         regs_buff[895] = IXGBE_GET_STAT(adapter, rlec);
 564         regs_buff[896] = IXGBE_GET_STAT(adapter, lxontxc);
 565         regs_buff[897] = IXGBE_GET_STAT(adapter, lxonrxc);
 566         regs_buff[898] = IXGBE_GET_STAT(adapter, lxofftxc);
 567         regs_buff[899] = IXGBE_GET_STAT(adapter, lxoffrxc);
 568         for (i = 0; i < 8; i++)
 569                 regs_buff[900 + i] = IXGBE_GET_STAT(adapter, pxontxc[i]);
 570         for (i = 0; i < 8; i++)
 571                 regs_buff[908 + i] = IXGBE_GET_STAT(adapter, pxonrxc[i]);
 572         for (i = 0; i < 8; i++)
 573                 regs_buff[916 + i] = IXGBE_GET_STAT(adapter, pxofftxc[i]);
 574         for (i = 0; i < 8; i++)
 575                 regs_buff[924 + i] = IXGBE_GET_STAT(adapter, pxoffrxc[i]);
 576         regs_buff[932] = IXGBE_GET_STAT(adapter, prc64);
 577         regs_buff[933] = IXGBE_GET_STAT(adapter, prc127);
 578         regs_buff[934] = IXGBE_GET_STAT(adapter, prc255);
 579         regs_buff[935] = IXGBE_GET_STAT(adapter, prc511);
 580         regs_buff[936] = IXGBE_GET_STAT(adapter, prc1023);
 581         regs_buff[937] = IXGBE_GET_STAT(adapter, prc1522);
 582         regs_buff[938] = IXGBE_GET_STAT(adapter, gprc);
 583         regs_buff[939] = IXGBE_GET_STAT(adapter, bprc);
 584         regs_buff[940] = IXGBE_GET_STAT(adapter, mprc);
 585         regs_buff[941] = IXGBE_GET_STAT(adapter, gptc);
 586         regs_buff[942] = IXGBE_GET_STAT(adapter, gorc);
 587         regs_buff[944] = IXGBE_GET_STAT(adapter, gotc);
 588         for (i = 0; i < 8; i++)
 589                 regs_buff[946 + i] = IXGBE_GET_STAT(adapter, rnbc[i]);
 590         regs_buff[954] = IXGBE_GET_STAT(adapter, ruc);
 591         regs_buff[955] = IXGBE_GET_STAT(adapter, rfc);
 592         regs_buff[956] = IXGBE_GET_STAT(adapter, roc);
 593         regs_buff[957] = IXGBE_GET_STAT(adapter, rjc);
 594         regs_buff[958] = IXGBE_GET_STAT(adapter, mngprc);
 595         regs_buff[959] = IXGBE_GET_STAT(adapter, mngpdc);
 596         regs_buff[960] = IXGBE_GET_STAT(adapter, mngptc);
 597         regs_buff[961] = IXGBE_GET_STAT(adapter, tor);
 598         regs_buff[963] = IXGBE_GET_STAT(adapter, tpr);
 599         regs_buff[964] = IXGBE_GET_STAT(adapter, tpt);
 600         regs_buff[965] = IXGBE_GET_STAT(adapter, ptc64);
 601         regs_buff[966] = IXGBE_GET_STAT(adapter, ptc127);
 602         regs_buff[967] = IXGBE_GET_STAT(adapter, ptc255);
 603         regs_buff[968] = IXGBE_GET_STAT(adapter, ptc511);
 604         regs_buff[969] = IXGBE_GET_STAT(adapter, ptc1023);
 605         regs_buff[970] = IXGBE_GET_STAT(adapter, ptc1522);
 606         regs_buff[971] = IXGBE_GET_STAT(adapter, mptc);
 607         regs_buff[972] = IXGBE_GET_STAT(adapter, bptc);
 608         regs_buff[973] = IXGBE_GET_STAT(adapter, xec);
 609         for (i = 0; i < 16; i++)
 610                 regs_buff[974 + i] = IXGBE_GET_STAT(adapter, qprc[i]);
 611         for (i = 0; i < 16; i++)
 612                 regs_buff[990 + i] = IXGBE_GET_STAT(adapter, qptc[i]);
 613         for (i = 0; i < 16; i++)
 614                 regs_buff[1006 + i] = IXGBE_GET_STAT(adapter, qbrc[i]);
 615         for (i = 0; i < 16; i++)
 616                 regs_buff[1022 + i] = IXGBE_GET_STAT(adapter, qbtc[i]);
 617
 618         /* MAC */
 619         regs_buff[1038] = IXGBE_READ_REG(hw, IXGBE_PCS1GCFIG);
 620         regs_buff[1039] = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
 621         regs_buff[1040] = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
 622         regs_buff[1041] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG0);
 623         regs_buff[1042] = IXGBE_READ_REG(hw, IXGBE_PCS1GDBG1);
 624         regs_buff[1043] = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
 625         regs_buff[1044] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
 626         regs_buff[1045] = IXGBE_READ_REG(hw, IXGBE_PCS1GANNP);
 627         regs_buff[1046] = IXGBE_READ_REG(hw, IXGBE_PCS1GANLPNP);
 628         regs_buff[1047] = IXGBE_READ_REG(hw, IXGBE_HLREG0);
 629         regs_buff[1048] = IXGBE_READ_REG(hw, IXGBE_HLREG1);
 630         regs_buff[1049] = IXGBE_READ_REG(hw, IXGBE_PAP);
 631         regs_buff[1050] = IXGBE_READ_REG(hw, IXGBE_MACA);
 632         regs_buff[1051] = IXGBE_READ_REG(hw, IXGBE_APAE);
 633         regs_buff[1052] = IXGBE_READ_REG(hw, IXGBE_ARD);
 634         regs_buff[1053] = IXGBE_READ_REG(hw, IXGBE_AIS);
 635         regs_buff[1054] = IXGBE_READ_REG(hw, IXGBE_MSCA);
 636         regs_buff[1055] = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 637         regs_buff[1056] = IXGBE_READ_REG(hw, IXGBE_MLADD);
 638         regs_buff[1057] = IXGBE_READ_REG(hw, IXGBE_MHADD);
 639         regs_buff[1058] = IXGBE_READ_REG(hw, IXGBE_TREG);
 640         regs_buff[1059] = IXGBE_READ_REG(hw, IXGBE_PCSS1);
 641         regs_buff[1060] = IXGBE_READ_REG(hw, IXGBE_PCSS2);
 642         regs_buff[1061] = IXGBE_READ_REG(hw, IXGBE_XPCSS);
 643         regs_buff[1062] = IXGBE_READ_REG(hw, IXGBE_SERDESC);
 644         regs_buff[1063] = IXGBE_READ_REG(hw, IXGBE_MACS);
 645         regs_buff[1064] = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 646         regs_buff[1065] = IXGBE_READ_REG(hw, IXGBE_LINKS);
 647         regs_buff[1066] = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
 648         regs_buff[1067] = IXGBE_READ_REG(hw, IXGBE_AUTOC3);
 649         regs_buff[1068] = IXGBE_READ_REG(hw, IXGBE_ANLP1);
 650         regs_buff[1069] = IXGBE_READ_REG(hw, IXGBE_ANLP2);
 651         regs_buff[1070] = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
 652
 653         /* Diagnostic */
 654         regs_buff[1071] = IXGBE_READ_REG(hw, IXGBE_RDSTATCTL);
 655         for (i = 0; i < 8; i++)
 656                 regs_buff[1072 + i] = IXGBE_READ_REG(hw, IXGBE_RDSTAT(i));
 657         regs_buff[1080] = IXGBE_READ_REG(hw, IXGBE_RDHMPN);
 658         for (i = 0; i < 4; i++)
 659                 regs_buff[1081 + i] = IXGBE_READ_REG(hw, IXGBE_RIC_DW(i));
 660         regs_buff[1085] = IXGBE_READ_REG(hw, IXGBE_RDPROBE);
 661         regs_buff[1086] = IXGBE_READ_REG(hw, IXGBE_TDSTATCTL);
 662         for (i = 0; i < 8; i++)
 663                 regs_buff[1087 + i] = IXGBE_READ_REG(hw, IXGBE_TDSTAT(i));
 664         regs_buff[1095] = IXGBE_READ_REG(hw, IXGBE_TDHMPN);
 665         for (i = 0; i < 4; i++)
 666                 regs_buff[1096 + i] = IXGBE_READ_REG(hw, IXGBE_TIC_DW(i));
 667         regs_buff[1100] = IXGBE_READ_REG(hw, IXGBE_TDPROBE);
 668         regs_buff[1101] = IXGBE_READ_REG(hw, IXGBE_TXBUFCTRL);
 669         regs_buff[1102] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA0);
 670         regs_buff[1103] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA1);
 671         regs_buff[1104] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA2);
 672         regs_buff[1105] = IXGBE_READ_REG(hw, IXGBE_TXBUFDATA3);
 673         regs_buff[1106] = IXGBE_READ_REG(hw, IXGBE_RXBUFCTRL);
 674         regs_buff[1107] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA0);
 675         regs_buff[1108] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA1);
 676         regs_buff[1109] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA2);
 677         regs_buff[1110] = IXGBE_READ_REG(hw, IXGBE_RXBUFDATA3);
 678         for (i = 0; i < 8; i++)
 679                 regs_buff[1111 + i] = IXGBE_READ_REG(hw, IXGBE_PCIE_DIAG(i));
 680         regs_buff[1119] = IXGBE_READ_REG(hw, IXGBE_RFVAL);
 681         regs_buff[1120] = IXGBE_READ_REG(hw, IXGBE_MDFTC1);
 682         regs_buff[1121] = IXGBE_READ_REG(hw, IXGBE_MDFTC2);
 683         regs_buff[1122] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO1);
 684         regs_buff[1123] = IXGBE_READ_REG(hw, IXGBE_MDFTFIFO2);
 685         regs_buff[1124] = IXGBE_READ_REG(hw, IXGBE_MDFTS);
 686         regs_buff[1125] = IXGBE_READ_REG(hw, IXGBE_PCIEECCCTL);
 687         regs_buff[1126] = IXGBE_READ_REG(hw, IXGBE_PBTXECC);
 688         regs_buff[1127] = IXGBE_READ_REG(hw, IXGBE_PBRXECC);
 689 }
 690
 691 static int ixgbe_get_eeprom_len(struct net_device *netdev)
 692 {
 693         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 694         return adapter->hw.eeprom.word_size * 2;
 695 }
 696
 697 static int ixgbe_get_eeprom(struct net_device *netdev,
 698                             struct ethtool_eeprom *eeprom, u8 *bytes)
 699 {
 700         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 701         struct ixgbe_hw *hw = &adapter->hw;
 702         u16 *eeprom_buff;
 703         int first_word, last_word, eeprom_len;
 704         int ret_val = 0;
 705         u16 i;
 706
 707         if (eeprom->len == 0)
 708                 return -EINVAL;
 709
 710         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
 711
 712         first_word = eeprom->offset >> 1;
 713         last_word = (eeprom->offset + eeprom->len - 1) >> 1;
 714         eeprom_len = last_word - first_word + 1;
 715
 716         eeprom_buff = kmalloc(sizeof(u16) * eeprom_len, GFP_KERNEL);
 717         if (!eeprom_buff)
 718                 return -ENOMEM;
 719
 720         for (i = 0; i < eeprom_len; i++) {
 721                 if ((ret_val = hw->eeprom.ops.read(hw, first_word + i,
 722                     &eeprom_buff[i])))
 723                         break;
 724         }
 725
 726         /* Device's eeprom is always little-endian, word addressable */
 727         for (i = 0; i < eeprom_len; i++)
 728                 le16_to_cpus(&eeprom_buff[i]);
 729
 730         memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
 731         kfree(eeprom_buff);
 732
 733         return ret_val;
 734 }
 735
 736 static void ixgbe_get_drvinfo(struct net_device *netdev,
 737                               struct ethtool_drvinfo *drvinfo)
 738 {
 739         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 740         char firmware_version[32];
 741
 742         strncpy(drvinfo->driver, ixgbe_driver_name, 32);
 743         strncpy(drvinfo->version, ixgbe_driver_version, 32);
 744
 745         sprintf(firmware_version, "%d.%d-%d",
 746                 (adapter->eeprom_version & 0xF000) >> 12,
 747                 (adapter->eeprom_version & 0x0FF0) >> 4,
 748                 adapter->eeprom_version & 0x000F);
 749
 750         strncpy(drvinfo->fw_version, firmware_version, 32);
 751         strncpy(drvinfo->bus_info, pci_name(adapter->pdev), 32);
 752         drvinfo->n_stats = IXGBE_STATS_LEN;
 753         drvinfo->testinfo_len = IXGBE_TEST_LEN;
 754         drvinfo->regdump_len = ixgbe_get_regs_len(netdev);
 755 }
 756
 757 static void ixgbe_get_ringparam(struct net_device *netdev,
 758                                 struct ethtool_ringparam *ring)
 759 {
 760         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 761         struct ixgbe_ring *tx_ring = adapter->tx_ring;
 762         struct ixgbe_ring *rx_ring = adapter->rx_ring;
 763
 764         ring->rx_max_pending = IXGBE_MAX_RXD;
 765         ring->tx_max_pending = IXGBE_MAX_TXD;
 766         ring->rx_mini_max_pending = 0;
 767         ring->rx_jumbo_max_pending = 0;
 768         ring->rx_pending = rx_ring->count;
 769         ring->tx_pending = tx_ring->count;
 770         ring->rx_mini_pending = 0;
 771         ring->rx_jumbo_pending = 0;
 772 }
 773
 774 static int ixgbe_set_ringparam(struct net_device *netdev,
 775                                struct ethtool_ringparam *ring)
 776 {
 777         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 778         struct ixgbe_ring *temp_tx_ring, *temp_rx_ring;
 779         int i, err;
 780         u32 new_rx_count, new_tx_count;
 781         bool need_update = false;
 782
 783         if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
 784                 return -EINVAL;
 785
 786         new_rx_count = max(ring->rx_pending, (u32)IXGBE_MIN_RXD);
 787         new_rx_count = min(new_rx_count, (u32)IXGBE_MAX_RXD);
 788         new_rx_count = ALIGN(new_rx_count, IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE);
 789
 790         new_tx_count = max(ring->tx_pending, (u32)IXGBE_MIN_TXD);
 791         new_tx_count = min(new_tx_count, (u32)IXGBE_MAX_TXD);
 792         new_tx_count = ALIGN(new_tx_count, IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE);
 793
 794         if ((new_tx_count == adapter->tx_ring->count) &&
 795             (new_rx_count == adapter->rx_ring->count)) {
 796                 /* nothing to do */
 797                 return 0;
 798         }
 799
 800         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
 801                 msleep(1);
 802
 803         temp_tx_ring = kcalloc(adapter->num_tx_queues,
 804                                sizeof(struct ixgbe_ring), GFP_KERNEL);
 805         if (!temp_tx_ring) {
 806                 err = -ENOMEM;
 807                 goto err_setup;
 808         }
 809
 810         if (new_tx_count != adapter->tx_ring_count) {
 811                 memcpy(temp_tx_ring, adapter->tx_ring,
 812                        adapter->num_tx_queues * sizeof(struct ixgbe_ring));
 813                 for (i = 0; i < adapter->num_tx_queues; i++) {
 814                         temp_tx_ring[i].count = new_tx_count;
 815                         err = ixgbe_setup_tx_resources(adapter,
 816                                                        &temp_tx_ring[i]);
 817                         if (err) {
 818                                 while (i) {
 819                                         i--;
 820                                         ixgbe_free_tx_resources(adapter,
 821                                                                 &temp_tx_ring[i]);
 822                                 }
 823                                 goto err_setup;
 824                         }
 825                         temp_tx_ring[i].v_idx = adapter->tx_ring[i].v_idx;
 826                 }
 827                 need_update = true;
 828         }
 829
 830         temp_rx_ring = kcalloc(adapter->num_rx_queues,
 831                                sizeof(struct ixgbe_ring), GFP_KERNEL);
 832         if ((!temp_rx_ring) && (need_update)) {
 833                 for (i = 0; i < adapter->num_tx_queues; i++)
 834                         ixgbe_free_tx_resources(adapter, &temp_tx_ring[i]);
 835                 kfree(temp_tx_ring);
 836                 err = -ENOMEM;
 837                 goto err_setup;
 838         }
 839
 840         if (new_rx_count != adapter->rx_ring_count) {
 841                 memcpy(temp_rx_ring, adapter->rx_ring,
 842                        adapter->num_rx_queues * sizeof(struct ixgbe_ring));
 843                 for (i = 0; i < adapter->num_rx_queues; i++) {
 844                         temp_rx_ring[i].count = new_rx_count;
 845                         err = ixgbe_setup_rx_resources(adapter,
 846                                                        &temp_rx_ring[i]);
 847                         if (err) {
 848                                 while (i) {
 849                                         i--;
 850                                         ixgbe_free_rx_resources(adapter,
 851                                                               &temp_rx_ring[i]);
 852                                 }
 853                                 goto err_setup;
 854                         }
 855                         temp_rx_ring[i].v_idx = adapter->rx_ring[i].v_idx;
 856                 }
 857                 need_update = true;
 858         }
 859
 860         /* if rings need to be updated, here's the place to do it in one shot */
 861         if (need_update) {
 862                 if (netif_running(netdev))
 863                         ixgbe_down(adapter);
 864
 865                 /* tx */
 866                 if (new_tx_count != adapter->tx_ring_count) {
 867                         kfree(adapter->tx_ring);
 868                         adapter->tx_ring = temp_tx_ring;
 869                         temp_tx_ring = NULL;
 870                         adapter->tx_ring_count = new_tx_count;
 871                 }
 872
 873                 /* rx */
 874                 if (new_rx_count != adapter->rx_ring_count) {
 875                         kfree(adapter->rx_ring);
 876                         adapter->rx_ring = temp_rx_ring;
 877                         temp_rx_ring = NULL;
 878                         adapter->rx_ring_count = new_rx_count;
 879                 }
 880         }
 881
 882         /* success! */
 883         err = 0;
 884         if (netif_running(netdev))
 885                 ixgbe_up(adapter);
 886
 887 err_setup:
 888         clear_bit(__IXGBE_RESETTING, &adapter->state);
 889         return err;
 890 }
 891
 892 static int ixgbe_get_sset_count(struct net_device *netdev, int sset)
 893 {
 894         switch (sset) {
 895         case ETH_SS_TEST:
 896                 return IXGBE_TEST_LEN;
 897         case ETH_SS_STATS:
 898                 return IXGBE_STATS_LEN;
 899         default:
 900                 return -EOPNOTSUPP;
 901         }
 902 }
 903
 904 static void ixgbe_get_ethtool_stats(struct net_device *netdev,
 905                                     struct ethtool_stats *stats, u64 *data)
 906 {
 907         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 908         u64 *queue_stat;
 909         int stat_count = sizeof(struct ixgbe_queue_stats) / sizeof(u64);
 910         int j, k;
 911         int i;
 912
 913         ixgbe_update_stats(adapter);
 914         for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
 915                 char *p = (char *)adapter + ixgbe_gstrings_stats[i].stat_offset;
 916                 data[i] = (ixgbe_gstrings_stats[i].sizeof_stat ==
 917                            sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
 918         }
 919         for (j = 0; j < adapter->num_tx_queues; j++) {
 920                 queue_stat = (u64 *)&adapter->tx_ring[j].stats;
 921                 for (k = 0; k < stat_count; k++)
 922                         data[i + k] = queue_stat[k];
 923                 i += k;
 924         }
 925         for (j = 0; j < adapter->num_rx_queues; j++) {
 926                 queue_stat = (u64 *)&adapter->rx_ring[j].stats;
 927                 for (k = 0; k < stat_count; k++)
 928                         data[i + k] = queue_stat[k];
 929                 i += k;
 930         }
 931         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
 932                 for (j = 0; j < MAX_TX_PACKET_BUFFERS; j++) {
 933                         data[i++] = adapter->stats.pxontxc[j];
 934                         data[i++] = adapter->stats.pxofftxc[j];
 935                 }
 936                 for (j = 0; j < MAX_RX_PACKET_BUFFERS; j++) {
 937                         data[i++] = adapter->stats.pxonrxc[j];
 938                         data[i++] = adapter->stats.pxoffrxc[j];
 939                 }
 940         }
 941 }
 942
 943 static void ixgbe_get_strings(struct net_device *netdev, u32 stringset,
 944                               u8 *data)
 945 {
 946         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 947         char *p = (char *)data;
 948         int i;
 949
 950         switch (stringset) {
 951         case ETH_SS_TEST:
 952                 memcpy(data, *ixgbe_gstrings_test,
 953                        IXGBE_TEST_LEN * ETH_GSTRING_LEN);
 954                 break;
 955         case ETH_SS_STATS:
 956                 for (i = 0; i < IXGBE_GLOBAL_STATS_LEN; i++) {
 957                         memcpy(p, ixgbe_gstrings_stats[i].stat_string,
 958                                ETH_GSTRING_LEN);
 959                         p += ETH_GSTRING_LEN;
 960                 }
 961                 for (i = 0; i < adapter->num_tx_queues; i++) {
 962                         sprintf(p, "tx_queue_%u_packets", i);
 963                         p += ETH_GSTRING_LEN;
 964                         sprintf(p, "tx_queue_%u_bytes", i);
 965                         p += ETH_GSTRING_LEN;
 966                 }
 967                 for (i = 0; i < adapter->num_rx_queues; i++) {
 968                         sprintf(p, "rx_queue_%u_packets", i);
 969                         p += ETH_GSTRING_LEN;
 970                         sprintf(p, "rx_queue_%u_bytes", i);
 971                         p += ETH_GSTRING_LEN;
 972                 }
 973                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
 974                         for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
 975                                 sprintf(p, "tx_pb_%u_pxon", i);
 976                                 p += ETH_GSTRING_LEN;
 977                                 sprintf(p, "tx_pb_%u_pxoff", i);
 978                                 p += ETH_GSTRING_LEN;
 979                         }
 980                         for (i = 0; i < MAX_RX_PACKET_BUFFERS; i++) {
 981                                 sprintf(p, "rx_pb_%u_pxon", i);
 982                                 p += ETH_GSTRING_LEN;
 983                                 sprintf(p, "rx_pb_%u_pxoff", i);
 984                                 p += ETH_GSTRING_LEN;
 985                         }
 986                 }
 987                 /* BUG_ON(p - data != IXGBE_STATS_LEN * ETH_GSTRING_LEN); */
 988                 break;
 989         }
 990 }
 991
 992 static int ixgbe_link_test(struct ixgbe_adapter *adapter, u64 *data)
 993 {
 994         struct ixgbe_hw *hw = &adapter->hw;
 995         bool link_up;
 996         u32 link_speed = 0;
 997         *data = 0;
 998
 999         hw->mac.ops.check_link(hw, &link_speed, &link_up, true);
1000         if (link_up)
1001                 return *data;
1002         else
1003                 *data = 1;
1004         return *data;
1005 }
1006
1007 /* ethtool register test data */
1008 struct ixgbe_reg_test {
1009         u16 reg;
1010         u8  array_len;
1011         u8  test_type;
1012         u32 mask;
1013         u32 write;
1014 };
1015
1016 /* In the hardware, registers are laid out either singly, in arrays
1017  * spaced 0x40 bytes apart, or in contiguous tables.  We assume
1018  * most tests take place on arrays or single registers (handled
1019  * as a single-element array) and special-case the tables.
1020  * Table tests are always pattern tests.
1021  *
1022  * We also make provision for some required setup steps by specifying
1023  * registers to be written without any read-back testing.
1024  */
1025
1026 #define PATTERN_TEST    1
1027 #define SET_READ_TEST   2
1028 #define WRITE_NO_TEST   3
1029 #define TABLE32_TEST    4
1030 #define TABLE64_TEST_LO 5
1031 #define TABLE64_TEST_HI 6
1032
1033 /* default 82599 register test */
1034 static struct ixgbe_reg_test reg_test_82599[] = {
1035         { IXGBE_FCRTL_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1036         { IXGBE_FCRTH_82599(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1037         { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1038         { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1039         { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFF80 },
1040         { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1041         { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1042         { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1043         { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1044         { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1045         { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1046         { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1047         { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1048         { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1049         { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFF80 },
1050         { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000001, 0x00000001 },
1051         { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1052         { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x8001FFFF, 0x800CFFFF },
1053         { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1054         { 0, 0, 0, 0 }
1055 };
1056
1057 /* default 82598 register test */
1058 static struct ixgbe_reg_test reg_test_82598[] = {
1059         { IXGBE_FCRTL(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1060         { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1061         { IXGBE_PFCTOP, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1062         { IXGBE_VLNCTRL, 1, PATTERN_TEST, 0x00000000, 0x00000000 },
1063         { IXGBE_RDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1064         { IXGBE_RDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1065         { IXGBE_RDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1066         /* Enable all four RX queues before testing. */
1067         { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, IXGBE_RXDCTL_ENABLE },
1068         /* RDH is read-only for 82598, only test RDT. */
1069         { IXGBE_RDT(0), 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1070         { IXGBE_RXDCTL(0), 4, WRITE_NO_TEST, 0, 0 },
1071         { IXGBE_FCRTH(0), 1, PATTERN_TEST, 0x8007FFF0, 0x8007FFF0 },
1072         { IXGBE_FCTTV(0), 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1073         { IXGBE_TIPG, 1, PATTERN_TEST, 0x000000FF, 0x000000FF },
1074         { IXGBE_TDBAL(0), 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1075         { IXGBE_TDBAH(0), 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1076         { IXGBE_TDLEN(0), 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1077         { IXGBE_RXCTRL, 1, SET_READ_TEST, 0x00000003, 0x00000003 },
1078         { IXGBE_DTXCTL, 1, SET_READ_TEST, 0x00000005, 0x00000005 },
1079         { IXGBE_RAL(0), 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1080         { IXGBE_RAL(0), 16, TABLE64_TEST_HI, 0x800CFFFF, 0x800CFFFF },
1081         { IXGBE_MTA(0), 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1082         { 0, 0, 0, 0 }
1083 };
1084
1085 #define REG_PATTERN_TEST(R, M, W)                                             \
1086 {                                                                             \
1087         u32 pat, val, before;                                                 \
1088         const u32 _test[] = {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; \
1089         for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {                       \
1090                 before = readl(adapter->hw.hw_addr + R);                      \
1091                 writel((_test[pat] & W), (adapter->hw.hw_addr + R));          \
1092                 val = readl(adapter->hw.hw_addr + R);                         \
1093                 if (val != (_test[pat] & W & M)) {                            \
1094                         DPRINTK(DRV, ERR, "pattern test reg %04X failed: got "\
1095                                           "0x%08X expected 0x%08X\n",         \
1096                                 R, val, (_test[pat] & W & M));                \
1097                         *data = R;                                            \
1098                         writel(before, adapter->hw.hw_addr + R);              \
1099                         return 1;                                             \
1100                 }                                                             \
1101                 writel(before, adapter->hw.hw_addr + R);                      \
1102         }                                                                     \
1103 }
1104
1105 #define REG_SET_AND_CHECK(R, M, W)                                            \
1106 {                                                                             \
1107         u32 val, before;                                                      \
1108         before = readl(adapter->hw.hw_addr + R);                              \
1109         writel((W & M), (adapter->hw.hw_addr + R));                           \
1110         val = readl(adapter->hw.hw_addr + R);                                 \
1111         if ((W & M) != (val & M)) {                                           \
1112                 DPRINTK(DRV, ERR, "set/check reg %04X test failed: got 0x%08X "\
1113                                  "expected 0x%08X\n", R, (val & M), (W & M)); \
1114                 *data = R;                                                    \
1115                 writel(before, (adapter->hw.hw_addr + R));                    \
1116                 return 1;                                                     \
1117         }                                                                     \
1118         writel(before, (adapter->hw.hw_addr + R));                            \
1119 }
1120
1121 static int ixgbe_reg_test(struct ixgbe_adapter *adapter, u64 *data)
1122 {
1123         struct ixgbe_reg_test *test;
1124         u32 value, before, after;
1125         u32 i, toggle;
1126
1127         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1128                 toggle = 0x7FFFF30F;
1129                 test = reg_test_82599;
1130         } else {
1131                 toggle = 0x7FFFF3FF;
1132                 test = reg_test_82598;
1133         }
1134
1135         /*
1136          * Because the status register is such a special case,
1137          * we handle it separately from the rest of the register
1138          * tests.  Some bits are read-only, some toggle, and some
1139          * are writeable on newer MACs.
1140          */
1141         before = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS);
1142         value = (IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle);
1143         IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, toggle);
1144         after = IXGBE_READ_REG(&adapter->hw, IXGBE_STATUS) & toggle;
1145         if (value != after) {
1146                 DPRINTK(DRV, ERR, "failed STATUS register test got: "
1147                         "0x%08X expected: 0x%08X\n", after, value);
1148                 *data = 1;
1149                 return 1;
1150         }
1151         /* restore previous status */
1152         IXGBE_WRITE_REG(&adapter->hw, IXGBE_STATUS, before);
1153
1154         /*
1155          * Perform the remainder of the register test, looping through
1156          * the test table until we either fail or reach the null entry.
1157          */
1158         while (test->reg) {
1159                 for (i = 0; i < test->array_len; i++) {
1160                         switch (test->test_type) {
1161                         case PATTERN_TEST:
1162                                 REG_PATTERN_TEST(test->reg + (i * 0x40),
1163                                                 test->mask,
1164                                                 test->write);
1165                                 break;
1166                         case SET_READ_TEST:
1167                                 REG_SET_AND_CHECK(test->reg + (i * 0x40),
1168                                                 test->mask,
1169                                                 test->write);
1170                                 break;
1171                         case WRITE_NO_TEST:
1172                                 writel(test->write,
1173                                        (adapter->hw.hw_addr + test->reg)
1174                                        + (i * 0x40));
1175                                 break;
1176                         case TABLE32_TEST:
1177                                 REG_PATTERN_TEST(test->reg + (i * 4),
1178                                                 test->mask,
1179                                                 test->write);
1180                                 break;
1181                         case TABLE64_TEST_LO:
1182                                 REG_PATTERN_TEST(test->reg + (i * 8),
1183                                                 test->mask,
1184                                                 test->write);
1185                                 break;
1186                         case TABLE64_TEST_HI:
1187                                 REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1188                                                 test->mask,
1189                                                 test->write);
1190                                 break;
1191                         }
1192                 }
1193                 test++;
1194         }
1195
1196         *data = 0;
1197         return 0;
1198 }
1199
1200 static int ixgbe_eeprom_test(struct ixgbe_adapter *adapter, u64 *data)
1201 {
1202         struct ixgbe_hw *hw = &adapter->hw;
1203         if (hw->eeprom.ops.validate_checksum(hw, NULL))
1204                 *data = 1;
1205         else
1206                 *data = 0;
1207         return *data;
1208 }
1209
1210 static irqreturn_t ixgbe_test_intr(int irq, void *data)
1211 {
1212         struct net_device *netdev = (struct net_device *) data;
1213         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1214
1215         adapter->test_icr |= IXGBE_READ_REG(&adapter->hw, IXGBE_EICR);
1216
1217         return IRQ_HANDLED;
1218 }
1219
1220 static int ixgbe_intr_test(struct ixgbe_adapter *adapter, u64 *data)
1221 {
1222         struct net_device *netdev = adapter->netdev;
1223         u32 mask, i = 0, shared_int = true;
1224         u32 irq = adapter->pdev->irq;
1225
1226         *data = 0;
1227
1228         /* Hook up test interrupt handler just for this test */
1229         if (adapter->msix_entries) {
1230                 /* NOTE: we don't test MSI-X interrupts here, yet */
1231                 return 0;
1232         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1233                 shared_int = false;
1234                 if (request_irq(irq, &ixgbe_test_intr, 0, netdev->name,
1235                                 netdev)) {
1236                         *data = 1;
1237                         return -1;
1238                 }
1239         } else if (!request_irq(irq, &ixgbe_test_intr, IRQF_PROBE_SHARED,
1240                                 netdev->name, netdev)) {
1241                 shared_int = false;
1242         } else if (request_irq(irq, &ixgbe_test_intr, IRQF_SHARED,
1243                                netdev->name, netdev)) {
1244                 *data = 1;
1245                 return -1;
1246         }
1247         DPRINTK(HW, INFO, "testing %s interrupt\n",
1248                 (shared_int ? "shared" : "unshared"));
1249
1250         /* Disable all the interrupts */
1251         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1252         msleep(10);
1253
1254         /* Test each interrupt */
1255         for (; i < 10; i++) {
1256                 /* Interrupt to test */
1257                 mask = 1 << i;
1258
1259                 if (!shared_int) {
1260                         /*
1261                          * Disable the interrupts to be reported in
1262                          * the cause register and then force the same
1263                          * interrupt and see if one gets posted.  If
1264                          * an interrupt was posted to the bus, the
1265                          * test failed.
1266                          */
1267                         adapter->test_icr = 0;
1268                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1269                                         ~mask & 0x00007FFF);
1270                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1271                                         ~mask & 0x00007FFF);
1272                         msleep(10);
1273
1274                         if (adapter->test_icr & mask) {
1275                                 *data = 3;
1276                                 break;
1277                         }
1278                 }
1279
1280                 /*
1281                  * Enable the interrupt to be reported in the cause
1282                  * register and then force the same interrupt and see
1283                  * if one gets posted.  If an interrupt was not posted
1284                  * to the bus, the test failed.
1285                  */
1286                 adapter->test_icr = 0;
1287                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1288                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
1289                 msleep(10);
1290
1291                 if (!(adapter->test_icr &mask)) {
1292                         *data = 4;
1293                         break;
1294                 }
1295
1296                 if (!shared_int) {
1297                         /*
1298                          * Disable the other interrupts to be reported in
1299                          * the cause register and then force the other
1300                          * interrupts and see if any get posted.  If
1301                          * an interrupt was posted to the bus, the
1302                          * test failed.
1303                          */
1304                         adapter->test_icr = 0;
1305                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
1306                                         ~mask & 0x00007FFF);
1307                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS,
1308                                         ~mask & 0x00007FFF);
1309                         msleep(10);
1310
1311                         if (adapter->test_icr) {
1312                                 *data = 5;
1313                                 break;
1314                         }
1315                 }
1316         }
1317
1318         /* Disable all the interrupts */
1319         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFFFFFF);
1320         msleep(10);
1321
1322         /* Unhook test interrupt handler */
1323         free_irq(irq, netdev);
1324
1325         return *data;
1326 }
1327
1328 static void ixgbe_free_desc_rings(struct ixgbe_adapter *adapter)
1329 {
1330         struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1331         struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1332         struct ixgbe_hw *hw = &adapter->hw;
1333         struct pci_dev *pdev = adapter->pdev;
1334         u32 reg_ctl;
1335         int i;
1336
1337         /* shut down the DMA engines now so they can be reinitialized later */
1338
1339         /* first Rx */
1340         reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1341         reg_ctl &= ~IXGBE_RXCTRL_RXEN;
1342         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg_ctl);
1343         reg_ctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(0));
1344         reg_ctl &= ~IXGBE_RXDCTL_ENABLE;
1345         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(0), reg_ctl);
1346
1347         /* now Tx */
1348         reg_ctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(0));
1349         reg_ctl &= ~IXGBE_TXDCTL_ENABLE;
1350         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(0), reg_ctl);
1351         if (hw->mac.type == ixgbe_mac_82599EB) {
1352                 reg_ctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
1353                 reg_ctl &= ~IXGBE_DMATXCTL_TE;
1354                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg_ctl);
1355         }
1356
1357         ixgbe_reset(adapter);
1358
1359         if (tx_ring->desc && tx_ring->tx_buffer_info) {
1360                 for (i = 0; i < tx_ring->count; i++) {
1361                         struct ixgbe_tx_buffer *buf =
1362                                         &(tx_ring->tx_buffer_info[i]);
1363                         if (buf->dma)
1364                                 pci_unmap_single(pdev, buf->dma, buf->length,
1365                                                  PCI_DMA_TODEVICE);
1366                         if (buf->skb)
1367                                 dev_kfree_skb(buf->skb);
1368                 }
1369         }
1370
1371         if (rx_ring->desc && rx_ring->rx_buffer_info) {
1372                 for (i = 0; i < rx_ring->count; i++) {
1373                         struct ixgbe_rx_buffer *buf =
1374                                         &(rx_ring->rx_buffer_info[i]);
1375                         if (buf->dma)
1376                                 pci_unmap_single(pdev, buf->dma,
1377                                                  IXGBE_RXBUFFER_2048,
1378                                                  PCI_DMA_FROMDEVICE);
1379                         if (buf->skb)
1380                                 dev_kfree_skb(buf->skb);
1381                 }
1382         }
1383
1384         if (tx_ring->desc) {
1385                 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc,
1386                                     tx_ring->dma);
1387                 tx_ring->desc = NULL;
1388         }
1389         if (rx_ring->desc) {
1390                 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc,
1391                                     rx_ring->dma);
1392                 rx_ring->desc = NULL;
1393         }
1394
1395         kfree(tx_ring->tx_buffer_info);
1396         tx_ring->tx_buffer_info = NULL;
1397         kfree(rx_ring->rx_buffer_info);
1398         rx_ring->rx_buffer_info = NULL;
1399
1400         return;
1401 }
1402
1403 static int ixgbe_setup_desc_rings(struct ixgbe_adapter *adapter)
1404 {
1405         struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1406         struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1407         struct pci_dev *pdev = adapter->pdev;
1408         u32 rctl, reg_data;
1409         int i, ret_val;
1410
1411         /* Setup Tx descriptor ring and Tx buffers */
1412
1413         if (!tx_ring->count)
1414                 tx_ring->count = IXGBE_DEFAULT_TXD;
1415
1416         tx_ring->tx_buffer_info = kcalloc(tx_ring->count,
1417                                           sizeof(struct ixgbe_tx_buffer),
1418                                           GFP_KERNEL);
1419         if (!(tx_ring->tx_buffer_info)) {
1420                 ret_val = 1;
1421                 goto err_nomem;
1422         }
1423
1424         tx_ring->size = tx_ring->count * sizeof(struct ixgbe_legacy_tx_desc);
1425         tx_ring->size = ALIGN(tx_ring->size, 4096);
1426         if (!(tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
1427                                                    &tx_ring->dma))) {
1428                 ret_val = 2;
1429                 goto err_nomem;
1430         }
1431         tx_ring->next_to_use = tx_ring->next_to_clean = 0;
1432
1433         IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDBAL(0),
1434                         ((u64) tx_ring->dma & 0x00000000FFFFFFFF));
1435         IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDBAH(0),
1436                         ((u64) tx_ring->dma >> 32));
1437         IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDLEN(0),
1438                         tx_ring->count * sizeof(struct ixgbe_legacy_tx_desc));
1439         IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDH(0), 0);
1440         IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDT(0), 0);
1441
1442         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1443         reg_data |= IXGBE_HLREG0_TXPADEN;
1444         IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1445
1446         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1447                 reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_DMATXCTL);
1448                 reg_data |= IXGBE_DMATXCTL_TE;
1449                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DMATXCTL, reg_data);
1450         }
1451         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_TXDCTL(0));
1452         reg_data |= IXGBE_TXDCTL_ENABLE;
1453         IXGBE_WRITE_REG(&adapter->hw, IXGBE_TXDCTL(0), reg_data);
1454
1455         for (i = 0; i < tx_ring->count; i++) {
1456                 struct ixgbe_legacy_tx_desc *desc = IXGBE_TX_DESC(*tx_ring, i);
1457                 struct sk_buff *skb;
1458                 unsigned int size = 1024;
1459
1460                 skb = alloc_skb(size, GFP_KERNEL);
1461                 if (!skb) {
1462                         ret_val = 3;
1463                         goto err_nomem;
1464                 }
1465                 skb_put(skb, size);
1466                 tx_ring->tx_buffer_info[i].skb = skb;
1467                 tx_ring->tx_buffer_info[i].length = skb->len;
1468                 tx_ring->tx_buffer_info[i].dma =
1469                         pci_map_single(pdev, skb->data, skb->len,
1470                                         PCI_DMA_TODEVICE);
1471                 desc->buffer_addr = cpu_to_le64(tx_ring->tx_buffer_info[i].dma);
1472                 desc->lower.data = cpu_to_le32(skb->len);
1473                 desc->lower.data |= cpu_to_le32(IXGBE_TXD_CMD_EOP |
1474                                                 IXGBE_TXD_CMD_IFCS |
1475                                                 IXGBE_TXD_CMD_RS);
1476                 desc->upper.data = 0;
1477         }
1478
1479         /* Setup Rx Descriptor ring and Rx buffers */
1480
1481         if (!rx_ring->count)
1482                 rx_ring->count = IXGBE_DEFAULT_RXD;
1483
1484         rx_ring->rx_buffer_info = kcalloc(rx_ring->count,
1485                                           sizeof(struct ixgbe_rx_buffer),
1486                                           GFP_KERNEL);
1487         if (!(rx_ring->rx_buffer_info)) {
1488                 ret_val = 4;
1489                 goto err_nomem;
1490         }
1491
1492         rx_ring->size = rx_ring->count * sizeof(struct ixgbe_legacy_rx_desc);
1493         rx_ring->size = ALIGN(rx_ring->size, 4096);
1494         if (!(rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size,
1495                                                    &rx_ring->dma))) {
1496                 ret_val = 5;
1497                 goto err_nomem;
1498         }
1499         rx_ring->next_to_use = rx_ring->next_to_clean = 0;
1500
1501         rctl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXCTRL);
1502         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl & ~IXGBE_RXCTRL_RXEN);
1503         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDBAL(0),
1504                         ((u64)rx_ring->dma & 0xFFFFFFFF));
1505         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDBAH(0),
1506                         ((u64) rx_ring->dma >> 32));
1507         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDLEN(0), rx_ring->size);
1508         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDH(0), 0);
1509         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDT(0), 0);
1510
1511         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1512         reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE;
1513         IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, reg_data);
1514
1515         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1516         reg_data &= ~IXGBE_HLREG0_LPBK;
1517         IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1518
1519         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_RDRXCTL);
1520 #define IXGBE_RDRXCTL_RDMTS_MASK    0x00000003 /* Receive Descriptor Minimum
1521                                                   Threshold Size mask */
1522         reg_data &= ~IXGBE_RDRXCTL_RDMTS_MASK;
1523         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDRXCTL, reg_data);
1524
1525         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_MCSTCTRL);
1526 #define IXGBE_MCSTCTRL_MO_MASK      0x00000003 /* Multicast Offset mask */
1527         reg_data &= ~IXGBE_MCSTCTRL_MO_MASK;
1528         reg_data |= adapter->hw.mac.mc_filter_type;
1529         IXGBE_WRITE_REG(&adapter->hw, IXGBE_MCSTCTRL, reg_data);
1530
1531         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(0));
1532         reg_data |= IXGBE_RXDCTL_ENABLE;
1533         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(0), reg_data);
1534         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1535                 int j = adapter->rx_ring[0].reg_idx;
1536                 u32 k;
1537                 for (k = 0; k < 10; k++) {
1538                         if (IXGBE_READ_REG(&adapter->hw,
1539                                            IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
1540                                 break;
1541                         else
1542                                 msleep(1);
1543                 }
1544         }
1545
1546         rctl |= IXGBE_RXCTRL_RXEN | IXGBE_RXCTRL_DMBYPS;
1547         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXCTRL, rctl);
1548
1549         for (i = 0; i < rx_ring->count; i++) {
1550                 struct ixgbe_legacy_rx_desc *rx_desc =
1551                                         IXGBE_RX_DESC(*rx_ring, i);
1552                 struct sk_buff *skb;
1553
1554                 skb = alloc_skb(IXGBE_RXBUFFER_2048 + NET_IP_ALIGN, GFP_KERNEL);
1555                 if (!skb) {
1556                         ret_val = 6;
1557                         goto err_nomem;
1558                 }
1559                 skb_reserve(skb, NET_IP_ALIGN);
1560                 rx_ring->rx_buffer_info[i].skb = skb;
1561                 rx_ring->rx_buffer_info[i].dma =
1562                         pci_map_single(pdev, skb->data, IXGBE_RXBUFFER_2048,
1563                                        PCI_DMA_FROMDEVICE);
1564                 rx_desc->buffer_addr =
1565                                 cpu_to_le64(rx_ring->rx_buffer_info[i].dma);
1566                 memset(skb->data, 0x00, skb->len);
1567         }
1568
1569         return 0;
1570
1571 err_nomem:
1572         ixgbe_free_desc_rings(adapter);
1573         return ret_val;
1574 }
1575
1576 static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter)
1577 {
1578         struct ixgbe_hw *hw = &adapter->hw;
1579         u32 reg_data;
1580
1581         /* right now we only support MAC loopback in the driver */
1582
1583         /* Setup MAC loopback */
1584         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1585         reg_data |= IXGBE_HLREG0_LPBK;
1586         IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1587
1588         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_AUTOC);
1589         reg_data &= ~IXGBE_AUTOC_LMS_MASK;
1590         reg_data |= IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU;
1591         IXGBE_WRITE_REG(&adapter->hw, IXGBE_AUTOC, reg_data);
1592
1593         /* Disable Atlas Tx lanes; re-enabled in reset path */
1594         if (hw->mac.type == ixgbe_mac_82598EB) {
1595                 u8 atlas;
1596
1597                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &atlas);
1598                 atlas |= IXGBE_ATLAS_PDN_TX_REG_EN;
1599                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, atlas);
1600
1601                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, &atlas);
1602                 atlas |= IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
1603                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G, atlas);
1604
1605                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, &atlas);
1606                 atlas |= IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
1607                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G, atlas);
1608
1609                 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, &atlas);
1610                 atlas |= IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
1611                 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN, atlas);
1612         }
1613
1614         return 0;
1615 }
1616
1617 static void ixgbe_loopback_cleanup(struct ixgbe_adapter *adapter)
1618 {
1619         u32 reg_data;
1620
1621         reg_data = IXGBE_READ_REG(&adapter->hw, IXGBE_HLREG0);
1622         reg_data &= ~IXGBE_HLREG0_LPBK;
1623         IXGBE_WRITE_REG(&adapter->hw, IXGBE_HLREG0, reg_data);
1624 }
1625
1626 static void ixgbe_create_lbtest_frame(struct sk_buff *skb,
1627                                       unsigned int frame_size)
1628 {
1629         memset(skb->data, 0xFF, frame_size);
1630         frame_size &= ~1;
1631         memset(&skb->data[frame_size / 2], 0xAA, frame_size / 2 - 1);
1632         memset(&skb->data[frame_size / 2 + 10], 0xBE, 1);
1633         memset(&skb->data[frame_size / 2 + 12], 0xAF, 1);
1634 }
1635
1636 static int ixgbe_check_lbtest_frame(struct sk_buff *skb,
1637                                     unsigned int frame_size)
1638 {
1639         frame_size &= ~1;
1640         if (*(skb->data + 3) == 0xFF) {
1641                 if ((*(skb->data + frame_size / 2 + 10) == 0xBE) &&
1642                     (*(skb->data + frame_size / 2 + 12) == 0xAF)) {
1643                         return 0;
1644                 }
1645         }
1646         return 13;
1647 }
1648
1649 static int ixgbe_run_loopback_test(struct ixgbe_adapter *adapter)
1650 {
1651         struct ixgbe_ring *tx_ring = &adapter->test_tx_ring;
1652         struct ixgbe_ring *rx_ring = &adapter->test_rx_ring;
1653         struct pci_dev *pdev = adapter->pdev;
1654         int i, j, k, l, lc, good_cnt, ret_val = 0;
1655         unsigned long time;
1656
1657         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RDT(0), rx_ring->count - 1);
1658
1659         /*
1660          * Calculate the loop count based on the largest descriptor ring
1661          * The idea is to wrap the largest ring a number of times using 64
1662          * send/receive pairs during each loop
1663          */
1664
1665         if (rx_ring->count <= tx_ring->count)
1666                 lc = ((tx_ring->count / 64) * 2) + 1;
1667         else
1668                 lc = ((rx_ring->count / 64) * 2) + 1;
1669
1670         k = l = 0;
1671         for (j = 0; j <= lc; j++) {
1672                 for (i = 0; i < 64; i++) {
1673                         ixgbe_create_lbtest_frame(
1674                                         tx_ring->tx_buffer_info[k].skb,
1675                                         1024);
1676                         pci_dma_sync_single_for_device(pdev,
1677                                 tx_ring->tx_buffer_info[k].dma,
1678                                 tx_ring->tx_buffer_info[k].length,
1679                                 PCI_DMA_TODEVICE);
1680                         if (unlikely(++k == tx_ring->count))
1681                                 k = 0;
1682                 }
1683                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_TDT(0), k);
1684                 msleep(200);
1685                 /* set the start time for the receive */
1686                 time = jiffies;
1687                 good_cnt = 0;
1688                 do {
1689                         /* receive the sent packets */
1690                         pci_dma_sync_single_for_cpu(pdev,
1691                                         rx_ring->rx_buffer_info[l].dma,
1692                                         IXGBE_RXBUFFER_2048,
1693                                         PCI_DMA_FROMDEVICE);
1694                         ret_val = ixgbe_check_lbtest_frame(
1695                                         rx_ring->rx_buffer_info[l].skb, 1024);
1696                         if (!ret_val)
1697                                 good_cnt++;
1698                         if (++l == rx_ring->count)
1699                                 l = 0;
1700                         /*
1701                          * time + 20 msecs (200 msecs on 2.4) is more than
1702                          * enough time to complete the receives, if it's
1703                          * exceeded, break and error off
1704                          */
1705                 } while (good_cnt < 64 && jiffies < (time + 20));
1706                 if (good_cnt != 64) {
1707                         /* ret_val is the same as mis-compare */
1708                         ret_val = 13;
1709                         break;
1710                 }
1711                 if (jiffies >= (time + 20)) {
1712                         /* Error code for time out error */
1713                         ret_val = 14;
1714                         break;
1715                 }
1716         }
1717
1718         return ret_val;
1719 }
1720
1721 static int ixgbe_loopback_test(struct ixgbe_adapter *adapter, u64 *data)
1722 {
1723         *data = ixgbe_setup_desc_rings(adapter);
1724         if (*data)
1725                 goto out;
1726         *data = ixgbe_setup_loopback_test(adapter);
1727         if (*data)
1728                 goto err_loopback;
1729         *data = ixgbe_run_loopback_test(adapter);
1730         ixgbe_loopback_cleanup(adapter);
1731
1732 err_loopback:
1733         ixgbe_free_desc_rings(adapter);
1734 out:
1735         return *data;
1736 }
1737
1738 static void ixgbe_diag_test(struct net_device *netdev,
1739                             struct ethtool_test *eth_test, u64 *data)
1740 {
1741         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1742         bool if_running = netif_running(netdev);
1743
1744         set_bit(__IXGBE_TESTING, &adapter->state);
1745         if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1746                 /* Offline tests */
1747
1748                 DPRINTK(HW, INFO, "offline testing starting\n");
1749
1750                 /* Link test performed before hardware reset so autoneg doesn't
1751                  * interfere with test result */
1752                 if (ixgbe_link_test(adapter, &data[4]))
1753                         eth_test->flags |= ETH_TEST_FL_FAILED;
1754
1755                 if (if_running)
1756                         /* indicate we're in test mode */
1757                         dev_close(netdev);
1758                 else
1759                         ixgbe_reset(adapter);
1760
1761                 DPRINTK(HW, INFO, "register testing starting\n");
1762                 if (ixgbe_reg_test(adapter, &data[0]))
1763                         eth_test->flags |= ETH_TEST_FL_FAILED;
1764
1765                 ixgbe_reset(adapter);
1766                 DPRINTK(HW, INFO, "eeprom testing starting\n");
1767                 if (ixgbe_eeprom_test(adapter, &data[1]))
1768                         eth_test->flags |= ETH_TEST_FL_FAILED;
1769
1770                 ixgbe_reset(adapter);
1771                 DPRINTK(HW, INFO, "interrupt testing starting\n");
1772                 if (ixgbe_intr_test(adapter, &data[2]))
1773                         eth_test->flags |= ETH_TEST_FL_FAILED;
1774
1775                 ixgbe_reset(adapter);
1776                 DPRINTK(HW, INFO, "loopback testing starting\n");
1777                 if (ixgbe_loopback_test(adapter, &data[3]))
1778                         eth_test->flags |= ETH_TEST_FL_FAILED;
1779
1780                 ixgbe_reset(adapter);
1781
1782                 clear_bit(__IXGBE_TESTING, &adapter->state);
1783                 if (if_running)
1784                         dev_open(netdev);
1785         } else {
1786                 DPRINTK(HW, INFO, "online testing starting\n");
1787                 /* Online tests */
1788                 if (ixgbe_link_test(adapter, &data[4]))
1789                         eth_test->flags |= ETH_TEST_FL_FAILED;
1790
1791                 /* Online tests aren't run; pass by default */
1792                 data[0] = 0;
1793                 data[1] = 0;
1794                 data[2] = 0;
1795                 data[3] = 0;
1796
1797                 clear_bit(__IXGBE_TESTING, &adapter->state);
1798         }
1799         msleep_interruptible(4 * 1000);
1800 }
1801
1802 static int ixgbe_wol_exclusion(struct ixgbe_adapter *adapter,
1803                                struct ethtool_wolinfo *wol)
1804 {
1805         struct ixgbe_hw *hw = &adapter->hw;
1806         int retval = 1;
1807
1808         switch(hw->device_id) {
1809         case IXGBE_DEV_ID_82599_KX4:
1810                 retval = 0;
1811                 break;
1812         default:
1813                 wol->supported = 0;
1814                 retval = 0;
1815         }
1816
1817         return retval;
1818 }
1819
1820 static void ixgbe_get_wol(struct net_device *netdev,
1821                           struct ethtool_wolinfo *wol)
1822 {
1823         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1824
1825         wol->supported = WAKE_UCAST | WAKE_MCAST |
1826                          WAKE_BCAST | WAKE_MAGIC;
1827         wol->wolopts = 0;
1828
1829         if (ixgbe_wol_exclusion(adapter, wol) ||
1830             !device_can_wakeup(&adapter->pdev->dev))
1831                 return;
1832
1833         if (adapter->wol & IXGBE_WUFC_EX)
1834                 wol->wolopts |= WAKE_UCAST;
1835         if (adapter->wol & IXGBE_WUFC_MC)
1836                 wol->wolopts |= WAKE_MCAST;
1837         if (adapter->wol & IXGBE_WUFC_BC)
1838                 wol->wolopts |= WAKE_BCAST;
1839         if (adapter->wol & IXGBE_WUFC_MAG)
1840                 wol->wolopts |= WAKE_MAGIC;
1841
1842         return;
1843 }
1844
1845 static int ixgbe_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
1846 {
1847         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1848
1849         if (wol->wolopts & (WAKE_PHY | WAKE_ARP | WAKE_MAGICSECURE))
1850                 return -EOPNOTSUPP;
1851
1852         if (ixgbe_wol_exclusion(adapter, wol))
1853                 return wol->wolopts ? -EOPNOTSUPP : 0;
1854
1855         adapter->wol = 0;
1856
1857         if (wol->wolopts & WAKE_UCAST)
1858                 adapter->wol |= IXGBE_WUFC_EX;
1859         if (wol->wolopts & WAKE_MCAST)
1860                 adapter->wol |= IXGBE_WUFC_MC;
1861         if (wol->wolopts & WAKE_BCAST)
1862                 adapter->wol |= IXGBE_WUFC_BC;
1863         if (wol->wolopts & WAKE_MAGIC)
1864                 adapter->wol |= IXGBE_WUFC_MAG;
1865
1866         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
1867
1868         return 0;
1869 }
1870
1871 static int ixgbe_nway_reset(struct net_device *netdev)
1872 {
1873         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1874
1875         if (netif_running(netdev))
1876                 ixgbe_reinit_locked(adapter);
1877
1878         return 0;
1879 }
1880
1881 static int ixgbe_phys_id(struct net_device *netdev, u32 data)
1882 {
1883         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1884         struct ixgbe_hw *hw = &adapter->hw;
1885         u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1886         u32 i;
1887
1888         if (!data || data > 300)
1889                 data = 300;
1890
1891         for (i = 0; i < (data * 1000); i += 400) {
1892                 hw->mac.ops.led_on(hw, IXGBE_LED_ON);
1893                 msleep_interruptible(200);
1894                 hw->mac.ops.led_off(hw, IXGBE_LED_ON);
1895                 msleep_interruptible(200);
1896         }
1897
1898         /* Restore LED settings */
1899         IXGBE_WRITE_REG(&adapter->hw, IXGBE_LEDCTL, led_reg);
1900
1901         return 0;
1902 }
1903
1904 static int ixgbe_get_coalesce(struct net_device *netdev,
1905                               struct ethtool_coalesce *ec)
1906 {
1907         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1908
1909         ec->tx_max_coalesced_frames_irq = adapter->tx_ring[0].work_limit;
1910
1911         /* only valid if in constant ITR mode */
1912         switch (adapter->itr_setting) {
1913         case 0:
1914                 /* throttling disabled */
1915                 ec->rx_coalesce_usecs = 0;
1916                 break;
1917         case 1:
1918                 /* dynamic ITR mode */
1919                 ec->rx_coalesce_usecs = 1;
1920                 break;
1921         default:
1922                 /* fixed interrupt rate mode */
1923                 ec->rx_coalesce_usecs = 1000000/adapter->eitr_param;
1924                 break;
1925         }
1926         return 0;
1927 }
1928
1929 static int ixgbe_set_coalesce(struct net_device *netdev,
1930                               struct ethtool_coalesce *ec)
1931 {
1932         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1933         int i;
1934
1935         if (ec->tx_max_coalesced_frames_irq)
1936                 adapter->tx_ring[0].work_limit = ec->tx_max_coalesced_frames_irq;
1937
1938         if (ec->rx_coalesce_usecs > 1) {
1939                 /* check the limits */
1940                 if ((1000000/ec->rx_coalesce_usecs > IXGBE_MAX_INT_RATE) ||
1941                     (1000000/ec->rx_coalesce_usecs < IXGBE_MIN_INT_RATE))
1942                         return -EINVAL;
1943
1944                 /* store the value in ints/second */
1945                 adapter->eitr_param = 1000000/ec->rx_coalesce_usecs;
1946
1947                 /* static value of interrupt rate */
1948                 adapter->itr_setting = adapter->eitr_param;
1949                 /* clear the lower bit as its used for dynamic state */
1950                 adapter->itr_setting &= ~1;
1951         } else if (ec->rx_coalesce_usecs == 1) {
1952                 /* 1 means dynamic mode */
1953                 adapter->eitr_param = 20000;
1954                 adapter->itr_setting = 1;
1955         } else {
1956                 /*
1957                  * any other value means disable eitr, which is best
1958                  * served by setting the interrupt rate very high
1959                  */
1960                 adapter->eitr_param = IXGBE_MAX_INT_RATE;
1961                 adapter->itr_setting = 0;
1962         }
1963
1964         for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
1965                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
1966                 if (q_vector->txr_count && !q_vector->rxr_count)
1967                         /* tx vector gets half the rate */
1968                         q_vector->eitr = (adapter->eitr_param >> 1);
1969                 else
1970                         /* rx only or mixed */
1971                         q_vector->eitr = adapter->eitr_param;
1972                 ixgbe_write_eitr(adapter, i,
1973                                  EITR_INTS_PER_SEC_TO_REG(q_vector->eitr));
1974         }
1975
1976         return 0;
1977 }
1978
1979 static int ixgbe_set_flags(struct net_device *netdev, u32 data)
1980 {
1981         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1982
1983         ethtool_op_set_flags(netdev, data);
1984
1985         if (!(adapter->flags & IXGBE_FLAG_RSC_CAPABLE))
1986                 return 0;
1987
1988         /* if state changes we need to update adapter->flags and reset */
1989         if ((!!(data & ETH_FLAG_LRO)) !=
1990             (!!(adapter->flags & IXGBE_FLAG_RSC_ENABLED))) {
1991                 adapter->flags ^= IXGBE_FLAG_RSC_ENABLED;
1992                 if (netif_running(netdev))
1993                         ixgbe_reinit_locked(adapter);
1994                 else
1995                         ixgbe_reset(adapter);
1996         }
1997         return 0;
1998
1999 }
2000
2001 static const struct ethtool_ops ixgbe_ethtool_ops = {
2002         .get_settings           = ixgbe_get_settings,
2003         .set_settings           = ixgbe_set_settings,
2004         .get_drvinfo            = ixgbe_get_drvinfo,
2005         .get_regs_len           = ixgbe_get_regs_len,
2006         .get_regs               = ixgbe_get_regs,
2007         .get_wol                = ixgbe_get_wol,
2008         .set_wol                = ixgbe_set_wol,
2009         .nway_reset             = ixgbe_nway_reset,
2010         .get_link               = ethtool_op_get_link,
2011         .get_eeprom_len         = ixgbe_get_eeprom_len,
2012         .get_eeprom             = ixgbe_get_eeprom,
2013         .get_ringparam          = ixgbe_get_ringparam,
2014         .set_ringparam          = ixgbe_set_ringparam,
2015         .get_pauseparam         = ixgbe_get_pauseparam,
2016         .set_pauseparam         = ixgbe_set_pauseparam,
2017         .get_rx_csum            = ixgbe_get_rx_csum,
2018         .set_rx_csum            = ixgbe_set_rx_csum,
2019         .get_tx_csum            = ixgbe_get_tx_csum,
2020         .set_tx_csum            = ixgbe_set_tx_csum,
2021         .get_sg                 = ethtool_op_get_sg,
2022         .set_sg                 = ethtool_op_set_sg,
2023         .get_msglevel           = ixgbe_get_msglevel,
2024         .set_msglevel           = ixgbe_set_msglevel,
2025         .get_tso                = ethtool_op_get_tso,
2026         .set_tso                = ixgbe_set_tso,
2027         .self_test              = ixgbe_diag_test,
2028         .get_strings            = ixgbe_get_strings,
2029         .phys_id                = ixgbe_phys_id,
2030         .get_sset_count         = ixgbe_get_sset_count,
2031         .get_ethtool_stats      = ixgbe_get_ethtool_stats,
2032         .get_coalesce           = ixgbe_get_coalesce,
2033         .set_coalesce           = ixgbe_set_coalesce,
2034         .get_flags              = ethtool_op_get_flags,
2035         .set_flags              = ixgbe_set_flags,
2036 };
2037
2038 void ixgbe_set_ethtool_ops(struct net_device *netdev)
2039 {
2040         SET_ETHTOOL_OPS(netdev, &ixgbe_ethtool_ops);
2041 }