git.oblomov.eu Git - linux-2.6/blob - drivers/staging/pata_rdc/pata_rdc.c

   1 #include <linux/kernel.h>
   2 #include <linux/init.h>
   3 #include <linux/module.h>
   4
   5 #include <linux/pci.h>
   6 #include <linux/device.h>
   7
   8 #include <scsi/scsi_host.h>
   9 #include <linux/libata.h>
  10
  11 #include "pata_rdc.h"
  12
  13 /* Driver Info. */
  14 #define DRIVER_NAME         "pata_rdc"  /* sata_rdc for SATA */
  15 #define DRIVER_VERSION      "2.6.28"    /* based on kernel version. */
  16                                         /* because each kernel main version has
  17                                          * its libata, we follow kernel to
  18                                          * determine the last libata version.
  19                                          */
  20
  21
  22 static const struct pci_device_id rdc_pata_id_table[] = {
  23         { PCI_DEVICE(0x17F3, 0x1011), RDC_17F31011},
  24         { PCI_DEVICE(0x17F3, 0x1012), RDC_17F31012},
  25         { }     /* terminate list */
  26 };
  27 MODULE_DEVICE_TABLE(pci, rdc_pata_id_table);
  28
  29 /* see ATA Host Adapters Standards. */
  30 static struct pci_bits ATA_Decode_Enable_Bits[] = {
  31         { 0x41U, 1U, 0x80UL, 0x80UL },  /* port (Channel) 0 */
  32         { 0x43U, 1U, 0x80UL, 0x80UL },  /* port (Channel) 1 */
  33 };
  34
  35 static uint PCIDeviceIO_ReadPCIConfiguration(struct pci_dev *pdev, uint Offset, uint Length, void *pBuffer)
  36 {
  37         uint funcresult;
  38         unchar *pchar;
  39         uint i;
  40
  41         funcresult = TRUE;
  42
  43         pchar = pBuffer;
  44
  45         for (i = 0; i < Length; i++) {
  46                 pci_read_config_byte(pdev, Offset, pchar);
  47                 Offset++;
  48                 pchar++;
  49         }
  50
  51         funcresult = TRUE;
  52
  53         goto funcexit;
  54 funcexit:
  55
  56         return funcresult;
  57 }
  58
  59 static uint PCIDeviceIO_WritePCIConfiguration(struct pci_dev *pdev, uint Offset, uint Length, void *pBuffer)
  60 {
  61         uint funcresult;
  62         unchar *pchar;
  63         uint i;
  64
  65         funcresult = TRUE;
  66
  67         pchar = pBuffer;
  68
  69         for (i = 0; i < Length; i++) {
  70                 pci_write_config_byte(pdev, Offset, *pchar);
  71                 Offset++;
  72                 pchar++;
  73         }
  74
  75         funcresult = TRUE;
  76
  77         goto funcexit;
  78 funcexit:
  79
  80         return funcresult;
  81 }
  82
  83 static uint ATAHostAdapter_SetPrimaryPIO(struct pci_dev *pdev, uint DeviceID,
  84                                          uint PIOTimingMode, uint DMAEnable,
  85                                          uint PrefetchPostingEnable)
  86 {
  87         uint funcresult;
  88         uint result;
  89         uint ATATimingRegister;
  90         uint Device1TimingRegister;
  91
  92         funcresult = TRUE;
  93
  94         ATATimingRegister = 0;
  95         Device1TimingRegister = 0;
  96
  97         result = PCIDeviceIO_ReadPCIConfiguration(pdev,
  98                                                  ATAConfiguration_ID_PrimaryTiming + ATAConfiguration_PCIOffset,
  99                                                  ATAConfiguration_ID_PrimaryTiming_Size,
 100                                                  &ATATimingRegister);
 101         if (result == FALSE) {
 102                 funcresult = FALSE;
 103                 goto funcexit;
 104         }
 105
 106         result = PCIDeviceIO_ReadPCIConfiguration(pdev,
 107                                                   ATAConfiguration_ID_Device1Timing + ATAConfiguration_PCIOffset,
 108                                                   ATAConfiguration_ID_Device1Timing_Size,
 109                                                   &Device1TimingRegister);
 110         if (result == FALSE) {
 111                 funcresult = FALSE;
 112                 goto funcexit;
 113         }
 114
 115         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1TimingRegisterEnable;
 116
 117         switch (DeviceID) {
 118         case 0:
 119                 /* mask clear */
 120                 ATATimingRegister &= ~(ATAConfiguration_PrimaryTiming_Device0FastTimingEnable |
 121                                       ATAConfiguration_PrimaryTiming_Device0IORDYSampleModeEnable |
 122                                       ATAConfiguration_PrimaryTiming_Device0PrefetchandPostingEnable |
 123                                       ATAConfiguration_PrimaryTiming_Device0DMATimingEnable |
 124                                       ATAConfiguration_PrimaryTiming_Device0RecoveryMode |
 125                                       ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode);
 126
 127                 if (PIOTimingMode > PIO0)
 128                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0FastTimingEnable;
 129
 130                 if (PIOTimingMode >= PIO3)
 131                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleModeEnable;
 132
 133                 if (PIOTimingMode >= PIO2 && PrefetchPostingEnable == TRUE)
 134                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0PrefetchandPostingEnable;
 135
 136                 if (DMAEnable == TRUE && PIOTimingMode >= PIO2)
 137                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0DMATimingEnable;
 138
 139                 if (PIOTimingMode <= PIO2)
 140                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_0;
 141                 else if (PIOTimingMode == PIO3)
 142                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_1;
 143                 else if (PIOTimingMode == PIO4)
 144                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_3;
 145
 146                 if (PIOTimingMode <= PIO1)
 147                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_0;
 148                 else if (PIOTimingMode == PIO2)
 149                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_1;
 150                 else if (PIOTimingMode <= PIO4)
 151                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_2;
 152                 break;
 153         case 1:
 154                 ATATimingRegister &= ~(ATAConfiguration_PrimaryTiming_Device1FastTimingEnable |
 155                                        ATAConfiguration_PrimaryTiming_Device1IORDYSampleModeEnable |
 156                                        ATAConfiguration_PrimaryTiming_Device1PrefetchandPostingEnable |
 157                                        ATAConfiguration_PrimaryTiming_Device1DMATimingEnable);
 158
 159                 if (PIOTimingMode > PIO0)
 160                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1FastTimingEnable;
 161
 162                 if (PIOTimingMode >= PIO3)
 163                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1IORDYSampleModeEnable;
 164
 165                 if (PIOTimingMode >= PIO2 && PrefetchPostingEnable == TRUE)
 166                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1PrefetchandPostingEnable;
 167
 168                 if (DMAEnable == TRUE && PIOTimingMode >= PIO2)
 169                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1DMATimingEnable;
 170
 171                 Device1TimingRegister &= ~(ATAConfiguration_Device1Timing_PrimaryRecoveryMode |
 172                                            ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode);
 173
 174                 if (PIOTimingMode <= PIO2)
 175                         Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryRecoveryMode_0;
 176                 else if (PIOTimingMode == PIO3)
 177                         Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryRecoveryMode_1;
 178                 else if (PIOTimingMode == PIO4)
 179                         Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryRecoveryMode_3;
 180
 181                 if (PIOTimingMode <= PIO1)
 182                         Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_0;
 183                 else if (PIOTimingMode == PIO2)
 184                         Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_1;
 185                 else if (PIOTimingMode <= PIO4)
 186                         Device1TimingRegister |= ATAConfiguration_Device1Timing_PrimaryIORDYSampleMode_2;
 187                 break;
 188         default:
 189                 funcresult = FALSE;
 190                 goto funcexit;
 191                 break;
 192         }
 193
 194         result = PCIDeviceIO_WritePCIConfiguration(pdev,
 195                                                    ATAConfiguration_ID_PrimaryTiming + ATAConfiguration_PCIOffset,
 196                                                    ATAConfiguration_ID_PrimaryTiming_Size,
 197                                                    &ATATimingRegister);
 198         if (result == FALSE) {
 199                 funcresult = FALSE;
 200                 goto funcexit;
 201         }
 202
 203         result = PCIDeviceIO_WritePCIConfiguration(pdev,
 204                                                    ATAConfiguration_ID_Device1Timing + ATAConfiguration_PCIOffset,
 205                                                    ATAConfiguration_ID_Device1Timing_Size,
 206                                                    &Device1TimingRegister);
 207         if (result == FALSE) {
 208                 funcresult = FALSE;
 209                 goto funcexit;
 210         }
 211
 212         goto funcexit;
 213 funcexit:
 214
 215         return funcresult;
 216 }
 217
 218 static uint ATAHostAdapter_SetSecondaryPIO(struct pci_dev *pdev, uint DeviceID,
 219                                            uint PIOTimingMode, uint DMAEnable,
 220                                            uint PrefetchPostingEnable)
 221 {
 222         uint funcresult;
 223         uint result;
 224         uint ATATimingRegister;
 225         uint Device1TimingRegister;
 226
 227         funcresult = TRUE;
 228
 229         ATATimingRegister = 0;
 230         Device1TimingRegister = 0;
 231
 232         result = PCIDeviceIO_ReadPCIConfiguration(pdev,
 233                                                   ATAConfiguration_ID_SecondaryTiming + ATAConfiguration_PCIOffset,
 234                                                   ATAConfiguration_ID_SecondaryTiming_Size,
 235                                                   &ATATimingRegister);
 236         if (result == FALSE) {
 237                 funcresult = FALSE;
 238                 goto funcexit;
 239         }
 240
 241         result = PCIDeviceIO_ReadPCIConfiguration(pdev,
 242                                                   ATAConfiguration_ID_Device1Timing + ATAConfiguration_PCIOffset,
 243                                                   ATAConfiguration_ID_Device1Timing_Size,
 244                                                   &Device1TimingRegister);
 245         if (result == FALSE) {
 246                 funcresult = FALSE;
 247                 goto funcexit;
 248         }
 249
 250         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1TimingRegisterEnable;
 251
 252         switch (DeviceID) {
 253         case 0:
 254                 /* mask clear */
 255                 ATATimingRegister &= ~(ATAConfiguration_PrimaryTiming_Device0FastTimingEnable |
 256                                        ATAConfiguration_PrimaryTiming_Device0IORDYSampleModeEnable |
 257                                        ATAConfiguration_PrimaryTiming_Device0PrefetchandPostingEnable |
 258                                        ATAConfiguration_PrimaryTiming_Device0DMATimingEnable |
 259                                        ATAConfiguration_PrimaryTiming_Device0RecoveryMode |
 260                                        ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode);
 261
 262                 if (PIOTimingMode > PIO0)
 263                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0FastTimingEnable;
 264
 265                 if (PIOTimingMode >= PIO3)
 266                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleModeEnable;
 267
 268                 if (PIOTimingMode >= PIO2 && PrefetchPostingEnable == TRUE)
 269                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0PrefetchandPostingEnable;
 270
 271                 if (DMAEnable == TRUE && PIOTimingMode >= PIO2)
 272                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0DMATimingEnable;
 273
 274                 if (PIOTimingMode <= PIO2)
 275                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_0;
 276                 else if (PIOTimingMode == PIO3)
 277                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_1;
 278                 else if (PIOTimingMode == PIO4)
 279                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0RecoveryMode_3;
 280
 281                 if (PIOTimingMode <= PIO1)
 282                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_0;
 283                 else if (PIOTimingMode == PIO2)
 284                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_1;
 285                 else if (PIOTimingMode <= PIO4)
 286                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device0IORDYSampleMode_2;
 287                 break;
 288         case 1:
 289                 ATATimingRegister &= ~(ATAConfiguration_PrimaryTiming_Device1FastTimingEnable |
 290                                        ATAConfiguration_PrimaryTiming_Device1IORDYSampleModeEnable |
 291                                        ATAConfiguration_PrimaryTiming_Device1PrefetchandPostingEnable |
 292                                        ATAConfiguration_PrimaryTiming_Device1DMATimingEnable);
 293
 294                 if (PIOTimingMode > PIO0)
 295                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1FastTimingEnable;
 296
 297                 if (PIOTimingMode >= PIO3)
 298                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1IORDYSampleModeEnable;
 299
 300                 if (PIOTimingMode >= PIO2 && PrefetchPostingEnable == TRUE)
 301                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1PrefetchandPostingEnable;
 302
 303                 if (DMAEnable == TRUE && PIOTimingMode >= PIO2)
 304                         ATATimingRegister |= ATAConfiguration_PrimaryTiming_Device1DMATimingEnable;
 305
 306                 Device1TimingRegister &= ~(ATAConfiguration_Device1Timing_SecondaryRecoveryMode |
 307                                            ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode);
 308
 309                 if (PIOTimingMode <= PIO2)
 310                         Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryRecoveryMode_0;
 311                 else if (PIOTimingMode == PIO3)
 312                         Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryRecoveryMode_1;
 313                 else if (PIOTimingMode == PIO4)
 314                         Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryRecoveryMode_3;
 315
 316                 if (PIOTimingMode <= PIO1)
 317                         Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_0;
 318                 else if (PIOTimingMode == PIO2)
 319                         Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_1;
 320                 else if (PIOTimingMode <= PIO4)
 321                         Device1TimingRegister |= ATAConfiguration_Device1Timing_SecondaryIORDYSampleMode_2;
 322                 break;
 323         default:
 324                 funcresult = FALSE;
 325                 goto funcexit;
 326                 break;
 327         }
 328
 329         result = PCIDeviceIO_WritePCIConfiguration(pdev,
 330                                                    ATAConfiguration_ID_SecondaryTiming + ATAConfiguration_PCIOffset,
 331                                                    ATAConfiguration_ID_SecondaryTiming_Size,
 332                                                    &ATATimingRegister);
 333         if (result == FALSE) {
 334                 funcresult = FALSE;
 335                 goto funcexit;
 336         }
 337
 338         result = PCIDeviceIO_WritePCIConfiguration(pdev,
 339                                                    ATAConfiguration_ID_Device1Timing + ATAConfiguration_PCIOffset,
 340                                                    ATAConfiguration_ID_Device1Timing_Size,
 341                                                    &Device1TimingRegister);
 342         if (result == FALSE) {
 343                 funcresult = FALSE;
 344                 goto funcexit;
 345         }
 346
 347         goto funcexit;
 348 funcexit:
 349         return funcresult;
 350 }
 351
 352 static uint ATAHostAdapter_SetPrimaryUDMA(struct pci_dev *pdev, uint DeviceID,
 353                                           uint UDMAEnable, uint UDMATimingMode)
 354 {
 355         uint funcresult;
 356         uint result;
 357         uint UDMAControlRegister;
 358         uint UDMATimingRegister;
 359         ulong IDEIOConfigurationRegister;
 360
 361         funcresult = TRUE;
 362         UDMAControlRegister = 0;
 363         UDMATimingRegister = 0;
 364         IDEIOConfigurationRegister = 0;
 365
 366         result = PCIDeviceIO_ReadPCIConfiguration(pdev,
 367                                                   ATAConfiguration_ID_UDMAControl + ATAConfiguration_PCIOffset,
 368                                                   ATAConfiguration_ID_UDMAControl_Size,
 369                                                   &UDMAControlRegister);
 370         if (result == FALSE) {
 371                 funcresult = FALSE;
 372                 goto funcexit;
 373         }
 374
 375         result = PCIDeviceIO_ReadPCIConfiguration(pdev,
 376                                                   ATAConfiguration_ID_UDMATiming + ATAConfiguration_PCIOffset,
 377                                                   ATAConfiguration_ID_UDMATiming_Size,
 378                                                   &UDMATimingRegister);
 379         if (result == FALSE) {
 380                 funcresult = FALSE;
 381                 goto funcexit;
 382         }
 383
 384         result = PCIDeviceIO_ReadPCIConfiguration(pdev,
 385                                                   ATAConfiguration_ID_IDEIOConfiguration + ATAConfiguration_PCIOffset,
 386                                                   ATAConfiguration_ID_IDEIOConfiguration_Size,
 387                                                   &IDEIOConfigurationRegister);
 388         if (result == FALSE) {
 389                 funcresult = FALSE;
 390                 goto funcexit;
 391         }
 392
 393         /*Rom Code will determine the device cable type and ATA 100.*/
 394         /*IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_DeviceCable80Report;*/
 395         /*IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_ATA100IsSupported;*/
 396
 397         switch (DeviceID) {
 398         case 0:
 399                 UDMAControlRegister &= ~(ATAConfiguration_UDMAControl_PrimaryDevice0UDMAModeEnable);
 400                 if (UDMAEnable == TRUE)
 401                         UDMAControlRegister |= ATAConfiguration_UDMAControl_PrimaryDevice0UDMAModeEnable;
 402
 403                 IDEIOConfigurationRegister &= ~(ATAConfiguration_IDEIOConfiguration_PrimaryDevice066MhzEnable |
 404                                                 ATAConfiguration_IDEIOConfiguration_PrimaryDevice0100MhzEnable);
 405
 406                 if (UDMATimingMode >= UDMA5)
 407                         IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_PrimaryDevice0100MhzEnable;
 408                 else if (UDMATimingMode >= UDMA3)
 409                         IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_PrimaryDevice066MhzEnable;
 410
 411                 /* if 80 cable report */
 412                 UDMATimingRegister &= ~(ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime);
 413
 414                 if (UDMATimingMode == UDMA0) {
 415                         UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_0;
 416                 } else if (UDMATimingMode == UDMA1 ||
 417                            UDMATimingMode == UDMA3 ||
 418                            UDMATimingMode == UDMA5) {
 419                         UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_1;
 420                 } else if (UDMATimingMode == UDMA2 ||
 421                            UDMATimingMode == UDMA4) {
 422                         UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice0CycleTime_2;
 423                 }
 424                 break;
 425         case 1:
 426                 UDMAControlRegister &= ~(ATAConfiguration_UDMAControl_PrimaryDevice1UDMAModeEnable);
 427                 if (UDMAEnable == TRUE)
 428                         UDMAControlRegister |= ATAConfiguration_UDMAControl_PrimaryDevice1UDMAModeEnable;
 429
 430                 IDEIOConfigurationRegister &= ~(ATAConfiguration_IDEIOConfiguration_PrimaryDevice166MhzEnable |
 431                                                 ATAConfiguration_IDEIOConfiguration_PrimaryDevice1100MhzEnable);
 432
 433                 if (UDMATimingMode >= UDMA5)
 434                         IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_PrimaryDevice1100MhzEnable;
 435                 else if (UDMATimingMode >= UDMA3)
 436                         IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_PrimaryDevice166MhzEnable;
 437
 438                 /* if 80 cable report */
 439                 UDMATimingRegister &= ~(ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime);
 440
 441                 if (UDMATimingMode == UDMA0) {
 442                         UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_0;
 443                 } else if (UDMATimingMode == UDMA1 ||
 444                            UDMATimingMode == UDMA3 ||
 445                            UDMATimingMode == UDMA5) {
 446                         UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_1;
 447                 } else if (UDMATimingMode == UDMA2 ||
 448                            UDMATimingMode == UDMA4) {
 449                         UDMATimingRegister |= ATAConfiguration_UDMATiming_PrimaryDevice1CycleTime_2;
 450                 }
 451                 break;
 452         default:
 453                 funcresult = FALSE;
 454                 goto funcexit;
 455                 break;
 456         }
 457
 458         result = PCIDeviceIO_WritePCIConfiguration(pdev,
 459                                                    ATAConfiguration_ID_UDMAControl + ATAConfiguration_PCIOffset,
 460                                                    ATAConfiguration_ID_UDMAControl_Size,
 461                                                    &UDMAControlRegister);
 462         if (result == FALSE) {
 463                 funcresult = FALSE;
 464                 goto funcexit;
 465         }
 466
 467         result = PCIDeviceIO_WritePCIConfiguration(pdev,
 468                                                    ATAConfiguration_ID_UDMATiming + ATAConfiguration_PCIOffset,
 469                                                    ATAConfiguration_ID_UDMATiming_Size,
 470                                                    &UDMATimingRegister);
 471         if (result == FALSE) {
 472                 funcresult = FALSE;
 473                 goto funcexit;
 474         }
 475
 476         result = PCIDeviceIO_WritePCIConfiguration(pdev,
 477                                                    ATAConfiguration_ID_IDEIOConfiguration + ATAConfiguration_PCIOffset,
 478                                                    ATAConfiguration_ID_IDEIOConfiguration_Size,
 479                                                    &IDEIOConfigurationRegister);
 480         if (result == FALSE) {
 481                 funcresult = FALSE;
 482                 goto funcexit;
 483         }
 484
 485         goto funcexit;
 486 funcexit:
 487         return funcresult;
 488 }
 489
 490 static uint ATAHostAdapter_SetSecondaryUDMA(struct pci_dev *pdev, uint DeviceID,
 491                                             uint UDMAEnable, uint UDMATimingMode)
 492 {
 493         uint funcresult;
 494         uint result;
 495         uint UDMAControlRegister;
 496         uint UDMATimingRegister;
 497         ulong IDEIOConfigurationRegister;
 498
 499         funcresult = TRUE;
 500
 501         UDMAControlRegister = 0;
 502         UDMATimingRegister = 0;
 503         IDEIOConfigurationRegister = 0;
 504
 505         result = PCIDeviceIO_ReadPCIConfiguration(pdev,
 506                                                   ATAConfiguration_ID_UDMAControl + ATAConfiguration_PCIOffset,
 507                                                   ATAConfiguration_ID_UDMAControl_Size,
 508                                                   &UDMAControlRegister);
 509         if (result == FALSE) {
 510                 funcresult = FALSE;
 511                 goto funcexit;
 512         }
 513
 514         result = PCIDeviceIO_ReadPCIConfiguration(pdev,
 515                                                   ATAConfiguration_ID_UDMATiming + ATAConfiguration_PCIOffset,
 516                                                   ATAConfiguration_ID_UDMATiming_Size,
 517                                                   &UDMATimingRegister);
 518         if (result == FALSE) {
 519                 funcresult = FALSE;
 520                 goto funcexit;
 521         }
 522
 523         result = PCIDeviceIO_ReadPCIConfiguration(pdev,
 524                                                   ATAConfiguration_ID_IDEIOConfiguration + ATAConfiguration_PCIOffset,
 525                                                   ATAConfiguration_ID_IDEIOConfiguration_Size,
 526                                                   &IDEIOConfigurationRegister);
 527         if (result == FALSE) {
 528                 funcresult = FALSE;
 529                 goto funcexit;
 530         }
 531
 532         /* Rom Code will determine the device cable type and ATA 100. */
 533         /* IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_DeviceCable80Report; */
 534         /* IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_ATA100IsSupported; */
 535
 536         switch (DeviceID) {
 537         case 0:
 538                 UDMAControlRegister &= ~(ATAConfiguration_UDMAControl_SecondaryDevice0UDMAModeEnable);
 539                 if (UDMAEnable == TRUE)
 540                         UDMAControlRegister |= ATAConfiguration_UDMAControl_SecondaryDevice0UDMAModeEnable;
 541
 542                 IDEIOConfigurationRegister &= ~(ATAConfiguration_IDEIOConfiguration_SecondaryDevice066MhzEnable |
 543                                                 ATAConfiguration_IDEIOConfiguration_SecondaryDevice0100MhzEnable);
 544
 545                 if (UDMATimingMode >= UDMA5)
 546                         IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_SecondaryDevice0100MhzEnable;
 547                 else if (UDMATimingMode >= UDMA3)
 548                         IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_SecondaryDevice066MhzEnable;
 549
 550                 /* if 80 cable report */
 551                 UDMATimingRegister &= ~(ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime);
 552
 553                 if (UDMATimingMode == UDMA0) {
 554                         UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_0;
 555                 } else if (UDMATimingMode == UDMA1 ||
 556                            UDMATimingMode == UDMA3 ||
 557                            UDMATimingMode == UDMA5) {
 558                         UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_1;
 559                 } else if (UDMATimingMode == UDMA2 ||
 560                            UDMATimingMode == UDMA4) {
 561                         UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice0CycleTime_2;
 562                 }
 563                 break;
 564         case 1:
 565                 UDMAControlRegister &= ~(ATAConfiguration_UDMAControl_SecondaryDevice1UDMAModeEnable);
 566                 if (UDMAEnable == TRUE)
 567                         UDMAControlRegister |= ATAConfiguration_UDMAControl_SecondaryDevice1UDMAModeEnable;
 568
 569                 IDEIOConfigurationRegister &= ~(ATAConfiguration_IDEIOConfiguration_SecondaryDevice166MhzEnable |
 570                                                 ATAConfiguration_IDEIOConfiguration_SecondaryDevice1100MhzEnable);
 571
 572                 if (UDMATimingMode >= UDMA5)
 573                         IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_SecondaryDevice1100MhzEnable;
 574                 else if (UDMATimingMode >= UDMA3)
 575                         IDEIOConfigurationRegister |= ATAConfiguration_IDEIOConfiguration_SecondaryDevice166MhzEnable;
 576
 577                 /* if 80 cable report */
 578                 UDMATimingRegister &= ~(ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime);
 579
 580                 if (UDMATimingMode == UDMA0) {
 581                         UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_0;
 582                 } else if (UDMATimingMode == UDMA1 ||
 583                            UDMATimingMode == UDMA3 ||
 584                            UDMATimingMode == UDMA5) {
 585                         UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_1;
 586                 } else if (UDMATimingMode == UDMA2 ||
 587                            UDMATimingMode == UDMA4) {
 588                         UDMATimingRegister |= ATAConfiguration_UDMATiming_SecondaryDevice1CycleTime_2;
 589                 }
 590                 break;
 591         default:
 592                 funcresult = FALSE;
 593                 goto funcexit;
 594                 break;
 595         }
 596
 597         result = PCIDeviceIO_WritePCIConfiguration(pdev,
 598                                                    ATAConfiguration_ID_UDMAControl + ATAConfiguration_PCIOffset,
 599                                                    ATAConfiguration_ID_UDMAControl_Size,
 600                                                    &UDMAControlRegister);
 601         if (result == FALSE) {
 602                 funcresult = FALSE;
 603                 goto funcexit;
 604         }
 605
 606         result = PCIDeviceIO_WritePCIConfiguration(pdev,
 607                                                    ATAConfiguration_ID_UDMATiming + ATAConfiguration_PCIOffset,
 608                                                    ATAConfiguration_ID_UDMATiming_Size,
 609                                                    &UDMATimingRegister);
 610         if (result == FALSE) {
 611                 funcresult = FALSE;
 612                 goto funcexit;
 613         }
 614
 615         result = PCIDeviceIO_WritePCIConfiguration(pdev,
 616                                                    ATAConfiguration_ID_IDEIOConfiguration + ATAConfiguration_PCIOffset,
 617                                                    ATAConfiguration_ID_IDEIOConfiguration_Size,
 618                                                    &IDEIOConfigurationRegister);
 619         if (result == FALSE) {
 620                 funcresult = FALSE;
 621                 goto funcexit;
 622         }
 623
 624         goto funcexit;
 625 funcexit:
 626         return funcresult;
 627 }
 628
 629 /**
 630  *    Set port up for dma.
 631  *    @ap: Port to initialize
 632  *
 633  *    Called just after data structures for each port are
 634  *    initialized.  Allocates space for PRD table if the device
 635  *    is DMA capable SFF.
 636
 637     Some drivers also use this entry point as a chance to allocate driverprivate
 638     memory for ap->private_data.
 639
 640  *
 641  *    May be used as the port_start() entry in ata_port_operations.
 642  *
 643  *    LOCKING:
 644  *    Inherited from caller.
 645  */
 646 static int rdc_pata_port_start(struct ata_port *ap)
 647 {
 648         uint    Channel;
 649
 650         Channel = ap->port_no;
 651         dev_dbg(ap->dev, "%s: Channel: %u\n", __func__, Channel);
 652         if (ap->ioaddr.bmdma_addr) {
 653                 return ata_port_start(ap);
 654         } else {
 655                 dev_dbg(ap->dev, "%s: return 0!!!\n", __func__);
 656                 return 0;
 657         }
 658 }
 659
 660 static void rdc_pata_port_stop(struct ata_port *ap)
 661 {
 662         uint    Channel;
 663
 664         Channel = ap->port_no;
 665
 666         dev_dbg(ap->dev, "%s Channel: %u\n", __func__, Channel);
 667 }
 668
 669 /**
 670  *    prereset for PATA host controller
 671  *    @link: Target link
 672  *    @deadline: deadline jiffies for the operation
 673  *
 674  *    LOCKING:
 675  *    None (inherited from caller).
 676  */
 677 static int rdc_pata_prereset(struct ata_link *link, unsigned long deadline)
 678 {
 679         struct pci_dev *pdev;
 680         struct ata_port *ap;
 681         uint Channel;
 682
 683         dev_dbg(link->ap->dev, "%s\n", __func__);
 684
 685         ap = link->ap;
 686         pdev = to_pci_dev(ap->host->dev);
 687
 688         Channel = ap->port_no;
 689
 690         /* test ATA Decode Enable Bits, should be enable. */
 691         if (!pci_test_config_bits(pdev, &ATA_Decode_Enable_Bits[Channel])) {
 692                 dev_dbg(link->ap->dev, "%s: Channel: %u, Decode Disable\n",
 693                         __func__, Channel);
 694                 return -ENOENT;
 695         } else {
 696                 dev_dbg(link->ap->dev, "%s: Channel: %u, Decode Enable\n",
 697                         __func__, Channel);
 698                 return ata_std_prereset(link, deadline);
 699         }
 700 }
 701
 702 /**
 703  *    Probe host controller cable detect info
 704  *    @ap: Port for which cable detect info is desired
 705  *
 706  *    Read cable indicator from ATA PCI device's PCI config
 707  *    register.  This register is normally set by firmware (BIOS).
 708  *
 709  *    LOCKING:
 710  *    None (inherited from caller).
 711  */
 712 static int rdc_pata_cable_detect(struct ata_port *ap)
 713 {
 714         struct pci_dev *pdev;
 715         uint Channel;
 716         uint Mask;
 717         u32 u32Value;
 718
 719         dev_dbg(ap->dev, "%s\n", __func__);
 720
 721         pdev = to_pci_dev(ap->host->dev);
 722
 723         Channel = ap->port_no;
 724
 725         if (Channel == 0)
 726                 Mask = ATAConfiguration_IDEIOConfiguration_PrimaryDeviceCable80Report;
 727         else
 728                 Mask = ATAConfiguration_IDEIOConfiguration_SecondaryDeviceCable80Report;
 729
 730         /* check BIOS cable detect results */
 731         pci_read_config_dword(pdev, ATAConfiguration_ID_IDEIOConfiguration + ATAConfiguration_PCIOffset, &u32Value);
 732
 733         if ((u32Value & Mask) == 0) {
 734                 dev_dbg(ap->dev, "%s: Channel: %u, PATA40 \n",
 735                         __func__, Channel);
 736                 return ATA_CBL_PATA40;
 737         } else {
 738                 dev_dbg(ap->dev, "%s: Channel: %u, PATA80 \n",
 739                         __func__, Channel);
 740                 return ATA_CBL_PATA80;
 741         }
 742 }
 743
 744 /**
 745  *    Initialize host controller PATA PIO timings
 746  *    @ap: Port whose timings we are configuring
 747  *    @adev: um
 748  *
 749  *    Set PIO mode for device, in host controller PCI config space.
 750  *
 751  *    LOCKING:
 752  *    None (inherited from caller).
 753  */
 754 static void rdc_pata_set_piomode(struct ata_port *ap, struct ata_device *adev)
 755 {
 756         struct pci_dev *pdev;
 757         uint    Channel;
 758         uint    DeviceID;
 759         uint    PIOTimingMode;
 760         uint    PrefetchPostingEnable;
 761
 762         dev_dbg(ap->dev, "%s\n", __func__);
 763
 764         pdev = to_pci_dev(ap->host->dev);
 765
 766         Channel = ap->port_no;
 767         DeviceID = adev->devno;
 768         /*
 769          * piomode = 0, 1, 2, 3... ; adev->pio_mode = XFER_PIO_0, XFER_PIO_1,
 770          * XFER_PIO_2, XFER_PIO_3...
 771          */
 772         PIOTimingMode = adev->pio_mode - XFER_PIO_0;
 773
 774         if (adev->class == ATA_DEV_ATA) {
 775                 PrefetchPostingEnable = TRUE;
 776         } else {
 777                 /* ATAPI, CD DVD Rom */
 778                 PrefetchPostingEnable = FALSE;
 779         }
 780
 781         /* PIO configuration clears DTE unconditionally.  It will be
 782          * programmed in set_dmamode which is guaranteed to be called
 783          * after set_piomode if any DMA mode is available.
 784          */
 785
 786         /* Ensure the UDMA bit is off - it will be turned back on if UDMA is
 787          * selected */
 788
 789         if (Channel == 0) {
 790                 ATAHostAdapter_SetPrimaryPIO(
 791                     pdev,
 792                     DeviceID,
 793                     PIOTimingMode,
 794                     TRUE,/* DMAEnable, */
 795                     PrefetchPostingEnable
 796                     );
 797
 798                 ATAHostAdapter_SetPrimaryUDMA(
 799                     pdev,
 800                     DeviceID,
 801                     FALSE,/* UDMAEnable, */
 802                     UDMA0
 803                     );
 804         } else {
 805                 ATAHostAdapter_SetSecondaryPIO(
 806                     pdev,
 807                     DeviceID,
 808                     PIOTimingMode,
 809                     TRUE,/* DMAEnable, */
 810                     PrefetchPostingEnable
 811                     );
 812
 813                 ATAHostAdapter_SetSecondaryUDMA(
 814                     pdev,
 815                     DeviceID,
 816                     FALSE,/* UDMAEnable, */
 817                     UDMA0
 818                     );
 819         }
 820         dev_dbg(ap->dev, "%s: Channel: %u, DeviceID: %u, PIO: %d\n",
 821                 __func__, Channel, DeviceID, PIOTimingMode);
 822 }
 823
 824 /**
 825  *    Initialize host controller PATA DMA timings
 826  *    @ap: Port whose timings we are configuring
 827  *    @adev: um
 828  *
 829  *    Set MW/UDMA mode for device, in host controller PCI config space.
 830  *
 831  *    LOCKING:
 832  *    None (inherited from caller).
 833  */
 834 static void rdc_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev)
 835 {
 836         struct pci_dev *pdev;
 837         uint    Channel;
 838         uint    DeviceID;
 839         uint    PIOTimingMode;
 840         uint    PrefetchPostingEnable;
 841         uint    DMATimingMode;
 842         uint    UDMAEnable;
 843
 844         dev_dbg(ap->dev, "%s\n", __func__);
 845
 846         pdev = to_pci_dev(ap->host->dev);
 847
 848         Channel = ap->port_no;
 849         DeviceID = adev->devno;
 850         PIOTimingMode = adev->pio_mode - XFER_PIO_0;  /* piomode = 0, 1, 2, 3... ; adev->pio_mode = XFER_PIO_0, XFER_PIO_1, XFER_PIO_2, XFER_PIO_3... */
 851         DMATimingMode = adev->dma_mode; /* UDMA or MDMA */
 852
 853         if (adev->class == ATA_DEV_ATA) {
 854                 PrefetchPostingEnable = TRUE;
 855         } else {
 856                 /* ATAPI, CD DVD Rom */
 857                 PrefetchPostingEnable = FALSE;
 858         }
 859
 860         if (ap->udma_mask == 0) {
 861                 /* ata_port dont support udma. depend on hardware spec. */
 862                 UDMAEnable = FALSE;
 863         } else {
 864                 UDMAEnable = TRUE;
 865         }
 866
 867         /*if (ap->mdma_mask == 0) {
 868         }*/
 869
 870         if (Channel == 0) {
 871                 if (DMATimingMode >= XFER_UDMA_0) {
 872                         /* UDMA */
 873                         ATAHostAdapter_SetPrimaryPIO(pdev,
 874                                 DeviceID,
 875                                 PIOTimingMode,
 876                                 TRUE,/*DMAEnable,*/
 877                                 PrefetchPostingEnable);
 878
 879                         ATAHostAdapter_SetPrimaryUDMA(pdev,
 880                                 DeviceID,
 881                                 UDMAEnable,
 882                                 DMATimingMode - XFER_UDMA_0);
 883                         dev_dbg(ap->dev,
 884                                 "%s: Channel: %u, DeviceID: %u, UDMA: %u\n",
 885                                 __func__, Channel, DeviceID,
 886                                 (uint)(DMATimingMode - XFER_UDMA_0));
 887                 } else {
 888                         /* MDMA */
 889                         ATAHostAdapter_SetPrimaryPIO(pdev,
 890                                 DeviceID,
 891                                 (DMATimingMode - XFER_MW_DMA_0) + PIO2, /* MDMA0 = PIO2 */
 892                                 TRUE,/*DMAEnable,*/
 893                                 PrefetchPostingEnable);
 894
 895                         ATAHostAdapter_SetPrimaryUDMA(pdev,
 896                                 DeviceID,
 897                                 FALSE,/*UDMAEnable,*/
 898                                 UDMA0);
 899                         dev_dbg(ap->dev,
 900                                 "%s: Channel: %u, DeviceID: %u, MDMA: %u\n",
 901                                 __func__, Channel, DeviceID,
 902                                 (uint)(DMATimingMode - XFER_MW_DMA_0));
 903                 }
 904         } else {
 905                 if (DMATimingMode >= XFER_UDMA_0) {
 906                         /* UDMA */
 907                         ATAHostAdapter_SetSecondaryPIO(pdev,
 908                                 DeviceID,
 909                                 PIOTimingMode,
 910                                 TRUE,/*DMAEnable,*/
 911                                 PrefetchPostingEnable);
 912
 913                         ATAHostAdapter_SetSecondaryUDMA(pdev,
 914                                 DeviceID,
 915                                 UDMAEnable,
 916                                 DMATimingMode - XFER_UDMA_0);
 917                         dev_dbg(ap->dev,
 918                                 "%s: Channel: %u, DeviceID: %u, UDMA: %u\n",
 919                                 __func__, Channel, DeviceID,
 920                                 (uint)(DMATimingMode - XFER_UDMA_0));
 921                 } else {
 922                         /* MDMA */
 923                         ATAHostAdapter_SetSecondaryPIO(pdev,
 924                                 DeviceID,
 925                                 (DMATimingMode - XFER_MW_DMA_0) + PIO2, /* MDMA0 = PIO2 */
 926                                 TRUE,/*DMAEnable,*/
 927                                 PrefetchPostingEnable);
 928
 929                         ATAHostAdapter_SetSecondaryUDMA(pdev,
 930                                 DeviceID,
 931                                 FALSE,/*UDMAEnable,*/
 932                                 UDMA0);
 933                         dev_dbg(ap->dev,
 934                                 "%s: Channel: %u, DeviceID: %u, MDMA: %u \n",
 935                                 __func__, Channel, DeviceID,
 936                                 (uint)(DMATimingMode - XFER_MW_DMA_0));
 937                 }
 938         }
 939 }
 940
 941 /* pata host template */
 942 static struct scsi_host_template rdc_pata_sht = {
 943         ATA_BMDMA_SHT(DRIVER_NAME),
 944 };
 945
 946 static struct ata_port_operations rdc_pata_ops = {
 947         .inherits       = &ata_bmdma_port_ops,
 948
 949         .port_start     = rdc_pata_port_start,
 950         .port_stop      = rdc_pata_port_stop,
 951         .prereset       = rdc_pata_prereset,
 952         .cable_detect   = rdc_pata_cable_detect,
 953         .set_piomode    = rdc_pata_set_piomode,
 954         .set_dmamode    = rdc_pata_set_dmamode,
 955 };
 956
 957 static struct ata_port_info rdc_pata_port_info[] = {
 958         [RDC_17F31011] = {
 959         .flags          = ATA_FLAG_SLAVE_POSS,
 960         .pio_mask       = 0x1f,         /* pio0-4 */
 961         .mwdma_mask     = 0x07,         /* mwdma0-2 */
 962         .udma_mask      = ATA_UDMA5,    /* udma0-5 */
 963         .port_ops       = &rdc_pata_ops,
 964         },
 965
 966         [RDC_17F31012] = {
 967         .flags          = ATA_FLAG_SLAVE_POSS,
 968         .pio_mask       = 0x1f,         /* pio0-4 */
 969         .mwdma_mask     = 0x07,         /* mwdma0-2 */
 970         .udma_mask      = ATA_UDMA5,    /* udma0-5 */
 971         .port_ops       = &rdc_pata_ops,
 972         },
 973 };
 974
 975 static int __devinit rdc_init_one(struct pci_dev *pdev,
 976                                   const struct pci_device_id *ent)
 977 {
 978         struct ata_port_info port_info[2];
 979         const struct ata_port_info *ppinfo[] = { &port_info[0], &port_info[1] };
 980
 981         int rc;
 982
 983         dev_dbg(&pdev->dev, "%s\n", __func__);
 984
 985         port_info[0] = rdc_pata_port_info[ent->driver_data];
 986         port_info[1] = rdc_pata_port_info[ent->driver_data];
 987
 988         /* enable device and prepare host */
 989         rc = pci_enable_device(pdev);
 990         if (rc) {
 991                 dev_dbg(&pdev->dev, "%s pci_enable_device failed\n", __func__);
 992                 return rc;
 993         }
 994
 995         /* enable interrupt */
 996         pci_intx(pdev, 1);
 997
 998         return ata_pci_sff_init_one(pdev, ppinfo, &rdc_pata_sht, NULL);
 999 }
1000
1001 /* a pci driver */
1002 static struct pci_driver rdc_pata_driver = {
1003         .name           = DRIVER_NAME,
1004         .id_table       = rdc_pata_id_table,
1005         .probe          = rdc_init_one,
1006         .remove         = ata_pci_remove_one,
1007 #ifdef CONFIG_PM
1008         .suspend        = ata_pci_device_suspend,
1009         .resume         = ata_pci_device_resume,
1010 #endif
1011 };
1012
1013 static int __init pata_rdc_init(void)
1014 {
1015         return pci_register_driver(&rdc_pata_driver);
1016 }
1017
1018 static void __exit pata_rdc_exit(void)
1019 {
1020         pci_unregister_driver(&rdc_pata_driver);
1021 }
1022
1023 module_init(pata_rdc_init);
1024 module_exit(pata_rdc_exit);
1025
1026 MODULE_LICENSE("GPL");
1027 MODULE_DESCRIPTION("RDC PCI IDE Driver");
1028 MODULE_VERSION(DRIVER_VERSION);