git.oblomov.eu Git - linux-2.6/blob - arch/blackfin/kernel/cplb-nompu/cplbinit.c

   1 /*
   2  * Blackfin CPLB initialization
   3  *
   4  *               Copyright 2004-2007 Analog Devices Inc.
   5  *
   6  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, see the file COPYING, or write
  20  * to the Free Software Foundation, Inc.,
  21  * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  22  */
  23
  24 #include <linux/module.h>
  25
  26 #include <asm/blackfin.h>
  27 #include <asm/cacheflush.h>
  28 #include <asm/cplb.h>
  29 #include <asm/cplbinit.h>
  30 #include <asm/mem_map.h>
  31
  32 u_long icplb_tables[NR_CPUS][CPLB_TBL_ENTRIES+1];
  33 u_long dcplb_tables[NR_CPUS][CPLB_TBL_ENTRIES+1];
  34
  35 #ifdef CONFIG_CPLB_SWITCH_TAB_L1
  36 #define PDT_ATTR __attribute__((l1_data))
  37 #else
  38 #define PDT_ATTR
  39 #endif
  40
  41 u_long ipdt_tables[NR_CPUS][MAX_SWITCH_I_CPLBS+1] PDT_ATTR;
  42 u_long dpdt_tables[NR_CPUS][MAX_SWITCH_D_CPLBS+1] PDT_ATTR;
  43 #ifdef CONFIG_CPLB_INFO
  44 u_long ipdt_swapcount_tables[NR_CPUS][MAX_SWITCH_I_CPLBS] PDT_ATTR;
  45 u_long dpdt_swapcount_tables[NR_CPUS][MAX_SWITCH_D_CPLBS] PDT_ATTR;
  46 #endif
  47
  48 struct s_cplb {
  49         struct cplb_tab init_i;
  50         struct cplb_tab init_d;
  51         struct cplb_tab switch_i;
  52         struct cplb_tab switch_d;
  53 };
  54
  55 #if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
  56 static struct cplb_desc cplb_data[] = {
  57         {
  58                 .start = 0,
  59                 .end = SIZE_1K,
  60                 .psize = SIZE_1K,
  61                 .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
  62                 .i_conf = SDRAM_OOPS,
  63                 .d_conf = SDRAM_OOPS,
  64 #if defined(CONFIG_DEBUG_HUNT_FOR_ZERO)
  65                 .valid = 1,
  66 #else
  67                 .valid = 0,
  68 #endif
  69                 .name = "Zero Pointer Guard Page",
  70         },
  71         {
  72                 .start = 0,     /* dyanmic */
  73                 .end = 0,       /* dynamic */
  74                 .psize = SIZE_4M,
  75                 .attr = INITIAL_T | SWITCH_T | I_CPLB,
  76                 .i_conf = L1_IMEMORY,
  77                 .d_conf = 0,
  78                 .valid = 1,
  79                 .name = "L1 I-Memory",
  80         },
  81         {
  82                 .start = 0,     /* dynamic */
  83                 .end = 0,       /* dynamic */
  84                 .psize = SIZE_4M,
  85                 .attr = INITIAL_T | SWITCH_T | D_CPLB,
  86                 .i_conf = 0,
  87                 .d_conf = L1_DMEMORY,
  88 #if ((L1_DATA_A_LENGTH > 0) || (L1_DATA_B_LENGTH > 0))
  89                 .valid = 1,
  90 #else
  91                 .valid = 0,
  92 #endif
  93                 .name = "L1 D-Memory",
  94         },
  95         {
  96                 .start = L2_START,
  97                 .end = L2_START + L2_LENGTH,
  98                 .psize = SIZE_1M,
  99                 .attr = L2_ATTR,
 100                 .i_conf = L2_IMEMORY,
 101                 .d_conf = L2_DMEMORY,
 102                 .valid = (L2_LENGTH > 0),
 103                 .name = "L2 Memory",
 104         },
 105         {
 106                 .start = 0,
 107                 .end = 0,  /* dynamic */
 108                 .psize = 0,
 109                 .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
 110                 .i_conf = SDRAM_IGENERIC,
 111                 .d_conf = SDRAM_DGENERIC,
 112                 .valid = 1,
 113                 .name = "Kernel Memory",
 114         },
 115         {
 116                 .start = 0, /* dynamic */
 117                 .end = 0, /* dynamic */
 118                 .psize = 0,
 119                 .attr = INITIAL_T | SWITCH_T | D_CPLB,
 120                 .i_conf = SDRAM_IGENERIC,
 121                 .d_conf = SDRAM_DNON_CHBL,
 122                 .valid = 1,
 123                 .name = "uClinux MTD Memory",
 124         },
 125         {
 126                 .start = 0, /* dynamic */
 127                 .end = 0,   /* dynamic */
 128                 .psize = SIZE_1M,
 129                 .attr = INITIAL_T | SWITCH_T | D_CPLB,
 130                 .d_conf = SDRAM_DNON_CHBL,
 131                 .valid = 1,
 132                 .name = "Uncached DMA Zone",
 133         },
 134         {
 135                 .start = 0, /* dynamic */
 136                 .end = 0, /* dynamic */
 137                 .psize = 0,
 138                 .attr = SWITCH_T | D_CPLB,
 139                 .i_conf = 0, /* dynamic */
 140                 .d_conf = 0, /* dynamic */
 141                 .valid = 1,
 142                 .name = "Reserved Memory",
 143         },
 144         {
 145                 .start = ASYNC_BANK0_BASE,
 146                 .end = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE,
 147                 .psize = 0,
 148                 .attr = SWITCH_T | D_CPLB,
 149                 .d_conf = SDRAM_EBIU,
 150                 .valid = 1,
 151                 .name = "Asynchronous Memory Banks",
 152         },
 153         {
 154                 .start = BOOT_ROM_START,
 155                 .end = BOOT_ROM_START + BOOT_ROM_LENGTH,
 156                 .psize = SIZE_1M,
 157                 .attr = SWITCH_T | I_CPLB | D_CPLB,
 158                 .i_conf = SDRAM_IGENERIC,
 159                 .d_conf = SDRAM_DGENERIC,
 160                 .valid = 1,
 161                 .name = "On-Chip BootROM",
 162         },
 163 };
 164
 165 static bool __init lock_kernel_check(u32 start, u32 end)
 166 {
 167         if (start >= (u32)__init_begin || end <= (u32)_stext)
 168                 return false;
 169
 170         /* This cplb block overlapped with kernel area. */
 171         return true;
 172 }
 173
 174 static void __init
 175 fill_cplbtab(struct cplb_tab *table,
 176              unsigned long start, unsigned long end,
 177              unsigned long block_size, unsigned long cplb_data)
 178 {
 179         int i;
 180
 181         switch (block_size) {
 182         case SIZE_4M:
 183                 i = 3;
 184                 break;
 185         case SIZE_1M:
 186                 i = 2;
 187                 break;
 188         case SIZE_4K:
 189                 i = 1;
 190                 break;
 191         case SIZE_1K:
 192         default:
 193                 i = 0;
 194                 break;
 195         }
 196
 197         cplb_data = (cplb_data & ~(3 << 16)) | (i << 16);
 198
 199         while ((start < end) && (table->pos < table->size)) {
 200
 201                 table->tab[table->pos++] = start;
 202
 203                 if (lock_kernel_check(start, start + block_size))
 204                         table->tab[table->pos++] =
 205                             cplb_data | CPLB_LOCK | CPLB_DIRTY;
 206                 else
 207                         table->tab[table->pos++] = cplb_data;
 208
 209                 start += block_size;
 210         }
 211 }
 212
 213 static void __init close_cplbtab(struct cplb_tab *table)
 214 {
 215         while (table->pos < table->size)
 216                 table->tab[table->pos++] = 0;
 217 }
 218
 219 /* helper function */
 220 static void __init
 221 __fill_code_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end)
 222 {
 223         if (cplb_data[i].psize) {
 224                 fill_cplbtab(t,
 225                                 cplb_data[i].start,
 226                                 cplb_data[i].end,
 227                                 cplb_data[i].psize,
 228                                 cplb_data[i].i_conf);
 229         } else {
 230 #if defined(CONFIG_BFIN_ICACHE)
 231                 if (ANOMALY_05000263 && i == SDRAM_KERN) {
 232                         fill_cplbtab(t,
 233                                         cplb_data[i].start,
 234                                         cplb_data[i].end,
 235                                         SIZE_4M,
 236                                         cplb_data[i].i_conf);
 237                 } else
 238 #endif
 239                 {
 240                         fill_cplbtab(t,
 241                                         cplb_data[i].start,
 242                                         a_start,
 243                                         SIZE_1M,
 244                                         cplb_data[i].i_conf);
 245                         fill_cplbtab(t,
 246                                         a_start,
 247                                         a_end,
 248                                         SIZE_4M,
 249                                         cplb_data[i].i_conf);
 250                         fill_cplbtab(t, a_end,
 251                                         cplb_data[i].end,
 252                                         SIZE_1M,
 253                                         cplb_data[i].i_conf);
 254                 }
 255         }
 256 }
 257
 258 static void __init
 259 __fill_data_cplbtab(struct cplb_tab *t, int i, u32 a_start, u32 a_end)
 260 {
 261         if (cplb_data[i].psize) {
 262                 fill_cplbtab(t,
 263                                 cplb_data[i].start,
 264                                 cplb_data[i].end,
 265                                 cplb_data[i].psize,
 266                                 cplb_data[i].d_conf);
 267         } else {
 268                 fill_cplbtab(t,
 269                                 cplb_data[i].start,
 270                                 a_start, SIZE_1M,
 271                                 cplb_data[i].d_conf);
 272                 fill_cplbtab(t, a_start,
 273                                 a_end, SIZE_4M,
 274                                 cplb_data[i].d_conf);
 275                 fill_cplbtab(t, a_end,
 276                                 cplb_data[i].end,
 277                                 SIZE_1M,
 278                                 cplb_data[i].d_conf);
 279         }
 280 }
 281
 282 void __init generate_cplb_tables_cpu(unsigned int cpu)
 283 {
 284
 285         u16 i, j, process;
 286         u32 a_start, a_end, as, ae, as_1m;
 287
 288         struct cplb_tab *t_i = NULL;
 289         struct cplb_tab *t_d = NULL;
 290         struct s_cplb cplb;
 291
 292         printk(KERN_INFO "NOMPU: setting up cplb tables for global access\n");
 293
 294         cplb.init_i.size = CPLB_TBL_ENTRIES;
 295         cplb.init_d.size = CPLB_TBL_ENTRIES;
 296         cplb.switch_i.size = MAX_SWITCH_I_CPLBS;
 297         cplb.switch_d.size = MAX_SWITCH_D_CPLBS;
 298
 299         cplb.init_i.pos = 0;
 300         cplb.init_d.pos = 0;
 301         cplb.switch_i.pos = 0;
 302         cplb.switch_d.pos = 0;
 303
 304         cplb.init_i.tab = icplb_tables[cpu];
 305         cplb.init_d.tab = dcplb_tables[cpu];
 306         cplb.switch_i.tab = ipdt_tables[cpu];
 307         cplb.switch_d.tab = dpdt_tables[cpu];
 308
 309         cplb_data[L1I_MEM].start = get_l1_code_start_cpu(cpu);
 310         cplb_data[L1I_MEM].end = cplb_data[L1I_MEM].start + L1_CODE_LENGTH;
 311         cplb_data[L1D_MEM].start = get_l1_data_a_start_cpu(cpu);
 312         cplb_data[L1D_MEM].end = get_l1_data_b_start_cpu(cpu) + L1_DATA_B_LENGTH;
 313         cplb_data[SDRAM_KERN].end = memory_end;
 314
 315 #ifdef CONFIG_MTD_UCLINUX
 316         cplb_data[SDRAM_RAM_MTD].start = memory_mtd_start;
 317         cplb_data[SDRAM_RAM_MTD].end = memory_mtd_start + mtd_size;
 318         cplb_data[SDRAM_RAM_MTD].valid = mtd_size > 0;
 319 # if defined(CONFIG_ROMFS_FS)
 320         cplb_data[SDRAM_RAM_MTD].attr |= I_CPLB;
 321
 322         /*
 323          * The ROMFS_FS size is often not multiple of 1MB.
 324          * This can cause multiple CPLB sets covering the same memory area.
 325          * This will then cause multiple CPLB hit exceptions.
 326          * Workaround: We ensure a contiguous memory area by extending the kernel
 327          * memory section over the mtd section.
 328          * For ROMFS_FS memory must be covered with ICPLBs anyways.
 329          * So there is no difference between kernel and mtd memory setup.
 330          */
 331
 332         cplb_data[SDRAM_KERN].end = memory_mtd_start + mtd_size;;
 333         cplb_data[SDRAM_RAM_MTD].valid = 0;
 334
 335 # endif
 336 #else
 337         cplb_data[SDRAM_RAM_MTD].valid = 0;
 338 #endif
 339
 340         cplb_data[SDRAM_DMAZ].start = _ramend - DMA_UNCACHED_REGION;
 341         cplb_data[SDRAM_DMAZ].end = _ramend;
 342
 343         cplb_data[RES_MEM].start = _ramend;
 344         cplb_data[RES_MEM].end = physical_mem_end;
 345
 346         if (reserved_mem_dcache_on)
 347                 cplb_data[RES_MEM].d_conf = SDRAM_DGENERIC;
 348         else
 349                 cplb_data[RES_MEM].d_conf = SDRAM_DNON_CHBL;
 350
 351         if (reserved_mem_icache_on)
 352                 cplb_data[RES_MEM].i_conf = SDRAM_IGENERIC;
 353         else
 354                 cplb_data[RES_MEM].i_conf = SDRAM_INON_CHBL;
 355
 356         for (i = ZERO_P; i < ARRAY_SIZE(cplb_data); ++i) {
 357                 if (!cplb_data[i].valid)
 358                         continue;
 359
 360                 as_1m = cplb_data[i].start % SIZE_1M;
 361
 362                 /* We need to make sure all sections are properly 1M aligned
 363                  * However between Kernel Memory and the Kernel mtd section, depending on the
 364                  * rootfs size, there can be overlapping memory areas.
 365                  */
 366
 367                 if (as_1m && i != L1I_MEM && i != L1D_MEM) {
 368 #ifdef CONFIG_MTD_UCLINUX
 369                         if (i == SDRAM_RAM_MTD) {
 370                                 if ((cplb_data[SDRAM_KERN].end + 1) > cplb_data[SDRAM_RAM_MTD].start)
 371                                         cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M)) + SIZE_1M;
 372                                 else
 373                                         cplb_data[SDRAM_RAM_MTD].start = (cplb_data[i].start & (-2*SIZE_1M));
 374                         } else
 375 #endif
 376                                 printk(KERN_WARNING "Unaligned Start of %s at 0x%X\n",
 377                                        cplb_data[i].name, cplb_data[i].start);
 378                 }
 379
 380                 as = cplb_data[i].start % SIZE_4M;
 381                 ae = cplb_data[i].end % SIZE_4M;
 382
 383                 if (as)
 384                         a_start = cplb_data[i].start + (SIZE_4M - (as));
 385                 else
 386                         a_start = cplb_data[i].start;
 387
 388                 a_end = cplb_data[i].end - ae;
 389
 390                 for (j = INITIAL_T; j <= SWITCH_T; j++) {
 391
 392                         switch (j) {
 393                         case INITIAL_T:
 394                                 if (cplb_data[i].attr & INITIAL_T) {
 395                                         t_i = &cplb.init_i;
 396                                         t_d = &cplb.init_d;
 397                                         process = 1;
 398                                 } else
 399                                         process = 0;
 400                                 break;
 401                         case SWITCH_T:
 402                                 if (cplb_data[i].attr & SWITCH_T) {
 403                                         t_i = &cplb.switch_i;
 404                                         t_d = &cplb.switch_d;
 405                                         process = 1;
 406                                 } else
 407                                         process = 0;
 408                                 break;
 409                         default:
 410                                         process = 0;
 411                                 break;
 412                         }
 413
 414                         if (!process)
 415                                 continue;
 416                         if (cplb_data[i].attr & I_CPLB)
 417                                 __fill_code_cplbtab(t_i, i, a_start, a_end);
 418
 419                         if (cplb_data[i].attr & D_CPLB)
 420                                 __fill_data_cplbtab(t_d, i, a_start, a_end);
 421                 }
 422         }
 423
 424         /* make sure we locked the kernel start */
 425         BUG_ON(cplb.init_i.pos < 2 + cplb_data[ZERO_P].valid);
 426         BUG_ON(cplb.init_d.pos < 1 + cplb_data[ZERO_P].valid + cplb_data[L1D_MEM].valid);
 427
 428         /* make sure we didnt overflow the table */
 429         BUG_ON(cplb.init_i.size < cplb.init_i.pos);
 430         BUG_ON(cplb.init_d.size < cplb.init_d.pos);
 431         BUG_ON(cplb.switch_i.size < cplb.switch_i.pos);
 432         BUG_ON(cplb.switch_d.size < cplb.switch_d.pos);
 433
 434         /* close tables */
 435         close_cplbtab(&cplb.init_i);
 436         close_cplbtab(&cplb.init_d);
 437
 438         cplb.init_i.tab[cplb.init_i.pos] = -1;
 439         cplb.init_d.tab[cplb.init_d.pos] = -1;
 440         cplb.switch_i.tab[cplb.switch_i.pos] = -1;
 441         cplb.switch_d.tab[cplb.switch_d.pos] = -1;
 442
 443 }
 444
 445 #endif