git.oblomov.eu Git - linux-2.6/blob - arch/powerpc/kernel/perf_counter.c

   1 /*
   2  * Performance counter support - powerpc architecture code
   3  *
   4  * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11 #include <linux/kernel.h>
  12 #include <linux/sched.h>
  13 #include <linux/perf_counter.h>
  14 #include <linux/percpu.h>
  15 #include <linux/hardirq.h>
  16 #include <asm/reg.h>
  17 #include <asm/pmc.h>
  18 #include <asm/machdep.h>
  19 #include <asm/firmware.h>
  20 #include <asm/ptrace.h>
  21
  22 struct cpu_hw_counters {
  23         int n_counters;
  24         int n_percpu;
  25         int disabled;
  26         int n_added;
  27         int n_limited;
  28         u8  pmcs_enabled;
  29         struct perf_counter *counter[MAX_HWCOUNTERS];
  30         u64 events[MAX_HWCOUNTERS];
  31         unsigned int flags[MAX_HWCOUNTERS];
  32         u64 mmcr[3];
  33         struct perf_counter *limited_counter[MAX_LIMITED_HWCOUNTERS];
  34         u8  limited_hwidx[MAX_LIMITED_HWCOUNTERS];
  35 };
  36 DEFINE_PER_CPU(struct cpu_hw_counters, cpu_hw_counters);
  37
  38 struct power_pmu *ppmu;
  39
  40 /*
  41  * Normally, to ignore kernel events we set the FCS (freeze counters
  42  * in supervisor mode) bit in MMCR0, but if the kernel runs with the
  43  * hypervisor bit set in the MSR, or if we are running on a processor
  44  * where the hypervisor bit is forced to 1 (as on Apple G5 processors),
  45  * then we need to use the FCHV bit to ignore kernel events.
  46  */
  47 static unsigned int freeze_counters_kernel = MMCR0_FCS;
  48
  49 static void perf_counter_interrupt(struct pt_regs *regs);
  50
  51 void perf_counter_print_debug(void)
  52 {
  53 }
  54
  55 /*
  56  * Read one performance monitor counter (PMC).
  57  */
  58 static unsigned long read_pmc(int idx)
  59 {
  60         unsigned long val;
  61
  62         switch (idx) {
  63         case 1:
  64                 val = mfspr(SPRN_PMC1);
  65                 break;
  66         case 2:
  67                 val = mfspr(SPRN_PMC2);
  68                 break;
  69         case 3:
  70                 val = mfspr(SPRN_PMC3);
  71                 break;
  72         case 4:
  73                 val = mfspr(SPRN_PMC4);
  74                 break;
  75         case 5:
  76                 val = mfspr(SPRN_PMC5);
  77                 break;
  78         case 6:
  79                 val = mfspr(SPRN_PMC6);
  80                 break;
  81         case 7:
  82                 val = mfspr(SPRN_PMC7);
  83                 break;
  84         case 8:
  85                 val = mfspr(SPRN_PMC8);
  86                 break;
  87         default:
  88                 printk(KERN_ERR "oops trying to read PMC%d\n", idx);
  89                 val = 0;
  90         }
  91         return val;
  92 }
  93
  94 /*
  95  * Write one PMC.
  96  */
  97 static void write_pmc(int idx, unsigned long val)
  98 {
  99         switch (idx) {
 100         case 1:
 101                 mtspr(SPRN_PMC1, val);
 102                 break;
 103         case 2:
 104                 mtspr(SPRN_PMC2, val);
 105                 break;
 106         case 3:
 107                 mtspr(SPRN_PMC3, val);
 108                 break;
 109         case 4:
 110                 mtspr(SPRN_PMC4, val);
 111                 break;
 112         case 5:
 113                 mtspr(SPRN_PMC5, val);
 114                 break;
 115         case 6:
 116                 mtspr(SPRN_PMC6, val);
 117                 break;
 118         case 7:
 119                 mtspr(SPRN_PMC7, val);
 120                 break;
 121         case 8:
 122                 mtspr(SPRN_PMC8, val);
 123                 break;
 124         default:
 125                 printk(KERN_ERR "oops trying to write PMC%d\n", idx);
 126         }
 127 }
 128
 129 /*
 130  * Check if a set of events can all go on the PMU at once.
 131  * If they can't, this will look at alternative codes for the events
 132  * and see if any combination of alternative codes is feasible.
 133  * The feasible set is returned in event[].
 134  */
 135 static int power_check_constraints(u64 event[], unsigned int cflags[],
 136                                    int n_ev)
 137 {
 138         u64 mask, value, nv;
 139         u64 alternatives[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES];
 140         u64 amasks[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES];
 141         u64 avalues[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES];
 142         u64 smasks[MAX_HWCOUNTERS], svalues[MAX_HWCOUNTERS];
 143         int n_alt[MAX_HWCOUNTERS], choice[MAX_HWCOUNTERS];
 144         int i, j;
 145         u64 addf = ppmu->add_fields;
 146         u64 tadd = ppmu->test_adder;
 147
 148         if (n_ev > ppmu->n_counter)
 149                 return -1;
 150
 151         /* First see if the events will go on as-is */
 152         for (i = 0; i < n_ev; ++i) {
 153                 if ((cflags[i] & PPMU_LIMITED_PMC_REQD)
 154                     && !ppmu->limited_pmc_event(event[i])) {
 155                         ppmu->get_alternatives(event[i], cflags[i],
 156                                                alternatives[i]);
 157                         event[i] = alternatives[i][0];
 158                 }
 159                 if (ppmu->get_constraint(event[i], &amasks[i][0],
 160                                          &avalues[i][0]))
 161                         return -1;
 162         }
 163         value = mask = 0;
 164         for (i = 0; i < n_ev; ++i) {
 165                 nv = (value | avalues[i][0]) + (value & avalues[i][0] & addf);
 166                 if ((((nv + tadd) ^ value) & mask) != 0 ||
 167                     (((nv + tadd) ^ avalues[i][0]) & amasks[i][0]) != 0)
 168                         break;
 169                 value = nv;
 170                 mask |= amasks[i][0];
 171         }
 172         if (i == n_ev)
 173                 return 0;       /* all OK */
 174
 175         /* doesn't work, gather alternatives... */
 176         if (!ppmu->get_alternatives)
 177                 return -1;
 178         for (i = 0; i < n_ev; ++i) {
 179                 choice[i] = 0;
 180                 n_alt[i] = ppmu->get_alternatives(event[i], cflags[i],
 181                                                   alternatives[i]);
 182                 for (j = 1; j < n_alt[i]; ++j)
 183                         ppmu->get_constraint(alternatives[i][j],
 184                                              &amasks[i][j], &avalues[i][j]);
 185         }
 186
 187         /* enumerate all possibilities and see if any will work */
 188         i = 0;
 189         j = -1;
 190         value = mask = nv = 0;
 191         while (i < n_ev) {
 192                 if (j >= 0) {
 193                         /* we're backtracking, restore context */
 194                         value = svalues[i];
 195                         mask = smasks[i];
 196                         j = choice[i];
 197                 }
 198                 /*
 199                  * See if any alternative k for event i,
 200                  * where k > j, will satisfy the constraints.
 201                  */
 202                 while (++j < n_alt[i]) {
 203                         nv = (value | avalues[i][j]) +
 204                                 (value & avalues[i][j] & addf);
 205                         if ((((nv + tadd) ^ value) & mask) == 0 &&
 206                             (((nv + tadd) ^ avalues[i][j])
 207                              & amasks[i][j]) == 0)
 208                                 break;
 209                 }
 210                 if (j >= n_alt[i]) {
 211                         /*
 212                          * No feasible alternative, backtrack
 213                          * to event i-1 and continue enumerating its
 214                          * alternatives from where we got up to.
 215                          */
 216                         if (--i < 0)
 217                                 return -1;
 218                 } else {
 219                         /*
 220                          * Found a feasible alternative for event i,
 221                          * remember where we got up to with this event,
 222                          * go on to the next event, and start with
 223                          * the first alternative for it.
 224                          */
 225                         choice[i] = j;
 226                         svalues[i] = value;
 227                         smasks[i] = mask;
 228                         value = nv;
 229                         mask |= amasks[i][j];
 230                         ++i;
 231                         j = -1;
 232                 }
 233         }
 234
 235         /* OK, we have a feasible combination, tell the caller the solution */
 236         for (i = 0; i < n_ev; ++i)
 237                 event[i] = alternatives[i][choice[i]];
 238         return 0;
 239 }
 240
 241 /*
 242  * Check if newly-added counters have consistent settings for
 243  * exclude_{user,kernel,hv} with each other and any previously
 244  * added counters.
 245  */
 246 static int check_excludes(struct perf_counter **ctrs, unsigned int cflags[],
 247                           int n_prev, int n_new)
 248 {
 249         int eu = 0, ek = 0, eh = 0;
 250         int i, n, first;
 251         struct perf_counter *counter;
 252
 253         n = n_prev + n_new;
 254         if (n <= 1)
 255                 return 0;
 256
 257         first = 1;
 258         for (i = 0; i < n; ++i) {
 259                 if (cflags[i] & PPMU_LIMITED_PMC_OK) {
 260                         cflags[i] &= ~PPMU_LIMITED_PMC_REQD;
 261                         continue;
 262                 }
 263                 counter = ctrs[i];
 264                 if (first) {
 265                         eu = counter->hw_event.exclude_user;
 266                         ek = counter->hw_event.exclude_kernel;
 267                         eh = counter->hw_event.exclude_hv;
 268                         first = 0;
 269                 } else if (counter->hw_event.exclude_user != eu ||
 270                            counter->hw_event.exclude_kernel != ek ||
 271                            counter->hw_event.exclude_hv != eh) {
 272                         return -EAGAIN;
 273                 }
 274         }
 275
 276         if (eu || ek || eh)
 277                 for (i = 0; i < n; ++i)
 278                         if (cflags[i] & PPMU_LIMITED_PMC_OK)
 279                                 cflags[i] |= PPMU_LIMITED_PMC_REQD;
 280
 281         return 0;
 282 }
 283
 284 static void power_pmu_read(struct perf_counter *counter)
 285 {
 286         long val, delta, prev;
 287
 288         if (!counter->hw.idx)
 289                 return;
 290         /*
 291          * Performance monitor interrupts come even when interrupts
 292          * are soft-disabled, as long as interrupts are hard-enabled.
 293          * Therefore we treat them like NMIs.
 294          */
 295         do {
 296                 prev = atomic64_read(&counter->hw.prev_count);
 297                 barrier();
 298                 val = read_pmc(counter->hw.idx);
 299         } while (atomic64_cmpxchg(&counter->hw.prev_count, prev, val) != prev);
 300
 301         /* The counters are only 32 bits wide */
 302         delta = (val - prev) & 0xfffffffful;
 303         atomic64_add(delta, &counter->count);
 304         atomic64_sub(delta, &counter->hw.period_left);
 305 }
 306
 307 /*
 308  * On some machines, PMC5 and PMC6 can't be written, don't respect
 309  * the freeze conditions, and don't generate interrupts.  This tells
 310  * us if `counter' is using such a PMC.
 311  */
 312 static int is_limited_pmc(int pmcnum)
 313 {
 314         return (ppmu->flags & PPMU_LIMITED_PMC5_6)
 315                 && (pmcnum == 5 || pmcnum == 6);
 316 }
 317
 318 static void freeze_limited_counters(struct cpu_hw_counters *cpuhw,
 319                                     unsigned long pmc5, unsigned long pmc6)
 320 {
 321         struct perf_counter *counter;
 322         u64 val, prev, delta;
 323         int i;
 324
 325         for (i = 0; i < cpuhw->n_limited; ++i) {
 326                 counter = cpuhw->limited_counter[i];
 327                 if (!counter->hw.idx)
 328                         continue;
 329                 val = (counter->hw.idx == 5) ? pmc5 : pmc6;
 330                 prev = atomic64_read(&counter->hw.prev_count);
 331                 counter->hw.idx = 0;
 332                 delta = (val - prev) & 0xfffffffful;
 333                 atomic64_add(delta, &counter->count);
 334         }
 335 }
 336
 337 static void thaw_limited_counters(struct cpu_hw_counters *cpuhw,
 338                                   unsigned long pmc5, unsigned long pmc6)
 339 {
 340         struct perf_counter *counter;
 341         u64 val;
 342         int i;
 343
 344         for (i = 0; i < cpuhw->n_limited; ++i) {
 345                 counter = cpuhw->limited_counter[i];
 346                 counter->hw.idx = cpuhw->limited_hwidx[i];
 347                 val = (counter->hw.idx == 5) ? pmc5 : pmc6;
 348                 atomic64_set(&counter->hw.prev_count, val);
 349                 perf_counter_update_userpage(counter);
 350         }
 351 }
 352
 353 /*
 354  * Since limited counters don't respect the freeze conditions, we
 355  * have to read them immediately after freezing or unfreezing the
 356  * other counters.  We try to keep the values from the limited
 357  * counters as consistent as possible by keeping the delay (in
 358  * cycles and instructions) between freezing/unfreezing and reading
 359  * the limited counters as small and consistent as possible.
 360  * Therefore, if any limited counters are in use, we read them
 361  * both, and always in the same order, to minimize variability,
 362  * and do it inside the same asm that writes MMCR0.
 363  */
 364 static void write_mmcr0(struct cpu_hw_counters *cpuhw, unsigned long mmcr0)
 365 {
 366         unsigned long pmc5, pmc6;
 367
 368         if (!cpuhw->n_limited) {
 369                 mtspr(SPRN_MMCR0, mmcr0);
 370                 return;
 371         }
 372
 373         /*
 374          * Write MMCR0, then read PMC5 and PMC6 immediately.
 375          */
 376         asm volatile("mtspr %3,%2; mfspr %0,%4; mfspr %1,%5"
 377                      : "=&r" (pmc5), "=&r" (pmc6)
 378                      : "r" (mmcr0), "i" (SPRN_MMCR0),
 379                        "i" (SPRN_PMC5), "i" (SPRN_PMC6));
 380
 381         if (mmcr0 & MMCR0_FC)
 382                 freeze_limited_counters(cpuhw, pmc5, pmc6);
 383         else
 384                 thaw_limited_counters(cpuhw, pmc5, pmc6);
 385 }
 386
 387 /*
 388  * Disable all counters to prevent PMU interrupts and to allow
 389  * counters to be added or removed.
 390  */
 391 void hw_perf_disable(void)
 392 {
 393         struct cpu_hw_counters *cpuhw;
 394         unsigned long ret;
 395         unsigned long flags;
 396
 397         local_irq_save(flags);
 398         cpuhw = &__get_cpu_var(cpu_hw_counters);
 399
 400         ret = cpuhw->disabled;
 401         if (!ret) {
 402                 cpuhw->disabled = 1;
 403                 cpuhw->n_added = 0;
 404
 405                 /*
 406                  * Check if we ever enabled the PMU on this cpu.
 407                  */
 408                 if (!cpuhw->pmcs_enabled) {
 409                         if (ppc_md.enable_pmcs)
 410                                 ppc_md.enable_pmcs();
 411                         cpuhw->pmcs_enabled = 1;
 412                 }
 413
 414                 /*
 415                  * Disable instruction sampling if it was enabled
 416                  */
 417                 if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) {
 418                         mtspr(SPRN_MMCRA,
 419                               cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
 420                         mb();
 421                 }
 422
 423                 /*
 424                  * Set the 'freeze counters' bit.
 425                  * The barrier is to make sure the mtspr has been
 426                  * executed and the PMU has frozen the counters
 427                  * before we return.
 428                  */
 429                 write_mmcr0(cpuhw, mfspr(SPRN_MMCR0) | MMCR0_FC);
 430                 mb();
 431         }
 432         local_irq_restore(flags);
 433 }
 434
 435 /*
 436  * Re-enable all counters if disable == 0.
 437  * If we were previously disabled and counters were added, then
 438  * put the new config on the PMU.
 439  */
 440 void hw_perf_enable(void)
 441 {
 442         struct perf_counter *counter;
 443         struct cpu_hw_counters *cpuhw;
 444         unsigned long flags;
 445         long i;
 446         unsigned long val;
 447         s64 left;
 448         unsigned int hwc_index[MAX_HWCOUNTERS];
 449         int n_lim;
 450         int idx;
 451
 452         local_irq_save(flags);
 453         if (!cpuhw->disabled) {
 454                 local_irq_restore(flags);
 455                 return;
 456         }
 457
 458         cpuhw = &__get_cpu_var(cpu_hw_counters);
 459         cpuhw->disabled = 0;
 460
 461         /*
 462          * If we didn't change anything, or only removed counters,
 463          * no need to recalculate MMCR* settings and reset the PMCs.
 464          * Just reenable the PMU with the current MMCR* settings
 465          * (possibly updated for removal of counters).
 466          */
 467         if (!cpuhw->n_added) {
 468                 mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
 469                 mtspr(SPRN_MMCR1, cpuhw->mmcr[1]);
 470                 if (cpuhw->n_counters == 0)
 471                         get_lppaca()->pmcregs_in_use = 0;
 472                 goto out_enable;
 473         }
 474
 475         /*
 476          * Compute MMCR* values for the new set of counters
 477          */
 478         if (ppmu->compute_mmcr(cpuhw->events, cpuhw->n_counters, hwc_index,
 479                                cpuhw->mmcr)) {
 480                 /* shouldn't ever get here */
 481                 printk(KERN_ERR "oops compute_mmcr failed\n");
 482                 goto out;
 483         }
 484
 485         /*
 486          * Add in MMCR0 freeze bits corresponding to the
 487          * hw_event.exclude_* bits for the first counter.
 488          * We have already checked that all counters have the
 489          * same values for these bits as the first counter.
 490          */
 491         counter = cpuhw->counter[0];
 492         if (counter->hw_event.exclude_user)
 493                 cpuhw->mmcr[0] |= MMCR0_FCP;
 494         if (counter->hw_event.exclude_kernel)
 495                 cpuhw->mmcr[0] |= freeze_counters_kernel;
 496         if (counter->hw_event.exclude_hv)
 497                 cpuhw->mmcr[0] |= MMCR0_FCHV;
 498
 499         /*
 500          * Write the new configuration to MMCR* with the freeze
 501          * bit set and set the hardware counters to their initial values.
 502          * Then unfreeze the counters.
 503          */
 504         get_lppaca()->pmcregs_in_use = 1;
 505         mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
 506         mtspr(SPRN_MMCR1, cpuhw->mmcr[1]);
 507         mtspr(SPRN_MMCR0, (cpuhw->mmcr[0] & ~(MMCR0_PMC1CE | MMCR0_PMCjCE))
 508                                 | MMCR0_FC);
 509
 510         /*
 511          * Read off any pre-existing counters that need to move
 512          * to another PMC.
 513          */
 514         for (i = 0; i < cpuhw->n_counters; ++i) {
 515                 counter = cpuhw->counter[i];
 516                 if (counter->hw.idx && counter->hw.idx != hwc_index[i] + 1) {
 517                         power_pmu_read(counter);
 518                         write_pmc(counter->hw.idx, 0);
 519                         counter->hw.idx = 0;
 520                 }
 521         }
 522
 523         /*
 524          * Initialize the PMCs for all the new and moved counters.
 525          */
 526         cpuhw->n_limited = n_lim = 0;
 527         for (i = 0; i < cpuhw->n_counters; ++i) {
 528                 counter = cpuhw->counter[i];
 529                 if (counter->hw.idx)
 530                         continue;
 531                 idx = hwc_index[i] + 1;
 532                 if (is_limited_pmc(idx)) {
 533                         cpuhw->limited_counter[n_lim] = counter;
 534                         cpuhw->limited_hwidx[n_lim] = idx;
 535                         ++n_lim;
 536                         continue;
 537                 }
 538                 val = 0;
 539                 if (counter->hw.irq_period) {
 540                         left = atomic64_read(&counter->hw.period_left);
 541                         if (left < 0x80000000L)
 542                                 val = 0x80000000L - left;
 543                 }
 544                 atomic64_set(&counter->hw.prev_count, val);
 545                 counter->hw.idx = idx;
 546                 write_pmc(idx, val);
 547                 perf_counter_update_userpage(counter);
 548         }
 549         cpuhw->n_limited = n_lim;
 550         cpuhw->mmcr[0] |= MMCR0_PMXE | MMCR0_FCECE;
 551
 552  out_enable:
 553         mb();
 554         write_mmcr0(cpuhw, cpuhw->mmcr[0]);
 555
 556         /*
 557          * Enable instruction sampling if necessary
 558          */
 559         if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) {
 560                 mb();
 561                 mtspr(SPRN_MMCRA, cpuhw->mmcr[2]);
 562         }
 563
 564  out:
 565         local_irq_restore(flags);
 566 }
 567
 568 static int collect_events(struct perf_counter *group, int max_count,
 569                           struct perf_counter *ctrs[], u64 *events,
 570                           unsigned int *flags)
 571 {
 572         int n = 0;
 573         struct perf_counter *counter;
 574
 575         if (!is_software_counter(group)) {
 576                 if (n >= max_count)
 577                         return -1;
 578                 ctrs[n] = group;
 579                 flags[n] = group->hw.counter_base;
 580                 events[n++] = group->hw.config;
 581         }
 582         list_for_each_entry(counter, &group->sibling_list, list_entry) {
 583                 if (!is_software_counter(counter) &&
 584                     counter->state != PERF_COUNTER_STATE_OFF) {
 585                         if (n >= max_count)
 586                                 return -1;
 587                         ctrs[n] = counter;
 588                         flags[n] = counter->hw.counter_base;
 589                         events[n++] = counter->hw.config;
 590                 }
 591         }
 592         return n;
 593 }
 594
 595 static void counter_sched_in(struct perf_counter *counter, int cpu)
 596 {
 597         counter->state = PERF_COUNTER_STATE_ACTIVE;
 598         counter->oncpu = cpu;
 599         counter->tstamp_running += counter->ctx->time - counter->tstamp_stopped;
 600         if (is_software_counter(counter))
 601                 counter->pmu->enable(counter);
 602 }
 603
 604 /*
 605  * Called to enable a whole group of counters.
 606  * Returns 1 if the group was enabled, or -EAGAIN if it could not be.
 607  * Assumes the caller has disabled interrupts and has
 608  * frozen the PMU with hw_perf_save_disable.
 609  */
 610 int hw_perf_group_sched_in(struct perf_counter *group_leader,
 611                struct perf_cpu_context *cpuctx,
 612                struct perf_counter_context *ctx, int cpu)
 613 {
 614         struct cpu_hw_counters *cpuhw;
 615         long i, n, n0;
 616         struct perf_counter *sub;
 617
 618         cpuhw = &__get_cpu_var(cpu_hw_counters);
 619         n0 = cpuhw->n_counters;
 620         n = collect_events(group_leader, ppmu->n_counter - n0,
 621                            &cpuhw->counter[n0], &cpuhw->events[n0],
 622                            &cpuhw->flags[n0]);
 623         if (n < 0)
 624                 return -EAGAIN;
 625         if (check_excludes(cpuhw->counter, cpuhw->flags, n0, n))
 626                 return -EAGAIN;
 627         i = power_check_constraints(cpuhw->events, cpuhw->flags, n + n0);
 628         if (i < 0)
 629                 return -EAGAIN;
 630         cpuhw->n_counters = n0 + n;
 631         cpuhw->n_added += n;
 632
 633         /*
 634          * OK, this group can go on; update counter states etc.,
 635          * and enable any software counters
 636          */
 637         for (i = n0; i < n0 + n; ++i)
 638                 cpuhw->counter[i]->hw.config = cpuhw->events[i];
 639         cpuctx->active_oncpu += n;
 640         n = 1;
 641         counter_sched_in(group_leader, cpu);
 642         list_for_each_entry(sub, &group_leader->sibling_list, list_entry) {
 643                 if (sub->state != PERF_COUNTER_STATE_OFF) {
 644                         counter_sched_in(sub, cpu);
 645                         ++n;
 646                 }
 647         }
 648         ctx->nr_active += n;
 649
 650         return 1;
 651 }
 652
 653 /*
 654  * Add a counter to the PMU.
 655  * If all counters are not already frozen, then we disable and
 656  * re-enable the PMU in order to get hw_perf_enable to do the
 657  * actual work of reconfiguring the PMU.
 658  */
 659 static int power_pmu_enable(struct perf_counter *counter)
 660 {
 661         struct cpu_hw_counters *cpuhw;
 662         unsigned long flags;
 663         int n0;
 664         int ret = -EAGAIN;
 665
 666         local_irq_save(flags);
 667         perf_disable();
 668
 669         /*
 670          * Add the counter to the list (if there is room)
 671          * and check whether the total set is still feasible.
 672          */
 673         cpuhw = &__get_cpu_var(cpu_hw_counters);
 674         n0 = cpuhw->n_counters;
 675         if (n0 >= ppmu->n_counter)
 676                 goto out;
 677         cpuhw->counter[n0] = counter;
 678         cpuhw->events[n0] = counter->hw.config;
 679         cpuhw->flags[n0] = counter->hw.counter_base;
 680         if (check_excludes(cpuhw->counter, cpuhw->flags, n0, 1))
 681                 goto out;
 682         if (power_check_constraints(cpuhw->events, cpuhw->flags, n0 + 1))
 683                 goto out;
 684
 685         counter->hw.config = cpuhw->events[n0];
 686         ++cpuhw->n_counters;
 687         ++cpuhw->n_added;
 688
 689         ret = 0;
 690  out:
 691         perf_enable();
 692         local_irq_restore(flags);
 693         return ret;
 694 }
 695
 696 /*
 697  * Remove a counter from the PMU.
 698  */
 699 static void power_pmu_disable(struct perf_counter *counter)
 700 {
 701         struct cpu_hw_counters *cpuhw;
 702         long i;
 703         unsigned long flags;
 704
 705         local_irq_save(flags);
 706         perf_disable();
 707
 708         power_pmu_read(counter);
 709
 710         cpuhw = &__get_cpu_var(cpu_hw_counters);
 711         for (i = 0; i < cpuhw->n_counters; ++i) {
 712                 if (counter == cpuhw->counter[i]) {
 713                         while (++i < cpuhw->n_counters)
 714                                 cpuhw->counter[i-1] = cpuhw->counter[i];
 715                         --cpuhw->n_counters;
 716                         ppmu->disable_pmc(counter->hw.idx - 1, cpuhw->mmcr);
 717                         if (counter->hw.idx) {
 718                                 write_pmc(counter->hw.idx, 0);
 719                                 counter->hw.idx = 0;
 720                         }
 721                         perf_counter_update_userpage(counter);
 722                         break;
 723                 }
 724         }
 725         for (i = 0; i < cpuhw->n_limited; ++i)
 726                 if (counter == cpuhw->limited_counter[i])
 727                         break;
 728         if (i < cpuhw->n_limited) {
 729                 while (++i < cpuhw->n_limited) {
 730                         cpuhw->limited_counter[i-1] = cpuhw->limited_counter[i];
 731                         cpuhw->limited_hwidx[i-1] = cpuhw->limited_hwidx[i];
 732                 }
 733                 --cpuhw->n_limited;
 734         }
 735         if (cpuhw->n_counters == 0) {
 736                 /* disable exceptions if no counters are running */
 737                 cpuhw->mmcr[0] &= ~(MMCR0_PMXE | MMCR0_FCECE);
 738         }
 739
 740         perf_enable();
 741         local_irq_restore(flags);
 742 }
 743
 744 struct pmu power_pmu = {
 745         .enable         = power_pmu_enable,
 746         .disable        = power_pmu_disable,
 747         .read           = power_pmu_read,
 748 };
 749
 750 /*
 751  * Return 1 if we might be able to put counter on a limited PMC,
 752  * or 0 if not.
 753  * A counter can only go on a limited PMC if it counts something
 754  * that a limited PMC can count, doesn't require interrupts, and
 755  * doesn't exclude any processor mode.
 756  */
 757 static int can_go_on_limited_pmc(struct perf_counter *counter, u64 ev,
 758                                  unsigned int flags)
 759 {
 760         int n;
 761         u64 alt[MAX_EVENT_ALTERNATIVES];
 762
 763         if (counter->hw_event.exclude_user
 764             || counter->hw_event.exclude_kernel
 765             || counter->hw_event.exclude_hv
 766             || counter->hw_event.irq_period)
 767                 return 0;
 768
 769         if (ppmu->limited_pmc_event(ev))
 770                 return 1;
 771
 772         /*
 773          * The requested event isn't on a limited PMC already;
 774          * see if any alternative code goes on a limited PMC.
 775          */
 776         if (!ppmu->get_alternatives)
 777                 return 0;
 778
 779         flags |= PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD;
 780         n = ppmu->get_alternatives(ev, flags, alt);
 781
 782         return n > 0;
 783 }
 784
 785 /*
 786  * Find an alternative event that goes on a normal PMC, if possible,
 787  * and return the event code, or 0 if there is no such alternative.
 788  * (Note: event code 0 is "don't count" on all machines.)
 789  */
 790 static u64 normal_pmc_alternative(u64 ev, unsigned long flags)
 791 {
 792         u64 alt[MAX_EVENT_ALTERNATIVES];
 793         int n;
 794
 795         flags &= ~(PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD);
 796         n = ppmu->get_alternatives(ev, flags, alt);
 797         if (!n)
 798                 return 0;
 799         return alt[0];
 800 }
 801
 802 /* Number of perf_counters counting hardware events */
 803 static atomic_t num_counters;
 804 /* Used to avoid races in calling reserve/release_pmc_hardware */
 805 static DEFINE_MUTEX(pmc_reserve_mutex);
 806
 807 /*
 808  * Release the PMU if this is the last perf_counter.
 809  */
 810 static void hw_perf_counter_destroy(struct perf_counter *counter)
 811 {
 812         if (!atomic_add_unless(&num_counters, -1, 1)) {
 813                 mutex_lock(&pmc_reserve_mutex);
 814                 if (atomic_dec_return(&num_counters) == 0)
 815                         release_pmc_hardware();
 816                 mutex_unlock(&pmc_reserve_mutex);
 817         }
 818 }
 819
 820 const struct pmu *hw_perf_counter_init(struct perf_counter *counter)
 821 {
 822         u64 ev;
 823         unsigned long flags;
 824         struct perf_counter *ctrs[MAX_HWCOUNTERS];
 825         u64 events[MAX_HWCOUNTERS];
 826         unsigned int cflags[MAX_HWCOUNTERS];
 827         int n;
 828         int err;
 829
 830         if (!ppmu)
 831                 return ERR_PTR(-ENXIO);
 832         if (!perf_event_raw(&counter->hw_event)) {
 833                 ev = perf_event_id(&counter->hw_event);
 834                 if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0)
 835                         return ERR_PTR(-EOPNOTSUPP);
 836                 ev = ppmu->generic_events[ev];
 837         } else {
 838                 ev = perf_event_config(&counter->hw_event);
 839         }
 840         counter->hw.config_base = ev;
 841         counter->hw.idx = 0;
 842
 843         /*
 844          * If we are not running on a hypervisor, force the
 845          * exclude_hv bit to 0 so that we don't care what
 846          * the user set it to.
 847          */
 848         if (!firmware_has_feature(FW_FEATURE_LPAR))
 849                 counter->hw_event.exclude_hv = 0;
 850
 851         /*
 852          * If this is a per-task counter, then we can use
 853          * PM_RUN_* events interchangeably with their non RUN_*
 854          * equivalents, e.g. PM_RUN_CYC instead of PM_CYC.
 855          * XXX we should check if the task is an idle task.
 856          */
 857         flags = 0;
 858         if (counter->ctx->task)
 859                 flags |= PPMU_ONLY_COUNT_RUN;
 860
 861         /*
 862          * If this machine has limited counters, check whether this
 863          * event could go on a limited counter.
 864          */
 865         if (ppmu->flags & PPMU_LIMITED_PMC5_6) {
 866                 if (can_go_on_limited_pmc(counter, ev, flags)) {
 867                         flags |= PPMU_LIMITED_PMC_OK;
 868                 } else if (ppmu->limited_pmc_event(ev)) {
 869                         /*
 870                          * The requested event is on a limited PMC,
 871                          * but we can't use a limited PMC; see if any
 872                          * alternative goes on a normal PMC.
 873                          */
 874                         ev = normal_pmc_alternative(ev, flags);
 875                         if (!ev)
 876                                 return ERR_PTR(-EINVAL);
 877                 }
 878         }
 879
 880         /*
 881          * If this is in a group, check if it can go on with all the
 882          * other hardware counters in the group.  We assume the counter
 883          * hasn't been linked into its leader's sibling list at this point.
 884          */
 885         n = 0;
 886         if (counter->group_leader != counter) {
 887                 n = collect_events(counter->group_leader, ppmu->n_counter - 1,
 888                                    ctrs, events, cflags);
 889                 if (n < 0)
 890                         return ERR_PTR(-EINVAL);
 891         }
 892         events[n] = ev;
 893         ctrs[n] = counter;
 894         cflags[n] = flags;
 895         if (check_excludes(ctrs, cflags, n, 1))
 896                 return ERR_PTR(-EINVAL);
 897         if (power_check_constraints(events, cflags, n + 1))
 898                 return ERR_PTR(-EINVAL);
 899
 900         counter->hw.config = events[n];
 901         counter->hw.counter_base = cflags[n];
 902         atomic64_set(&counter->hw.period_left, counter->hw.irq_period);
 903
 904         /*
 905          * See if we need to reserve the PMU.
 906          * If no counters are currently in use, then we have to take a
 907          * mutex to ensure that we don't race with another task doing
 908          * reserve_pmc_hardware or release_pmc_hardware.
 909          */
 910         err = 0;
 911         if (!atomic_inc_not_zero(&num_counters)) {
 912                 mutex_lock(&pmc_reserve_mutex);
 913                 if (atomic_read(&num_counters) == 0 &&
 914                     reserve_pmc_hardware(perf_counter_interrupt))
 915                         err = -EBUSY;
 916                 else
 917                         atomic_inc(&num_counters);
 918                 mutex_unlock(&pmc_reserve_mutex);
 919         }
 920         counter->destroy = hw_perf_counter_destroy;
 921
 922         if (err)
 923                 return ERR_PTR(err);
 924         return &power_pmu;
 925 }
 926
 927 /*
 928  * A counter has overflowed; update its count and record
 929  * things if requested.  Note that interrupts are hard-disabled
 930  * here so there is no possibility of being interrupted.
 931  */
 932 static void record_and_restart(struct perf_counter *counter, long val,
 933                                struct pt_regs *regs, int nmi)
 934 {
 935         u64 period = counter->hw.irq_period;
 936         s64 prev, delta, left;
 937         int record = 0;
 938         u64 addr, mmcra, sdsync;
 939
 940         /* we don't have to worry about interrupts here */
 941         prev = atomic64_read(&counter->hw.prev_count);
 942         delta = (val - prev) & 0xfffffffful;
 943         atomic64_add(delta, &counter->count);
 944
 945         /*
 946          * See if the total period for this counter has expired,
 947          * and update for the next period.
 948          */
 949         val = 0;
 950         left = atomic64_read(&counter->hw.period_left) - delta;
 951         if (period) {
 952                 if (left <= 0) {
 953                         left += period;
 954                         if (left <= 0)
 955                                 left = period;
 956                         record = 1;
 957                 }
 958                 if (left < 0x80000000L)
 959                         val = 0x80000000L - left;
 960         }
 961         write_pmc(counter->hw.idx, val);
 962         atomic64_set(&counter->hw.prev_count, val);
 963         atomic64_set(&counter->hw.period_left, left);
 964         perf_counter_update_userpage(counter);
 965
 966         /*
 967          * Finally record data if requested.
 968          */
 969         if (record) {
 970                 addr = 0;
 971                 if (counter->hw_event.record_type & PERF_RECORD_ADDR) {
 972                         /*
 973                          * The user wants a data address recorded.
 974                          * If we're not doing instruction sampling,
 975                          * give them the SDAR (sampled data address).
 976                          * If we are doing instruction sampling, then only
 977                          * give them the SDAR if it corresponds to the
 978                          * instruction pointed to by SIAR; this is indicated
 979                          * by the [POWER6_]MMCRA_SDSYNC bit in MMCRA.
 980                          */
 981                         mmcra = regs->dsisr;
 982                         sdsync = (ppmu->flags & PPMU_ALT_SIPR) ?
 983                                 POWER6_MMCRA_SDSYNC : MMCRA_SDSYNC;
 984                         if (!(mmcra & MMCRA_SAMPLE_ENABLE) || (mmcra & sdsync))
 985                                 addr = mfspr(SPRN_SDAR);
 986                 }
 987                 perf_counter_overflow(counter, nmi, regs, addr);
 988         }
 989 }
 990
 991 /*
 992  * Called from generic code to get the misc flags (i.e. processor mode)
 993  * for an event.
 994  */
 995 unsigned long perf_misc_flags(struct pt_regs *regs)
 996 {
 997         unsigned long mmcra;
 998
 999         if (TRAP(regs) != 0xf00) {
1000                 /* not a PMU interrupt */
1001                 return user_mode(regs) ? PERF_EVENT_MISC_USER :
1002                         PERF_EVENT_MISC_KERNEL;
1003         }
1004
1005         mmcra = regs->dsisr;
1006         if (ppmu->flags & PPMU_ALT_SIPR) {
1007                 if (mmcra & POWER6_MMCRA_SIHV)
1008                         return PERF_EVENT_MISC_HYPERVISOR;
1009                 return (mmcra & POWER6_MMCRA_SIPR) ? PERF_EVENT_MISC_USER :
1010                         PERF_EVENT_MISC_KERNEL;
1011         }
1012         if (mmcra & MMCRA_SIHV)
1013                 return PERF_EVENT_MISC_HYPERVISOR;
1014         return (mmcra & MMCRA_SIPR) ? PERF_EVENT_MISC_USER :
1015                         PERF_EVENT_MISC_KERNEL;
1016 }
1017
1018 /*
1019  * Called from generic code to get the instruction pointer
1020  * for an event.
1021  */
1022 unsigned long perf_instruction_pointer(struct pt_regs *regs)
1023 {
1024         unsigned long mmcra;
1025         unsigned long ip;
1026         unsigned long slot;
1027
1028         if (TRAP(regs) != 0xf00)
1029                 return regs->nip;       /* not a PMU interrupt */
1030
1031         ip = mfspr(SPRN_SIAR);
1032         mmcra = regs->dsisr;
1033         if ((mmcra & MMCRA_SAMPLE_ENABLE) && !(ppmu->flags & PPMU_ALT_SIPR)) {
1034                 slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT;
1035                 if (slot > 1)
1036                         ip += 4 * (slot - 1);
1037         }
1038         return ip;
1039 }
1040
1041 /*
1042  * Performance monitor interrupt stuff
1043  */
1044 static void perf_counter_interrupt(struct pt_regs *regs)
1045 {
1046         int i;
1047         struct cpu_hw_counters *cpuhw = &__get_cpu_var(cpu_hw_counters);
1048         struct perf_counter *counter;
1049         long val;
1050         int found = 0;
1051         int nmi;
1052
1053         if (cpuhw->n_limited)
1054                 freeze_limited_counters(cpuhw, mfspr(SPRN_PMC5),
1055                                         mfspr(SPRN_PMC6));
1056
1057         /*
1058          * Overload regs->dsisr to store MMCRA so we only need to read it once.
1059          */
1060         regs->dsisr = mfspr(SPRN_MMCRA);
1061
1062         /*
1063          * If interrupts were soft-disabled when this PMU interrupt
1064          * occurred, treat it as an NMI.
1065          */
1066         nmi = !regs->softe;
1067         if (nmi)
1068                 nmi_enter();
1069         else
1070                 irq_enter();
1071
1072         for (i = 0; i < cpuhw->n_counters; ++i) {
1073                 counter = cpuhw->counter[i];
1074                 if (is_limited_pmc(counter->hw.idx))
1075                         continue;
1076                 val = read_pmc(counter->hw.idx);
1077                 if ((int)val < 0) {
1078                         /* counter has overflowed */
1079                         found = 1;
1080                         record_and_restart(counter, val, regs, nmi);
1081                 }
1082         }
1083
1084         /*
1085          * In case we didn't find and reset the counter that caused
1086          * the interrupt, scan all counters and reset any that are
1087          * negative, to avoid getting continual interrupts.
1088          * Any that we processed in the previous loop will not be negative.
1089          */
1090         if (!found) {
1091                 for (i = 0; i < ppmu->n_counter; ++i) {
1092                         if (is_limited_pmc(i + 1))
1093                                 continue;
1094                         val = read_pmc(i + 1);
1095                         if ((int)val < 0)
1096                                 write_pmc(i + 1, 0);
1097                 }
1098         }
1099
1100         /*
1101          * Reset MMCR0 to its normal value.  This will set PMXE and
1102          * clear FC (freeze counters) and PMAO (perf mon alert occurred)
1103          * and thus allow interrupts to occur again.
1104          * XXX might want to use MSR.PM to keep the counters frozen until
1105          * we get back out of this interrupt.
1106          */
1107         write_mmcr0(cpuhw, cpuhw->mmcr[0]);
1108
1109         if (nmi)
1110                 nmi_exit();
1111         else
1112                 irq_exit();
1113 }
1114
1115 void hw_perf_counter_setup(int cpu)
1116 {
1117         struct cpu_hw_counters *cpuhw = &per_cpu(cpu_hw_counters, cpu);
1118
1119         memset(cpuhw, 0, sizeof(*cpuhw));
1120         cpuhw->mmcr[0] = MMCR0_FC;
1121 }
1122
1123 extern struct power_pmu power4_pmu;
1124 extern struct power_pmu ppc970_pmu;
1125 extern struct power_pmu power5_pmu;
1126 extern struct power_pmu power5p_pmu;
1127 extern struct power_pmu power6_pmu;
1128
1129 static int init_perf_counters(void)
1130 {
1131         unsigned long pvr;
1132
1133         /* XXX should get this from cputable */
1134         pvr = mfspr(SPRN_PVR);
1135         switch (PVR_VER(pvr)) {
1136         case PV_POWER4:
1137         case PV_POWER4p:
1138                 ppmu = &power4_pmu;
1139                 break;
1140         case PV_970:
1141         case PV_970FX:
1142         case PV_970MP:
1143                 ppmu = &ppc970_pmu;
1144                 break;
1145         case PV_POWER5:
1146                 ppmu = &power5_pmu;
1147                 break;
1148         case PV_POWER5p:
1149                 ppmu = &power5p_pmu;
1150                 break;
1151         case 0x3e:
1152                 ppmu = &power6_pmu;
1153                 break;
1154         }
1155
1156         /*
1157          * Use FCHV to ignore kernel events if MSR.HV is set.
1158          */
1159         if (mfmsr() & MSR_HV)
1160                 freeze_counters_kernel = MMCR0_FCHV;
1161
1162         return 0;
1163 }
1164
1165 arch_initcall(init_perf_counters);