git.oblomov.eu Git - linux-2.6/blob - arch/mips/sibyte/sb1250/irq.c

   1 /*
   2  * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version 2
   7  * of the License, or (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  17  */
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/linkage.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/smp.h>
  24 #include <linux/mm.h>
  25 #include <linux/slab.h>
  26 #include <linux/kernel_stat.h>
  27
  28 #include <asm/errno.h>
  29 #include <asm/signal.h>
  30 #include <asm/system.h>
  31 #include <asm/ptrace.h>
  32 #include <asm/io.h>
  33
  34 #include <asm/sibyte/sb1250_regs.h>
  35 #include <asm/sibyte/sb1250_int.h>
  36 #include <asm/sibyte/sb1250_uart.h>
  37 #include <asm/sibyte/sb1250_scd.h>
  38 #include <asm/sibyte/sb1250.h>
  39
  40 /*
  41  * These are the routines that handle all the low level interrupt stuff.
  42  * Actions handled here are: initialization of the interrupt map, requesting of
  43  * interrupt lines by handlers, dispatching if interrupts to handlers, probing
  44  * for interrupt lines
  45  */
  46
  47
  48 #define shutdown_sb1250_irq     disable_sb1250_irq
  49 static void end_sb1250_irq(unsigned int irq);
  50 static void enable_sb1250_irq(unsigned int irq);
  51 static void disable_sb1250_irq(unsigned int irq);
  52 static unsigned int startup_sb1250_irq(unsigned int irq);
  53 static void ack_sb1250_irq(unsigned int irq);
  54 #ifdef CONFIG_SMP
  55 static void sb1250_set_affinity(unsigned int irq, cpumask_t mask);
  56 #endif
  57
  58 #ifdef CONFIG_SIBYTE_HAS_LDT
  59 extern unsigned long ldt_eoi_space;
  60 #endif
  61
  62 #ifdef CONFIG_KGDB
  63 static int kgdb_irq;
  64
  65 /* Default to UART1 */
  66 int kgdb_port = 1;
  67 #ifdef CONFIG_SIBYTE_SB1250_DUART
  68 extern char sb1250_duart_present[];
  69 #endif
  70 #endif
  71
  72 static struct irq_chip sb1250_irq_type = {
  73         .typename = "SB1250-IMR",
  74         .startup = startup_sb1250_irq,
  75         .shutdown = shutdown_sb1250_irq,
  76         .enable = enable_sb1250_irq,
  77         .disable = disable_sb1250_irq,
  78         .ack = ack_sb1250_irq,
  79         .end = end_sb1250_irq,
  80 #ifdef CONFIG_SMP
  81         .set_affinity = sb1250_set_affinity
  82 #endif
  83 };
  84
  85 /* Store the CPU id (not the logical number) */
  86 int sb1250_irq_owner[SB1250_NR_IRQS];
  87
  88 DEFINE_SPINLOCK(sb1250_imr_lock);
  89
  90 void sb1250_mask_irq(int cpu, int irq)
  91 {
  92         unsigned long flags;
  93         u64 cur_ints;
  94
  95         spin_lock_irqsave(&sb1250_imr_lock, flags);
  96         cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
  97                                         R_IMR_INTERRUPT_MASK));
  98         cur_ints |= (((u64) 1) << irq);
  99         ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
 100                                         R_IMR_INTERRUPT_MASK));
 101         spin_unlock_irqrestore(&sb1250_imr_lock, flags);
 102 }
 103
 104 void sb1250_unmask_irq(int cpu, int irq)
 105 {
 106         unsigned long flags;
 107         u64 cur_ints;
 108
 109         spin_lock_irqsave(&sb1250_imr_lock, flags);
 110         cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
 111                                         R_IMR_INTERRUPT_MASK));
 112         cur_ints &= ~(((u64) 1) << irq);
 113         ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
 114                                         R_IMR_INTERRUPT_MASK));
 115         spin_unlock_irqrestore(&sb1250_imr_lock, flags);
 116 }
 117
 118 #ifdef CONFIG_SMP
 119 static void sb1250_set_affinity(unsigned int irq, cpumask_t mask)
 120 {
 121         int i = 0, old_cpu, cpu, int_on;
 122         u64 cur_ints;
 123         struct irq_desc *desc = irq_desc + irq;
 124         unsigned long flags;
 125
 126         i = first_cpu(mask);
 127
 128         if (cpus_weight(mask) > 1) {
 129                 printk("attempted to set irq affinity for irq %d to multiple CPUs\n", irq);
 130                 return;
 131         }
 132
 133         /* Convert logical CPU to physical CPU */
 134         cpu = cpu_logical_map(i);
 135
 136         /* Protect against other affinity changers and IMR manipulation */
 137         spin_lock_irqsave(&desc->lock, flags);
 138         spin_lock(&sb1250_imr_lock);
 139
 140         /* Swizzle each CPU's IMR (but leave the IP selection alone) */
 141         old_cpu = sb1250_irq_owner[irq];
 142         cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(old_cpu) +
 143                                         R_IMR_INTERRUPT_MASK));
 144         int_on = !(cur_ints & (((u64) 1) << irq));
 145         if (int_on) {
 146                 /* If it was on, mask it */
 147                 cur_ints |= (((u64) 1) << irq);
 148                 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(old_cpu) +
 149                                         R_IMR_INTERRUPT_MASK));
 150         }
 151         sb1250_irq_owner[irq] = cpu;
 152         if (int_on) {
 153                 /* unmask for the new CPU */
 154                 cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) +
 155                                         R_IMR_INTERRUPT_MASK));
 156                 cur_ints &= ~(((u64) 1) << irq);
 157                 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) +
 158                                         R_IMR_INTERRUPT_MASK));
 159         }
 160         spin_unlock(&sb1250_imr_lock);
 161         spin_unlock_irqrestore(&desc->lock, flags);
 162 }
 163 #endif
 164
 165 /*****************************************************************************/
 166
 167 static unsigned int startup_sb1250_irq(unsigned int irq)
 168 {
 169         sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
 170
 171         return 0;               /* never anything pending */
 172 }
 173
 174
 175 static void disable_sb1250_irq(unsigned int irq)
 176 {
 177         sb1250_mask_irq(sb1250_irq_owner[irq], irq);
 178 }
 179
 180 static void enable_sb1250_irq(unsigned int irq)
 181 {
 182         sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
 183 }
 184
 185
 186 static void ack_sb1250_irq(unsigned int irq)
 187 {
 188 #ifdef CONFIG_SIBYTE_HAS_LDT
 189         u64 pending;
 190
 191         /*
 192          * If the interrupt was an HT interrupt, now is the time to
 193          * clear it.  NOTE: we assume the HT bridge was set up to
 194          * deliver the interrupts to all CPUs (which makes affinity
 195          * changing easier for us)
 196          */
 197         pending = __raw_readq(IOADDR(A_IMR_REGISTER(sb1250_irq_owner[irq],
 198                                                     R_IMR_LDT_INTERRUPT)));
 199         pending &= ((u64)1 << (irq));
 200         if (pending) {
 201                 int i;
 202                 for (i=0; i<NR_CPUS; i++) {
 203                         int cpu;
 204 #ifdef CONFIG_SMP
 205                         cpu = cpu_logical_map(i);
 206 #else
 207                         cpu = i;
 208 #endif
 209                         /*
 210                          * Clear for all CPUs so an affinity switch
 211                          * doesn't find an old status
 212                          */
 213                         __raw_writeq(pending,
 214                                      IOADDR(A_IMR_REGISTER(cpu,
 215                                                 R_IMR_LDT_INTERRUPT_CLR)));
 216                 }
 217
 218                 /*
 219                  * Generate EOI.  For Pass 1 parts, EOI is a nop.  For
 220                  * Pass 2, the LDT world may be edge-triggered, but
 221                  * this EOI shouldn't hurt.  If they are
 222                  * level-sensitive, the EOI is required.
 223                  */
 224                 *(uint32_t *)(ldt_eoi_space+(irq<<16)+(7<<2)) = 0;
 225         }
 226 #endif
 227         sb1250_mask_irq(sb1250_irq_owner[irq], irq);
 228 }
 229
 230
 231 static void end_sb1250_irq(unsigned int irq)
 232 {
 233         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
 234                 sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
 235         }
 236 }
 237
 238
 239 void __init init_sb1250_irqs(void)
 240 {
 241         int i;
 242
 243         for (i = 0; i < NR_IRQS; i++) {
 244                 irq_desc[i].status = IRQ_DISABLED;
 245                 irq_desc[i].action = 0;
 246                 irq_desc[i].depth = 1;
 247                 if (i < SB1250_NR_IRQS) {
 248                         irq_desc[i].chip = &sb1250_irq_type;
 249                         sb1250_irq_owner[i] = 0;
 250                 } else {
 251                         irq_desc[i].chip = &no_irq_chip;
 252                 }
 253         }
 254 }
 255
 256
 257 static irqreturn_t  sb1250_dummy_handler(int irq, void *dev_id,
 258         struct pt_regs *regs)
 259 {
 260         return IRQ_NONE;
 261 }
 262
 263 static struct irqaction sb1250_dummy_action = {
 264         .handler = sb1250_dummy_handler,
 265         .flags   = 0,
 266         .mask    = CPU_MASK_NONE,
 267         .name    = "sb1250-private",
 268         .next    = NULL,
 269         .dev_id  = 0
 270 };
 271
 272 int sb1250_steal_irq(int irq)
 273 {
 274         struct irq_desc *desc = irq_desc + irq;
 275         unsigned long flags;
 276         int retval = 0;
 277
 278         if (irq >= SB1250_NR_IRQS)
 279                 return -EINVAL;
 280
 281         spin_lock_irqsave(&desc->lock,flags);
 282         /* Don't allow sharing at all for these */
 283         if (desc->action != NULL)
 284                 retval = -EBUSY;
 285         else {
 286                 desc->action = &sb1250_dummy_action;
 287                 desc->depth = 0;
 288         }
 289         spin_unlock_irqrestore(&desc->lock,flags);
 290         return 0;
 291 }
 292
 293 /*
 294  *  arch_init_irq is called early in the boot sequence from init/main.c via
 295  *  init_IRQ.  It is responsible for setting up the interrupt mapper and
 296  *  installing the handler that will be responsible for dispatching interrupts
 297  *  to the "right" place.
 298  */
 299 /*
 300  * For now, map all interrupts to IP[2].  We could save
 301  * some cycles by parceling out system interrupts to different
 302  * IP lines, but keep it simple for bringup.  We'll also direct
 303  * all interrupts to a single CPU; we should probably route
 304  * PCI and LDT to one cpu and everything else to the other
 305  * to balance the load a bit.
 306  *
 307  * On the second cpu, everything is set to IP5, which is
 308  * ignored, EXCEPT the mailbox interrupt.  That one is
 309  * set to IP[2] so it is handled.  This is needed so we
 310  * can do cross-cpu function calls, as requred by SMP
 311  */
 312
 313 #define IMR_IP2_VAL     K_INT_MAP_I0
 314 #define IMR_IP3_VAL     K_INT_MAP_I1
 315 #define IMR_IP4_VAL     K_INT_MAP_I2
 316 #define IMR_IP5_VAL     K_INT_MAP_I3
 317 #define IMR_IP6_VAL     K_INT_MAP_I4
 318
 319 void __init arch_init_irq(void)
 320 {
 321
 322         unsigned int i;
 323         u64 tmp;
 324         unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
 325                 STATUSF_IP1 | STATUSF_IP0;
 326
 327         /* Default everything to IP2 */
 328         for (i = 0; i < SB1250_NR_IRQS; i++) {  /* was I0 */
 329                 __raw_writeq(IMR_IP2_VAL,
 330                              IOADDR(A_IMR_REGISTER(0,
 331                                                    R_IMR_INTERRUPT_MAP_BASE) +
 332                                     (i << 3)));
 333                 __raw_writeq(IMR_IP2_VAL,
 334                              IOADDR(A_IMR_REGISTER(1,
 335                                                    R_IMR_INTERRUPT_MAP_BASE) +
 336                                     (i << 3)));
 337         }
 338
 339         init_sb1250_irqs();
 340
 341         /*
 342          * Map the high 16 bits of the mailbox registers to IP[3], for
 343          * inter-cpu messages
 344          */
 345         /* Was I1 */
 346         __raw_writeq(IMR_IP3_VAL,
 347                      IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
 348                             (K_INT_MBOX_0 << 3)));
 349         __raw_writeq(IMR_IP3_VAL,
 350                      IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) +
 351                             (K_INT_MBOX_0 << 3)));
 352
 353         /* Clear the mailboxes.  The firmware may leave them dirty */
 354         __raw_writeq(0xffffffffffffffffULL,
 355                      IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU)));
 356         __raw_writeq(0xffffffffffffffffULL,
 357                      IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU)));
 358
 359         /* Mask everything except the mailbox registers for both cpus */
 360         tmp = ~((u64) 0) ^ (((u64) 1) << K_INT_MBOX_0);
 361         __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK)));
 362         __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK)));
 363
 364         sb1250_steal_irq(K_INT_MBOX_0);
 365
 366         /*
 367          * Note that the timer interrupts are also mapped, but this is
 368          * done in sb1250_time_init().  Also, the profiling driver
 369          * does its own management of IP7.
 370          */
 371
 372 #ifdef CONFIG_KGDB
 373         imask |= STATUSF_IP6;
 374 #endif
 375         /* Enable necessary IPs, disable the rest */
 376         change_c0_status(ST0_IM, imask);
 377
 378 #ifdef CONFIG_KGDB
 379         if (kgdb_flag) {
 380                 kgdb_irq = K_INT_UART_0 + kgdb_port;
 381
 382 #ifdef CONFIG_SIBYTE_SB1250_DUART
 383                 sb1250_duart_present[kgdb_port] = 0;
 384 #endif
 385                 /* Setup uart 1 settings, mapper */
 386                 __raw_writeq(M_DUART_IMR_BRK,
 387                              IOADDR(A_DUART_IMRREG(kgdb_port)));
 388
 389                 sb1250_steal_irq(kgdb_irq);
 390                 __raw_writeq(IMR_IP6_VAL,
 391                              IOADDR(A_IMR_REGISTER(0,
 392                                                    R_IMR_INTERRUPT_MAP_BASE) +
 393                                     (kgdb_irq << 3)));
 394                 sb1250_unmask_irq(0, kgdb_irq);
 395         }
 396 #endif
 397 }
 398
 399 #ifdef CONFIG_KGDB
 400
 401 #include <linux/delay.h>
 402
 403 #define duart_out(reg, val)     csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port,reg)))
 404 #define duart_in(reg)           csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port,reg)))
 405
 406 static void sb1250_kgdb_interrupt(struct pt_regs *regs)
 407 {
 408         /*
 409          * Clear break-change status (allow some time for the remote
 410          * host to stop the break, since we would see another
 411          * interrupt on the end-of-break too)
 412          */
 413         kstat_this_cpu.irqs[kgdb_irq]++;
 414         mdelay(500);
 415         duart_out(R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT |
 416                                 M_DUART_RX_EN | M_DUART_TX_EN);
 417         set_async_breakpoint(&regs->cp0_epc);
 418 }
 419
 420 #endif  /* CONFIG_KGDB */
 421
 422 extern void sb1250_timer_interrupt(struct pt_regs *regs);
 423 extern void sb1250_mailbox_interrupt(struct pt_regs *regs);
 424 extern void sb1250_kgdb_interrupt(struct pt_regs *regs);
 425
 426 asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
 427 {
 428         unsigned int pending;
 429
 430 #ifdef CONFIG_SIBYTE_SB1250_PROF
 431         /* Set compare to count to silence count/compare timer interrupts */
 432         write_c0_compare(read_c0_count());
 433 #endif
 434
 435         /*
 436          * What a pain. We have to be really careful saving the upper 32 bits
 437          * of any * register across function calls if we don't want them
 438          * trashed--since were running in -o32, the calling routing never saves
 439          * the full 64 bits of a register across a function call.  Being the
 440          * interrupt handler, we're guaranteed that interrupts are disabled
 441          * during this code so we don't have to worry about random interrupts
 442          * blasting the high 32 bits.
 443          */
 444
 445         pending = read_c0_cause();
 446
 447 #ifdef CONFIG_SIBYTE_SB1250_PROF
 448         if (pending & CAUSEF_IP7) /* Cpu performance counter interrupt */
 449                 sbprof_cpu_intr(exception_epc(regs));
 450         else
 451 #endif
 452
 453         if (pending & CAUSEF_IP4)
 454                 sb1250_timer_interrupt(regs);
 455
 456 #ifdef CONFIG_SMP
 457         else if (pending & CAUSEF_IP3)
 458                 sb1250_mailbox_interrupt(regs);
 459 #endif
 460
 461 #ifdef CONFIG_KGDB
 462         else if (pending & CAUSEF_IP6)                  /* KGDB (uart 1) */
 463                 sb1250_kgdb_interrupt(regs);
 464 #endif
 465
 466         else if (pending & CAUSEF_IP2) {
 467                 unsigned long long mask;
 468
 469                 /*
 470                  * Default...we've hit an IP[2] interrupt, which means we've
 471                  * got to check the 1250 interrupt registers to figure out what
 472                  * to do.  Need to detect which CPU we're on, now that
 473                  * smp_affinity is supported.
 474                  */
 475                 mask = __raw_readq(IOADDR(A_IMR_REGISTER(smp_processor_id(),
 476                                               R_IMR_INTERRUPT_STATUS_BASE)));
 477                 if (mask)
 478                         do_IRQ(fls64(mask) - 1, regs);
 479         }
 480 }