2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2000, 01 MIPS Technologies, Inc.
12 * Copyright (C) 2002, 2003, 2004, 2005 Maciej W. Rozycki
14 #include <linux/bug.h>
15 #include <linux/init.h>
17 #include <linux/module.h>
18 #include <linux/sched.h>
19 #include <linux/smp.h>
20 #include <linux/spinlock.h>
21 #include <linux/kallsyms.h>
22 #include <linux/bootmem.h>
23 #include <linux/interrupt.h>
25 #include <asm/bootinfo.h>
26 #include <asm/branch.h>
27 #include <asm/break.h>
31 #include <asm/mipsregs.h>
32 #include <asm/mipsmtregs.h>
33 #include <asm/module.h>
34 #include <asm/pgtable.h>
35 #include <asm/ptrace.h>
36 #include <asm/sections.h>
37 #include <asm/system.h>
38 #include <asm/tlbdebug.h>
39 #include <asm/traps.h>
40 #include <asm/uaccess.h>
41 #include <asm/mmu_context.h>
42 #include <asm/types.h>
43 #include <asm/stacktrace.h>
45 extern asmlinkage void handle_int(void);
46 extern asmlinkage void handle_tlbm(void);
47 extern asmlinkage void handle_tlbl(void);
48 extern asmlinkage void handle_tlbs(void);
49 extern asmlinkage void handle_adel(void);
50 extern asmlinkage void handle_ades(void);
51 extern asmlinkage void handle_ibe(void);
52 extern asmlinkage void handle_dbe(void);
53 extern asmlinkage void handle_sys(void);
54 extern asmlinkage void handle_bp(void);
55 extern asmlinkage void handle_ri(void);
56 extern asmlinkage void handle_ri_rdhwr_vivt(void);
57 extern asmlinkage void handle_ri_rdhwr(void);
58 extern asmlinkage void handle_cpu(void);
59 extern asmlinkage void handle_ov(void);
60 extern asmlinkage void handle_tr(void);
61 extern asmlinkage void handle_fpe(void);
62 extern asmlinkage void handle_mdmx(void);
63 extern asmlinkage void handle_watch(void);
64 extern asmlinkage void handle_mt(void);
65 extern asmlinkage void handle_dsp(void);
66 extern asmlinkage void handle_mcheck(void);
67 extern asmlinkage void handle_reserved(void);
69 extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
70 struct mips_fpu_struct *ctx, int has_fpu);
72 void (*board_watchpoint_handler)(struct pt_regs *regs);
73 void (*board_be_init)(void);
74 int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
75 void (*board_nmi_handler_setup)(void);
76 void (*board_ejtag_handler_setup)(void);
77 void (*board_bind_eic_interrupt)(int irq, int regset);
80 static void show_raw_backtrace(unsigned long reg29)
82 unsigned long *sp = (unsigned long *)reg29;
85 printk("Call Trace:");
86 #ifdef CONFIG_KALLSYMS
89 while (!kstack_end(sp)) {
91 if (__kernel_text_address(addr))
97 #ifdef CONFIG_KALLSYMS
99 static int __init set_raw_show_trace(char *str)
104 __setup("raw_show_trace", set_raw_show_trace);
107 static void show_backtrace(struct task_struct *task, struct pt_regs *regs)
109 unsigned long sp = regs->regs[29];
110 unsigned long ra = regs->regs[31];
111 unsigned long pc = regs->cp0_epc;
113 if (raw_show_trace || !__kernel_text_address(pc)) {
114 show_raw_backtrace(sp);
117 printk("Call Trace:\n");
120 pc = unwind_stack(task, &sp, pc, &ra);
126 * This routine abuses get_user()/put_user() to reference pointers
127 * with at least a bit of error checking ...
129 static void show_stacktrace(struct task_struct *task, struct pt_regs *regs)
131 const int field = 2 * sizeof(unsigned long);
134 unsigned long *sp = (unsigned long *)regs->regs[29];
138 while ((unsigned long) sp & (PAGE_SIZE - 1)) {
139 if (i && ((i % (64 / field)) == 0))
146 if (__get_user(stackdata, sp++)) {
147 printk(" (Bad stack address)");
151 printk(" %0*lx", field, stackdata);
155 show_backtrace(task, regs);
158 void show_stack(struct task_struct *task, unsigned long *sp)
162 regs.regs[29] = (unsigned long)sp;
166 if (task && task != current) {
167 regs.regs[29] = task->thread.reg29;
169 regs.cp0_epc = task->thread.reg31;
171 prepare_frametrace(®s);
174 show_stacktrace(task, ®s);
178 * The architecture-independent dump_stack generator
180 void dump_stack(void)
184 prepare_frametrace(®s);
185 show_backtrace(current, ®s);
188 EXPORT_SYMBOL(dump_stack);
190 void show_code(unsigned int *pc)
196 for(i = -3 ; i < 6 ; i++) {
198 if (__get_user(insn, pc + i)) {
199 printk(" (Bad address in epc)\n");
202 printk("%c%08x%c", (i?' ':'<'), insn, (i?' ':'>'));
206 void show_regs(struct pt_regs *regs)
208 const int field = 2 * sizeof(unsigned long);
209 unsigned int cause = regs->cp0_cause;
212 printk("Cpu %d\n", smp_processor_id());
215 * Saved main processor registers
217 for (i = 0; i < 32; ) {
221 printk(" %0*lx", field, 0UL);
222 else if (i == 26 || i == 27)
223 printk(" %*s", field, "");
225 printk(" %0*lx", field, regs->regs[i]);
232 #ifdef CONFIG_CPU_HAS_SMARTMIPS
233 printk("Acx : %0*lx\n", field, regs->acx);
235 printk("Hi : %0*lx\n", field, regs->hi);
236 printk("Lo : %0*lx\n", field, regs->lo);
239 * Saved cp0 registers
241 printk("epc : %0*lx ", field, regs->cp0_epc);
242 print_symbol("%s ", regs->cp0_epc);
243 printk(" %s\n", print_tainted());
244 printk("ra : %0*lx ", field, regs->regs[31]);
245 print_symbol("%s\n", regs->regs[31]);
247 printk("Status: %08x ", (uint32_t) regs->cp0_status);
249 if (current_cpu_data.isa_level == MIPS_CPU_ISA_I) {
250 if (regs->cp0_status & ST0_KUO)
252 if (regs->cp0_status & ST0_IEO)
254 if (regs->cp0_status & ST0_KUP)
256 if (regs->cp0_status & ST0_IEP)
258 if (regs->cp0_status & ST0_KUC)
260 if (regs->cp0_status & ST0_IEC)
263 if (regs->cp0_status & ST0_KX)
265 if (regs->cp0_status & ST0_SX)
267 if (regs->cp0_status & ST0_UX)
269 switch (regs->cp0_status & ST0_KSU) {
274 printk("SUPERVISOR ");
283 if (regs->cp0_status & ST0_ERL)
285 if (regs->cp0_status & ST0_EXL)
287 if (regs->cp0_status & ST0_IE)
292 printk("Cause : %08x\n", cause);
294 cause = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE;
295 if (1 <= cause && cause <= 5)
296 printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
298 printk("PrId : %08x\n", read_c0_prid());
301 void show_registers(struct pt_regs *regs)
305 printk("Process %s (pid: %d, threadinfo=%p, task=%p)\n",
306 current->comm, current->pid, current_thread_info(), current);
307 show_stacktrace(current, regs);
308 show_code((unsigned int *) regs->cp0_epc);
312 static DEFINE_SPINLOCK(die_lock);
314 void __noreturn die(const char * str, struct pt_regs * regs)
316 static int die_counter;
317 #ifdef CONFIG_MIPS_MT_SMTC
318 unsigned long dvpret = dvpe();
319 #endif /* CONFIG_MIPS_MT_SMTC */
322 spin_lock_irq(&die_lock);
324 #ifdef CONFIG_MIPS_MT_SMTC
325 mips_mt_regdump(dvpret);
326 #endif /* CONFIG_MIPS_MT_SMTC */
327 printk("%s[#%d]:\n", str, ++die_counter);
328 show_registers(regs);
329 spin_unlock_irq(&die_lock);
332 panic("Fatal exception in interrupt");
335 printk(KERN_EMERG "Fatal exception: panic in 5 seconds\n");
337 panic("Fatal exception");
343 extern const struct exception_table_entry __start___dbe_table[];
344 extern const struct exception_table_entry __stop___dbe_table[];
347 " .section __dbe_table, \"a\"\n"
350 /* Given an address, look for it in the exception tables. */
351 static const struct exception_table_entry *search_dbe_tables(unsigned long addr)
353 const struct exception_table_entry *e;
355 e = search_extable(__start___dbe_table, __stop___dbe_table - 1, addr);
357 e = search_module_dbetables(addr);
361 asmlinkage void do_be(struct pt_regs *regs)
363 const int field = 2 * sizeof(unsigned long);
364 const struct exception_table_entry *fixup = NULL;
365 int data = regs->cp0_cause & 4;
366 int action = MIPS_BE_FATAL;
368 /* XXX For now. Fixme, this searches the wrong table ... */
369 if (data && !user_mode(regs))
370 fixup = search_dbe_tables(exception_epc(regs));
373 action = MIPS_BE_FIXUP;
375 if (board_be_handler)
376 action = board_be_handler(regs, fixup != NULL);
379 case MIPS_BE_DISCARD:
383 regs->cp0_epc = fixup->nextinsn;
392 * Assume it would be too dangerous to continue ...
394 printk(KERN_ALERT "%s bus error, epc == %0*lx, ra == %0*lx\n",
395 data ? "Data" : "Instruction",
396 field, regs->cp0_epc, field, regs->regs[31]);
397 die_if_kernel("Oops", regs);
398 force_sig(SIGBUS, current);
405 #define OPCODE 0xfc000000
406 #define BASE 0x03e00000
407 #define RT 0x001f0000
408 #define OFFSET 0x0000ffff
409 #define LL 0xc0000000
410 #define SC 0xe0000000
411 #define SPEC3 0x7c000000
412 #define RD 0x0000f800
413 #define FUNC 0x0000003f
414 #define RDHWR 0x0000003b
417 * The ll_bit is cleared by r*_switch.S
420 unsigned long ll_bit;
422 static struct task_struct *ll_task = NULL;
424 static inline void simulate_ll(struct pt_regs *regs, unsigned int opcode)
426 unsigned long value, __user *vaddr;
431 * analyse the ll instruction that just caused a ri exception
432 * and put the referenced address to addr.
435 /* sign extend offset */
436 offset = opcode & OFFSET;
440 vaddr = (unsigned long __user *)
441 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
443 if ((unsigned long)vaddr & 3) {
447 if (get_user(value, vaddr)) {
454 if (ll_task == NULL || ll_task == current) {
463 compute_return_epc(regs);
465 regs->regs[(opcode & RT) >> 16] = value;
470 force_sig(signal, current);
473 static inline void simulate_sc(struct pt_regs *regs, unsigned int opcode)
475 unsigned long __user *vaddr;
481 * analyse the sc instruction that just caused a ri exception
482 * and put the referenced address to addr.
485 /* sign extend offset */
486 offset = opcode & OFFSET;
490 vaddr = (unsigned long __user *)
491 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset);
492 reg = (opcode & RT) >> 16;
494 if ((unsigned long)vaddr & 3) {
501 if (ll_bit == 0 || ll_task != current) {
502 compute_return_epc(regs);
510 if (put_user(regs->regs[reg], vaddr)) {
515 compute_return_epc(regs);
521 force_sig(signal, current);
525 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
526 * opcodes are supposed to result in coprocessor unusable exceptions if
527 * executed on ll/sc-less processors. That's the theory. In practice a
528 * few processors such as NEC's VR4100 throw reserved instruction exceptions
529 * instead, so we're doing the emulation thing in both exception handlers.
531 static inline int simulate_llsc(struct pt_regs *regs)
535 if (get_user(opcode, (unsigned int __user *) exception_epc(regs)))
538 if ((opcode & OPCODE) == LL) {
539 simulate_ll(regs, opcode);
542 if ((opcode & OPCODE) == SC) {
543 simulate_sc(regs, opcode);
547 return -EFAULT; /* Strange things going on ... */
550 force_sig(SIGSEGV, current);
555 * Simulate trapping 'rdhwr' instructions to provide user accessible
556 * registers not implemented in hardware. The only current use of this
557 * is the thread area pointer.
559 static inline int simulate_rdhwr(struct pt_regs *regs)
561 struct thread_info *ti = task_thread_info(current);
564 if (get_user(opcode, (unsigned int __user *) exception_epc(regs)))
567 if (unlikely(compute_return_epc(regs)))
570 if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
571 int rd = (opcode & RD) >> 11;
572 int rt = (opcode & RT) >> 16;
575 regs->regs[rt] = ti->tp_value;
586 force_sig(SIGSEGV, current);
590 asmlinkage void do_ov(struct pt_regs *regs)
594 die_if_kernel("Integer overflow", regs);
596 info.si_code = FPE_INTOVF;
597 info.si_signo = SIGFPE;
599 info.si_addr = (void __user *) regs->cp0_epc;
600 force_sig_info(SIGFPE, &info, current);
604 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
606 asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
608 die_if_kernel("FP exception in kernel code", regs);
610 if (fcr31 & FPU_CSR_UNI_X) {
614 * Unimplemented operation exception. If we've got the full
615 * software emulator on-board, let's use it...
617 * Force FPU to dump state into task/thread context. We're
618 * moving a lot of data here for what is probably a single
619 * instruction, but the alternative is to pre-decode the FP
620 * register operands before invoking the emulator, which seems
621 * a bit extreme for what should be an infrequent event.
623 /* Ensure 'resume' not overwrite saved fp context again. */
626 /* Run the emulator */
627 sig = fpu_emulator_cop1Handler (regs, ¤t->thread.fpu, 1);
630 * We can't allow the emulated instruction to leave any of
631 * the cause bit set in $fcr31.
633 current->thread.fpu.fcr31 &= ~FPU_CSR_ALL_X;
635 /* Restore the hardware register state */
636 own_fpu(1); /* Using the FPU again. */
638 /* If something went wrong, signal */
640 force_sig(sig, current);
645 force_sig(SIGFPE, current);
648 asmlinkage void do_bp(struct pt_regs *regs)
650 unsigned int opcode, bcode;
653 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs)))
657 * There is the ancient bug in the MIPS assemblers that the break
658 * code starts left to bit 16 instead to bit 6 in the opcode.
659 * Gas is bug-compatible, but not always, grrr...
660 * We handle both cases with a simple heuristics. --macro
662 bcode = ((opcode >> 6) & ((1 << 20) - 1));
663 if (bcode < (1 << 10))
667 * (A short test says that IRIX 5.3 sends SIGTRAP for all break
668 * insns, even for break codes that indicate arithmetic failures.
670 * But should we continue the brokenness??? --macro
673 case BRK_OVERFLOW << 10:
674 case BRK_DIVZERO << 10:
675 die_if_kernel("Break instruction in kernel code", regs);
676 if (bcode == (BRK_DIVZERO << 10))
677 info.si_code = FPE_INTDIV;
679 info.si_code = FPE_INTOVF;
680 info.si_signo = SIGFPE;
682 info.si_addr = (void __user *) regs->cp0_epc;
683 force_sig_info(SIGFPE, &info, current);
686 die("Kernel bug detected", regs);
689 die_if_kernel("Break instruction in kernel code", regs);
690 force_sig(SIGTRAP, current);
695 force_sig(SIGSEGV, current);
698 asmlinkage void do_tr(struct pt_regs *regs)
700 unsigned int opcode, tcode = 0;
703 if (__get_user(opcode, (unsigned int __user *) exception_epc(regs)))
706 /* Immediate versions don't provide a code. */
707 if (!(opcode & OPCODE))
708 tcode = ((opcode >> 6) & ((1 << 10) - 1));
711 * (A short test says that IRIX 5.3 sends SIGTRAP for all trap
712 * insns, even for trap codes that indicate arithmetic failures.
714 * But should we continue the brokenness??? --macro
719 die_if_kernel("Trap instruction in kernel code", regs);
720 if (tcode == BRK_DIVZERO)
721 info.si_code = FPE_INTDIV;
723 info.si_code = FPE_INTOVF;
724 info.si_signo = SIGFPE;
726 info.si_addr = (void __user *) regs->cp0_epc;
727 force_sig_info(SIGFPE, &info, current);
730 die("Kernel bug detected", regs);
733 die_if_kernel("Trap instruction in kernel code", regs);
734 force_sig(SIGTRAP, current);
739 force_sig(SIGSEGV, current);
742 asmlinkage void do_ri(struct pt_regs *regs)
744 die_if_kernel("Reserved instruction in kernel code", regs);
747 if (!simulate_llsc(regs))
750 if (!simulate_rdhwr(regs))
753 force_sig(SIGILL, current);
757 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've
758 * emulated more than some threshold number of instructions, force migration to
759 * a "CPU" that has FP support.
761 static void mt_ase_fp_affinity(void)
763 #ifdef CONFIG_MIPS_MT_FPAFF
764 if (mt_fpemul_threshold > 0 &&
765 ((current->thread.emulated_fp++ > mt_fpemul_threshold))) {
767 * If there's no FPU present, or if the application has already
768 * restricted the allowed set to exclude any CPUs with FPUs,
769 * we'll skip the procedure.
771 if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) {
774 cpus_and(tmask, current->thread.user_cpus_allowed,
776 set_cpus_allowed(current, tmask);
777 current->thread.mflags |= MF_FPUBOUND;
780 #endif /* CONFIG_MIPS_MT_FPAFF */
783 asmlinkage void do_cpu(struct pt_regs *regs)
787 die_if_kernel("do_cpu invoked from kernel context!", regs);
789 cpid = (regs->cp0_cause >> CAUSEB_CE) & 3;
794 if (!simulate_llsc(regs))
797 if (!simulate_rdhwr(regs))
803 if (used_math()) /* Using the FPU again. */
805 else { /* First time FPU user. */
810 if (!raw_cpu_has_fpu) {
812 sig = fpu_emulator_cop1Handler(regs,
813 ¤t->thread.fpu, 0);
815 force_sig(sig, current);
817 mt_ase_fp_affinity();
827 force_sig(SIGILL, current);
830 asmlinkage void do_mdmx(struct pt_regs *regs)
832 force_sig(SIGILL, current);
835 asmlinkage void do_watch(struct pt_regs *regs)
837 if (board_watchpoint_handler) {
838 (*board_watchpoint_handler)(regs);
843 * We use the watch exception where available to detect stack
848 panic("Caught WATCH exception - probably caused by stack overflow.");
851 asmlinkage void do_mcheck(struct pt_regs *regs)
853 const int field = 2 * sizeof(unsigned long);
854 int multi_match = regs->cp0_status & ST0_TS;
859 printk("Index : %0x\n", read_c0_index());
860 printk("Pagemask: %0x\n", read_c0_pagemask());
861 printk("EntryHi : %0*lx\n", field, read_c0_entryhi());
862 printk("EntryLo0: %0*lx\n", field, read_c0_entrylo0());
863 printk("EntryLo1: %0*lx\n", field, read_c0_entrylo1());
868 show_code((unsigned int *) regs->cp0_epc);
871 * Some chips may have other causes of machine check (e.g. SB1
874 panic("Caught Machine Check exception - %scaused by multiple "
875 "matching entries in the TLB.",
876 (multi_match) ? "" : "not ");
879 asmlinkage void do_mt(struct pt_regs *regs)
883 subcode = (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT)
884 >> VPECONTROL_EXCPT_SHIFT;
887 printk(KERN_DEBUG "Thread Underflow\n");
890 printk(KERN_DEBUG "Thread Overflow\n");
893 printk(KERN_DEBUG "Invalid YIELD Qualifier\n");
896 printk(KERN_DEBUG "Gating Storage Exception\n");
899 printk(KERN_DEBUG "YIELD Scheduler Exception\n");
902 printk(KERN_DEBUG "Gating Storage Schedulier Exception\n");
905 printk(KERN_DEBUG "*** UNKNOWN THREAD EXCEPTION %d ***\n",
909 die_if_kernel("MIPS MT Thread exception in kernel", regs);
911 force_sig(SIGILL, current);
915 asmlinkage void do_dsp(struct pt_regs *regs)
918 panic("Unexpected DSP exception\n");
920 force_sig(SIGILL, current);
923 asmlinkage void do_reserved(struct pt_regs *regs)
926 * Game over - no way to handle this if it ever occurs. Most probably
927 * caused by a new unknown cpu type or after another deadly
928 * hard/software error.
931 panic("Caught reserved exception %ld - should not happen.",
932 (regs->cp0_cause & 0x7f) >> 2);
936 * Some MIPS CPUs can enable/disable for cache parity detection, but do
939 static inline void parity_protection_init(void)
941 switch (current_cpu_data.cputype) {
945 write_c0_ecc(0x80000000);
946 back_to_back_c0_hazard();
947 /* Set the PE bit (bit 31) in the c0_errctl register. */
948 printk(KERN_INFO "Cache parity protection %sabled\n",
949 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
953 /* Clear the DE bit (bit 16) in the c0_status register. */
954 printk(KERN_INFO "Enable cache parity protection for "
955 "MIPS 20KC/25KF CPUs.\n");
956 clear_c0_status(ST0_DE);
963 asmlinkage void cache_parity_error(void)
965 const int field = 2 * sizeof(unsigned long);
966 unsigned int reg_val;
968 /* For the moment, report the problem and hang. */
969 printk("Cache error exception:\n");
970 printk("cp0_errorepc == %0*lx\n", field, read_c0_errorepc());
971 reg_val = read_c0_cacheerr();
972 printk("c0_cacheerr == %08x\n", reg_val);
974 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
975 reg_val & (1<<30) ? "secondary" : "primary",
976 reg_val & (1<<31) ? "data" : "insn");
977 printk("Error bits: %s%s%s%s%s%s%s\n",
978 reg_val & (1<<29) ? "ED " : "",
979 reg_val & (1<<28) ? "ET " : "",
980 reg_val & (1<<26) ? "EE " : "",
981 reg_val & (1<<25) ? "EB " : "",
982 reg_val & (1<<24) ? "EI " : "",
983 reg_val & (1<<23) ? "E1 " : "",
984 reg_val & (1<<22) ? "E0 " : "");
985 printk("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
987 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
988 if (reg_val & (1<<22))
989 printk("DErrAddr0: 0x%0*lx\n", field, read_c0_derraddr0());
991 if (reg_val & (1<<23))
992 printk("DErrAddr1: 0x%0*lx\n", field, read_c0_derraddr1());
995 panic("Can't handle the cache error!");
999 * SDBBP EJTAG debug exception handler.
1000 * We skip the instruction and return to the next instruction.
1002 void ejtag_exception_handler(struct pt_regs *regs)
1004 const int field = 2 * sizeof(unsigned long);
1005 unsigned long depc, old_epc;
1008 printk(KERN_DEBUG "SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
1009 depc = read_c0_depc();
1010 debug = read_c0_debug();
1011 printk(KERN_DEBUG "c0_depc = %0*lx, DEBUG = %08x\n", field, depc, debug);
1012 if (debug & 0x80000000) {
1014 * In branch delay slot.
1015 * We cheat a little bit here and use EPC to calculate the
1016 * debug return address (DEPC). EPC is restored after the
1019 old_epc = regs->cp0_epc;
1020 regs->cp0_epc = depc;
1021 __compute_return_epc(regs);
1022 depc = regs->cp0_epc;
1023 regs->cp0_epc = old_epc;
1026 write_c0_depc(depc);
1029 printk(KERN_DEBUG "\n\n----- Enable EJTAG single stepping ----\n\n");
1030 write_c0_debug(debug | 0x100);
1035 * NMI exception handler.
1037 void nmi_exception_handler(struct pt_regs *regs)
1039 #ifdef CONFIG_MIPS_MT_SMTC
1040 unsigned long dvpret = dvpe();
1042 printk("NMI taken!!!!\n");
1043 mips_mt_regdump(dvpret);
1046 printk("NMI taken!!!!\n");
1047 #endif /* CONFIG_MIPS_MT_SMTC */
1052 #define VECTORSPACING 0x100 /* for EI/VI mode */
1054 unsigned long ebase;
1055 unsigned long exception_handlers[32];
1056 unsigned long vi_handlers[64];
1059 * As a side effect of the way this is implemented we're limited
1060 * to interrupt handlers in the address range from
1061 * KSEG0 <= x < KSEG0 + 256mb on the Nevada. Oh well ...
1063 void *set_except_vector(int n, void *addr)
1065 unsigned long handler = (unsigned long) addr;
1066 unsigned long old_handler = exception_handlers[n];
1068 exception_handlers[n] = handler;
1069 if (n == 0 && cpu_has_divec) {
1070 *(volatile u32 *)(ebase + 0x200) = 0x08000000 |
1071 (0x03ffffff & (handler >> 2));
1072 flush_icache_range(ebase + 0x200, ebase + 0x204);
1074 return (void *)old_handler;
1077 #ifdef CONFIG_CPU_MIPSR2_SRS
1079 * MIPSR2 shadow register set allocation
1083 static struct shadow_registers {
1085 * Number of shadow register sets supported
1087 unsigned long sr_supported;
1089 * Bitmap of allocated shadow registers
1091 unsigned long sr_allocated;
1094 static void mips_srs_init(void)
1096 shadow_registers.sr_supported = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1097 printk(KERN_INFO "%ld MIPSR2 register sets available\n",
1098 shadow_registers.sr_supported);
1099 shadow_registers.sr_allocated = 1; /* Set 0 used by kernel */
1102 int mips_srs_max(void)
1104 return shadow_registers.sr_supported;
1107 int mips_srs_alloc(void)
1109 struct shadow_registers *sr = &shadow_registers;
1113 set = find_first_zero_bit(&sr->sr_allocated, sr->sr_supported);
1114 if (set >= sr->sr_supported)
1117 if (test_and_set_bit(set, &sr->sr_allocated))
1123 void mips_srs_free(int set)
1125 struct shadow_registers *sr = &shadow_registers;
1127 clear_bit(set, &sr->sr_allocated);
1130 static asmlinkage void do_default_vi(void)
1132 show_regs(get_irq_regs());
1133 panic("Caught unexpected vectored interrupt.");
1136 static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs)
1138 unsigned long handler;
1139 unsigned long old_handler = vi_handlers[n];
1143 if (!cpu_has_veic && !cpu_has_vint)
1147 handler = (unsigned long) do_default_vi;
1150 handler = (unsigned long) addr;
1151 vi_handlers[n] = (unsigned long) addr;
1153 b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING);
1155 if (srs >= mips_srs_max())
1156 panic("Shadow register set %d not supported", srs);
1159 if (board_bind_eic_interrupt)
1160 board_bind_eic_interrupt (n, srs);
1161 } else if (cpu_has_vint) {
1162 /* SRSMap is only defined if shadow sets are implemented */
1163 if (mips_srs_max() > 1)
1164 change_c0_srsmap (0xf << n*4, srs << n*4);
1169 * If no shadow set is selected then use the default handler
1170 * that does normal register saving and a standard interrupt exit
1173 extern char except_vec_vi, except_vec_vi_lui;
1174 extern char except_vec_vi_ori, except_vec_vi_end;
1175 #ifdef CONFIG_MIPS_MT_SMTC
1177 * We need to provide the SMTC vectored interrupt handler
1178 * not only with the address of the handler, but with the
1179 * Status.IM bit to be masked before going there.
1181 extern char except_vec_vi_mori;
1182 const int mori_offset = &except_vec_vi_mori - &except_vec_vi;
1183 #endif /* CONFIG_MIPS_MT_SMTC */
1184 const int handler_len = &except_vec_vi_end - &except_vec_vi;
1185 const int lui_offset = &except_vec_vi_lui - &except_vec_vi;
1186 const int ori_offset = &except_vec_vi_ori - &except_vec_vi;
1188 if (handler_len > VECTORSPACING) {
1190 * Sigh... panicing won't help as the console
1191 * is probably not configured :(
1193 panic ("VECTORSPACING too small");
1196 memcpy (b, &except_vec_vi, handler_len);
1197 #ifdef CONFIG_MIPS_MT_SMTC
1198 BUG_ON(n > 7); /* Vector index %d exceeds SMTC maximum. */
1200 w = (u32 *)(b + mori_offset);
1201 *w = (*w & 0xffff0000) | (0x100 << n);
1202 #endif /* CONFIG_MIPS_MT_SMTC */
1203 w = (u32 *)(b + lui_offset);
1204 *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff);
1205 w = (u32 *)(b + ori_offset);
1206 *w = (*w & 0xffff0000) | ((u32)handler & 0xffff);
1207 flush_icache_range((unsigned long)b, (unsigned long)(b+handler_len));
1211 * In other cases jump directly to the interrupt handler
1213 * It is the handlers responsibility to save registers if required
1214 * (eg hi/lo) and return from the exception using "eret"
1217 *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */
1219 flush_icache_range((unsigned long)b, (unsigned long)(b+8));
1222 return (void *)old_handler;
1225 void *set_vi_handler(int n, vi_handler_t addr)
1227 return set_vi_srs_handler(n, addr, 0);
1232 static inline void mips_srs_init(void)
1236 #endif /* CONFIG_CPU_MIPSR2_SRS */
1239 * This is used by native signal handling
1241 asmlinkage int (*save_fp_context)(struct sigcontext __user *sc);
1242 asmlinkage int (*restore_fp_context)(struct sigcontext __user *sc);
1244 extern asmlinkage int _save_fp_context(struct sigcontext __user *sc);
1245 extern asmlinkage int _restore_fp_context(struct sigcontext __user *sc);
1247 extern asmlinkage int fpu_emulator_save_context(struct sigcontext __user *sc);
1248 extern asmlinkage int fpu_emulator_restore_context(struct sigcontext __user *sc);
1251 static int smp_save_fp_context(struct sigcontext __user *sc)
1253 return raw_cpu_has_fpu
1254 ? _save_fp_context(sc)
1255 : fpu_emulator_save_context(sc);
1258 static int smp_restore_fp_context(struct sigcontext __user *sc)
1260 return raw_cpu_has_fpu
1261 ? _restore_fp_context(sc)
1262 : fpu_emulator_restore_context(sc);
1266 static inline void signal_init(void)
1269 /* For now just do the cpu_has_fpu check when the functions are invoked */
1270 save_fp_context = smp_save_fp_context;
1271 restore_fp_context = smp_restore_fp_context;
1274 save_fp_context = _save_fp_context;
1275 restore_fp_context = _restore_fp_context;
1277 save_fp_context = fpu_emulator_save_context;
1278 restore_fp_context = fpu_emulator_restore_context;
1283 #ifdef CONFIG_MIPS32_COMPAT
1286 * This is used by 32-bit signal stuff on the 64-bit kernel
1288 asmlinkage int (*save_fp_context32)(struct sigcontext32 __user *sc);
1289 asmlinkage int (*restore_fp_context32)(struct sigcontext32 __user *sc);
1291 extern asmlinkage int _save_fp_context32(struct sigcontext32 __user *sc);
1292 extern asmlinkage int _restore_fp_context32(struct sigcontext32 __user *sc);
1294 extern asmlinkage int fpu_emulator_save_context32(struct sigcontext32 __user *sc);
1295 extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 __user *sc);
1297 static inline void signal32_init(void)
1300 save_fp_context32 = _save_fp_context32;
1301 restore_fp_context32 = _restore_fp_context32;
1303 save_fp_context32 = fpu_emulator_save_context32;
1304 restore_fp_context32 = fpu_emulator_restore_context32;
1309 extern void cpu_cache_init(void);
1310 extern void tlb_init(void);
1311 extern void flush_tlb_handlers(void);
1313 void __init per_cpu_trap_init(void)
1315 unsigned int cpu = smp_processor_id();
1316 unsigned int status_set = ST0_CU0;
1317 #ifdef CONFIG_MIPS_MT_SMTC
1318 int secondaryTC = 0;
1319 int bootTC = (cpu == 0);
1322 * Only do per_cpu_trap_init() for first TC of Each VPE.
1323 * Note that this hack assumes that the SMTC init code
1324 * assigns TCs consecutively and in ascending order.
1327 if (((read_c0_tcbind() & TCBIND_CURTC) != 0) &&
1328 ((read_c0_tcbind() & TCBIND_CURVPE) == cpu_data[cpu - 1].vpe_id))
1330 #endif /* CONFIG_MIPS_MT_SMTC */
1333 * Disable coprocessors and select 32-bit or 64-bit addressing
1334 * and the 16/32 or 32/32 FPR register model. Reset the BEV
1335 * flag that some firmware may have left set and the TS bit (for
1336 * IP27). Set XX for ISA IV code to work.
1339 status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
1341 if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
1342 status_set |= ST0_XX;
1343 change_c0_status(ST0_CU|ST0_MX|ST0_RE|ST0_FR|ST0_BEV|ST0_TS|ST0_KX|ST0_SX|ST0_UX,
1347 set_c0_status(ST0_MX);
1349 #ifdef CONFIG_CPU_MIPSR2
1350 if (cpu_has_mips_r2) {
1351 unsigned int enable = 0x0000000f;
1353 if (cpu_has_userlocal)
1354 enable |= (1 << 29);
1356 write_c0_hwrena(enable);
1360 #ifdef CONFIG_MIPS_MT_SMTC
1362 #endif /* CONFIG_MIPS_MT_SMTC */
1364 if (cpu_has_veic || cpu_has_vint) {
1365 write_c0_ebase (ebase);
1366 /* Setting vector spacing enables EI/VI mode */
1367 change_c0_intctl (0x3e0, VECTORSPACING);
1369 if (cpu_has_divec) {
1370 if (cpu_has_mipsmt) {
1371 unsigned int vpflags = dvpe();
1372 set_c0_cause(CAUSEF_IV);
1375 set_c0_cause(CAUSEF_IV);
1379 * Before R2 both interrupt numbers were fixed to 7, so on R2 only:
1381 * o read IntCtl.IPTI to determine the timer interrupt
1382 * o read IntCtl.IPPCI to determine the performance counter interrupt
1384 if (cpu_has_mips_r2) {
1385 cp0_compare_irq = (read_c0_intctl () >> 29) & 7;
1386 cp0_perfcount_irq = (read_c0_intctl () >> 26) & 7;
1387 if (cp0_perfcount_irq == cp0_compare_irq)
1388 cp0_perfcount_irq = -1;
1390 cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
1391 cp0_perfcount_irq = -1;
1394 #ifdef CONFIG_MIPS_MT_SMTC
1396 #endif /* CONFIG_MIPS_MT_SMTC */
1398 cpu_data[cpu].asid_cache = ASID_FIRST_VERSION;
1399 TLBMISS_HANDLER_SETUP();
1401 atomic_inc(&init_mm.mm_count);
1402 current->active_mm = &init_mm;
1403 BUG_ON(current->mm);
1404 enter_lazy_tlb(&init_mm, current);
1406 #ifdef CONFIG_MIPS_MT_SMTC
1408 #endif /* CONFIG_MIPS_MT_SMTC */
1411 #ifdef CONFIG_MIPS_MT_SMTC
1412 } else if (!secondaryTC) {
1414 * First TC in non-boot VPE must do subset of tlb_init()
1415 * for MMU countrol registers.
1417 write_c0_pagemask(PM_DEFAULT_MASK);
1420 #endif /* CONFIG_MIPS_MT_SMTC */
1423 /* Install CPU exception handler */
1424 void __init set_handler (unsigned long offset, void *addr, unsigned long size)
1426 memcpy((void *)(ebase + offset), addr, size);
1427 flush_icache_range(ebase + offset, ebase + offset + size);
1430 /* Install uncached CPU exception handler */
1431 void __init set_uncached_handler (unsigned long offset, void *addr, unsigned long size)
1434 unsigned long uncached_ebase = KSEG1ADDR(ebase);
1437 unsigned long uncached_ebase = TO_UNCAC(ebase);
1440 memcpy((void *)(uncached_ebase + offset), addr, size);
1443 static int __initdata rdhwr_noopt;
1444 static int __init set_rdhwr_noopt(char *str)
1450 __setup("rdhwr_noopt", set_rdhwr_noopt);
1452 void __init trap_init(void)
1454 extern char except_vec3_generic, except_vec3_r4000;
1455 extern char except_vec4;
1458 if (cpu_has_veic || cpu_has_vint)
1459 ebase = (unsigned long) alloc_bootmem_low_pages (0x200 + VECTORSPACING*64);
1465 per_cpu_trap_init();
1468 * Copy the generic exception handlers to their final destination.
1469 * This will be overriden later as suitable for a particular
1472 set_handler(0x180, &except_vec3_generic, 0x80);
1475 * Setup default vectors
1477 for (i = 0; i <= 31; i++)
1478 set_except_vector(i, handle_reserved);
1481 * Copy the EJTAG debug exception vector handler code to it's final
1484 if (cpu_has_ejtag && board_ejtag_handler_setup)
1485 board_ejtag_handler_setup ();
1488 * Only some CPUs have the watch exceptions.
1491 set_except_vector(23, handle_watch);
1494 * Initialise interrupt handlers
1496 if (cpu_has_veic || cpu_has_vint) {
1497 int nvec = cpu_has_veic ? 64 : 8;
1498 for (i = 0; i < nvec; i++)
1499 set_vi_handler(i, NULL);
1501 else if (cpu_has_divec)
1502 set_handler(0x200, &except_vec4, 0x8);
1505 * Some CPUs can enable/disable for cache parity detection, but does
1506 * it different ways.
1508 parity_protection_init();
1511 * The Data Bus Errors / Instruction Bus Errors are signaled
1512 * by external hardware. Therefore these two exceptions
1513 * may have board specific handlers.
1518 set_except_vector(0, handle_int);
1519 set_except_vector(1, handle_tlbm);
1520 set_except_vector(2, handle_tlbl);
1521 set_except_vector(3, handle_tlbs);
1523 set_except_vector(4, handle_adel);
1524 set_except_vector(5, handle_ades);
1526 set_except_vector(6, handle_ibe);
1527 set_except_vector(7, handle_dbe);
1529 set_except_vector(8, handle_sys);
1530 set_except_vector(9, handle_bp);
1531 set_except_vector(10, rdhwr_noopt ? handle_ri :
1532 (cpu_has_vtag_icache ?
1533 handle_ri_rdhwr_vivt : handle_ri_rdhwr));
1534 set_except_vector(11, handle_cpu);
1535 set_except_vector(12, handle_ov);
1536 set_except_vector(13, handle_tr);
1538 if (current_cpu_data.cputype == CPU_R6000 ||
1539 current_cpu_data.cputype == CPU_R6000A) {
1541 * The R6000 is the only R-series CPU that features a machine
1542 * check exception (similar to the R4000 cache error) and
1543 * unaligned ldc1/sdc1 exception. The handlers have not been
1544 * written yet. Well, anyway there is no R6000 machine on the
1545 * current list of targets for Linux/MIPS.
1546 * (Duh, crap, there is someone with a triple R6k machine)
1548 //set_except_vector(14, handle_mc);
1549 //set_except_vector(15, handle_ndc);
1553 if (board_nmi_handler_setup)
1554 board_nmi_handler_setup();
1556 if (cpu_has_fpu && !cpu_has_nofpuex)
1557 set_except_vector(15, handle_fpe);
1559 set_except_vector(22, handle_mdmx);
1562 set_except_vector(24, handle_mcheck);
1565 set_except_vector(25, handle_mt);
1567 set_except_vector(26, handle_dsp);
1570 /* Special exception: R4[04]00 uses also the divec space. */
1571 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_r4000, 0x100);
1572 else if (cpu_has_4kex)
1573 memcpy((void *)(CAC_BASE + 0x180), &except_vec3_generic, 0x80);
1575 memcpy((void *)(CAC_BASE + 0x080), &except_vec3_generic, 0x80);
1578 #ifdef CONFIG_MIPS32_COMPAT
1582 flush_icache_range(ebase, ebase + 0x400);
1583 flush_tlb_handlers();