1 /* sun4v_tlb_miss.S: Sun4v TLB miss handlers.
3 * Copyright (C) 2006 <davem@davemloft.net>
9 /* Load ITLB fault information into VADDR and CTX, using BASE. */
10 #define LOAD_ITLB_INFO(BASE, VADDR, CTX) \
11 ldx [BASE + HV_FAULT_I_ADDR_OFFSET], VADDR; \
12 ldx [BASE + HV_FAULT_I_CTX_OFFSET], CTX;
14 /* Load DTLB fault information into VADDR and CTX, using BASE. */
15 #define LOAD_DTLB_INFO(BASE, VADDR, CTX) \
16 ldx [BASE + HV_FAULT_D_ADDR_OFFSET], VADDR; \
17 ldx [BASE + HV_FAULT_D_CTX_OFFSET], CTX;
19 /* DEST = (VADDR >> 22)
21 * Branch to ZERO_CTX_LABEL if context is zero.
23 #define COMPUTE_TAG_TARGET(DEST, VADDR, CTX, ZERO_CTX_LABEL) \
24 srlx VADDR, 22, DEST; \
25 brz,pn CTX, ZERO_CTX_LABEL; \
28 /* Create TSB pointer. This is something like:
30 * index_mask = (512 << (tsb_reg & 0x7UL)) - 1UL;
31 * tsb_base = tsb_reg & ~0x7UL;
32 * tsb_index = ((vaddr >> HASH_SHIFT) & tsb_mask);
33 * tsb_ptr = tsb_base + (tsb_index * 16);
35 #define COMPUTE_TSB_PTR(TSB_PTR, VADDR, HASH_SHIFT, TMP1, TMP2) \
36 and TSB_PTR, 0x7, TMP1; \
38 andn TSB_PTR, 0x7, TSB_PTR; \
39 sllx TMP2, TMP1, TMP2; \
40 srlx VADDR, HASH_SHIFT, TMP1; \
42 and TMP1, TMP2, TMP1; \
44 add TSB_PTR, TMP1, TSB_PTR;
47 /* Load MMU Miss base into %g2. */
48 ldxa [%g0] ASI_SCRATCHPAD, %g2
50 /* Load UTSB reg into %g1. */
51 mov SCRATCHPAD_UTSBREG1, %g1
52 ldxa [%g1] ASI_SCRATCHPAD, %g1
54 LOAD_ITLB_INFO(%g2, %g4, %g5)
55 COMPUTE_TAG_TARGET(%g6, %g4, %g5, kvmap_itlb_4v)
56 COMPUTE_TSB_PTR(%g1, %g4, PAGE_SHIFT, %g3, %g7)
58 /* Load TSB tag/pte into %g2/%g3 and compare the tag. */
59 ldda [%g1] ASI_QUAD_LDD_PHYS_4V, %g2
61 bne,a,pn %xcc, tsb_miss_page_table_walk
62 mov FAULT_CODE_ITLB, %g3
63 andcc %g3, _PAGE_EXEC_4V, %g0
64 be,a,pn %xcc, tsb_do_fault
65 mov FAULT_CODE_ITLB, %g3
67 /* We have a valid entry, make hypervisor call to load
68 * I-TLB and return from trap.
74 ldxa [%g0] ASI_SCRATCHPAD, %g6
75 mov %o0, %g1 ! save %o0
76 mov %o1, %g2 ! save %o1
77 mov %o2, %g5 ! save %o2
78 mov %o3, %g7 ! save %o3
80 ldx [%g6 + HV_FAULT_I_CTX_OFFSET], %o1 ! ctx
82 mov HV_MMU_IMMU, %o3 ! flags
83 ta HV_MMU_MAP_ADDR_TRAP
84 brnz,pn %o0, sun4v_itlb_error
85 mov %g2, %o1 ! restore %o1
86 mov %g1, %o0 ! restore %o0
87 mov %g5, %o2 ! restore %o2
88 mov %g7, %o3 ! restore %o3
93 /* Load MMU Miss base into %g2. */
94 ldxa [%g0] ASI_SCRATCHPAD, %g2
96 /* Load UTSB reg into %g1. */
97 mov SCRATCHPAD_UTSBREG1, %g1
98 ldxa [%g1] ASI_SCRATCHPAD, %g1
100 LOAD_DTLB_INFO(%g2, %g4, %g5)
101 COMPUTE_TAG_TARGET(%g6, %g4, %g5, kvmap_dtlb_4v)
102 COMPUTE_TSB_PTR(%g1, %g4, PAGE_SHIFT, %g3, %g7)
104 /* Load TSB tag/pte into %g2/%g3 and compare the tag. */
105 ldda [%g1] ASI_QUAD_LDD_PHYS_4V, %g2
107 bne,a,pn %xcc, tsb_miss_page_table_walk
108 mov FAULT_CODE_DTLB, %g3
110 /* We have a valid entry, make hypervisor call to load
111 * D-TLB and return from trap.
117 ldxa [%g0] ASI_SCRATCHPAD, %g6
118 mov %o0, %g1 ! save %o0
119 mov %o1, %g2 ! save %o1
120 mov %o2, %g5 ! save %o2
121 mov %o3, %g7 ! save %o3
123 ldx [%g6 + HV_FAULT_D_CTX_OFFSET], %o1 ! ctx
125 mov HV_MMU_DMMU, %o3 ! flags
126 ta HV_MMU_MAP_ADDR_TRAP
127 brnz,pn %o0, sun4v_dtlb_error
128 mov %g2, %o1 ! restore %o1
129 mov %g1, %o0 ! restore %o0
130 mov %g5, %o2 ! restore %o2
131 mov %g7, %o3 ! restore %o3
138 /* Load MMU Miss base into %g5. */
139 ldxa [%g0] ASI_SCRATCHPAD, %g5
141 ldx [%g5 + HV_FAULT_D_ADDR_OFFSET], %g5
144 bgu,pn %xcc, winfix_trampoline
145 mov FAULT_CODE_DTLB | FAULT_CODE_WRITE, %g4
146 ba,pt %xcc, sparc64_realfault_common
149 /* Called from trap table:
155 mov SCRATCHPAD_UTSBREG1, %g1
156 ldxa [%g1] ASI_SCRATCHPAD, %g1
157 brz,pn %g5, kvmap_itlb_4v
158 mov FAULT_CODE_ITLB, %g3
159 ba,a,pt %xcc, sun4v_tsb_miss_common
161 /* Called from trap table:
167 mov SCRATCHPAD_UTSBREG1, %g1
168 ldxa [%g1] ASI_SCRATCHPAD, %g1
169 brz,pn %g5, kvmap_dtlb_4v
170 mov FAULT_CODE_DTLB, %g3
174 sun4v_tsb_miss_common:
175 COMPUTE_TSB_PTR(%g1, %g4, PAGE_SHIFT, %g5, %g7)
177 sub %g2, TRAP_PER_CPU_FAULT_INFO, %g2
179 #ifdef CONFIG_HUGETLB_PAGE
180 mov SCRATCHPAD_UTSBREG2, %g5
181 ldxa [%g5] ASI_SCRATCHPAD, %g5
185 COMPUTE_TSB_PTR(%g5, %g4, HPAGE_SHIFT, %g2, %g7)
187 /* That clobbered %g2, reload it. */
188 ldxa [%g0] ASI_SCRATCHPAD, %g2
189 sub %g2, TRAP_PER_CPU_FAULT_INFO, %g2
191 80: stx %g5, [%g2 + TRAP_PER_CPU_TSB_HUGE_TEMP]
194 ba,pt %xcc, tsb_miss_page_table_walk_sun4v_fastpath
195 ldx [%g2 + TRAP_PER_CPU_PGD_PADDR], %g7
198 sethi %hi(sun4v_err_itlb_vaddr), %g1
199 stx %g4, [%g1 + %lo(sun4v_err_itlb_vaddr)]
200 sethi %hi(sun4v_err_itlb_ctx), %g1
201 ldxa [%g0] ASI_SCRATCHPAD, %g6
202 ldx [%g6 + HV_FAULT_I_CTX_OFFSET], %o1
203 stx %o1, [%g1 + %lo(sun4v_err_itlb_ctx)]
204 sethi %hi(sun4v_err_itlb_pte), %g1
205 stx %g3, [%g1 + %lo(sun4v_err_itlb_pte)]
206 sethi %hi(sun4v_err_itlb_error), %g1
207 stx %o0, [%g1 + %lo(sun4v_err_itlb_error)]
217 2: or %g7, %lo(2b), %g7
219 call sun4v_itlb_error_report
220 add %sp, PTREGS_OFF, %o0
225 sethi %hi(sun4v_err_dtlb_vaddr), %g1
226 stx %g4, [%g1 + %lo(sun4v_err_dtlb_vaddr)]
227 sethi %hi(sun4v_err_dtlb_ctx), %g1
228 ldxa [%g0] ASI_SCRATCHPAD, %g6
229 ldx [%g6 + HV_FAULT_D_CTX_OFFSET], %o1
230 stx %o1, [%g1 + %lo(sun4v_err_dtlb_ctx)]
231 sethi %hi(sun4v_err_dtlb_pte), %g1
232 stx %g3, [%g1 + %lo(sun4v_err_dtlb_pte)]
233 sethi %hi(sun4v_err_dtlb_error), %g1
234 stx %o0, [%g1 + %lo(sun4v_err_dtlb_error)]
244 2: or %g7, %lo(2b), %g7
246 call sun4v_dtlb_error_report
247 add %sp, PTREGS_OFF, %o0
251 /* Instruction Access Exception, tl0. */
253 ldxa [%g0] ASI_SCRATCHPAD, %g2
254 ldx [%g2 + HV_FAULT_I_TYPE_OFFSET], %g3
255 ldx [%g2 + HV_FAULT_I_ADDR_OFFSET], %g4
256 ldx [%g2 + HV_FAULT_I_CTX_OFFSET], %g5
263 call sun4v_insn_access_exception
264 add %sp, PTREGS_OFF, %o0
265 ba,a,pt %xcc, rtrap_clr_l6
267 /* Instruction Access Exception, tl1. */
269 ldxa [%g0] ASI_SCRATCHPAD, %g2
270 ldx [%g2 + HV_FAULT_I_TYPE_OFFSET], %g3
271 ldx [%g2 + HV_FAULT_I_ADDR_OFFSET], %g4
272 ldx [%g2 + HV_FAULT_I_CTX_OFFSET], %g5
279 call sun4v_insn_access_exception_tl1
280 add %sp, PTREGS_OFF, %o0
281 ba,a,pt %xcc, rtrap_clr_l6
283 /* Data Access Exception, tl0. */
285 ldxa [%g0] ASI_SCRATCHPAD, %g2
286 ldx [%g2 + HV_FAULT_D_TYPE_OFFSET], %g3
287 ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g4
288 ldx [%g2 + HV_FAULT_D_CTX_OFFSET], %g5
295 call sun4v_data_access_exception
296 add %sp, PTREGS_OFF, %o0
297 ba,a,pt %xcc, rtrap_clr_l6
299 /* Data Access Exception, tl1. */
301 ldxa [%g0] ASI_SCRATCHPAD, %g2
302 ldx [%g2 + HV_FAULT_D_TYPE_OFFSET], %g3
303 ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g4
304 ldx [%g2 + HV_FAULT_D_CTX_OFFSET], %g5
311 call sun4v_data_access_exception_tl1
312 add %sp, PTREGS_OFF, %o0
313 ba,a,pt %xcc, rtrap_clr_l6
315 /* Memory Address Unaligned. */
324 ldxa [%g0] ASI_SCRATCHPAD, %g2
325 ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g5
326 mov HV_FAULT_TYPE_UNALIGNED, %g3
327 ldx [%g2 + HV_FAULT_D_CTX_OFFSET], %g4
330 ba,pt %xcc, winfix_mna
334 1: ldxa [%g0] ASI_SCRATCHPAD, %g2
335 mov HV_FAULT_TYPE_UNALIGNED, %g3
336 ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g4
337 ldx [%g2 + HV_FAULT_D_CTX_OFFSET], %g5
346 add %sp, PTREGS_OFF, %o0
347 ba,a,pt %xcc, rtrap_clr_l6
349 /* Privileged Action. */
354 add %sp, PTREGS_OFF, %o0
355 ba,a,pt %xcc, rtrap_clr_l6
357 /* Unaligned ldd float, tl0. */
359 ldxa [%g0] ASI_SCRATCHPAD, %g2
360 ldx [%g2 + HV_FAULT_D_TYPE_OFFSET], %g3
361 ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g4
362 ldx [%g2 + HV_FAULT_D_CTX_OFFSET], %g5
370 add %sp, PTREGS_OFF, %o0
371 ba,a,pt %xcc, rtrap_clr_l6
373 /* Unaligned std float, tl0. */
375 ldxa [%g0] ASI_SCRATCHPAD, %g2
376 ldx [%g2 + HV_FAULT_D_TYPE_OFFSET], %g3
377 ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g4
378 ldx [%g2 + HV_FAULT_D_CTX_OFFSET], %g5
386 add %sp, PTREGS_OFF, %o0
387 ba,a,pt %xcc, rtrap_clr_l6
389 #define BRANCH_ALWAYS 0x10680000
390 #define NOP 0x01000000
391 #define SUN4V_DO_PATCH(OLD, NEW) \
392 sethi %hi(NEW), %g1; \
393 or %g1, %lo(NEW), %g1; \
394 sethi %hi(OLD), %g2; \
395 or %g2, %lo(OLD), %g2; \
397 sethi %hi(BRANCH_ALWAYS), %g3; \
399 srl %g1, 11 + 2, %g1; \
400 or %g3, %lo(BRANCH_ALWAYS), %g3; \
403 sethi %hi(NOP), %g3; \
404 or %g3, %lo(NOP), %g3; \
405 stw %g3, [%g2 + 0x4]; \
408 .globl sun4v_patch_tlb_handlers
409 .type sun4v_patch_tlb_handlers,#function
410 sun4v_patch_tlb_handlers:
411 SUN4V_DO_PATCH(tl0_iamiss, sun4v_itlb_miss)
412 SUN4V_DO_PATCH(tl1_iamiss, sun4v_itlb_miss)
413 SUN4V_DO_PATCH(tl0_damiss, sun4v_dtlb_miss)
414 SUN4V_DO_PATCH(tl1_damiss, sun4v_dtlb_miss)
415 SUN4V_DO_PATCH(tl0_daprot, sun4v_dtlb_prot)
416 SUN4V_DO_PATCH(tl1_daprot, sun4v_dtlb_prot)
417 SUN4V_DO_PATCH(tl0_iax, sun4v_iacc)
418 SUN4V_DO_PATCH(tl1_iax, sun4v_iacc_tl1)
419 SUN4V_DO_PATCH(tl0_dax, sun4v_dacc)
420 SUN4V_DO_PATCH(tl1_dax, sun4v_dacc_tl1)
421 SUN4V_DO_PATCH(tl0_mna, sun4v_mna)
422 SUN4V_DO_PATCH(tl1_mna, sun4v_mna)
423 SUN4V_DO_PATCH(tl0_lddfmna, sun4v_lddfmna)
424 SUN4V_DO_PATCH(tl0_stdfmna, sun4v_stdfmna)
425 SUN4V_DO_PATCH(tl0_privact, sun4v_privact)
428 .size sun4v_patch_tlb_handlers,.-sun4v_patch_tlb_handlers