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   1 /*
   2  * MPC8544 DS Device Tree Source
   3  *
   4  * Copyright 2007 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 / {
  13         model = "MPC8544DS";
  14         compatible = "MPC8544DS", "MPC85xxDS";
  15         #address-cells = <1>;
  16         #size-cells = <1>;
  17
  18         cpus {
  19                 #cpus = <1>;
  20                 #address-cells = <1>;
  21                 #size-cells = <0>;
  22
  23                 PowerPC,8544@0 {
  24                         device_type = "cpu";
  25                         reg = <0>;
  26                         d-cache-line-size = <20>;       // 32 bytes
  27                         i-cache-line-size = <20>;       // 32 bytes
  28                         d-cache-size = <8000>;          // L1, 32K
  29                         i-cache-size = <8000>;          // L1, 32K
  30                         timebase-frequency = <0>;
  31                         bus-frequency = <0>;
  32                         clock-frequency = <0>;
  33                         32-bit;
  34                 };
  35         };
  36
  37         memory {
  38                 device_type = "memory";
  39                 reg = <00000000 00000000>;      // Filled by U-Boot
  40         };
  41
  42         soc8544@e0000000 {
  43                 #address-cells = <1>;
  44                 #size-cells = <1>;
  45                 #interrupt-cells = <2>;
  46                 device_type = "soc";
  47                 ranges = <0 e0000000 00100000>;
  48                 reg = <e0000000 00100000>;      // CCSRBAR 1M
  49                 bus-frequency = <0>;            // Filled out by uboot.
  50
  51                 memory-controller@2000 {
  52                         compatible = "fsl,8544-memory-controller";
  53                         reg = <2000 1000>;
  54                         interrupt-parent = <&mpic>;
  55                         interrupts = <12 2>;
  56                 };
  57
  58                 l2-cache-controller@20000 {
  59                         compatible = "fsl,8544-l2-cache-controller";
  60                         reg = <20000 1000>;
  61                         cache-line-size = <20>; // 32 bytes
  62                         cache-size = <40000>;   // L2, 256K
  63                         interrupt-parent = <&mpic>;
  64                         interrupts = <10 2>;
  65                 };
  66
  67                 i2c@3000 {
  68                         device_type = "i2c";
  69                         compatible = "fsl-i2c";
  70                         reg = <3000 100>;
  71                         interrupts = <2b 2>;
  72                         interrupt-parent = <&mpic>;
  73                         dfsrr;
  74                 };
  75
  76                 mdio@24520 {
  77                         #address-cells = <1>;
  78                         #size-cells = <0>;
  79                         device_type = "mdio";
  80                         compatible = "gianfar";
  81                         reg = <24520 20>;
  82                         phy0: ethernet-phy@0 {
  83                                 interrupt-parent = <&mpic>;
  84                                 interrupts = <a 1>;
  85                                 reg = <0>;
  86                                 device_type = "ethernet-phy";
  87                         };
  88                         phy1: ethernet-phy@1 {
  89                                 interrupt-parent = <&mpic>;
  90                                 interrupts = <a 1>;
  91                                 reg = <1>;
  92                                 device_type = "ethernet-phy";
  93                         };
  94                 };
  95
  96                 ethernet@24000 {
  97                         #address-cells = <1>;
  98                         #size-cells = <0>;
  99                         device_type = "network";
 100                         model = "TSEC";
 101                         compatible = "gianfar";
 102                         reg = <24000 1000>;
 103                         local-mac-address = [ 00 00 00 00 00 00 ];
 104                         interrupts = <1d 2 1e 2 22 2>;
 105                         interrupt-parent = <&mpic>;
 106                         phy-handle = <&phy0>;
 107                 };
 108
 109                 ethernet@26000 {
 110                         #address-cells = <1>;
 111                         #size-cells = <0>;
 112                         device_type = "network";
 113                         model = "TSEC";
 114                         compatible = "gianfar";
 115                         reg = <26000 1000>;
 116                         local-mac-address = [ 00 00 00 00 00 00 ];
 117                         interrupts = <1f 2 20 2 21 2>;
 118                         interrupt-parent = <&mpic>;
 119                         phy-handle = <&phy1>;
 120                 };
 121
 122                 serial@4500 {
 123                         device_type = "serial";
 124                         compatible = "ns16550";
 125                         reg = <4500 100>;
 126                         clock-frequency = <0>;
 127                         interrupts = <2a 2>;
 128                         interrupt-parent = <&mpic>;
 129                 };
 130
 131                 serial@4600 {
 132                         device_type = "serial";
 133                         compatible = "ns16550";
 134                         reg = <4600 100>;
 135                         clock-frequency = <0>;
 136                         interrupts = <2a 2>;
 137                         interrupt-parent = <&mpic>;
 138                 };
 139
 140                 mpic: pic@40000 {
 141                         clock-frequency = <0>;
 142                         interrupt-controller;
 143                         #address-cells = <0>;
 144                         #interrupt-cells = <2>;
 145                         reg = <40000 40000>;
 146                         built-in;
 147                         compatible = "chrp,open-pic";
 148                         device_type = "open-pic";
 149                         big-endian;
 150                 };
 151         };
 152 };