git.oblomov.eu Git - linux-2.6/blob - drivers/spi/pxa2xx_spi.c

   1 /*
   2  * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17  */
  18
  19 #include <linux/init.h>
  20 #include <linux/module.h>
  21 #include <linux/device.h>
  22 #include <linux/ioport.h>
  23 #include <linux/errno.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/spi/spi.h>
  28 #include <linux/workqueue.h>
  29 #include <linux/errno.h>
  30 #include <linux/delay.h>
  31
  32 #include <asm/io.h>
  33 #include <asm/irq.h>
  34 #include <asm/hardware.h>
  35 #include <asm/delay.h>
  36 #include <asm/dma.h>
  37
  38 #include <asm/arch/hardware.h>
  39 #include <asm/arch/pxa-regs.h>
  40 #include <asm/arch/pxa2xx_spi.h>
  41
  42 MODULE_AUTHOR("Stephen Street");
  43 MODULE_DESCRIPTION("PXA2xx SSP SPI Contoller");
  44 MODULE_LICENSE("GPL");
  45
  46 #define MAX_BUSES 3
  47
  48 #define DMA_INT_MASK (DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERR)
  49 #define RESET_DMA_CHANNEL (DCSR_NODESC | DMA_INT_MASK)
  50 #define IS_DMA_ALIGNED(x) (((u32)(x)&0x07)==0)
  51
  52 /* for testing SSCR1 changes that require SSP restart, basically
  53  * everything except the service and interrupt enables */
  54 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_EBCEI | SSCR1_SCFR \
  55                                 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
  56                                 | SSCR1_RWOT | SSCR1_TRAIL | SSCR1_PINTE \
  57                                 | SSCR1_STRF | SSCR1_EFWR |SSCR1_RFT \
  58                                 | SSCR1_TFT | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
  59
  60 #define DEFINE_SSP_REG(reg, off) \
  61 static inline u32 read_##reg(void *p) { return __raw_readl(p + (off)); } \
  62 static inline void write_##reg(u32 v, void *p) { __raw_writel(v, p + (off)); }
  63
  64 DEFINE_SSP_REG(SSCR0, 0x00)
  65 DEFINE_SSP_REG(SSCR1, 0x04)
  66 DEFINE_SSP_REG(SSSR, 0x08)
  67 DEFINE_SSP_REG(SSITR, 0x0c)
  68 DEFINE_SSP_REG(SSDR, 0x10)
  69 DEFINE_SSP_REG(SSTO, 0x28)
  70 DEFINE_SSP_REG(SSPSP, 0x2c)
  71
  72 #define START_STATE ((void*)0)
  73 #define RUNNING_STATE ((void*)1)
  74 #define DONE_STATE ((void*)2)
  75 #define ERROR_STATE ((void*)-1)
  76
  77 #define QUEUE_RUNNING 0
  78 #define QUEUE_STOPPED 1
  79
  80 struct driver_data {
  81         /* Driver model hookup */
  82         struct platform_device *pdev;
  83
  84         /* SPI framework hookup */
  85         enum pxa_ssp_type ssp_type;
  86         struct spi_master *master;
  87
  88         /* PXA hookup */
  89         struct pxa2xx_spi_master *master_info;
  90
  91         /* DMA setup stuff */
  92         int rx_channel;
  93         int tx_channel;
  94         u32 *null_dma_buf;
  95
  96         /* SSP register addresses */
  97         void *ioaddr;
  98         u32 ssdr_physical;
  99
 100         /* SSP masks*/
 101         u32 dma_cr1;
 102         u32 int_cr1;
 103         u32 clear_sr;
 104         u32 mask_sr;
 105
 106         /* Driver message queue */
 107         struct workqueue_struct *workqueue;
 108         struct work_struct pump_messages;
 109         spinlock_t lock;
 110         struct list_head queue;
 111         int busy;
 112         int run;
 113
 114         /* Message Transfer pump */
 115         struct tasklet_struct pump_transfers;
 116
 117         /* Current message transfer state info */
 118         struct spi_message* cur_msg;
 119         struct spi_transfer* cur_transfer;
 120         struct chip_data *cur_chip;
 121         size_t len;
 122         void *tx;
 123         void *tx_end;
 124         void *rx;
 125         void *rx_end;
 126         int dma_mapped;
 127         dma_addr_t rx_dma;
 128         dma_addr_t tx_dma;
 129         size_t rx_map_len;
 130         size_t tx_map_len;
 131         u8 n_bytes;
 132         u32 dma_width;
 133         int cs_change;
 134         int (*write)(struct driver_data *drv_data);
 135         int (*read)(struct driver_data *drv_data);
 136         irqreturn_t (*transfer_handler)(struct driver_data *drv_data);
 137         void (*cs_control)(u32 command);
 138 };
 139
 140 struct chip_data {
 141         u32 cr0;
 142         u32 cr1;
 143         u32 psp;
 144         u32 timeout;
 145         u8 n_bytes;
 146         u32 dma_width;
 147         u32 dma_burst_size;
 148         u32 threshold;
 149         u32 dma_threshold;
 150         u8 enable_dma;
 151         u8 bits_per_word;
 152         u32 speed_hz;
 153         int (*write)(struct driver_data *drv_data);
 154         int (*read)(struct driver_data *drv_data);
 155         void (*cs_control)(u32 command);
 156 };
 157
 158 static void pump_messages(struct work_struct *work);
 159
 160 static int flush(struct driver_data *drv_data)
 161 {
 162         unsigned long limit = loops_per_jiffy << 1;
 163
 164         void *reg = drv_data->ioaddr;
 165
 166         do {
 167                 while (read_SSSR(reg) & SSSR_RNE) {
 168                         read_SSDR(reg);
 169                 }
 170         } while ((read_SSSR(reg) & SSSR_BSY) && limit--);
 171         write_SSSR(SSSR_ROR, reg);
 172
 173         return limit;
 174 }
 175
 176 static void null_cs_control(u32 command)
 177 {
 178 }
 179
 180 static int null_writer(struct driver_data *drv_data)
 181 {
 182         void *reg = drv_data->ioaddr;
 183         u8 n_bytes = drv_data->n_bytes;
 184
 185         if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)
 186                 || (drv_data->tx == drv_data->tx_end))
 187                 return 0;
 188
 189         write_SSDR(0, reg);
 190         drv_data->tx += n_bytes;
 191
 192         return 1;
 193 }
 194
 195 static int null_reader(struct driver_data *drv_data)
 196 {
 197         void *reg = drv_data->ioaddr;
 198         u8 n_bytes = drv_data->n_bytes;
 199
 200         while ((read_SSSR(reg) & SSSR_RNE)
 201                 && (drv_data->rx < drv_data->rx_end)) {
 202                 read_SSDR(reg);
 203                 drv_data->rx += n_bytes;
 204         }
 205
 206         return drv_data->rx == drv_data->rx_end;
 207 }
 208
 209 static int u8_writer(struct driver_data *drv_data)
 210 {
 211         void *reg = drv_data->ioaddr;
 212
 213         if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)
 214                 || (drv_data->tx == drv_data->tx_end))
 215                 return 0;
 216
 217         write_SSDR(*(u8 *)(drv_data->tx), reg);
 218         ++drv_data->tx;
 219
 220         return 1;
 221 }
 222
 223 static int u8_reader(struct driver_data *drv_data)
 224 {
 225         void *reg = drv_data->ioaddr;
 226
 227         while ((read_SSSR(reg) & SSSR_RNE)
 228                 && (drv_data->rx < drv_data->rx_end)) {
 229                 *(u8 *)(drv_data->rx) = read_SSDR(reg);
 230                 ++drv_data->rx;
 231         }
 232
 233         return drv_data->rx == drv_data->rx_end;
 234 }
 235
 236 static int u16_writer(struct driver_data *drv_data)
 237 {
 238         void *reg = drv_data->ioaddr;
 239
 240         if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)
 241                 || (drv_data->tx == drv_data->tx_end))
 242                 return 0;
 243
 244         write_SSDR(*(u16 *)(drv_data->tx), reg);
 245         drv_data->tx += 2;
 246
 247         return 1;
 248 }
 249
 250 static int u16_reader(struct driver_data *drv_data)
 251 {
 252         void *reg = drv_data->ioaddr;
 253
 254         while ((read_SSSR(reg) & SSSR_RNE)
 255                 && (drv_data->rx < drv_data->rx_end)) {
 256                 *(u16 *)(drv_data->rx) = read_SSDR(reg);
 257                 drv_data->rx += 2;
 258         }
 259
 260         return drv_data->rx == drv_data->rx_end;
 261 }
 262
 263 static int u32_writer(struct driver_data *drv_data)
 264 {
 265         void *reg = drv_data->ioaddr;
 266
 267         if (((read_SSSR(reg) & 0x00000f00) == 0x00000f00)
 268                 || (drv_data->tx == drv_data->tx_end))
 269                 return 0;
 270
 271         write_SSDR(*(u32 *)(drv_data->tx), reg);
 272         drv_data->tx += 4;
 273
 274         return 1;
 275 }
 276
 277 static int u32_reader(struct driver_data *drv_data)
 278 {
 279         void *reg = drv_data->ioaddr;
 280
 281         while ((read_SSSR(reg) & SSSR_RNE)
 282                 && (drv_data->rx < drv_data->rx_end)) {
 283                 *(u32 *)(drv_data->rx) = read_SSDR(reg);
 284                 drv_data->rx += 4;
 285         }
 286
 287         return drv_data->rx == drv_data->rx_end;
 288 }
 289
 290 static void *next_transfer(struct driver_data *drv_data)
 291 {
 292         struct spi_message *msg = drv_data->cur_msg;
 293         struct spi_transfer *trans = drv_data->cur_transfer;
 294
 295         /* Move to next transfer */
 296         if (trans->transfer_list.next != &msg->transfers) {
 297                 drv_data->cur_transfer =
 298                         list_entry(trans->transfer_list.next,
 299                                         struct spi_transfer,
 300                                         transfer_list);
 301                 return RUNNING_STATE;
 302         } else
 303                 return DONE_STATE;
 304 }
 305
 306 static int map_dma_buffers(struct driver_data *drv_data)
 307 {
 308         struct spi_message *msg = drv_data->cur_msg;
 309         struct device *dev = &msg->spi->dev;
 310
 311         if (!drv_data->cur_chip->enable_dma)
 312                 return 0;
 313
 314         if (msg->is_dma_mapped)
 315                 return  drv_data->rx_dma && drv_data->tx_dma;
 316
 317         if (!IS_DMA_ALIGNED(drv_data->rx) || !IS_DMA_ALIGNED(drv_data->tx))
 318                 return 0;
 319
 320         /* Modify setup if rx buffer is null */
 321         if (drv_data->rx == NULL) {
 322                 *drv_data->null_dma_buf = 0;
 323                 drv_data->rx = drv_data->null_dma_buf;
 324                 drv_data->rx_map_len = 4;
 325         } else
 326                 drv_data->rx_map_len = drv_data->len;
 327
 328
 329         /* Modify setup if tx buffer is null */
 330         if (drv_data->tx == NULL) {
 331                 *drv_data->null_dma_buf = 0;
 332                 drv_data->tx = drv_data->null_dma_buf;
 333                 drv_data->tx_map_len = 4;
 334         } else
 335                 drv_data->tx_map_len = drv_data->len;
 336
 337         /* Stream map the rx buffer */
 338         drv_data->rx_dma = dma_map_single(dev, drv_data->rx,
 339                                                 drv_data->rx_map_len,
 340                                                 DMA_FROM_DEVICE);
 341         if (dma_mapping_error(drv_data->rx_dma))
 342                 return 0;
 343
 344         /* Stream map the tx buffer */
 345         drv_data->tx_dma = dma_map_single(dev, drv_data->tx,
 346                                                 drv_data->tx_map_len,
 347                                                 DMA_TO_DEVICE);
 348
 349         if (dma_mapping_error(drv_data->tx_dma)) {
 350                 dma_unmap_single(dev, drv_data->rx_dma,
 351                                         drv_data->rx_map_len, DMA_FROM_DEVICE);
 352                 return 0;
 353         }
 354
 355         return 1;
 356 }
 357
 358 static void unmap_dma_buffers(struct driver_data *drv_data)
 359 {
 360         struct device *dev;
 361
 362         if (!drv_data->dma_mapped)
 363                 return;
 364
 365         if (!drv_data->cur_msg->is_dma_mapped) {
 366                 dev = &drv_data->cur_msg->spi->dev;
 367                 dma_unmap_single(dev, drv_data->rx_dma,
 368                                         drv_data->rx_map_len, DMA_FROM_DEVICE);
 369                 dma_unmap_single(dev, drv_data->tx_dma,
 370                                         drv_data->tx_map_len, DMA_TO_DEVICE);
 371         }
 372
 373         drv_data->dma_mapped = 0;
 374 }
 375
 376 /* caller already set message->status; dma and pio irqs are blocked */
 377 static void giveback(struct driver_data *drv_data)
 378 {
 379         struct spi_transfer* last_transfer;
 380         unsigned long flags;
 381         struct spi_message *msg;
 382
 383         spin_lock_irqsave(&drv_data->lock, flags);
 384         msg = drv_data->cur_msg;
 385         drv_data->cur_msg = NULL;
 386         drv_data->cur_transfer = NULL;
 387         drv_data->cur_chip = NULL;
 388         queue_work(drv_data->workqueue, &drv_data->pump_messages);
 389         spin_unlock_irqrestore(&drv_data->lock, flags);
 390
 391         last_transfer = list_entry(msg->transfers.prev,
 392                                         struct spi_transfer,
 393                                         transfer_list);
 394
 395         if (!last_transfer->cs_change)
 396                 drv_data->cs_control(PXA2XX_CS_DEASSERT);
 397
 398         msg->state = NULL;
 399         if (msg->complete)
 400                 msg->complete(msg->context);
 401 }
 402
 403 static int wait_ssp_rx_stall(void *ioaddr)
 404 {
 405         unsigned long limit = loops_per_jiffy << 1;
 406
 407         while ((read_SSSR(ioaddr) & SSSR_BSY) && limit--)
 408                 cpu_relax();
 409
 410         return limit;
 411 }
 412
 413 static int wait_dma_channel_stop(int channel)
 414 {
 415         unsigned long limit = loops_per_jiffy << 1;
 416
 417         while (!(DCSR(channel) & DCSR_STOPSTATE) && limit--)
 418                 cpu_relax();
 419
 420         return limit;
 421 }
 422
 423 void dma_error_stop(struct driver_data *drv_data, const char *msg)
 424 {
 425         void *reg = drv_data->ioaddr;
 426
 427         /* Stop and reset */
 428         DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
 429         DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
 430         write_SSSR(drv_data->clear_sr, reg);
 431         write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
 432         if (drv_data->ssp_type != PXA25x_SSP)
 433                 write_SSTO(0, reg);
 434         flush(drv_data);
 435         write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
 436
 437         unmap_dma_buffers(drv_data);
 438
 439         dev_err(&drv_data->pdev->dev, "%s\n", msg);
 440
 441         drv_data->cur_msg->state = ERROR_STATE;
 442         tasklet_schedule(&drv_data->pump_transfers);
 443 }
 444
 445 static void dma_transfer_complete(struct driver_data *drv_data)
 446 {
 447         void *reg = drv_data->ioaddr;
 448         struct spi_message *msg = drv_data->cur_msg;
 449
 450         /* Clear and disable interrupts on SSP and DMA channels*/
 451         write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
 452         write_SSSR(drv_data->clear_sr, reg);
 453         DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
 454         DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
 455
 456         if (wait_dma_channel_stop(drv_data->rx_channel) == 0)
 457                 dev_err(&drv_data->pdev->dev,
 458                         "dma_handler: dma rx channel stop failed\n");
 459
 460         if (wait_ssp_rx_stall(drv_data->ioaddr) == 0)
 461                 dev_err(&drv_data->pdev->dev,
 462                         "dma_transfer: ssp rx stall failed\n");
 463
 464         unmap_dma_buffers(drv_data);
 465
 466         /* update the buffer pointer for the amount completed in dma */
 467         drv_data->rx += drv_data->len -
 468                         (DCMD(drv_data->rx_channel) & DCMD_LENGTH);
 469
 470         /* read trailing data from fifo, it does not matter how many
 471          * bytes are in the fifo just read until buffer is full
 472          * or fifo is empty, which ever occurs first */
 473         drv_data->read(drv_data);
 474
 475         /* return count of what was actually read */
 476         msg->actual_length += drv_data->len -
 477                                 (drv_data->rx_end - drv_data->rx);
 478
 479         /* Release chip select if requested, transfer delays are
 480          * handled in pump_transfers */
 481         if (drv_data->cs_change)
 482                 drv_data->cs_control(PXA2XX_CS_DEASSERT);
 483
 484         /* Move to next transfer */
 485         msg->state = next_transfer(drv_data);
 486
 487         /* Schedule transfer tasklet */
 488         tasklet_schedule(&drv_data->pump_transfers);
 489 }
 490
 491 static void dma_handler(int channel, void *data)
 492 {
 493         struct driver_data *drv_data = data;
 494         u32 irq_status = DCSR(channel) & DMA_INT_MASK;
 495
 496         if (irq_status & DCSR_BUSERR) {
 497
 498                 if (channel == drv_data->tx_channel)
 499                         dma_error_stop(drv_data,
 500                                         "dma_handler: "
 501                                         "bad bus address on tx channel");
 502                 else
 503                         dma_error_stop(drv_data,
 504                                         "dma_handler: "
 505                                         "bad bus address on rx channel");
 506                 return;
 507         }
 508
 509         /* PXA255x_SSP has no timeout interrupt, wait for tailing bytes */
 510         if ((channel == drv_data->tx_channel)
 511                 && (irq_status & DCSR_ENDINTR)
 512                 && (drv_data->ssp_type == PXA25x_SSP)) {
 513
 514                 /* Wait for rx to stall */
 515                 if (wait_ssp_rx_stall(drv_data->ioaddr) == 0)
 516                         dev_err(&drv_data->pdev->dev,
 517                                 "dma_handler: ssp rx stall failed\n");
 518
 519                 /* finish this transfer, start the next */
 520                 dma_transfer_complete(drv_data);
 521         }
 522 }
 523
 524 static irqreturn_t dma_transfer(struct driver_data *drv_data)
 525 {
 526         u32 irq_status;
 527         void *reg = drv_data->ioaddr;
 528
 529         irq_status = read_SSSR(reg) & drv_data->mask_sr;
 530         if (irq_status & SSSR_ROR) {
 531                 dma_error_stop(drv_data, "dma_transfer: fifo overrun");
 532                 return IRQ_HANDLED;
 533         }
 534
 535         /* Check for false positive timeout */
 536         if ((irq_status & SSSR_TINT)
 537                 && (DCSR(drv_data->tx_channel) & DCSR_RUN)) {
 538                 write_SSSR(SSSR_TINT, reg);
 539                 return IRQ_HANDLED;
 540         }
 541
 542         if (irq_status & SSSR_TINT || drv_data->rx == drv_data->rx_end) {
 543
 544                 /* Clear and disable timeout interrupt, do the rest in
 545                  * dma_transfer_complete */
 546                 if (drv_data->ssp_type != PXA25x_SSP)
 547                         write_SSTO(0, reg);
 548
 549                 /* finish this transfer, start the next */
 550                 dma_transfer_complete(drv_data);
 551
 552                 return IRQ_HANDLED;
 553         }
 554
 555         /* Opps problem detected */
 556         return IRQ_NONE;
 557 }
 558
 559 static void int_error_stop(struct driver_data *drv_data, const char* msg)
 560 {
 561         void *reg = drv_data->ioaddr;
 562
 563         /* Stop and reset SSP */
 564         write_SSSR(drv_data->clear_sr, reg);
 565         write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
 566         if (drv_data->ssp_type != PXA25x_SSP)
 567                 write_SSTO(0, reg);
 568         flush(drv_data);
 569         write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
 570
 571         dev_err(&drv_data->pdev->dev, "%s\n", msg);
 572
 573         drv_data->cur_msg->state = ERROR_STATE;
 574         tasklet_schedule(&drv_data->pump_transfers);
 575 }
 576
 577 static void int_transfer_complete(struct driver_data *drv_data)
 578 {
 579         void *reg = drv_data->ioaddr;
 580
 581         /* Stop SSP */
 582         write_SSSR(drv_data->clear_sr, reg);
 583         write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
 584         if (drv_data->ssp_type != PXA25x_SSP)
 585                 write_SSTO(0, reg);
 586
 587         /* Update total byte transfered return count actual bytes read */
 588         drv_data->cur_msg->actual_length += drv_data->len -
 589                                 (drv_data->rx_end - drv_data->rx);
 590
 591         /* Release chip select if requested, transfer delays are
 592          * handled in pump_transfers */
 593         if (drv_data->cs_change)
 594                 drv_data->cs_control(PXA2XX_CS_DEASSERT);
 595
 596         /* Move to next transfer */
 597         drv_data->cur_msg->state = next_transfer(drv_data);
 598
 599         /* Schedule transfer tasklet */
 600         tasklet_schedule(&drv_data->pump_transfers);
 601 }
 602
 603 static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
 604 {
 605         void *reg = drv_data->ioaddr;
 606
 607         u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ?
 608                         drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
 609
 610         u32 irq_status = read_SSSR(reg) & irq_mask;
 611
 612         if (irq_status & SSSR_ROR) {
 613                 int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
 614                 return IRQ_HANDLED;
 615         }
 616
 617         if (irq_status & SSSR_TINT) {
 618                 write_SSSR(SSSR_TINT, reg);
 619                 if (drv_data->read(drv_data)) {
 620                         int_transfer_complete(drv_data);
 621                         return IRQ_HANDLED;
 622                 }
 623         }
 624
 625         /* Drain rx fifo, Fill tx fifo and prevent overruns */
 626         do {
 627                 if (drv_data->read(drv_data)) {
 628                         int_transfer_complete(drv_data);
 629                         return IRQ_HANDLED;
 630                 }
 631         } while (drv_data->write(drv_data));
 632
 633         if (drv_data->read(drv_data)) {
 634                 int_transfer_complete(drv_data);
 635                 return IRQ_HANDLED;
 636         }
 637
 638         if (drv_data->tx == drv_data->tx_end) {
 639                 write_SSCR1(read_SSCR1(reg) & ~SSCR1_TIE, reg);
 640                 /* PXA25x_SSP has no timeout, read trailing bytes */
 641                 if (drv_data->ssp_type == PXA25x_SSP) {
 642                         if (!wait_ssp_rx_stall(reg))
 643                         {
 644                                 int_error_stop(drv_data, "interrupt_transfer: "
 645                                                 "rx stall failed");
 646                                 return IRQ_HANDLED;
 647                         }
 648                         if (!drv_data->read(drv_data))
 649                         {
 650                                 int_error_stop(drv_data,
 651                                                 "interrupt_transfer: "
 652                                                 "trailing byte read failed");
 653                                 return IRQ_HANDLED;
 654                         }
 655                         int_transfer_complete(drv_data);
 656                 }
 657         }
 658
 659         /* We did something */
 660         return IRQ_HANDLED;
 661 }
 662
 663 static irqreturn_t ssp_int(int irq, void *dev_id)
 664 {
 665         struct driver_data *drv_data = dev_id;
 666         void *reg = drv_data->ioaddr;
 667
 668         if (!drv_data->cur_msg) {
 669
 670                 write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
 671                 write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
 672                 if (drv_data->ssp_type != PXA25x_SSP)
 673                         write_SSTO(0, reg);
 674                 write_SSSR(drv_data->clear_sr, reg);
 675
 676                 dev_err(&drv_data->pdev->dev, "bad message state "
 677                         "in interrupt handler\n");
 678
 679                 /* Never fail */
 680                 return IRQ_HANDLED;
 681         }
 682
 683         return drv_data->transfer_handler(drv_data);
 684 }
 685
 686 int set_dma_burst_and_threshold(struct chip_data *chip, struct spi_device *spi,
 687                                 u8 bits_per_word, u32 *burst_code,
 688                                 u32 *threshold)
 689 {
 690         struct pxa2xx_spi_chip *chip_info =
 691                         (struct pxa2xx_spi_chip *)spi->controller_data;
 692         int bytes_per_word;
 693         int burst_bytes;
 694         int thresh_words;
 695         int req_burst_size;
 696         int retval = 0;
 697
 698         /* Set the threshold (in registers) to equal the same amount of data
 699          * as represented by burst size (in bytes).  The computation below
 700          * is (burst_size rounded up to nearest 8 byte, word or long word)
 701          * divided by (bytes/register); the tx threshold is the inverse of
 702          * the rx, so that there will always be enough data in the rx fifo
 703          * to satisfy a burst, and there will always be enough space in the
 704          * tx fifo to accept a burst (a tx burst will overwrite the fifo if
 705          * there is not enough space), there must always remain enough empty
 706          * space in the rx fifo for any data loaded to the tx fifo.
 707          * Whenever burst_size (in bytes) equals bits/word, the fifo threshold
 708          * will be 8, or half the fifo;
 709          * The threshold can only be set to 2, 4 or 8, but not 16, because
 710          * to burst 16 to the tx fifo, the fifo would have to be empty;
 711          * however, the minimum fifo trigger level is 1, and the tx will
 712          * request service when the fifo is at this level, with only 15 spaces.
 713          */
 714
 715         /* find bytes/word */
 716         if (bits_per_word <= 8)
 717                 bytes_per_word = 1;
 718         else if (bits_per_word <= 16)
 719                 bytes_per_word = 2;
 720         else
 721                 bytes_per_word = 4;
 722
 723         /* use struct pxa2xx_spi_chip->dma_burst_size if available */
 724         if (chip_info)
 725                 req_burst_size = chip_info->dma_burst_size;
 726         else {
 727                 switch (chip->dma_burst_size) {
 728                 default:
 729                         /* if the default burst size is not set,
 730                          * do it now */
 731                         chip->dma_burst_size = DCMD_BURST8;
 732                 case DCMD_BURST8:
 733                         req_burst_size = 8;
 734                         break;
 735                 case DCMD_BURST16:
 736                         req_burst_size = 16;
 737                         break;
 738                 case DCMD_BURST32:
 739                         req_burst_size = 32;
 740                         break;
 741                 }
 742         }
 743         if (req_burst_size <= 8) {
 744                 *burst_code = DCMD_BURST8;
 745                 burst_bytes = 8;
 746         } else if (req_burst_size <= 16) {
 747                 if (bytes_per_word == 1) {
 748                         /* don't burst more than 1/2 the fifo */
 749                         *burst_code = DCMD_BURST8;
 750                         burst_bytes = 8;
 751                         retval = 1;
 752                 } else {
 753                         *burst_code = DCMD_BURST16;
 754                         burst_bytes = 16;
 755                 }
 756         } else {
 757                 if (bytes_per_word == 1) {
 758                         /* don't burst more than 1/2 the fifo */
 759                         *burst_code = DCMD_BURST8;
 760                         burst_bytes = 8;
 761                         retval = 1;
 762                 } else if (bytes_per_word == 2) {
 763                         /* don't burst more than 1/2 the fifo */
 764                         *burst_code = DCMD_BURST16;
 765                         burst_bytes = 16;
 766                         retval = 1;
 767                 } else {
 768                         *burst_code = DCMD_BURST32;
 769                         burst_bytes = 32;
 770                 }
 771         }
 772
 773         thresh_words = burst_bytes / bytes_per_word;
 774
 775         /* thresh_words will be between 2 and 8 */
 776         *threshold = (SSCR1_RxTresh(thresh_words) & SSCR1_RFT)
 777                         | (SSCR1_TxTresh(16-thresh_words) & SSCR1_TFT);
 778
 779         return retval;
 780 }
 781
 782 static void pump_transfers(unsigned long data)
 783 {
 784         struct driver_data *drv_data = (struct driver_data *)data;
 785         struct spi_message *message = NULL;
 786         struct spi_transfer *transfer = NULL;
 787         struct spi_transfer *previous = NULL;
 788         struct chip_data *chip = NULL;
 789         void *reg = drv_data->ioaddr;
 790         u32 clk_div = 0;
 791         u8 bits = 0;
 792         u32 speed = 0;
 793         u32 cr0;
 794         u32 cr1;
 795         u32 dma_thresh = drv_data->cur_chip->dma_threshold;
 796         u32 dma_burst = drv_data->cur_chip->dma_burst_size;
 797
 798         /* Get current state information */
 799         message = drv_data->cur_msg;
 800         transfer = drv_data->cur_transfer;
 801         chip = drv_data->cur_chip;
 802
 803         /* Handle for abort */
 804         if (message->state == ERROR_STATE) {
 805                 message->status = -EIO;
 806                 giveback(drv_data);
 807                 return;
 808         }
 809
 810         /* Handle end of message */
 811         if (message->state == DONE_STATE) {
 812                 message->status = 0;
 813                 giveback(drv_data);
 814                 return;
 815         }
 816
 817         /* Delay if requested at end of transfer*/
 818         if (message->state == RUNNING_STATE) {
 819                 previous = list_entry(transfer->transfer_list.prev,
 820                                         struct spi_transfer,
 821                                         transfer_list);
 822                 if (previous->delay_usecs)
 823                         udelay(previous->delay_usecs);
 824         }
 825
 826         /* Check transfer length */
 827         if (transfer->len > 8191)
 828         {
 829                 dev_warn(&drv_data->pdev->dev, "pump_transfers: transfer "
 830                                 "length greater than 8191\n");
 831                 message->status = -EINVAL;
 832                 giveback(drv_data);
 833                 return;
 834         }
 835
 836         /* Setup the transfer state based on the type of transfer */
 837         if (flush(drv_data) == 0) {
 838                 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
 839                 message->status = -EIO;
 840                 giveback(drv_data);
 841                 return;
 842         }
 843         drv_data->n_bytes = chip->n_bytes;
 844         drv_data->dma_width = chip->dma_width;
 845         drv_data->cs_control = chip->cs_control;
 846         drv_data->tx = (void *)transfer->tx_buf;
 847         drv_data->tx_end = drv_data->tx + transfer->len;
 848         drv_data->rx = transfer->rx_buf;
 849         drv_data->rx_end = drv_data->rx + transfer->len;
 850         drv_data->rx_dma = transfer->rx_dma;
 851         drv_data->tx_dma = transfer->tx_dma;
 852         drv_data->len = transfer->len & DCMD_LENGTH;
 853         drv_data->write = drv_data->tx ? chip->write : null_writer;
 854         drv_data->read = drv_data->rx ? chip->read : null_reader;
 855         drv_data->cs_change = transfer->cs_change;
 856
 857         /* Change speed and bit per word on a per transfer */
 858         cr0 = chip->cr0;
 859         if (transfer->speed_hz || transfer->bits_per_word) {
 860
 861                 bits = chip->bits_per_word;
 862                 speed = chip->speed_hz;
 863
 864                 if (transfer->speed_hz)
 865                         speed = transfer->speed_hz;
 866
 867                 if (transfer->bits_per_word)
 868                         bits = transfer->bits_per_word;
 869
 870                 if (reg == SSP1_VIRT)
 871                         clk_div = SSP1_SerClkDiv(speed);
 872                 else if (reg == SSP2_VIRT)
 873                         clk_div = SSP2_SerClkDiv(speed);
 874                 else if (reg == SSP3_VIRT)
 875                         clk_div = SSP3_SerClkDiv(speed);
 876
 877                 if (bits <= 8) {
 878                         drv_data->n_bytes = 1;
 879                         drv_data->dma_width = DCMD_WIDTH1;
 880                         drv_data->read = drv_data->read != null_reader ?
 881                                                 u8_reader : null_reader;
 882                         drv_data->write = drv_data->write != null_writer ?
 883                                                 u8_writer : null_writer;
 884                 } else if (bits <= 16) {
 885                         drv_data->n_bytes = 2;
 886                         drv_data->dma_width = DCMD_WIDTH2;
 887                         drv_data->read = drv_data->read != null_reader ?
 888                                                 u16_reader : null_reader;
 889                         drv_data->write = drv_data->write != null_writer ?
 890                                                 u16_writer : null_writer;
 891                 } else if (bits <= 32) {
 892                         drv_data->n_bytes = 4;
 893                         drv_data->dma_width = DCMD_WIDTH4;
 894                         drv_data->read = drv_data->read != null_reader ?
 895                                                 u32_reader : null_reader;
 896                         drv_data->write = drv_data->write != null_writer ?
 897                                                 u32_writer : null_writer;
 898                 }
 899                 /* if bits/word is changed in dma mode, then must check the
 900                  * thresholds and burst also */
 901                 if (chip->enable_dma) {
 902                         if (set_dma_burst_and_threshold(chip, message->spi,
 903                                                         bits, &dma_burst,
 904                                                         &dma_thresh))
 905                                 if (printk_ratelimit())
 906                                         dev_warn(&message->spi->dev,
 907                                                 "pump_transfer: "
 908                                                 "DMA burst size reduced to "
 909                                                 "match bits_per_word\n");
 910                 }
 911
 912                 cr0 = clk_div
 913                         | SSCR0_Motorola
 914                         | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
 915                         | SSCR0_SSE
 916                         | (bits > 16 ? SSCR0_EDSS : 0);
 917         }
 918
 919         message->state = RUNNING_STATE;
 920
 921         /* Try to map dma buffer and do a dma transfer if successful */
 922         if ((drv_data->dma_mapped = map_dma_buffers(drv_data))) {
 923
 924                 /* Ensure we have the correct interrupt handler */
 925                 drv_data->transfer_handler = dma_transfer;
 926
 927                 /* Setup rx DMA Channel */
 928                 DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
 929                 DSADR(drv_data->rx_channel) = drv_data->ssdr_physical;
 930                 DTADR(drv_data->rx_channel) = drv_data->rx_dma;
 931                 if (drv_data->rx == drv_data->null_dma_buf)
 932                         /* No target address increment */
 933                         DCMD(drv_data->rx_channel) = DCMD_FLOWSRC
 934                                                         | drv_data->dma_width
 935                                                         | dma_burst
 936                                                         | drv_data->len;
 937                 else
 938                         DCMD(drv_data->rx_channel) = DCMD_INCTRGADDR
 939                                                         | DCMD_FLOWSRC
 940                                                         | drv_data->dma_width
 941                                                         | dma_burst
 942                                                         | drv_data->len;
 943
 944                 /* Setup tx DMA Channel */
 945                 DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
 946                 DSADR(drv_data->tx_channel) = drv_data->tx_dma;
 947                 DTADR(drv_data->tx_channel) = drv_data->ssdr_physical;
 948                 if (drv_data->tx == drv_data->null_dma_buf)
 949                         /* No source address increment */
 950                         DCMD(drv_data->tx_channel) = DCMD_FLOWTRG
 951                                                         | drv_data->dma_width
 952                                                         | dma_burst
 953                                                         | drv_data->len;
 954                 else
 955                         DCMD(drv_data->tx_channel) = DCMD_INCSRCADDR
 956                                                         | DCMD_FLOWTRG
 957                                                         | drv_data->dma_width
 958                                                         | dma_burst
 959                                                         | drv_data->len;
 960
 961                 /* Enable dma end irqs on SSP to detect end of transfer */
 962                 if (drv_data->ssp_type == PXA25x_SSP)
 963                         DCMD(drv_data->tx_channel) |= DCMD_ENDIRQEN;
 964
 965                 /* Fix me, need to handle cs polarity */
 966                 drv_data->cs_control(PXA2XX_CS_ASSERT);
 967
 968                 /* Clear status and start DMA engine */
 969                 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
 970                 write_SSSR(drv_data->clear_sr, reg);
 971                 DCSR(drv_data->rx_channel) |= DCSR_RUN;
 972                 DCSR(drv_data->tx_channel) |= DCSR_RUN;
 973         } else {
 974                 /* Ensure we have the correct interrupt handler */
 975                 drv_data->transfer_handler = interrupt_transfer;
 976
 977                 /* Fix me, need to handle cs polarity */
 978                 drv_data->cs_control(PXA2XX_CS_ASSERT);
 979
 980                 /* Clear status  */
 981                 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
 982                 write_SSSR(drv_data->clear_sr, reg);
 983         }
 984
 985         /* see if we need to reload the config registers */
 986         if ((read_SSCR0(reg) != cr0)
 987                 || (read_SSCR1(reg) & SSCR1_CHANGE_MASK) !=
 988                         (cr1 & SSCR1_CHANGE_MASK)) {
 989
 990                 write_SSCR0(cr0 & ~SSCR0_SSE, reg);
 991                 if (drv_data->ssp_type != PXA25x_SSP)
 992                         write_SSTO(chip->timeout, reg);
 993                 write_SSCR1(cr1, reg);
 994                 write_SSCR0(cr0, reg);
 995         } else {
 996                 if (drv_data->ssp_type != PXA25x_SSP)
 997                         write_SSTO(chip->timeout, reg);
 998                 write_SSCR1(cr1, reg);
 999         }
1000 }
1001
1002 static void pump_messages(struct work_struct *work)
1003 {
1004         struct driver_data *drv_data =
1005                 container_of(work, struct driver_data, pump_messages);
1006         unsigned long flags;
1007
1008         /* Lock queue and check for queue work */
1009         spin_lock_irqsave(&drv_data->lock, flags);
1010         if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
1011                 drv_data->busy = 0;
1012                 spin_unlock_irqrestore(&drv_data->lock, flags);
1013                 return;
1014         }
1015
1016         /* Make sure we are not already running a message */
1017         if (drv_data->cur_msg) {
1018                 spin_unlock_irqrestore(&drv_data->lock, flags);
1019                 return;
1020         }
1021
1022         /* Extract head of queue */
1023         drv_data->cur_msg = list_entry(drv_data->queue.next,
1024                                         struct spi_message, queue);
1025         list_del_init(&drv_data->cur_msg->queue);
1026
1027         /* Initial message state*/
1028         drv_data->cur_msg->state = START_STATE;
1029         drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
1030                                                 struct spi_transfer,
1031                                                 transfer_list);
1032
1033         /* prepare to setup the SSP, in pump_transfers, using the per
1034          * chip configuration */
1035         drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
1036
1037         /* Mark as busy and launch transfers */
1038         tasklet_schedule(&drv_data->pump_transfers);
1039
1040         drv_data->busy = 1;
1041         spin_unlock_irqrestore(&drv_data->lock, flags);
1042 }
1043
1044 static int transfer(struct spi_device *spi, struct spi_message *msg)
1045 {
1046         struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1047         unsigned long flags;
1048
1049         spin_lock_irqsave(&drv_data->lock, flags);
1050
1051         if (drv_data->run == QUEUE_STOPPED) {
1052                 spin_unlock_irqrestore(&drv_data->lock, flags);
1053                 return -ESHUTDOWN;
1054         }
1055
1056         msg->actual_length = 0;
1057         msg->status = -EINPROGRESS;
1058         msg->state = START_STATE;
1059
1060         list_add_tail(&msg->queue, &drv_data->queue);
1061
1062         if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
1063                 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1064
1065         spin_unlock_irqrestore(&drv_data->lock, flags);
1066
1067         return 0;
1068 }
1069
1070 /* the spi->mode bits understood by this driver: */
1071 #define MODEBITS (SPI_CPOL | SPI_CPHA)
1072
1073 static int setup(struct spi_device *spi)
1074 {
1075         struct pxa2xx_spi_chip *chip_info = NULL;
1076         struct chip_data *chip;
1077         struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1078         unsigned int clk_div;
1079
1080         if (!spi->bits_per_word)
1081                 spi->bits_per_word = 8;
1082
1083         if (drv_data->ssp_type != PXA25x_SSP
1084                 && (spi->bits_per_word < 4 || spi->bits_per_word > 32)) {
1085                 dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "
1086                                 "b/w not 4-32 for type non-PXA25x_SSP\n",
1087                                 drv_data->ssp_type, spi->bits_per_word);
1088                 return -EINVAL;
1089         }
1090         else if (drv_data->ssp_type == PXA25x_SSP
1091                         && (spi->bits_per_word < 4
1092                                 || spi->bits_per_word > 16)) {
1093                 dev_err(&spi->dev, "failed setup: ssp_type=%d, bits/wrd=%d "
1094                                 "b/w not 4-16 for type PXA25x_SSP\n",
1095                                 drv_data->ssp_type, spi->bits_per_word);
1096                 return -EINVAL;
1097         }
1098
1099         if (spi->mode & ~MODEBITS) {
1100                 dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
1101                         spi->mode & ~MODEBITS);
1102                 return -EINVAL;
1103         }
1104
1105         /* Only alloc on first setup */
1106         chip = spi_get_ctldata(spi);
1107         if (!chip) {
1108                 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1109                 if (!chip) {
1110                         dev_err(&spi->dev,
1111                                 "failed setup: can't allocate chip data\n");
1112                         return -ENOMEM;
1113                 }
1114
1115                 chip->cs_control = null_cs_control;
1116                 chip->enable_dma = 0;
1117                 chip->timeout = 1000;
1118                 chip->threshold = SSCR1_RxTresh(1) | SSCR1_TxTresh(1);
1119                 chip->dma_burst_size = drv_data->master_info->enable_dma ?
1120                                         DCMD_BURST8 : 0;
1121         }
1122
1123         /* protocol drivers may change the chip settings, so...
1124          * if chip_info exists, use it */
1125         chip_info = spi->controller_data;
1126
1127         /* chip_info isn't always needed */
1128         chip->cr1 = 0;
1129         if (chip_info) {
1130                 if (chip_info->cs_control)
1131                         chip->cs_control = chip_info->cs_control;
1132
1133                 chip->timeout = chip_info->timeout;
1134
1135                 chip->threshold = (SSCR1_RxTresh(chip_info->rx_threshold) &
1136                                                                 SSCR1_RFT) |
1137                                 (SSCR1_TxTresh(chip_info->tx_threshold) &
1138                                                                 SSCR1_TFT);
1139
1140                 chip->enable_dma = chip_info->dma_burst_size != 0
1141                                         && drv_data->master_info->enable_dma;
1142                 chip->dma_threshold = 0;
1143
1144                 if (chip_info->enable_loopback)
1145                         chip->cr1 = SSCR1_LBM;
1146         }
1147
1148         /* set dma burst and threshold outside of chip_info path so that if
1149          * chip_info goes away after setting chip->enable_dma, the
1150          * burst and threshold can still respond to changes in bits_per_word */
1151         if (chip->enable_dma) {
1152                 /* set up legal burst and threshold for dma */
1153                 if (set_dma_burst_and_threshold(chip, spi, spi->bits_per_word,
1154                                                 &chip->dma_burst_size,
1155                                                 &chip->dma_threshold)) {
1156                         dev_warn(&spi->dev, "in setup: DMA burst size reduced "
1157                                         "to match bits_per_word\n");
1158                 }
1159         }
1160
1161         if (drv_data->ioaddr == SSP1_VIRT)
1162                 clk_div = SSP1_SerClkDiv(spi->max_speed_hz);
1163         else if (drv_data->ioaddr == SSP2_VIRT)
1164                 clk_div = SSP2_SerClkDiv(spi->max_speed_hz);
1165         else if (drv_data->ioaddr == SSP3_VIRT)
1166                 clk_div = SSP3_SerClkDiv(spi->max_speed_hz);
1167         else
1168         {
1169                 dev_err(&spi->dev, "failed setup: unknown IO address=0x%p\n",
1170                         drv_data->ioaddr);
1171                 return -ENODEV;
1172         }
1173         chip->speed_hz = spi->max_speed_hz;
1174
1175         chip->cr0 = clk_div
1176                         | SSCR0_Motorola
1177                         | SSCR0_DataSize(spi->bits_per_word > 16 ?
1178                                 spi->bits_per_word - 16 : spi->bits_per_word)
1179                         | SSCR0_SSE
1180                         | (spi->bits_per_word > 16 ? SSCR0_EDSS : 0);
1181         chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1182         chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
1183                         | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
1184
1185         /* NOTE:  PXA25x_SSP _could_ use external clocking ... */
1186         if (drv_data->ssp_type != PXA25x_SSP)
1187                 dev_dbg(&spi->dev, "%d bits/word, %d Hz, mode %d\n",
1188                                 spi->bits_per_word,
1189                                 (CLOCK_SPEED_HZ)
1190                                         / (1 + ((chip->cr0 & SSCR0_SCR) >> 8)),
1191                                 spi->mode & 0x3);
1192         else
1193                 dev_dbg(&spi->dev, "%d bits/word, %d Hz, mode %d\n",
1194                                 spi->bits_per_word,
1195                                 (CLOCK_SPEED_HZ/2)
1196                                         / (1 + ((chip->cr0 & SSCR0_SCR) >> 8)),
1197                                 spi->mode & 0x3);
1198
1199         if (spi->bits_per_word <= 8) {
1200                 chip->n_bytes = 1;
1201                 chip->dma_width = DCMD_WIDTH1;
1202                 chip->read = u8_reader;
1203                 chip->write = u8_writer;
1204         } else if (spi->bits_per_word <= 16) {
1205                 chip->n_bytes = 2;
1206                 chip->dma_width = DCMD_WIDTH2;
1207                 chip->read = u16_reader;
1208                 chip->write = u16_writer;
1209         } else if (spi->bits_per_word <= 32) {
1210                 chip->cr0 |= SSCR0_EDSS;
1211                 chip->n_bytes = 4;
1212                 chip->dma_width = DCMD_WIDTH4;
1213                 chip->read = u32_reader;
1214                 chip->write = u32_writer;
1215         } else {
1216                 dev_err(&spi->dev, "invalid wordsize\n");
1217                 return -ENODEV;
1218         }
1219         chip->bits_per_word = spi->bits_per_word;
1220
1221         spi_set_ctldata(spi, chip);
1222
1223         return 0;
1224 }
1225
1226 static void cleanup(struct spi_device *spi)
1227 {
1228         struct chip_data *chip = spi_get_ctldata(spi);
1229
1230         kfree(chip);
1231 }
1232
1233 static int init_queue(struct driver_data *drv_data)
1234 {
1235         INIT_LIST_HEAD(&drv_data->queue);
1236         spin_lock_init(&drv_data->lock);
1237
1238         drv_data->run = QUEUE_STOPPED;
1239         drv_data->busy = 0;
1240
1241         tasklet_init(&drv_data->pump_transfers,
1242                         pump_transfers, (unsigned long)drv_data);
1243
1244         INIT_WORK(&drv_data->pump_messages, pump_messages);
1245         drv_data->workqueue = create_singlethread_workqueue(
1246                                         drv_data->master->cdev.dev->bus_id);
1247         if (drv_data->workqueue == NULL)
1248                 return -EBUSY;
1249
1250         return 0;
1251 }
1252
1253 static int start_queue(struct driver_data *drv_data)
1254 {
1255         unsigned long flags;
1256
1257         spin_lock_irqsave(&drv_data->lock, flags);
1258
1259         if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1260                 spin_unlock_irqrestore(&drv_data->lock, flags);
1261                 return -EBUSY;
1262         }
1263
1264         drv_data->run = QUEUE_RUNNING;
1265         drv_data->cur_msg = NULL;
1266         drv_data->cur_transfer = NULL;
1267         drv_data->cur_chip = NULL;
1268         spin_unlock_irqrestore(&drv_data->lock, flags);
1269
1270         queue_work(drv_data->workqueue, &drv_data->pump_messages);
1271
1272         return 0;
1273 }
1274
1275 static int stop_queue(struct driver_data *drv_data)
1276 {
1277         unsigned long flags;
1278         unsigned limit = 500;
1279         int status = 0;
1280
1281         spin_lock_irqsave(&drv_data->lock, flags);
1282
1283         /* This is a bit lame, but is optimized for the common execution path.
1284          * A wait_queue on the drv_data->busy could be used, but then the common
1285          * execution path (pump_messages) would be required to call wake_up or
1286          * friends on every SPI message. Do this instead */
1287         drv_data->run = QUEUE_STOPPED;
1288         while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1289                 spin_unlock_irqrestore(&drv_data->lock, flags);
1290                 msleep(10);
1291                 spin_lock_irqsave(&drv_data->lock, flags);
1292         }
1293
1294         if (!list_empty(&drv_data->queue) || drv_data->busy)
1295                 status = -EBUSY;
1296
1297         spin_unlock_irqrestore(&drv_data->lock, flags);
1298
1299         return status;
1300 }
1301
1302 static int destroy_queue(struct driver_data *drv_data)
1303 {
1304         int status;
1305
1306         status = stop_queue(drv_data);
1307         /* we are unloading the module or failing to load (only two calls
1308          * to this routine), and neither call can handle a return value.
1309          * However, destroy_workqueue calls flush_workqueue, and that will
1310          * block until all work is done.  If the reason that stop_queue
1311          * timed out is that the work will never finish, then it does no
1312          * good to call destroy_workqueue, so return anyway. */
1313         if (status != 0)
1314                 return status;
1315
1316         destroy_workqueue(drv_data->workqueue);
1317
1318         return 0;
1319 }
1320
1321 static int pxa2xx_spi_probe(struct platform_device *pdev)
1322 {
1323         struct device *dev = &pdev->dev;
1324         struct pxa2xx_spi_master *platform_info;
1325         struct spi_master *master;
1326         struct driver_data *drv_data = 0;
1327         struct resource *memory_resource;
1328         int irq;
1329         int status = 0;
1330
1331         platform_info = dev->platform_data;
1332
1333         if (platform_info->ssp_type == SSP_UNDEFINED) {
1334                 dev_err(&pdev->dev, "undefined SSP\n");
1335                 return -ENODEV;
1336         }
1337
1338         /* Allocate master with space for drv_data and null dma buffer */
1339         master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1340         if (!master) {
1341                 dev_err(&pdev->dev, "can not alloc spi_master\n");
1342                 return -ENOMEM;
1343         }
1344         drv_data = spi_master_get_devdata(master);
1345         drv_data->master = master;
1346         drv_data->master_info = platform_info;
1347         drv_data->pdev = pdev;
1348
1349         master->bus_num = pdev->id;
1350         master->num_chipselect = platform_info->num_chipselect;
1351         master->cleanup = cleanup;
1352         master->setup = setup;
1353         master->transfer = transfer;
1354
1355         drv_data->ssp_type = platform_info->ssp_type;
1356         drv_data->null_dma_buf = (u32 *)ALIGN((u32)(drv_data +
1357                                                 sizeof(struct driver_data)), 8);
1358
1359         /* Setup register addresses */
1360         memory_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1361         if (!memory_resource) {
1362                 dev_err(&pdev->dev, "memory resources not defined\n");
1363                 status = -ENODEV;
1364                 goto out_error_master_alloc;
1365         }
1366
1367         drv_data->ioaddr = (void *)io_p2v((unsigned long)(memory_resource->start));
1368         drv_data->ssdr_physical = memory_resource->start + 0x00000010;
1369         if (platform_info->ssp_type == PXA25x_SSP) {
1370                 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1371                 drv_data->dma_cr1 = 0;
1372                 drv_data->clear_sr = SSSR_ROR;
1373                 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1374         } else {
1375                 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1376                 drv_data->dma_cr1 = SSCR1_TSRE | SSCR1_RSRE | SSCR1_TINTE;
1377                 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1378                 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;
1379         }
1380
1381         /* Attach to IRQ */
1382         irq = platform_get_irq(pdev, 0);
1383         if (irq < 0) {
1384                 dev_err(&pdev->dev, "irq resource not defined\n");
1385                 status = -ENODEV;
1386                 goto out_error_master_alloc;
1387         }
1388
1389         status = request_irq(irq, ssp_int, 0, dev->bus_id, drv_data);
1390         if (status < 0) {
1391                 dev_err(&pdev->dev, "can not get IRQ\n");
1392                 goto out_error_master_alloc;
1393         }
1394
1395         /* Setup DMA if requested */
1396         drv_data->tx_channel = -1;
1397         drv_data->rx_channel = -1;
1398         if (platform_info->enable_dma) {
1399
1400                 /* Get two DMA channels (rx and tx) */
1401                 drv_data->rx_channel = pxa_request_dma("pxa2xx_spi_ssp_rx",
1402                                                         DMA_PRIO_HIGH,
1403                                                         dma_handler,
1404                                                         drv_data);
1405                 if (drv_data->rx_channel < 0) {
1406                         dev_err(dev, "problem (%d) requesting rx channel\n",
1407                                 drv_data->rx_channel);
1408                         status = -ENODEV;
1409                         goto out_error_irq_alloc;
1410                 }
1411                 drv_data->tx_channel = pxa_request_dma("pxa2xx_spi_ssp_tx",
1412                                                         DMA_PRIO_MEDIUM,
1413                                                         dma_handler,
1414                                                         drv_data);
1415                 if (drv_data->tx_channel < 0) {
1416                         dev_err(dev, "problem (%d) requesting tx channel\n",
1417                                 drv_data->tx_channel);
1418                         status = -ENODEV;
1419                         goto out_error_dma_alloc;
1420                 }
1421
1422                 if (drv_data->ioaddr == SSP1_VIRT) {
1423                                 DRCMRRXSSDR = DRCMR_MAPVLD
1424                                                 | drv_data->rx_channel;
1425                                 DRCMRTXSSDR = DRCMR_MAPVLD
1426                                                 | drv_data->tx_channel;
1427                 } else if (drv_data->ioaddr == SSP2_VIRT) {
1428                                 DRCMRRXSS2DR = DRCMR_MAPVLD
1429                                                 | drv_data->rx_channel;
1430                                 DRCMRTXSS2DR = DRCMR_MAPVLD
1431                                                 | drv_data->tx_channel;
1432                 } else if (drv_data->ioaddr == SSP3_VIRT) {
1433                                 DRCMRRXSS3DR = DRCMR_MAPVLD
1434                                                 | drv_data->rx_channel;
1435                                 DRCMRTXSS3DR = DRCMR_MAPVLD
1436                                                 | drv_data->tx_channel;
1437                 } else {
1438                         dev_err(dev, "bad SSP type\n");
1439                         goto out_error_dma_alloc;
1440                 }
1441         }
1442
1443         /* Enable SOC clock */
1444         pxa_set_cken(platform_info->clock_enable, 1);
1445
1446         /* Load default SSP configuration */
1447         write_SSCR0(0, drv_data->ioaddr);
1448         write_SSCR1(SSCR1_RxTresh(4) | SSCR1_TxTresh(12), drv_data->ioaddr);
1449         write_SSCR0(SSCR0_SerClkDiv(2)
1450                         | SSCR0_Motorola
1451                         | SSCR0_DataSize(8),
1452                         drv_data->ioaddr);
1453         if (drv_data->ssp_type != PXA25x_SSP)
1454                 write_SSTO(0, drv_data->ioaddr);
1455         write_SSPSP(0, drv_data->ioaddr);
1456
1457         /* Initial and start queue */
1458         status = init_queue(drv_data);
1459         if (status != 0) {
1460                 dev_err(&pdev->dev, "problem initializing queue\n");
1461                 goto out_error_clock_enabled;
1462         }
1463         status = start_queue(drv_data);
1464         if (status != 0) {
1465                 dev_err(&pdev->dev, "problem starting queue\n");
1466                 goto out_error_clock_enabled;
1467         }
1468
1469         /* Register with the SPI framework */
1470         platform_set_drvdata(pdev, drv_data);
1471         status = spi_register_master(master);
1472         if (status != 0) {
1473                 dev_err(&pdev->dev, "problem registering spi master\n");
1474                 goto out_error_queue_alloc;
1475         }
1476
1477         return status;
1478
1479 out_error_queue_alloc:
1480         destroy_queue(drv_data);
1481
1482 out_error_clock_enabled:
1483         pxa_set_cken(platform_info->clock_enable, 0);
1484
1485 out_error_dma_alloc:
1486         if (drv_data->tx_channel != -1)
1487                 pxa_free_dma(drv_data->tx_channel);
1488         if (drv_data->rx_channel != -1)
1489                 pxa_free_dma(drv_data->rx_channel);
1490
1491 out_error_irq_alloc:
1492         free_irq(irq, drv_data);
1493
1494 out_error_master_alloc:
1495         spi_master_put(master);
1496         return status;
1497 }
1498
1499 static int pxa2xx_spi_remove(struct platform_device *pdev)
1500 {
1501         struct driver_data *drv_data = platform_get_drvdata(pdev);
1502         int irq;
1503         int status = 0;
1504
1505         if (!drv_data)
1506                 return 0;
1507
1508         /* Remove the queue */
1509         status = destroy_queue(drv_data);
1510         if (status != 0)
1511                 /* the kernel does not check the return status of this
1512                  * this routine (mod->exit, within the kernel).  Therefore
1513                  * nothing is gained by returning from here, the module is
1514                  * going away regardless, and we should not leave any more
1515                  * resources allocated than necessary.  We cannot free the
1516                  * message memory in drv_data->queue, but we can release the
1517                  * resources below.  I think the kernel should honor -EBUSY
1518                  * returns but... */
1519                 dev_err(&pdev->dev, "pxa2xx_spi_remove: workqueue will not "
1520                         "complete, message memory not freed\n");
1521
1522         /* Disable the SSP at the peripheral and SOC level */
1523         write_SSCR0(0, drv_data->ioaddr);
1524         pxa_set_cken(drv_data->master_info->clock_enable, 0);
1525
1526         /* Release DMA */
1527         if (drv_data->master_info->enable_dma) {
1528                 if (drv_data->ioaddr == SSP1_VIRT) {
1529                         DRCMRRXSSDR = 0;
1530                         DRCMRTXSSDR = 0;
1531                 } else if (drv_data->ioaddr == SSP2_VIRT) {
1532                         DRCMRRXSS2DR = 0;
1533                         DRCMRTXSS2DR = 0;
1534                 } else if (drv_data->ioaddr == SSP3_VIRT) {
1535                         DRCMRRXSS3DR = 0;
1536                         DRCMRTXSS3DR = 0;
1537                 }
1538                 pxa_free_dma(drv_data->tx_channel);
1539                 pxa_free_dma(drv_data->rx_channel);
1540         }
1541
1542         /* Release IRQ */
1543         irq = platform_get_irq(pdev, 0);
1544         if (irq >= 0)
1545                 free_irq(irq, drv_data);
1546
1547         /* Disconnect from the SPI framework */
1548         spi_unregister_master(drv_data->master);
1549
1550         /* Prevent double remove */
1551         platform_set_drvdata(pdev, NULL);
1552
1553         return 0;
1554 }
1555
1556 static void pxa2xx_spi_shutdown(struct platform_device *pdev)
1557 {
1558         int status = 0;
1559
1560         if ((status = pxa2xx_spi_remove(pdev)) != 0)
1561                 dev_err(&pdev->dev, "shutdown failed with %d\n", status);
1562 }
1563
1564 #ifdef CONFIG_PM
1565 static int suspend_devices(struct device *dev, void *pm_message)
1566 {
1567         pm_message_t *state = pm_message;
1568
1569         if (dev->power.power_state.event != state->event) {
1570                 dev_warn(dev, "pm state does not match request\n");
1571                 return -1;
1572         }
1573
1574         return 0;
1575 }
1576
1577 static int pxa2xx_spi_suspend(struct platform_device *pdev, pm_message_t state)
1578 {
1579         struct driver_data *drv_data = platform_get_drvdata(pdev);
1580         int status = 0;
1581
1582         /* Check all childern for current power state */
1583         if (device_for_each_child(&pdev->dev, &state, suspend_devices) != 0) {
1584                 dev_warn(&pdev->dev, "suspend aborted\n");
1585                 return -1;
1586         }
1587
1588         status = stop_queue(drv_data);
1589         if (status != 0)
1590                 return status;
1591         write_SSCR0(0, drv_data->ioaddr);
1592         pxa_set_cken(drv_data->master_info->clock_enable, 0);
1593
1594         return 0;
1595 }
1596
1597 static int pxa2xx_spi_resume(struct platform_device *pdev)
1598 {
1599         struct driver_data *drv_data = platform_get_drvdata(pdev);
1600         int status = 0;
1601
1602         /* Enable the SSP clock */
1603         pxa_set_cken(drv_data->master_info->clock_enable, 1);
1604
1605         /* Start the queue running */
1606         status = start_queue(drv_data);
1607         if (status != 0) {
1608                 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1609                 return status;
1610         }
1611
1612         return 0;
1613 }
1614 #else
1615 #define pxa2xx_spi_suspend NULL
1616 #define pxa2xx_spi_resume NULL
1617 #endif /* CONFIG_PM */
1618
1619 static struct platform_driver driver = {
1620         .driver = {
1621                 .name = "pxa2xx-spi",
1622                 .bus = &platform_bus_type,
1623                 .owner = THIS_MODULE,
1624         },
1625         .probe = pxa2xx_spi_probe,
1626         .remove = __devexit_p(pxa2xx_spi_remove),
1627         .shutdown = pxa2xx_spi_shutdown,
1628         .suspend = pxa2xx_spi_suspend,
1629         .resume = pxa2xx_spi_resume,
1630 };
1631
1632 static int __init pxa2xx_spi_init(void)
1633 {
1634         platform_driver_register(&driver);
1635
1636         return 0;
1637 }
1638 module_init(pxa2xx_spi_init);
1639
1640 static void __exit pxa2xx_spi_exit(void)
1641 {
1642         platform_driver_unregister(&driver);
1643 }
1644 module_exit(pxa2xx_spi_exit);