git.oblomov.eu Git - linux-2.6/blob - drivers/media/dvb/frontends/cx24123.c

   1 /*
   2     Conexant cx24123/cx24109 - DVB QPSK Satellite demod/tuner driver
   3
   4     Copyright (C) 2005 Steven Toth <stoth@hauppauge.com>
   5
   6     Support for KWorld DVB-S 100 by Vadim Catana <skystar@moldova.cc>
   7
   8     This program is free software; you can redistribute it and/or modify
   9     it under the terms of the GNU General Public License as published by
  10     the Free Software Foundation; either version 2 of the License, or
  11     (at your option) any later version.
  12
  13     This program is distributed in the hope that it will be useful,
  14     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16     GNU General Public License for more details.
  17
  18     You should have received a copy of the GNU General Public License
  19     along with this program; if not, write to the Free Software
  20     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21 */
  22
  23 #include <linux/slab.h>
  24 #include <linux/kernel.h>
  25 #include <linux/module.h>
  26 #include <linux/moduleparam.h>
  27 #include <linux/init.h>
  28
  29 #include "dvb_frontend.h"
  30 #include "cx24123.h"
  31
  32 #define XTAL 10111000
  33
  34 static int debug;
  35 #define dprintk(args...) \
  36         do { \
  37                 if (debug) printk (KERN_DEBUG "cx24123: " args); \
  38         } while (0)
  39
  40 struct cx24123_state
  41 {
  42         struct i2c_adapter* i2c;
  43         struct dvb_frontend_ops ops;
  44         const struct cx24123_config* config;
  45
  46         struct dvb_frontend frontend;
  47
  48         u32 lastber;
  49         u16 snr;
  50         u8  lnbreg;
  51
  52         /* Some PLL specifics for tuning */
  53         u32 VCAarg;
  54         u32 VGAarg;
  55         u32 bandselectarg;
  56         u32 pllarg;
  57         u32 FILTune;
  58
  59         /* The Demod/Tuner can't easily provide these, we cache them */
  60         u32 currentfreq;
  61         u32 currentsymbolrate;
  62 };
  63
  64 /* Various tuner defaults need to be established for a given symbol rate Sps */
  65 static struct
  66 {
  67         u32 symbolrate_low;
  68         u32 symbolrate_high;
  69         u32 VCAprogdata;
  70         u32 VGAprogdata;
  71         u32 FILTune;
  72 } cx24123_AGC_vals[] =
  73 {
  74         {
  75                 .symbolrate_low         = 1000000,
  76                 .symbolrate_high        = 4999999,
  77                 /* the specs recommend other values for VGA offsets,
  78                    but tests show they are wrong */
  79                 .VGAprogdata            = (2 << 18) | (0x180 << 9) | 0x1e0,
  80                 .VCAprogdata            = (4 << 18) | (0x07 << 9) | 0x07,
  81                 .FILTune                = 0x280 /* 0.41 V */
  82         },
  83         {
  84                 .symbolrate_low         =  5000000,
  85                 .symbolrate_high        = 14999999,
  86                 .VGAprogdata            = (2 << 18) | (0x180 << 9) | 0x1e0,
  87                 .VCAprogdata            = (4 << 18) | (0x07 << 9) | 0x1f,
  88                 .FILTune                = 0x317 /* 0.90 V */
  89         },
  90         {
  91                 .symbolrate_low         = 15000000,
  92                 .symbolrate_high        = 45000000,
  93                 .VGAprogdata            = (2 << 18) | (0x100 << 9) | 0x180,
  94                 .VCAprogdata            = (4 << 18) | (0x07 << 9) | 0x3f,
  95                 .FILTune                = 0x146 /* 2.70 V */
  96         },
  97 };
  98
  99 /*
 100  * Various tuner defaults need to be established for a given frequency kHz.
 101  * fixme: The bounds on the bands do not match the doc in real life.
 102  * fixme: Some of them have been moved, other might need adjustment.
 103  */
 104 static struct
 105 {
 106         u32 freq_low;
 107         u32 freq_high;
 108         u32 VCOdivider;
 109         u32 progdata;
 110 } cx24123_bandselect_vals[] =
 111 {
 112         {
 113                 .freq_low       = 950000,
 114                 .freq_high      = 1018999,
 115                 .VCOdivider     = 4,
 116                 .progdata       = (0 << 18) | (0 << 9) | 0x40,
 117         },
 118         {
 119                 .freq_low       = 1019000,
 120                 .freq_high      = 1074999,
 121                 .VCOdivider     = 4,
 122                 .progdata       = (0 << 18) | (0 << 9) | 0x80,
 123         },
 124         {
 125                 .freq_low       = 1075000,
 126                 .freq_high      = 1227999,
 127                 .VCOdivider     = 2,
 128                 .progdata       = (0 << 18) | (1 << 9) | 0x01,
 129         },
 130         {
 131                 .freq_low       = 1228000,
 132                 .freq_high      = 1349999,
 133                 .VCOdivider     = 2,
 134                 .progdata       = (0 << 18) | (1 << 9) | 0x02,
 135         },
 136         {
 137                 .freq_low       = 1350000,
 138                 .freq_high      = 1481999,
 139                 .VCOdivider     = 2,
 140                 .progdata       = (0 << 18) | (1 << 9) | 0x04,
 141         },
 142         {
 143                 .freq_low       = 1482000,
 144                 .freq_high      = 1595999,
 145                 .VCOdivider     = 2,
 146                 .progdata       = (0 << 18) | (1 << 9) | 0x08,
 147         },
 148         {
 149                 .freq_low       = 1596000,
 150                 .freq_high      = 1717999,
 151                 .VCOdivider     = 2,
 152                 .progdata       = (0 << 18) | (1 << 9) | 0x10,
 153         },
 154         {
 155                 .freq_low       = 1718000,
 156                 .freq_high      = 1855999,
 157                 .VCOdivider     = 2,
 158                 .progdata       = (0 << 18) | (1 << 9) | 0x20,
 159         },
 160         {
 161                 .freq_low       = 1856000,
 162                 .freq_high      = 2035999,
 163                 .VCOdivider     = 2,
 164                 .progdata       = (0 << 18) | (1 << 9) | 0x40,
 165         },
 166         {
 167                 .freq_low       = 2036000,
 168                 .freq_high      = 2149999,
 169                 .VCOdivider     = 2,
 170                 .progdata       = (0 << 18) | (1 << 9) | 0x80,
 171         },
 172 };
 173
 174 static struct {
 175         u8 reg;
 176         u8 data;
 177 } cx24123_regdata[] =
 178 {
 179         {0x00, 0x03}, /* Reset system */
 180         {0x00, 0x00}, /* Clear reset */
 181         {0x03, 0x07},
 182         {0x04, 0x10},
 183         {0x05, 0x04},
 184         {0x06, 0x31},
 185         {0x0d, 0x02},
 186         {0x0e, 0x03},
 187         {0x0f, 0xfe},
 188         {0x10, 0x01},
 189         {0x14, 0x01},
 190         {0x16, 0x00},
 191         {0x17, 0x01},
 192         {0x1b, 0x05},
 193         {0x1c, 0x80},
 194         {0x1d, 0x00},
 195         {0x1e, 0x00},
 196         {0x20, 0x41},
 197         {0x21, 0x15},
 198         {0x29, 0x00},
 199         {0x2a, 0xb0},
 200         {0x2b, 0x73},
 201         {0x2c, 0x00},
 202         {0x2d, 0x00},
 203         {0x2e, 0x00},
 204         {0x2f, 0x00},
 205         {0x30, 0x00},
 206         {0x31, 0x00},
 207         {0x32, 0x8c},
 208         {0x33, 0x00},
 209         {0x34, 0x00},
 210         {0x35, 0x03},
 211         {0x36, 0x02},
 212         {0x37, 0x3a},
 213         {0x3a, 0x00},   /* Enable AGC accumulator */
 214         {0x44, 0x00},
 215         {0x45, 0x00},
 216         {0x46, 0x05},
 217         {0x56, 0x41},
 218         {0x57, 0xff},
 219         {0x67, 0x83},
 220 };
 221
 222 static int cx24123_writereg(struct cx24123_state* state, int reg, int data)
 223 {
 224         u8 buf[] = { reg, data };
 225         struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
 226         int err;
 227
 228         if (debug>1)
 229                 printk("cx24123: %s:  write reg 0x%02x, value 0x%02x\n",
 230                                                 __FUNCTION__,reg, data);
 231
 232         if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) {
 233                 printk("%s: writereg error(err == %i, reg == 0x%02x,"
 234                          " data == 0x%02x)\n", __FUNCTION__, err, reg, data);
 235                 return -EREMOTEIO;
 236         }
 237
 238         return 0;
 239 }
 240
 241 static int cx24123_writelnbreg(struct cx24123_state* state, int reg, int data)
 242 {
 243         u8 buf[] = { reg, data };
 244         /* fixme: put the intersil addr int the config */
 245         struct i2c_msg msg = { .addr = 0x08, .flags = 0, .buf = buf, .len = 2 };
 246         int err;
 247
 248         if (debug>1)
 249                 printk("cx24123: %s:  writeln addr=0x08, reg 0x%02x, value 0x%02x\n",
 250                                                 __FUNCTION__,reg, data);
 251
 252         if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) {
 253                 printk("%s: writelnbreg error (err == %i, reg == 0x%02x,"
 254                          " data == 0x%02x)\n", __FUNCTION__, err, reg, data);
 255                 return -EREMOTEIO;
 256         }
 257
 258         /* cache the write, no way to read back */
 259         state->lnbreg = data;
 260
 261         return 0;
 262 }
 263
 264 static int cx24123_readreg(struct cx24123_state* state, u8 reg)
 265 {
 266         int ret;
 267         u8 b0[] = { reg };
 268         u8 b1[] = { 0 };
 269         struct i2c_msg msg[] = {
 270                 { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 },
 271                 { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 }
 272         };
 273
 274         ret = i2c_transfer(state->i2c, msg, 2);
 275
 276         if (ret != 2) {
 277                 printk("%s: reg=0x%x (error=%d)\n", __FUNCTION__, reg, ret);
 278                 return ret;
 279         }
 280
 281         if (debug>1)
 282                 printk("cx24123: read reg 0x%02x, value 0x%02x\n",reg, ret);
 283
 284         return b1[0];
 285 }
 286
 287 static int cx24123_readlnbreg(struct cx24123_state* state, u8 reg)
 288 {
 289         return state->lnbreg;
 290 }
 291
 292 static int cx24123_set_inversion(struct cx24123_state* state, fe_spectral_inversion_t inversion)
 293 {
 294         switch (inversion) {
 295         case INVERSION_OFF:
 296                 dprintk("%s:  inversion off\n",__FUNCTION__);
 297                 cx24123_writereg(state, 0x0e, cx24123_readreg(state, 0x0e) & 0x7f);
 298                 cx24123_writereg(state, 0x10, cx24123_readreg(state, 0x10) | 0x80);
 299                 break;
 300         case INVERSION_ON:
 301                 dprintk("%s:  inversion on\n",__FUNCTION__);
 302                 cx24123_writereg(state, 0x0e, cx24123_readreg(state, 0x0e) | 0x80);
 303                 cx24123_writereg(state, 0x10, cx24123_readreg(state, 0x10) | 0x80);
 304                 break;
 305         case INVERSION_AUTO:
 306                 dprintk("%s:  inversion auto\n",__FUNCTION__);
 307                 cx24123_writereg(state, 0x10, cx24123_readreg(state, 0x10) & 0x7f);
 308                 break;
 309         default:
 310                 return -EINVAL;
 311         }
 312
 313         return 0;
 314 }
 315
 316 static int cx24123_get_inversion(struct cx24123_state* state, fe_spectral_inversion_t *inversion)
 317 {
 318         u8 val;
 319
 320         val = cx24123_readreg(state, 0x1b) >> 7;
 321
 322         if (val == 0) {
 323                 dprintk("%s:  read inversion off\n",__FUNCTION__);
 324                 *inversion = INVERSION_OFF;
 325         } else {
 326                 dprintk("%s:  read inversion on\n",__FUNCTION__);
 327                 *inversion = INVERSION_ON;
 328         }
 329
 330         return 0;
 331 }
 332
 333 static int cx24123_set_fec(struct cx24123_state* state, fe_code_rate_t fec)
 334 {
 335         if ( (fec < FEC_NONE) || (fec > FEC_AUTO) )
 336                 fec = FEC_AUTO;
 337
 338         /* Hardware has 5/11 and 3/5 but are never unused */
 339         switch (fec) {
 340         case FEC_NONE:
 341                 dprintk("%s:  set FEC to none\n",__FUNCTION__);
 342                 return cx24123_writereg(state, 0x0f, 0x01);
 343         case FEC_1_2:
 344                 dprintk("%s:  set FEC to 1/2\n",__FUNCTION__);
 345                 return cx24123_writereg(state, 0x0f, 0x02);
 346         case FEC_2_3:
 347                 dprintk("%s:  set FEC to 2/3\n",__FUNCTION__);
 348                 return cx24123_writereg(state, 0x0f, 0x04);
 349         case FEC_3_4:
 350                 dprintk("%s:  set FEC to 3/4\n",__FUNCTION__);
 351                 return cx24123_writereg(state, 0x0f, 0x08);
 352         case FEC_5_6:
 353                 dprintk("%s:  set FEC to 4/5\n",__FUNCTION__);
 354                 return cx24123_writereg(state, 0x0f, 0x20);
 355         case FEC_7_8:
 356                 dprintk("%s:  set FEC to 5/6\n",__FUNCTION__);
 357                 return cx24123_writereg(state, 0x0f, 0x80);
 358         case FEC_AUTO:
 359                 dprintk("%s:  set FEC to auto\n",__FUNCTION__);
 360                 return cx24123_writereg(state, 0x0f, 0xae);
 361         default:
 362                 return -EOPNOTSUPP;
 363         }
 364 }
 365
 366 static int cx24123_get_fec(struct cx24123_state* state, fe_code_rate_t *fec)
 367 {
 368         int ret;
 369
 370         ret = cx24123_readreg (state, 0x1b);
 371         if (ret < 0)
 372                 return ret;
 373         ret = ret & 0x07;
 374
 375         switch (ret) {
 376         case 1:
 377                 *fec = FEC_1_2;
 378                 break;
 379         case 2:
 380                 *fec = FEC_2_3;
 381                 break;
 382         case 3:
 383                 *fec = FEC_3_4;
 384                 break;
 385         case 4:
 386                 *fec = FEC_4_5;
 387                 break;
 388         case 5:
 389                 *fec = FEC_5_6;
 390                 break;
 391         case 6:
 392                 *fec = FEC_6_7;
 393                 break;
 394         case 7:
 395                 *fec = FEC_7_8;
 396                 break;
 397         default:
 398                 *fec = FEC_NONE; // can't happen
 399                 printk("FEC_NONE ?\n");
 400         }
 401
 402         return 0;
 403 }
 404
 405 static int cx24123_set_symbolrate(struct cx24123_state* state, u32 srate)
 406 {
 407         u32 tmp, sample_rate, ratio;
 408         u8 pll_mult;
 409
 410         /*  check if symbol rate is within limits */
 411         if ((srate > state->ops.info.symbol_rate_max) ||
 412             (srate < state->ops.info.symbol_rate_min))
 413                 return -EOPNOTSUPP;;
 414
 415         /* choose the sampling rate high enough for the required operation,
 416            while optimizing the power consumed by the demodulator */
 417         if (srate < (XTAL*2)/2)
 418                 pll_mult = 2;
 419         else if (srate < (XTAL*3)/2)
 420                 pll_mult = 3;
 421         else if (srate < (XTAL*4)/2)
 422                 pll_mult = 4;
 423         else if (srate < (XTAL*5)/2)
 424                 pll_mult = 5;
 425         else if (srate < (XTAL*6)/2)
 426                 pll_mult = 6;
 427         else if (srate < (XTAL*7)/2)
 428                 pll_mult = 7;
 429         else if (srate < (XTAL*8)/2)
 430                 pll_mult = 8;
 431         else
 432                 pll_mult = 9;
 433
 434
 435         sample_rate = pll_mult * XTAL;
 436
 437         /*
 438             SYSSymbolRate[21:0] = (srate << 23) / sample_rate
 439
 440             We have to use 32 bit unsigned arithmetic without precision loss.
 441             The maximum srate is 45000000 or 0x02AEA540. This number has
 442             only 6 clear bits on top, hence we can shift it left only 6 bits
 443             at a time. Borrowed from cx24110.c
 444         */
 445
 446         tmp = srate << 6;
 447         ratio = tmp / sample_rate;
 448
 449         tmp = (tmp % sample_rate) << 6;
 450         ratio = (ratio << 6) + (tmp / sample_rate);
 451
 452         tmp = (tmp % sample_rate) << 6;
 453         ratio = (ratio << 6) + (tmp / sample_rate);
 454
 455         tmp = (tmp % sample_rate) << 5;
 456         ratio = (ratio << 5) + (tmp / sample_rate);
 457
 458
 459         cx24123_writereg(state, 0x01, pll_mult * 6);
 460
 461         cx24123_writereg(state, 0x08, (ratio >> 16) & 0x3f );
 462         cx24123_writereg(state, 0x09, (ratio >>  8) & 0xff );
 463         cx24123_writereg(state, 0x0a, (ratio      ) & 0xff );
 464
 465         dprintk("%s: srate=%d, ratio=0x%08x, sample_rate=%i\n", __FUNCTION__, srate, ratio, sample_rate);
 466
 467         return 0;
 468 }
 469
 470 /*
 471  * Based on the required frequency and symbolrate, the tuner AGC has to be configured
 472  * and the correct band selected. Calculate those values
 473  */
 474 static int cx24123_pll_calculate(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
 475 {
 476         struct cx24123_state *state = fe->demodulator_priv;
 477         u32 ndiv = 0, adiv = 0, vco_div = 0;
 478         int i = 0;
 479         int pump = 2;
 480
 481         /* Defaults for low freq, low rate */
 482         state->VCAarg = cx24123_AGC_vals[0].VCAprogdata;
 483         state->VGAarg = cx24123_AGC_vals[0].VGAprogdata;
 484         state->bandselectarg = cx24123_bandselect_vals[0].progdata;
 485         vco_div = cx24123_bandselect_vals[0].VCOdivider;
 486
 487         /* For the given symbol rate, determine the VCA, VGA and FILTUNE programming bits */
 488         for (i = 0; i < sizeof(cx24123_AGC_vals) / sizeof(cx24123_AGC_vals[0]); i++)
 489         {
 490                 if ((cx24123_AGC_vals[i].symbolrate_low <= p->u.qpsk.symbol_rate) &&
 491                     (cx24123_AGC_vals[i].symbolrate_high >= p->u.qpsk.symbol_rate) ) {
 492                         state->VCAarg = cx24123_AGC_vals[i].VCAprogdata;
 493                         state->VGAarg = cx24123_AGC_vals[i].VGAprogdata;
 494                         state->FILTune = cx24123_AGC_vals[i].FILTune;
 495                 }
 496         }
 497
 498         /* For the given frequency, determine the bandselect programming bits */
 499         for (i = 0; i < sizeof(cx24123_bandselect_vals) / sizeof(cx24123_bandselect_vals[0]); i++)
 500         {
 501                 if ((cx24123_bandselect_vals[i].freq_low <= p->frequency) &&
 502                     (cx24123_bandselect_vals[i].freq_high >= p->frequency) ) {
 503                         state->bandselectarg = cx24123_bandselect_vals[i].progdata;
 504                         vco_div = cx24123_bandselect_vals[i].VCOdivider;
 505
 506                         /* determine the charge pump current */
 507                         if ( p->frequency < (cx24123_bandselect_vals[i].freq_low + cx24123_bandselect_vals[i].freq_high)/2 )
 508                                 pump = 0x01;
 509                         else
 510                                 pump = 0x02;
 511                 }
 512         }
 513
 514         /* Determine the N/A dividers for the requested lband freq (in kHz). */
 515         /* Note: the reference divider R=10, frequency is in KHz, XTAL is in Hz */
 516         ndiv = ( ((p->frequency * vco_div * 10) / (2 * XTAL / 1000)) / 32) & 0x1ff;
 517         adiv = ( ((p->frequency * vco_div * 10) / (2 * XTAL / 1000)) % 32) & 0x1f;
 518
 519         if (adiv == 0)
 520                 ndiv++;
 521
 522         /* control bits 11, refdiv 11, charge pump polarity 1, charge pump current, ndiv, adiv */
 523         state->pllarg = (3 << 19) | (3 << 17) | (1 << 16) | (pump << 14) | (ndiv << 5) | adiv;
 524
 525         return 0;
 526 }
 527
 528 /*
 529  * Tuner data is 21 bits long, must be left-aligned in data.
 530  * Tuner cx24109 is written through a dedicated 3wire interface on the demod chip.
 531  */
 532 static int cx24123_pll_writereg(struct dvb_frontend* fe, struct dvb_frontend_parameters *p, u32 data)
 533 {
 534         struct cx24123_state *state = fe->demodulator_priv;
 535         unsigned long timeout;
 536
 537         dprintk("%s:  pll writereg called, data=0x%08x\n",__FUNCTION__,data);
 538
 539         /* align the 21 bytes into to bit23 boundary */
 540         data = data << 3;
 541
 542         /* Reset the demod pll word length to 0x15 bits */
 543         cx24123_writereg(state, 0x21, 0x15);
 544
 545         /* write the msb 8 bits, wait for the send to be completed */
 546         timeout = jiffies + msecs_to_jiffies(40);
 547         cx24123_writereg(state, 0x22, (data >> 16) & 0xff);
 548         while ((cx24123_readreg(state, 0x20) & 0x40) == 0) {
 549                 if (time_after(jiffies, timeout)) {
 550                         printk("%s:  demodulator is not responding, possibly hung, aborting.\n", __FUNCTION__);
 551                         return -EREMOTEIO;
 552                 }
 553                 msleep(10);
 554         }
 555
 556         /* send another 8 bytes, wait for the send to be completed */
 557         timeout = jiffies + msecs_to_jiffies(40);
 558         cx24123_writereg(state, 0x22, (data>>8) & 0xff );
 559         while ((cx24123_readreg(state, 0x20) & 0x40) == 0) {
 560                 if (time_after(jiffies, timeout)) {
 561                         printk("%s:  demodulator is not responding, possibly hung, aborting.\n", __FUNCTION__);
 562                         return -EREMOTEIO;
 563                 }
 564                 msleep(10);
 565         }
 566
 567         /* send the lower 5 bits of this byte, padded with 3 LBB, wait for the send to be completed */
 568         timeout = jiffies + msecs_to_jiffies(40);
 569         cx24123_writereg(state, 0x22, (data) & 0xff );
 570         while ((cx24123_readreg(state, 0x20) & 0x80)) {
 571                 if (time_after(jiffies, timeout)) {
 572                         printk("%s:  demodulator is not responding, possibly hung, aborting.\n", __FUNCTION__);
 573                         return -EREMOTEIO;
 574                 }
 575                 msleep(10);
 576         }
 577
 578         /* Trigger the demod to configure the tuner */
 579         cx24123_writereg(state, 0x20, cx24123_readreg(state, 0x20) | 2);
 580         cx24123_writereg(state, 0x20, cx24123_readreg(state, 0x20) & 0xfd);
 581
 582         return 0;
 583 }
 584
 585 static int cx24123_pll_tune(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
 586 {
 587         struct cx24123_state *state = fe->demodulator_priv;
 588         u8 val;
 589
 590         dprintk("frequency=%i\n", p->frequency);
 591
 592         if (cx24123_pll_calculate(fe, p) != 0) {
 593                 printk("%s: cx24123_pll_calcutate failed\n",__FUNCTION__);
 594                 return -EINVAL;
 595         }
 596
 597         /* Write the new VCO/VGA */
 598         cx24123_pll_writereg(fe, p, state->VCAarg);
 599         cx24123_pll_writereg(fe, p, state->VGAarg);
 600
 601         /* Write the new bandselect and pll args */
 602         cx24123_pll_writereg(fe, p, state->bandselectarg);
 603         cx24123_pll_writereg(fe, p, state->pllarg);
 604
 605         /* set the FILTUNE voltage */
 606         val = cx24123_readreg(state, 0x28) & ~0x3;
 607         cx24123_writereg(state, 0x27, state->FILTune >> 2);
 608         cx24123_writereg(state, 0x28, val | (state->FILTune & 0x3));
 609
 610         dprintk("%s:  pll tune VCA=%d, band=%d, pll=%d\n",__FUNCTION__,state->VCAarg,
 611                         state->bandselectarg,state->pllarg);
 612
 613         return 0;
 614 }
 615
 616 static int cx24123_initfe(struct dvb_frontend* fe)
 617 {
 618         struct cx24123_state *state = fe->demodulator_priv;
 619         int i;
 620
 621         dprintk("%s:  init frontend\n",__FUNCTION__);
 622
 623         /* Configure the demod to a good set of defaults */
 624         for (i = 0; i < sizeof(cx24123_regdata) / sizeof(cx24123_regdata[0]); i++)
 625                 cx24123_writereg(state, cx24123_regdata[i].reg, cx24123_regdata[i].data);
 626
 627         if (state->config->pll_init)
 628                 state->config->pll_init(fe);
 629
 630         /* Configure the LNB for 14V */
 631         if (state->config->use_isl6421)
 632                 cx24123_writelnbreg(state, 0x0, 0x2a);
 633
 634         return 0;
 635 }
 636
 637 static int cx24123_set_voltage(struct dvb_frontend* fe, fe_sec_voltage_t voltage)
 638 {
 639         struct cx24123_state *state = fe->demodulator_priv;
 640         u8 val;
 641
 642         switch (state->config->use_isl6421) {
 643
 644         case 1:
 645
 646                 val = cx24123_readlnbreg(state, 0x0);
 647
 648                 switch (voltage) {
 649                 case SEC_VOLTAGE_13:
 650                         dprintk("%s:  isl6421 voltage = 13V\n",__FUNCTION__);
 651                         return cx24123_writelnbreg(state, 0x0, val & 0x32); /* V 13v */
 652                 case SEC_VOLTAGE_18:
 653                         dprintk("%s:  isl6421 voltage = 18V\n",__FUNCTION__);
 654                         return cx24123_writelnbreg(state, 0x0, val | 0x04); /* H 18v */
 655                 case SEC_VOLTAGE_OFF:
 656                         dprintk("%s:  isl5421 voltage off\n",__FUNCTION__);
 657                         return cx24123_writelnbreg(state, 0x0, val & 0x30);
 658                 default:
 659                         return -EINVAL;
 660                 };
 661
 662         case 0:
 663
 664                 val = cx24123_readreg(state, 0x29);
 665
 666                 switch (voltage) {
 667                 case SEC_VOLTAGE_13:
 668                         dprintk("%s: setting voltage 13V\n", __FUNCTION__);
 669                         if (state->config->enable_lnb_voltage)
 670                                 state->config->enable_lnb_voltage(fe, 1);
 671                         return cx24123_writereg(state, 0x29, val | 0x80);
 672                 case SEC_VOLTAGE_18:
 673                         dprintk("%s: setting voltage 18V\n", __FUNCTION__);
 674                         if (state->config->enable_lnb_voltage)
 675                                 state->config->enable_lnb_voltage(fe, 1);
 676                         return cx24123_writereg(state, 0x29, val & 0x7f);
 677                 case SEC_VOLTAGE_OFF:
 678                         dprintk("%s: setting voltage off\n", __FUNCTION__);
 679                         if (state->config->enable_lnb_voltage)
 680                                 state->config->enable_lnb_voltage(fe, 0);
 681                         return 0;
 682                 default:
 683                         return -EINVAL;
 684                 };
 685         }
 686
 687         return 0;
 688 }
 689
 690 /* wait for diseqc queue to become ready (or timeout) */
 691 static void cx24123_wait_for_diseqc(struct cx24123_state *state)
 692 {
 693         unsigned long timeout = jiffies + msecs_to_jiffies(200);
 694         while (!(cx24123_readreg(state, 0x29) & 0x40)) {
 695                 if(time_after(jiffies, timeout)) {
 696                         printk("%s: diseqc queue not ready, command may be lost.\n", __FUNCTION__);
 697                         break;
 698                 }
 699                 msleep(10);
 700         }
 701 }
 702
 703 static int cx24123_send_diseqc_msg(struct dvb_frontend* fe, struct dvb_diseqc_master_cmd *cmd)
 704 {
 705         struct cx24123_state *state = fe->demodulator_priv;
 706         int i, val;
 707
 708         dprintk("%s:\n",__FUNCTION__);
 709
 710         /* check if continuous tone has been stopped */
 711         if (state->config->use_isl6421)
 712                 val = cx24123_readlnbreg(state, 0x00) & 0x10;
 713         else
 714                 val = cx24123_readreg(state, 0x29) & 0x10;
 715
 716
 717         if (val) {
 718                 printk("%s: ERROR: attempt to send diseqc command before tone is off\n", __FUNCTION__);
 719                 return -ENOTSUPP;
 720         }
 721
 722         /* wait for diseqc queue ready */
 723         cx24123_wait_for_diseqc(state);
 724
 725         /* select tone mode */
 726         cx24123_writereg(state, 0x2a, cx24123_readreg(state, 0x2a) & 0xf8);
 727
 728         for (i = 0; i < cmd->msg_len; i++)
 729                 cx24123_writereg(state, 0x2C + i, cmd->msg[i]);
 730
 731         val = cx24123_readreg(state, 0x29);
 732         cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40) | ((cmd->msg_len-3) & 3));
 733
 734         /* wait for diseqc message to finish sending */
 735         cx24123_wait_for_diseqc(state);
 736
 737         return 0;
 738 }
 739
 740 static int cx24123_diseqc_send_burst(struct dvb_frontend* fe, fe_sec_mini_cmd_t burst)
 741 {
 742         struct cx24123_state *state = fe->demodulator_priv;
 743         int val;
 744
 745         dprintk("%s:\n", __FUNCTION__);
 746
 747         /* check if continuous tone has been stoped */
 748         if (state->config->use_isl6421)
 749                 val = cx24123_readlnbreg(state, 0x00) & 0x10;
 750         else
 751                 val = cx24123_readreg(state, 0x29) & 0x10;
 752
 753
 754         if (val) {
 755                 printk("%s: ERROR: attempt to send diseqc command before tone is off\n", __FUNCTION__);
 756                 return -ENOTSUPP;
 757         }
 758
 759         cx24123_wait_for_diseqc(state);
 760
 761         /* select tone mode */
 762         val = cx24123_readreg(state, 0x2a) & 0xf8;
 763         cx24123_writereg(state, 0x2a, val | 0x04);
 764
 765         val = cx24123_readreg(state, 0x29);
 766
 767         if (burst == SEC_MINI_A)
 768                 cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40 | 0x00));
 769         else if (burst == SEC_MINI_B)
 770                 cx24123_writereg(state, 0x29, ((val & 0x90) | 0x40 | 0x08));
 771         else
 772                 return -EINVAL;
 773
 774         cx24123_wait_for_diseqc(state);
 775
 776         return 0;
 777 }
 778
 779 static int cx24123_read_status(struct dvb_frontend* fe, fe_status_t* status)
 780 {
 781         struct cx24123_state *state = fe->demodulator_priv;
 782
 783         int sync = cx24123_readreg(state, 0x14);
 784         int lock = cx24123_readreg(state, 0x20);
 785
 786         *status = 0;
 787         if (lock & 0x01)
 788                 *status |= FE_HAS_SIGNAL;
 789         if (sync & 0x02)
 790                 *status |= FE_HAS_CARRIER;
 791         if (sync & 0x04)
 792                 *status |= FE_HAS_VITERBI;
 793         if (sync & 0x08)
 794                 *status |= FE_HAS_SYNC;
 795         if (sync & 0x80)
 796                 *status |= FE_HAS_LOCK;
 797
 798         return 0;
 799 }
 800
 801 /*
 802  * Configured to return the measurement of errors in blocks, because no UCBLOCKS value
 803  * is available, so this value doubles up to satisfy both measurements
 804  */
 805 static int cx24123_read_ber(struct dvb_frontend* fe, u32* ber)
 806 {
 807         struct cx24123_state *state = fe->demodulator_priv;
 808
 809         state->lastber =
 810                 ((cx24123_readreg(state, 0x1c) & 0x3f) << 16) |
 811                 (cx24123_readreg(state, 0x1d) << 8 |
 812                 cx24123_readreg(state, 0x1e));
 813
 814         /* Do the signal quality processing here, it's derived from the BER. */
 815         /* Scale the BER from a 24bit to a SNR 16 bit where higher = better */
 816         if (state->lastber < 5000)
 817                 state->snr = 655*100;
 818         else if ( (state->lastber >=   5000) && (state->lastber <  55000) )
 819                 state->snr = 655*90;
 820         else if ( (state->lastber >=  55000) && (state->lastber < 150000) )
 821                 state->snr = 655*80;
 822         else if ( (state->lastber >= 150000) && (state->lastber < 250000) )
 823                 state->snr = 655*70;
 824         else if ( (state->lastber >= 250000) && (state->lastber < 450000) )
 825                 state->snr = 655*65;
 826         else
 827                 state->snr = 0;
 828
 829         dprintk("%s:  BER = %d, S/N index = %d\n",__FUNCTION__,state->lastber, state->snr);
 830
 831         *ber = state->lastber;
 832
 833         return 0;
 834 }
 835
 836 static int cx24123_read_signal_strength(struct dvb_frontend* fe, u16* signal_strength)
 837 {
 838         struct cx24123_state *state = fe->demodulator_priv;
 839         *signal_strength = cx24123_readreg(state, 0x3b) << 8; /* larger = better */
 840
 841         dprintk("%s:  Signal strength = %d\n",__FUNCTION__,*signal_strength);
 842
 843         return 0;
 844 }
 845
 846 static int cx24123_read_snr(struct dvb_frontend* fe, u16* snr)
 847 {
 848         struct cx24123_state *state = fe->demodulator_priv;
 849         *snr = state->snr;
 850
 851         dprintk("%s:  read S/N index = %d\n",__FUNCTION__,*snr);
 852
 853         return 0;
 854 }
 855
 856 static int cx24123_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
 857 {
 858         struct cx24123_state *state = fe->demodulator_priv;
 859         *ucblocks = state->lastber;
 860
 861         dprintk("%s:  ucblocks (ber) = %d\n",__FUNCTION__,*ucblocks);
 862
 863         return 0;
 864 }
 865
 866 static int cx24123_set_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
 867 {
 868         struct cx24123_state *state = fe->demodulator_priv;
 869
 870         dprintk("%s:  set_frontend\n",__FUNCTION__);
 871
 872         if (state->config->set_ts_params)
 873                 state->config->set_ts_params(fe, 0);
 874
 875         state->currentfreq=p->frequency;
 876         state->currentsymbolrate = p->u.qpsk.symbol_rate;
 877
 878         cx24123_set_inversion(state, p->inversion);
 879         cx24123_set_fec(state, p->u.qpsk.fec_inner);
 880         cx24123_set_symbolrate(state, p->u.qpsk.symbol_rate);
 881         cx24123_pll_tune(fe, p);
 882
 883         /* Enable automatic aquisition and reset cycle */
 884         cx24123_writereg(state, 0x03, (cx24123_readreg(state, 0x03) | 0x07));
 885         cx24123_writereg(state, 0x00, 0x10);
 886         cx24123_writereg(state, 0x00, 0);
 887
 888         return 0;
 889 }
 890
 891 static int cx24123_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
 892 {
 893         struct cx24123_state *state = fe->demodulator_priv;
 894
 895         dprintk("%s:  get_frontend\n",__FUNCTION__);
 896
 897         if (cx24123_get_inversion(state, &p->inversion) != 0) {
 898                 printk("%s: Failed to get inversion status\n",__FUNCTION__);
 899                 return -EREMOTEIO;
 900         }
 901         if (cx24123_get_fec(state, &p->u.qpsk.fec_inner) != 0) {
 902                 printk("%s: Failed to get fec status\n",__FUNCTION__);
 903                 return -EREMOTEIO;
 904         }
 905         p->frequency = state->currentfreq;
 906         p->u.qpsk.symbol_rate = state->currentsymbolrate;
 907
 908         return 0;
 909 }
 910
 911 static int cx24123_set_tone(struct dvb_frontend* fe, fe_sec_tone_mode_t tone)
 912 {
 913         struct cx24123_state *state = fe->demodulator_priv;
 914         u8 val;
 915
 916         switch (state->config->use_isl6421) {
 917         case 1:
 918
 919                 val = cx24123_readlnbreg(state, 0x0);
 920
 921                 switch (tone) {
 922                 case SEC_TONE_ON:
 923                         dprintk("%s:  isl6421 sec tone on\n",__FUNCTION__);
 924                         return cx24123_writelnbreg(state, 0x0, val | 0x10);
 925                 case SEC_TONE_OFF:
 926                         dprintk("%s:  isl6421 sec tone off\n",__FUNCTION__);
 927                         return cx24123_writelnbreg(state, 0x0, val & 0x2f);
 928                 default:
 929                         printk("%s: CASE reached default with tone=%d\n", __FUNCTION__, tone);
 930                         return -EINVAL;
 931                 }
 932
 933         case 0:
 934
 935                 val = cx24123_readreg(state, 0x29);
 936
 937                 switch (tone) {
 938                 case SEC_TONE_ON:
 939                         dprintk("%s: setting tone on\n", __FUNCTION__);
 940                         return cx24123_writereg(state, 0x29, val | 0x10);
 941                 case SEC_TONE_OFF:
 942                         dprintk("%s: setting tone off\n",__FUNCTION__);
 943                         return cx24123_writereg(state, 0x29, val & 0xef);
 944                 default:
 945                         printk("%s: CASE reached default with tone=%d\n", __FUNCTION__, tone);
 946                         return -EINVAL;
 947                 }
 948         }
 949
 950         return 0;
 951 }
 952
 953 static void cx24123_release(struct dvb_frontend* fe)
 954 {
 955         struct cx24123_state* state = fe->demodulator_priv;
 956         dprintk("%s\n",__FUNCTION__);
 957         kfree(state);
 958 }
 959
 960 static struct dvb_frontend_ops cx24123_ops;
 961
 962 struct dvb_frontend* cx24123_attach(const struct cx24123_config* config,
 963                                     struct i2c_adapter* i2c)
 964 {
 965         struct cx24123_state* state = NULL;
 966         int ret;
 967
 968         dprintk("%s\n",__FUNCTION__);
 969
 970         /* allocate memory for the internal state */
 971         state = kmalloc(sizeof(struct cx24123_state), GFP_KERNEL);
 972         if (state == NULL) {
 973                 printk("Unable to kmalloc\n");
 974                 goto error;
 975         }
 976
 977         /* setup the state */
 978         state->config = config;
 979         state->i2c = i2c;
 980         memcpy(&state->ops, &cx24123_ops, sizeof(struct dvb_frontend_ops));
 981         state->lastber = 0;
 982         state->snr = 0;
 983         state->lnbreg = 0;
 984         state->VCAarg = 0;
 985         state->VGAarg = 0;
 986         state->bandselectarg = 0;
 987         state->pllarg = 0;
 988         state->currentfreq = 0;
 989         state->currentsymbolrate = 0;
 990
 991         /* check if the demod is there */
 992         ret = cx24123_readreg(state, 0x00);
 993         if ((ret != 0xd1) && (ret != 0xe1)) {
 994                 printk("Version != d1 or e1\n");
 995                 goto error;
 996         }
 997
 998         /* create dvb_frontend */
 999         state->frontend.ops = &state->ops;
1000         state->frontend.demodulator_priv = state;
1001         return &state->frontend;
1002
1003 error:
1004         kfree(state);
1005
1006         return NULL;
1007 }
1008
1009 static struct dvb_frontend_ops cx24123_ops = {
1010
1011         .info = {
1012                 .name = "Conexant CX24123/CX24109",
1013                 .type = FE_QPSK,
1014                 .frequency_min = 950000,
1015                 .frequency_max = 2150000,
1016                 .frequency_stepsize = 1011, /* kHz for QPSK frontends */
1017                 .frequency_tolerance = 29500,
1018                 .symbol_rate_min = 1000000,
1019                 .symbol_rate_max = 45000000,
1020                 .caps = FE_CAN_INVERSION_AUTO |
1021                         FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1022                         FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1023                         FE_CAN_QPSK | FE_CAN_RECOVER
1024         },
1025
1026         .release = cx24123_release,
1027
1028         .init = cx24123_initfe,
1029         .set_frontend = cx24123_set_frontend,
1030         .get_frontend = cx24123_get_frontend,
1031         .read_status = cx24123_read_status,
1032         .read_ber = cx24123_read_ber,
1033         .read_signal_strength = cx24123_read_signal_strength,
1034         .read_snr = cx24123_read_snr,
1035         .read_ucblocks = cx24123_read_ucblocks,
1036         .diseqc_send_master_cmd = cx24123_send_diseqc_msg,
1037         .diseqc_send_burst = cx24123_diseqc_send_burst,
1038         .set_tone = cx24123_set_tone,
1039         .set_voltage = cx24123_set_voltage,
1040 };
1041
1042 module_param(debug, int, 0644);
1043 MODULE_PARM_DESC(debug, "Activates frontend debugging (default:0)");
1044
1045 MODULE_DESCRIPTION("DVB Frontend module for Conexant cx24123/cx24109 hardware");
1046 MODULE_AUTHOR("Steven Toth");
1047 MODULE_LICENSE("GPL");
1048
1049 EXPORT_SYMBOL(cx24123_attach);