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   1 /*  $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
   2  *  arch/sparc64/mm/init.c
   3  *
   4  *  Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
   5  *  Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
   6  */
   7
   8 #include <linux/config.h>
   9 #include <linux/kernel.h>
  10 #include <linux/sched.h>
  11 #include <linux/string.h>
  12 #include <linux/init.h>
  13 #include <linux/bootmem.h>
  14 #include <linux/mm.h>
  15 #include <linux/hugetlb.h>
  16 #include <linux/slab.h>
  17 #include <linux/initrd.h>
  18 #include <linux/swap.h>
  19 #include <linux/pagemap.h>
  20 #include <linux/fs.h>
  21 #include <linux/seq_file.h>
  22 #include <linux/kprobes.h>
  23 #include <linux/cache.h>
  24 #include <linux/sort.h>
  25
  26 #include <asm/head.h>
  27 #include <asm/system.h>
  28 #include <asm/page.h>
  29 #include <asm/pgalloc.h>
  30 #include <asm/pgtable.h>
  31 #include <asm/oplib.h>
  32 #include <asm/iommu.h>
  33 #include <asm/io.h>
  34 #include <asm/uaccess.h>
  35 #include <asm/mmu_context.h>
  36 #include <asm/tlbflush.h>
  37 #include <asm/dma.h>
  38 #include <asm/starfire.h>
  39 #include <asm/tlb.h>
  40 #include <asm/spitfire.h>
  41 #include <asm/sections.h>
  42
  43 extern void device_scan(void);
  44
  45 #define MAX_BANKS       32
  46
  47 static struct linux_prom64_registers pavail[MAX_BANKS] __initdata;
  48 static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
  49 static int pavail_ents __initdata;
  50 static int pavail_rescan_ents __initdata;
  51
  52 static int cmp_p64(const void *a, const void *b)
  53 {
  54         const struct linux_prom64_registers *x = a, *y = b;
  55
  56         if (x->phys_addr > y->phys_addr)
  57                 return 1;
  58         if (x->phys_addr < y->phys_addr)
  59                 return -1;
  60         return 0;
  61 }
  62
  63 static void __init read_obp_memory(const char *property,
  64                                    struct linux_prom64_registers *regs,
  65                                    int *num_ents)
  66 {
  67         int node = prom_finddevice("/memory");
  68         int prop_size = prom_getproplen(node, property);
  69         int ents, ret, i;
  70
  71         ents = prop_size / sizeof(struct linux_prom64_registers);
  72         if (ents > MAX_BANKS) {
  73                 prom_printf("The machine has more %s property entries than "
  74                             "this kernel can support (%d).\n",
  75                             property, MAX_BANKS);
  76                 prom_halt();
  77         }
  78
  79         ret = prom_getproperty(node, property, (char *) regs, prop_size);
  80         if (ret == -1) {
  81                 prom_printf("Couldn't get %s property from /memory.\n");
  82                 prom_halt();
  83         }
  84
  85         *num_ents = ents;
  86
  87         /* Sanitize what we got from the firmware, by page aligning
  88          * everything.
  89          */
  90         for (i = 0; i < ents; i++) {
  91                 unsigned long base, size;
  92
  93                 base = regs[i].phys_addr;
  94                 size = regs[i].reg_size;
  95
  96                 size &= PAGE_MASK;
  97                 if (base & ~PAGE_MASK) {
  98                         unsigned long new_base = PAGE_ALIGN(base);
  99
 100                         size -= new_base - base;
 101                         if ((long) size < 0L)
 102                                 size = 0UL;
 103                         base = new_base;
 104                 }
 105                 regs[i].phys_addr = base;
 106                 regs[i].reg_size = size;
 107         }
 108         sort(regs, ents, sizeof(struct  linux_prom64_registers),
 109              cmp_p64, NULL);
 110 }
 111
 112 unsigned long *sparc64_valid_addr_bitmap __read_mostly;
 113
 114 /* Ugly, but necessary... -DaveM */
 115 unsigned long phys_base __read_mostly;
 116 unsigned long kern_base __read_mostly;
 117 unsigned long kern_size __read_mostly;
 118 unsigned long pfn_base __read_mostly;
 119
 120 /* get_new_mmu_context() uses "cache + 1".  */
 121 DEFINE_SPINLOCK(ctx_alloc_lock);
 122 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
 123 #define CTX_BMAP_SLOTS (1UL << (CTX_NR_BITS - 6))
 124 unsigned long mmu_context_bmap[CTX_BMAP_SLOTS];
 125
 126 /* References to special section boundaries */
 127 extern char  _start[], _end[];
 128
 129 /* Initial ramdisk setup */
 130 extern unsigned long sparc_ramdisk_image64;
 131 extern unsigned int sparc_ramdisk_image;
 132 extern unsigned int sparc_ramdisk_size;
 133
 134 struct page *mem_map_zero __read_mostly;
 135
 136 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
 137
 138 unsigned long sparc64_kern_pri_context __read_mostly;
 139 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
 140 unsigned long sparc64_kern_sec_context __read_mostly;
 141
 142 int bigkernel = 0;
 143
 144 /* XXX Tune this... */
 145 #define PGT_CACHE_LOW   25
 146 #define PGT_CACHE_HIGH  50
 147
 148 void check_pgt_cache(void)
 149 {
 150         preempt_disable();
 151         if (pgtable_cache_size > PGT_CACHE_HIGH) {
 152                 do {
 153                         if (pgd_quicklist)
 154                                 free_pgd_slow(get_pgd_fast());
 155                         if (pte_quicklist[0])
 156                                 free_pte_slow(pte_alloc_one_fast(NULL, 0));
 157                         if (pte_quicklist[1])
 158                                 free_pte_slow(pte_alloc_one_fast(NULL, 1 << (PAGE_SHIFT + 10)));
 159                 } while (pgtable_cache_size > PGT_CACHE_LOW);
 160         }
 161         preempt_enable();
 162 }
 163
 164 #ifdef CONFIG_DEBUG_DCFLUSH
 165 atomic_t dcpage_flushes = ATOMIC_INIT(0);
 166 #ifdef CONFIG_SMP
 167 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
 168 #endif
 169 #endif
 170
 171 __inline__ void flush_dcache_page_impl(struct page *page)
 172 {
 173 #ifdef CONFIG_DEBUG_DCFLUSH
 174         atomic_inc(&dcpage_flushes);
 175 #endif
 176
 177 #ifdef DCACHE_ALIASING_POSSIBLE
 178         __flush_dcache_page(page_address(page),
 179                             ((tlb_type == spitfire) &&
 180                              page_mapping(page) != NULL));
 181 #else
 182         if (page_mapping(page) != NULL &&
 183             tlb_type == spitfire)
 184                 __flush_icache_page(__pa(page_address(page)));
 185 #endif
 186 }
 187
 188 #define PG_dcache_dirty         PG_arch_1
 189 #define PG_dcache_cpu_shift     24
 190 #define PG_dcache_cpu_mask      (256 - 1)
 191
 192 #if NR_CPUS > 256
 193 #error D-cache dirty tracking and thread_info->cpu need fixing for > 256 cpus
 194 #endif
 195
 196 #define dcache_dirty_cpu(page) \
 197         (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
 198
 199 static __inline__ void set_dcache_dirty(struct page *page, int this_cpu)
 200 {
 201         unsigned long mask = this_cpu;
 202         unsigned long non_cpu_bits;
 203
 204         non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
 205         mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
 206
 207         __asm__ __volatile__("1:\n\t"
 208                              "ldx       [%2], %%g7\n\t"
 209                              "and       %%g7, %1, %%g1\n\t"
 210                              "or        %%g1, %0, %%g1\n\t"
 211                              "casx      [%2], %%g7, %%g1\n\t"
 212                              "cmp       %%g7, %%g1\n\t"
 213                              "membar    #StoreLoad | #StoreStore\n\t"
 214                              "bne,pn    %%xcc, 1b\n\t"
 215                              " nop"
 216                              : /* no outputs */
 217                              : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
 218                              : "g1", "g7");
 219 }
 220
 221 static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
 222 {
 223         unsigned long mask = (1UL << PG_dcache_dirty);
 224
 225         __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
 226                              "1:\n\t"
 227                              "ldx       [%2], %%g7\n\t"
 228                              "srlx      %%g7, %4, %%g1\n\t"
 229                              "and       %%g1, %3, %%g1\n\t"
 230                              "cmp       %%g1, %0\n\t"
 231                              "bne,pn    %%icc, 2f\n\t"
 232                              " andn     %%g7, %1, %%g1\n\t"
 233                              "casx      [%2], %%g7, %%g1\n\t"
 234                              "cmp       %%g7, %%g1\n\t"
 235                              "membar    #StoreLoad | #StoreStore\n\t"
 236                              "bne,pn    %%xcc, 1b\n\t"
 237                              " nop\n"
 238                              "2:"
 239                              : /* no outputs */
 240                              : "r" (cpu), "r" (mask), "r" (&page->flags),
 241                                "i" (PG_dcache_cpu_mask),
 242                                "i" (PG_dcache_cpu_shift)
 243                              : "g1", "g7");
 244 }
 245
 246 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
 247 {
 248         struct page *page;
 249         unsigned long pfn;
 250         unsigned long pg_flags;
 251
 252         pfn = pte_pfn(pte);
 253         if (pfn_valid(pfn) &&
 254             (page = pfn_to_page(pfn), page_mapping(page)) &&
 255             ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
 256                 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
 257                            PG_dcache_cpu_mask);
 258                 int this_cpu = get_cpu();
 259
 260                 /* This is just to optimize away some function calls
 261                  * in the SMP case.
 262                  */
 263                 if (cpu == this_cpu)
 264                         flush_dcache_page_impl(page);
 265                 else
 266                         smp_flush_dcache_page_impl(page, cpu);
 267
 268                 clear_dcache_dirty_cpu(page, cpu);
 269
 270                 put_cpu();
 271         }
 272 }
 273
 274 void flush_dcache_page(struct page *page)
 275 {
 276         struct address_space *mapping;
 277         int this_cpu;
 278
 279         /* Do not bother with the expensive D-cache flush if it
 280          * is merely the zero page.  The 'bigcore' testcase in GDB
 281          * causes this case to run millions of times.
 282          */
 283         if (page == ZERO_PAGE(0))
 284                 return;
 285
 286         this_cpu = get_cpu();
 287
 288         mapping = page_mapping(page);
 289         if (mapping && !mapping_mapped(mapping)) {
 290                 int dirty = test_bit(PG_dcache_dirty, &page->flags);
 291                 if (dirty) {
 292                         int dirty_cpu = dcache_dirty_cpu(page);
 293
 294                         if (dirty_cpu == this_cpu)
 295                                 goto out;
 296                         smp_flush_dcache_page_impl(page, dirty_cpu);
 297                 }
 298                 set_dcache_dirty(page, this_cpu);
 299         } else {
 300                 /* We could delay the flush for the !page_mapping
 301                  * case too.  But that case is for exec env/arg
 302                  * pages and those are %99 certainly going to get
 303                  * faulted into the tlb (and thus flushed) anyways.
 304                  */
 305                 flush_dcache_page_impl(page);
 306         }
 307
 308 out:
 309         put_cpu();
 310 }
 311
 312 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
 313 {
 314         /* Cheetah has coherent I-cache. */
 315         if (tlb_type == spitfire) {
 316                 unsigned long kaddr;
 317
 318                 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE)
 319                         __flush_icache_page(__get_phys(kaddr));
 320         }
 321 }
 322
 323 unsigned long page_to_pfn(struct page *page)
 324 {
 325         return (unsigned long) ((page - mem_map) + pfn_base);
 326 }
 327
 328 struct page *pfn_to_page(unsigned long pfn)
 329 {
 330         return (mem_map + (pfn - pfn_base));
 331 }
 332
 333 void show_mem(void)
 334 {
 335         printk("Mem-info:\n");
 336         show_free_areas();
 337         printk("Free swap:       %6ldkB\n",
 338                nr_swap_pages << (PAGE_SHIFT-10));
 339         printk("%ld pages of RAM\n", num_physpages);
 340         printk("%d free pages\n", nr_free_pages());
 341         printk("%d pages in page table cache\n",pgtable_cache_size);
 342 }
 343
 344 void mmu_info(struct seq_file *m)
 345 {
 346         if (tlb_type == cheetah)
 347                 seq_printf(m, "MMU Type\t: Cheetah\n");
 348         else if (tlb_type == cheetah_plus)
 349                 seq_printf(m, "MMU Type\t: Cheetah+\n");
 350         else if (tlb_type == spitfire)
 351                 seq_printf(m, "MMU Type\t: Spitfire\n");
 352         else
 353                 seq_printf(m, "MMU Type\t: ???\n");
 354
 355 #ifdef CONFIG_DEBUG_DCFLUSH
 356         seq_printf(m, "DCPageFlushes\t: %d\n",
 357                    atomic_read(&dcpage_flushes));
 358 #ifdef CONFIG_SMP
 359         seq_printf(m, "DCPageFlushesXC\t: %d\n",
 360                    atomic_read(&dcpage_flushes_xcall));
 361 #endif /* CONFIG_SMP */
 362 #endif /* CONFIG_DEBUG_DCFLUSH */
 363 }
 364
 365 struct linux_prom_translation {
 366         unsigned long virt;
 367         unsigned long size;
 368         unsigned long data;
 369 };
 370 static struct linux_prom_translation prom_trans[512] __initdata;
 371 static unsigned int prom_trans_ents __initdata;
 372
 373 extern unsigned long prom_boot_page;
 374 extern void prom_remap(unsigned long physpage, unsigned long virtpage, int mmu_ihandle);
 375 extern int prom_get_mmu_ihandle(void);
 376 extern void register_prom_callbacks(void);
 377
 378 /* Exported for SMP bootup purposes. */
 379 unsigned long kern_locked_tte_data;
 380
 381 /* Exported for kernel TLB miss handling in ktlb.S */
 382 unsigned long prom_pmd_phys __read_mostly;
 383 unsigned int swapper_pgd_zero __read_mostly;
 384
 385 static pmd_t *prompmd __read_mostly;
 386
 387 #define BASE_PAGE_SIZE 8192
 388
 389 /*
 390  * Translate PROM's mapping we capture at boot time into physical address.
 391  * The second parameter is only set from prom_callback() invocations.
 392  */
 393 unsigned long prom_virt_to_phys(unsigned long promva, int *error)
 394 {
 395         pmd_t *pmdp = prompmd + ((promva >> 23) & 0x7ff);
 396         pte_t *ptep;
 397         unsigned long base;
 398
 399         if (pmd_none(*pmdp)) {
 400                 if (error)
 401                         *error = 1;
 402                 return 0;
 403         }
 404         ptep = (pte_t *)__pmd_page(*pmdp) + ((promva >> 13) & 0x3ff);
 405         if (!pte_present(*ptep)) {
 406                 if (error)
 407                         *error = 1;
 408                 return 0;
 409         }
 410         if (error) {
 411                 *error = 0;
 412                 return pte_val(*ptep);
 413         }
 414         base = pte_val(*ptep) & _PAGE_PADDR;
 415
 416         return base + (promva & (BASE_PAGE_SIZE - 1));
 417 }
 418
 419 /* The obp translations are saved based on 8k pagesize, since obp can
 420  * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
 421  * HI_OBP_ADDRESS range are handled in entry.S and do not use the vpte
 422  * scheme (also, see rant in inherit_locked_prom_mappings()).
 423  */
 424 static void __init build_obp_range(unsigned long start, unsigned long end, unsigned long data)
 425 {
 426         unsigned long vaddr;
 427
 428         for (vaddr = start; vaddr < end; vaddr += BASE_PAGE_SIZE) {
 429                 unsigned long val;
 430                 pmd_t *pmd;
 431                 pte_t *pte;
 432
 433                 pmd = prompmd + ((vaddr >> 23) & 0x7ff);
 434                 if (pmd_none(*pmd)) {
 435                         pte = __alloc_bootmem(BASE_PAGE_SIZE, BASE_PAGE_SIZE,
 436                                               PAGE_SIZE);
 437                         if (!pte)
 438                                 prom_halt();
 439                         memset(pte, 0, BASE_PAGE_SIZE);
 440                         pmd_set(pmd, pte);
 441                 }
 442                 pte = (pte_t *) __pmd_page(*pmd) + ((vaddr >> 13) & 0x3ff);
 443
 444                 val = data;
 445
 446                 /* Clear diag TTE bits. */
 447                 if (tlb_type == spitfire)
 448                         val &= ~0x0003fe0000000000UL;
 449
 450                 set_pte_at(&init_mm, vaddr, pte,
 451                            __pte(val | _PAGE_MODIFIED));
 452
 453                 data += BASE_PAGE_SIZE;
 454         }
 455 }
 456
 457 static inline int in_obp_range(unsigned long vaddr)
 458 {
 459         return (vaddr >= LOW_OBP_ADDRESS &&
 460                 vaddr < HI_OBP_ADDRESS);
 461 }
 462
 463 #define OBP_PMD_SIZE 2048
 464 static void __init build_obp_pgtable(void)
 465 {
 466         unsigned long i;
 467
 468         prompmd = __alloc_bootmem(OBP_PMD_SIZE, OBP_PMD_SIZE, PAGE_SIZE);
 469         if (!prompmd)
 470                 prom_halt();
 471
 472         memset(prompmd, 0, OBP_PMD_SIZE);
 473
 474         prom_pmd_phys = __pa(prompmd);
 475
 476         for (i = 0; i < prom_trans_ents; i++) {
 477                 unsigned long start, end;
 478
 479                 if (!in_obp_range(prom_trans[i].virt))
 480                         continue;
 481
 482                 start = prom_trans[i].virt;
 483                 end = start + prom_trans[i].size;
 484                 if (end > HI_OBP_ADDRESS)
 485                         end = HI_OBP_ADDRESS;
 486
 487                 build_obp_range(start, end, prom_trans[i].data);
 488         }
 489 }
 490
 491 /* Read OBP translations property into 'prom_trans[]'.
 492  * Return the number of entries.
 493  */
 494 static void __init read_obp_translations(void)
 495 {
 496         int n, node;
 497
 498         node = prom_finddevice("/virtual-memory");
 499         n = prom_getproplen(node, "translations");
 500         if (unlikely(n == 0 || n == -1)) {
 501                 prom_printf("prom_mappings: Couldn't get size.\n");
 502                 prom_halt();
 503         }
 504         if (unlikely(n > sizeof(prom_trans))) {
 505                 prom_printf("prom_mappings: Size %Zd is too big.\n", n);
 506                 prom_halt();
 507         }
 508
 509         if ((n = prom_getproperty(node, "translations",
 510                                   (char *)&prom_trans[0],
 511                                   sizeof(prom_trans))) == -1) {
 512                 prom_printf("prom_mappings: Couldn't get property.\n");
 513                 prom_halt();
 514         }
 515
 516         n = n / sizeof(struct linux_prom_translation);
 517
 518         prom_trans_ents = n;
 519 }
 520
 521 static void __init remap_kernel(void)
 522 {
 523         unsigned long phys_page, tte_vaddr, tte_data;
 524         int tlb_ent = sparc64_highest_locked_tlbent();
 525
 526         tte_vaddr = (unsigned long) KERNBASE;
 527         phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
 528         tte_data = (phys_page | (_PAGE_VALID | _PAGE_SZ4MB |
 529                                  _PAGE_CP | _PAGE_CV | _PAGE_P |
 530                                  _PAGE_L | _PAGE_W));
 531
 532         kern_locked_tte_data = tte_data;
 533
 534         /* Now lock us into the TLBs via OBP. */
 535         prom_dtlb_load(tlb_ent, tte_data, tte_vaddr);
 536         prom_itlb_load(tlb_ent, tte_data, tte_vaddr);
 537         if (bigkernel) {
 538                 tlb_ent -= 1;
 539                 prom_dtlb_load(tlb_ent,
 540                                tte_data + 0x400000,
 541                                tte_vaddr + 0x400000);
 542                 prom_itlb_load(tlb_ent,
 543                                tte_data + 0x400000,
 544                                tte_vaddr + 0x400000);
 545         }
 546         sparc64_highest_unlocked_tlb_ent = tlb_ent - 1;
 547         if (tlb_type == cheetah_plus) {
 548                 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
 549                                             CTX_CHEETAH_PLUS_NUC);
 550                 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
 551                 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
 552         }
 553 }
 554
 555
 556 static void __init inherit_prom_mappings_pre(void)
 557 {
 558         read_obp_translations();
 559
 560         /* Now fixup OBP's idea about where we really are mapped. */
 561         prom_printf("Remapping the kernel... ");
 562         remap_kernel();
 563
 564         prom_printf("done.\n");
 565 }
 566
 567 static void __init inherit_prom_mappings_post(void)
 568 {
 569         build_obp_pgtable();
 570         register_prom_callbacks();
 571 }
 572
 573 /* The OBP specifications for sun4u mark 0xfffffffc00000000 and
 574  * upwards as reserved for use by the firmware (I wonder if this
 575  * will be the same on Cheetah...).  We use this virtual address
 576  * range for the VPTE table mappings of the nucleus so we need
 577  * to zap them when we enter the PROM.  -DaveM
 578  */
 579 static void __flush_nucleus_vptes(void)
 580 {
 581         unsigned long prom_reserved_base = 0xfffffffc00000000UL;
 582         int i;
 583
 584         /* Only DTLB must be checked for VPTE entries. */
 585         if (tlb_type == spitfire) {
 586                 for (i = 0; i < 63; i++) {
 587                         unsigned long tag;
 588
 589                         /* Spitfire Errata #32 workaround */
 590                         /* NOTE: Always runs on spitfire, so no cheetah+
 591                          *       page size encodings.
 592                          */
 593                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 594                                              "flush     %%g6"
 595                                              : /* No outputs */
 596                                              : "r" (0),
 597                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 598
 599                         tag = spitfire_get_dtlb_tag(i);
 600                         if (((tag & ~(PAGE_MASK)) == 0) &&
 601                             ((tag &  (PAGE_MASK)) >= prom_reserved_base)) {
 602                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 603                                                      "membar #Sync"
 604                                                      : /* no outputs */
 605                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
 606                                 spitfire_put_dtlb_data(i, 0x0UL);
 607                         }
 608                 }
 609         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 610                 for (i = 0; i < 512; i++) {
 611                         unsigned long tag = cheetah_get_dtlb_tag(i, 2);
 612
 613                         if ((tag & ~PAGE_MASK) == 0 &&
 614                             (tag & PAGE_MASK) >= prom_reserved_base) {
 615                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 616                                                      "membar #Sync"
 617                                                      : /* no outputs */
 618                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
 619                                 cheetah_put_dtlb_data(i, 0x0UL, 2);
 620                         }
 621
 622                         if (tlb_type != cheetah_plus)
 623                                 continue;
 624
 625                         tag = cheetah_get_dtlb_tag(i, 3);
 626
 627                         if ((tag & ~PAGE_MASK) == 0 &&
 628                             (tag & PAGE_MASK) >= prom_reserved_base) {
 629                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 630                                                      "membar #Sync"
 631                                                      : /* no outputs */
 632                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
 633                                 cheetah_put_dtlb_data(i, 0x0UL, 3);
 634                         }
 635                 }
 636         } else {
 637                 /* Implement me :-) */
 638                 BUG();
 639         }
 640 }
 641
 642 static int prom_ditlb_set;
 643 struct prom_tlb_entry {
 644         int             tlb_ent;
 645         unsigned long   tlb_tag;
 646         unsigned long   tlb_data;
 647 };
 648 struct prom_tlb_entry prom_itlb[16], prom_dtlb[16];
 649
 650 void prom_world(int enter)
 651 {
 652         unsigned long pstate;
 653         int i;
 654
 655         if (!enter)
 656                 set_fs((mm_segment_t) { get_thread_current_ds() });
 657
 658         if (!prom_ditlb_set)
 659                 return;
 660
 661         /* Make sure the following runs atomically. */
 662         __asm__ __volatile__("flushw\n\t"
 663                              "rdpr      %%pstate, %0\n\t"
 664                              "wrpr      %0, %1, %%pstate"
 665                              : "=r" (pstate)
 666                              : "i" (PSTATE_IE));
 667
 668         if (enter) {
 669                 /* Kick out nucleus VPTEs. */
 670                 __flush_nucleus_vptes();
 671
 672                 /* Install PROM world. */
 673                 for (i = 0; i < 16; i++) {
 674                         if (prom_dtlb[i].tlb_ent != -1) {
 675                                 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
 676                                                      "membar #Sync"
 677                                         : : "r" (prom_dtlb[i].tlb_tag), "r" (TLB_TAG_ACCESS),
 678                                         "i" (ASI_DMMU));
 679                                 if (tlb_type == spitfire)
 680                                         spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent,
 681                                                                prom_dtlb[i].tlb_data);
 682                                 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
 683                                         cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent,
 684                                                                prom_dtlb[i].tlb_data);
 685                         }
 686                         if (prom_itlb[i].tlb_ent != -1) {
 687                                 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
 688                                                      "membar #Sync"
 689                                                      : : "r" (prom_itlb[i].tlb_tag),
 690                                                      "r" (TLB_TAG_ACCESS),
 691                                                      "i" (ASI_IMMU));
 692                                 if (tlb_type == spitfire)
 693                                         spitfire_put_itlb_data(prom_itlb[i].tlb_ent,
 694                                                                prom_itlb[i].tlb_data);
 695                                 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
 696                                         cheetah_put_litlb_data(prom_itlb[i].tlb_ent,
 697                                                                prom_itlb[i].tlb_data);
 698                         }
 699                 }
 700         } else {
 701                 for (i = 0; i < 16; i++) {
 702                         if (prom_dtlb[i].tlb_ent != -1) {
 703                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 704                                                      "membar #Sync"
 705                                         : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
 706                                 if (tlb_type == spitfire)
 707                                         spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent, 0x0UL);
 708                                 else
 709                                         cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent, 0x0UL);
 710                         }
 711                         if (prom_itlb[i].tlb_ent != -1) {
 712                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 713                                                      "membar #Sync"
 714                                                      : : "r" (TLB_TAG_ACCESS),
 715                                                      "i" (ASI_IMMU));
 716                                 if (tlb_type == spitfire)
 717                                         spitfire_put_itlb_data(prom_itlb[i].tlb_ent, 0x0UL);
 718                                 else
 719                                         cheetah_put_litlb_data(prom_itlb[i].tlb_ent, 0x0UL);
 720                         }
 721                 }
 722         }
 723         __asm__ __volatile__("wrpr      %0, 0, %%pstate"
 724                              : : "r" (pstate));
 725 }
 726
 727 void inherit_locked_prom_mappings(int save_p)
 728 {
 729         int i;
 730         int dtlb_seen = 0;
 731         int itlb_seen = 0;
 732
 733         /* Fucking losing PROM has more mappings in the TLB, but
 734          * it (conveniently) fails to mention any of these in the
 735          * translations property.  The only ones that matter are
 736          * the locked PROM tlb entries, so we impose the following
 737          * irrecovable rule on the PROM, it is allowed 8 locked
 738          * entries in the ITLB and 8 in the DTLB.
 739          *
 740          * Supposedly the upper 16GB of the address space is
 741          * reserved for OBP, BUT I WISH THIS WAS DOCUMENTED
 742          * SOMEWHERE!!!!!!!!!!!!!!!!!  Furthermore the entire interface
 743          * used between the client program and the firmware on sun5
 744          * systems to coordinate mmu mappings is also COMPLETELY
 745          * UNDOCUMENTED!!!!!! Thanks S(t)un!
 746          */
 747         if (save_p) {
 748                 for (i = 0; i < 16; i++) {
 749                         prom_itlb[i].tlb_ent = -1;
 750                         prom_dtlb[i].tlb_ent = -1;
 751                 }
 752         }
 753         if (tlb_type == spitfire) {
 754                 int high = sparc64_highest_unlocked_tlb_ent;
 755                 for (i = 0; i <= high; i++) {
 756                         unsigned long data;
 757
 758                         /* Spitfire Errata #32 workaround */
 759                         /* NOTE: Always runs on spitfire, so no cheetah+
 760                          *       page size encodings.
 761                          */
 762                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 763                                              "flush     %%g6"
 764                                              : /* No outputs */
 765                                              : "r" (0),
 766                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 767
 768                         data = spitfire_get_dtlb_data(i);
 769                         if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
 770                                 unsigned long tag;
 771
 772                                 /* Spitfire Errata #32 workaround */
 773                                 /* NOTE: Always runs on spitfire, so no
 774                                  *       cheetah+ page size encodings.
 775                                  */
 776                                 __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 777                                                      "flush     %%g6"
 778                                                      : /* No outputs */
 779                                                      : "r" (0),
 780                                                      "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 781
 782                                 tag = spitfire_get_dtlb_tag(i);
 783                                 if (save_p) {
 784                                         prom_dtlb[dtlb_seen].tlb_ent = i;
 785                                         prom_dtlb[dtlb_seen].tlb_tag = tag;
 786                                         prom_dtlb[dtlb_seen].tlb_data = data;
 787                                 }
 788                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 789                                                      "membar #Sync"
 790                                                      : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
 791                                 spitfire_put_dtlb_data(i, 0x0UL);
 792
 793                                 dtlb_seen++;
 794                                 if (dtlb_seen > 15)
 795                                         break;
 796                         }
 797                 }
 798
 799                 for (i = 0; i < high; i++) {
 800                         unsigned long data;
 801
 802                         /* Spitfire Errata #32 workaround */
 803                         /* NOTE: Always runs on spitfire, so no
 804                          *       cheetah+ page size encodings.
 805                          */
 806                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 807                                              "flush     %%g6"
 808                                              : /* No outputs */
 809                                              : "r" (0),
 810                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 811
 812                         data = spitfire_get_itlb_data(i);
 813                         if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
 814                                 unsigned long tag;
 815
 816                                 /* Spitfire Errata #32 workaround */
 817                                 /* NOTE: Always runs on spitfire, so no
 818                                  *       cheetah+ page size encodings.
 819                                  */
 820                                 __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 821                                                      "flush     %%g6"
 822                                                      : /* No outputs */
 823                                                      : "r" (0),
 824                                                      "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 825
 826                                 tag = spitfire_get_itlb_tag(i);
 827                                 if (save_p) {
 828                                         prom_itlb[itlb_seen].tlb_ent = i;
 829                                         prom_itlb[itlb_seen].tlb_tag = tag;
 830                                         prom_itlb[itlb_seen].tlb_data = data;
 831                                 }
 832                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 833                                                      "membar #Sync"
 834                                                      : : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
 835                                 spitfire_put_itlb_data(i, 0x0UL);
 836
 837                                 itlb_seen++;
 838                                 if (itlb_seen > 15)
 839                                         break;
 840                         }
 841                 }
 842         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 843                 int high = sparc64_highest_unlocked_tlb_ent;
 844
 845                 for (i = 0; i <= high; i++) {
 846                         unsigned long data;
 847
 848                         data = cheetah_get_ldtlb_data(i);
 849                         if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
 850                                 unsigned long tag;
 851
 852                                 tag = cheetah_get_ldtlb_tag(i);
 853                                 if (save_p) {
 854                                         prom_dtlb[dtlb_seen].tlb_ent = i;
 855                                         prom_dtlb[dtlb_seen].tlb_tag = tag;
 856                                         prom_dtlb[dtlb_seen].tlb_data = data;
 857                                 }
 858                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 859                                                      "membar #Sync"
 860                                                      : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
 861                                 cheetah_put_ldtlb_data(i, 0x0UL);
 862
 863                                 dtlb_seen++;
 864                                 if (dtlb_seen > 15)
 865                                         break;
 866                         }
 867                 }
 868
 869                 for (i = 0; i < high; i++) {
 870                         unsigned long data;
 871
 872                         data = cheetah_get_litlb_data(i);
 873                         if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
 874                                 unsigned long tag;
 875
 876                                 tag = cheetah_get_litlb_tag(i);
 877                                 if (save_p) {
 878                                         prom_itlb[itlb_seen].tlb_ent = i;
 879                                         prom_itlb[itlb_seen].tlb_tag = tag;
 880                                         prom_itlb[itlb_seen].tlb_data = data;
 881                                 }
 882                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 883                                                      "membar #Sync"
 884                                                      : : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
 885                                 cheetah_put_litlb_data(i, 0x0UL);
 886
 887                                 itlb_seen++;
 888                                 if (itlb_seen > 15)
 889                                         break;
 890                         }
 891                 }
 892         } else {
 893                 /* Implement me :-) */
 894                 BUG();
 895         }
 896         if (save_p)
 897                 prom_ditlb_set = 1;
 898 }
 899
 900 /* Give PROM back his world, done during reboots... */
 901 void prom_reload_locked(void)
 902 {
 903         int i;
 904
 905         for (i = 0; i < 16; i++) {
 906                 if (prom_dtlb[i].tlb_ent != -1) {
 907                         __asm__ __volatile__("stxa %0, [%1] %2\n\t"
 908                                              "membar #Sync"
 909                                 : : "r" (prom_dtlb[i].tlb_tag), "r" (TLB_TAG_ACCESS),
 910                                 "i" (ASI_DMMU));
 911                         if (tlb_type == spitfire)
 912                                 spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent,
 913                                                        prom_dtlb[i].tlb_data);
 914                         else if (tlb_type == cheetah || tlb_type == cheetah_plus)
 915                                 cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent,
 916                                                       prom_dtlb[i].tlb_data);
 917                 }
 918
 919                 if (prom_itlb[i].tlb_ent != -1) {
 920                         __asm__ __volatile__("stxa %0, [%1] %2\n\t"
 921                                              "membar #Sync"
 922                                              : : "r" (prom_itlb[i].tlb_tag),
 923                                              "r" (TLB_TAG_ACCESS),
 924                                              "i" (ASI_IMMU));
 925                         if (tlb_type == spitfire)
 926                                 spitfire_put_itlb_data(prom_itlb[i].tlb_ent,
 927                                                        prom_itlb[i].tlb_data);
 928                         else
 929                                 cheetah_put_litlb_data(prom_itlb[i].tlb_ent,
 930                                                        prom_itlb[i].tlb_data);
 931                 }
 932         }
 933 }
 934
 935 #ifdef DCACHE_ALIASING_POSSIBLE
 936 void __flush_dcache_range(unsigned long start, unsigned long end)
 937 {
 938         unsigned long va;
 939
 940         if (tlb_type == spitfire) {
 941                 int n = 0;
 942
 943                 for (va = start; va < end; va += 32) {
 944                         spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
 945                         if (++n >= 512)
 946                                 break;
 947                 }
 948         } else {
 949                 start = __pa(start);
 950                 end = __pa(end);
 951                 for (va = start; va < end; va += 32)
 952                         __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 953                                              "membar #Sync"
 954                                              : /* no outputs */
 955                                              : "r" (va),
 956                                                "i" (ASI_DCACHE_INVALIDATE));
 957         }
 958 }
 959 #endif /* DCACHE_ALIASING_POSSIBLE */
 960
 961 /* If not locked, zap it. */
 962 void __flush_tlb_all(void)
 963 {
 964         unsigned long pstate;
 965         int i;
 966
 967         __asm__ __volatile__("flushw\n\t"
 968                              "rdpr      %%pstate, %0\n\t"
 969                              "wrpr      %0, %1, %%pstate"
 970                              : "=r" (pstate)
 971                              : "i" (PSTATE_IE));
 972         if (tlb_type == spitfire) {
 973                 for (i = 0; i < 64; i++) {
 974                         /* Spitfire Errata #32 workaround */
 975                         /* NOTE: Always runs on spitfire, so no
 976                          *       cheetah+ page size encodings.
 977                          */
 978                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 979                                              "flush     %%g6"
 980                                              : /* No outputs */
 981                                              : "r" (0),
 982                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
 983
 984                         if (!(spitfire_get_dtlb_data(i) & _PAGE_L)) {
 985                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
 986                                                      "membar #Sync"
 987                                                      : /* no outputs */
 988                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
 989                                 spitfire_put_dtlb_data(i, 0x0UL);
 990                         }
 991
 992                         /* Spitfire Errata #32 workaround */
 993                         /* NOTE: Always runs on spitfire, so no
 994                          *       cheetah+ page size encodings.
 995                          */
 996                         __asm__ __volatile__("stxa      %0, [%1] %2\n\t"
 997                                              "flush     %%g6"
 998                                              : /* No outputs */
 999                                              : "r" (0),
1000                                              "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1001
1002                         if (!(spitfire_get_itlb_data(i) & _PAGE_L)) {
1003                                 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1004                                                      "membar #Sync"
1005                                                      : /* no outputs */
1006                                                      : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
1007                                 spitfire_put_itlb_data(i, 0x0UL);
1008                         }
1009                 }
1010         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1011                 cheetah_flush_dtlb_all();
1012                 cheetah_flush_itlb_all();
1013         }
1014         __asm__ __volatile__("wrpr      %0, 0, %%pstate"
1015                              : : "r" (pstate));
1016 }
1017
1018 /* Caller does TLB context flushing on local CPU if necessary.
1019  * The caller also ensures that CTX_VALID(mm->context) is false.
1020  *
1021  * We must be careful about boundary cases so that we never
1022  * let the user have CTX 0 (nucleus) or we ever use a CTX
1023  * version of zero (and thus NO_CONTEXT would not be caught
1024  * by version mis-match tests in mmu_context.h).
1025  */
1026 void get_new_mmu_context(struct mm_struct *mm)
1027 {
1028         unsigned long ctx, new_ctx;
1029         unsigned long orig_pgsz_bits;
1030
1031
1032         spin_lock(&ctx_alloc_lock);
1033         orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
1034         ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
1035         new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
1036         if (new_ctx >= (1 << CTX_NR_BITS)) {
1037                 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
1038                 if (new_ctx >= ctx) {
1039                         int i;
1040                         new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
1041                                 CTX_FIRST_VERSION;
1042                         if (new_ctx == 1)
1043                                 new_ctx = CTX_FIRST_VERSION;
1044
1045                         /* Don't call memset, for 16 entries that's just
1046                          * plain silly...
1047                          */
1048                         mmu_context_bmap[0] = 3;
1049                         mmu_context_bmap[1] = 0;
1050                         mmu_context_bmap[2] = 0;
1051                         mmu_context_bmap[3] = 0;
1052                         for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
1053                                 mmu_context_bmap[i + 0] = 0;
1054                                 mmu_context_bmap[i + 1] = 0;
1055                                 mmu_context_bmap[i + 2] = 0;
1056                                 mmu_context_bmap[i + 3] = 0;
1057                         }
1058                         goto out;
1059                 }
1060         }
1061         mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
1062         new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
1063 out:
1064         tlb_context_cache = new_ctx;
1065         mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
1066         spin_unlock(&ctx_alloc_lock);
1067 }
1068
1069 #ifndef CONFIG_SMP
1070 struct pgtable_cache_struct pgt_quicklists;
1071 #endif
1072
1073 /* OK, we have to color these pages. The page tables are accessed
1074  * by non-Dcache enabled mapping in the VPTE area by the dtlb_backend.S
1075  * code, as well as by PAGE_OFFSET range direct-mapped addresses by
1076  * other parts of the kernel. By coloring, we make sure that the tlbmiss
1077  * fast handlers do not get data from old/garbage dcache lines that
1078  * correspond to an old/stale virtual address (user/kernel) that
1079  * previously mapped the pagetable page while accessing vpte range
1080  * addresses. The idea is that if the vpte color and PAGE_OFFSET range
1081  * color is the same, then when the kernel initializes the pagetable
1082  * using the later address range, accesses with the first address
1083  * range will see the newly initialized data rather than the garbage.
1084  */
1085 #ifdef DCACHE_ALIASING_POSSIBLE
1086 #define DC_ALIAS_SHIFT  1
1087 #else
1088 #define DC_ALIAS_SHIFT  0
1089 #endif
1090 pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
1091 {
1092         struct page *page;
1093         unsigned long color;
1094
1095         {
1096                 pte_t *ptep = pte_alloc_one_fast(mm, address);
1097
1098                 if (ptep)
1099                         return ptep;
1100         }
1101
1102         color = VPTE_COLOR(address);
1103         page = alloc_pages(GFP_KERNEL|__GFP_REPEAT, DC_ALIAS_SHIFT);
1104         if (page) {
1105                 unsigned long *to_free;
1106                 unsigned long paddr;
1107                 pte_t *pte;
1108
1109 #ifdef DCACHE_ALIASING_POSSIBLE
1110                 set_page_count(page, 1);
1111                 ClearPageCompound(page);
1112
1113                 set_page_count((page + 1), 1);
1114                 ClearPageCompound(page + 1);
1115 #endif
1116                 paddr = (unsigned long) page_address(page);
1117                 memset((char *)paddr, 0, (PAGE_SIZE << DC_ALIAS_SHIFT));
1118
1119                 if (!color) {
1120                         pte = (pte_t *) paddr;
1121                         to_free = (unsigned long *) (paddr + PAGE_SIZE);
1122                 } else {
1123                         pte = (pte_t *) (paddr + PAGE_SIZE);
1124                         to_free = (unsigned long *) paddr;
1125                 }
1126
1127 #ifdef DCACHE_ALIASING_POSSIBLE
1128                 /* Now free the other one up, adjust cache size. */
1129                 preempt_disable();
1130                 *to_free = (unsigned long) pte_quicklist[color ^ 0x1];
1131                 pte_quicklist[color ^ 0x1] = to_free;
1132                 pgtable_cache_size++;
1133                 preempt_enable();
1134 #endif
1135
1136                 return pte;
1137         }
1138         return NULL;
1139 }
1140
1141 void sparc_ultra_dump_itlb(void)
1142 {
1143         int slot;
1144
1145         if (tlb_type == spitfire) {
1146                 printk ("Contents of itlb: ");
1147                 for (slot = 0; slot < 14; slot++) printk ("    ");
1148                 printk ("%2x:%016lx,%016lx\n",
1149                         0,
1150                         spitfire_get_itlb_tag(0), spitfire_get_itlb_data(0));
1151                 for (slot = 1; slot < 64; slot+=3) {
1152                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1153                                 slot,
1154                                 spitfire_get_itlb_tag(slot), spitfire_get_itlb_data(slot),
1155                                 slot+1,
1156                                 spitfire_get_itlb_tag(slot+1), spitfire_get_itlb_data(slot+1),
1157                                 slot+2,
1158                                 spitfire_get_itlb_tag(slot+2), spitfire_get_itlb_data(slot+2));
1159                 }
1160         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1161                 printk ("Contents of itlb0:\n");
1162                 for (slot = 0; slot < 16; slot+=2) {
1163                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1164                                 slot,
1165                                 cheetah_get_litlb_tag(slot), cheetah_get_litlb_data(slot),
1166                                 slot+1,
1167                                 cheetah_get_litlb_tag(slot+1), cheetah_get_litlb_data(slot+1));
1168                 }
1169                 printk ("Contents of itlb2:\n");
1170                 for (slot = 0; slot < 128; slot+=2) {
1171                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1172                                 slot,
1173                                 cheetah_get_itlb_tag(slot), cheetah_get_itlb_data(slot),
1174                                 slot+1,
1175                                 cheetah_get_itlb_tag(slot+1), cheetah_get_itlb_data(slot+1));
1176                 }
1177         }
1178 }
1179
1180 void sparc_ultra_dump_dtlb(void)
1181 {
1182         int slot;
1183
1184         if (tlb_type == spitfire) {
1185                 printk ("Contents of dtlb: ");
1186                 for (slot = 0; slot < 14; slot++) printk ("    ");
1187                 printk ("%2x:%016lx,%016lx\n", 0,
1188                         spitfire_get_dtlb_tag(0), spitfire_get_dtlb_data(0));
1189                 for (slot = 1; slot < 64; slot+=3) {
1190                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1191                                 slot,
1192                                 spitfire_get_dtlb_tag(slot), spitfire_get_dtlb_data(slot),
1193                                 slot+1,
1194                                 spitfire_get_dtlb_tag(slot+1), spitfire_get_dtlb_data(slot+1),
1195                                 slot+2,
1196                                 spitfire_get_dtlb_tag(slot+2), spitfire_get_dtlb_data(slot+2));
1197                 }
1198         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1199                 printk ("Contents of dtlb0:\n");
1200                 for (slot = 0; slot < 16; slot+=2) {
1201                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1202                                 slot,
1203                                 cheetah_get_ldtlb_tag(slot), cheetah_get_ldtlb_data(slot),
1204                                 slot+1,
1205                                 cheetah_get_ldtlb_tag(slot+1), cheetah_get_ldtlb_data(slot+1));
1206                 }
1207                 printk ("Contents of dtlb2:\n");
1208                 for (slot = 0; slot < 512; slot+=2) {
1209                         printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1210                                 slot,
1211                                 cheetah_get_dtlb_tag(slot, 2), cheetah_get_dtlb_data(slot, 2),
1212                                 slot+1,
1213                                 cheetah_get_dtlb_tag(slot+1, 2), cheetah_get_dtlb_data(slot+1, 2));
1214                 }
1215                 if (tlb_type == cheetah_plus) {
1216                         printk ("Contents of dtlb3:\n");
1217                         for (slot = 0; slot < 512; slot+=2) {
1218                                 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1219                                         slot,
1220                                         cheetah_get_dtlb_tag(slot, 3), cheetah_get_dtlb_data(slot, 3),
1221                                         slot+1,
1222                                         cheetah_get_dtlb_tag(slot+1, 3), cheetah_get_dtlb_data(slot+1, 3));
1223                         }
1224                 }
1225         }
1226 }
1227
1228 extern unsigned long cmdline_memory_size;
1229
1230 unsigned long __init bootmem_init(unsigned long *pages_avail)
1231 {
1232         unsigned long bootmap_size, start_pfn, end_pfn;
1233         unsigned long end_of_phys_memory = 0UL;
1234         unsigned long bootmap_pfn, bytes_avail, size;
1235         int i;
1236
1237 #ifdef CONFIG_DEBUG_BOOTMEM
1238         prom_printf("bootmem_init: Scan pavail, ");
1239 #endif
1240
1241         bytes_avail = 0UL;
1242         for (i = 0; i < pavail_ents; i++) {
1243                 end_of_phys_memory = pavail[i].phys_addr +
1244                         pavail[i].reg_size;
1245                 bytes_avail += pavail[i].reg_size;
1246                 if (cmdline_memory_size) {
1247                         if (bytes_avail > cmdline_memory_size) {
1248                                 unsigned long slack = bytes_avail - cmdline_memory_size;
1249
1250                                 bytes_avail -= slack;
1251                                 end_of_phys_memory -= slack;
1252
1253                                 pavail[i].reg_size -= slack;
1254                                 if ((long)pavail[i].reg_size <= 0L) {
1255                                         pavail[i].phys_addr = 0xdeadbeefUL;
1256                                         pavail[i].reg_size = 0UL;
1257                                         pavail_ents = i;
1258                                 } else {
1259                                         pavail[i+1].reg_size = 0Ul;
1260                                         pavail[i+1].phys_addr = 0xdeadbeefUL;
1261                                         pavail_ents = i + 1;
1262                                 }
1263                                 break;
1264                         }
1265                 }
1266         }
1267
1268         *pages_avail = bytes_avail >> PAGE_SHIFT;
1269
1270         /* Start with page aligned address of last symbol in kernel
1271          * image.  The kernel is hard mapped below PAGE_OFFSET in a
1272          * 4MB locked TLB translation.
1273          */
1274         start_pfn = PAGE_ALIGN(kern_base + kern_size) >> PAGE_SHIFT;
1275
1276         bootmap_pfn = start_pfn;
1277
1278         end_pfn = end_of_phys_memory >> PAGE_SHIFT;
1279
1280 #ifdef CONFIG_BLK_DEV_INITRD
1281         /* Now have to check initial ramdisk, so that bootmap does not overwrite it */
1282         if (sparc_ramdisk_image || sparc_ramdisk_image64) {
1283                 unsigned long ramdisk_image = sparc_ramdisk_image ?
1284                         sparc_ramdisk_image : sparc_ramdisk_image64;
1285                 if (ramdisk_image >= (unsigned long)_end - 2 * PAGE_SIZE)
1286                         ramdisk_image -= KERNBASE;
1287                 initrd_start = ramdisk_image + phys_base;
1288                 initrd_end = initrd_start + sparc_ramdisk_size;
1289                 if (initrd_end > end_of_phys_memory) {
1290                         printk(KERN_CRIT "initrd extends beyond end of memory "
1291                                          "(0x%016lx > 0x%016lx)\ndisabling initrd\n",
1292                                initrd_end, end_of_phys_memory);
1293                         initrd_start = 0;
1294                 }
1295                 if (initrd_start) {
1296                         if (initrd_start >= (start_pfn << PAGE_SHIFT) &&
1297                             initrd_start < (start_pfn << PAGE_SHIFT) + 2 * PAGE_SIZE)
1298                                 bootmap_pfn = PAGE_ALIGN (initrd_end) >> PAGE_SHIFT;
1299                 }
1300         }
1301 #endif
1302         /* Initialize the boot-time allocator. */
1303         max_pfn = max_low_pfn = end_pfn;
1304         min_low_pfn = pfn_base;
1305
1306 #ifdef CONFIG_DEBUG_BOOTMEM
1307         prom_printf("init_bootmem(min[%lx], bootmap[%lx], max[%lx])\n",
1308                     min_low_pfn, bootmap_pfn, max_low_pfn);
1309 #endif
1310         bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn, pfn_base, end_pfn);
1311
1312         /* Now register the available physical memory with the
1313          * allocator.
1314          */
1315         for (i = 0; i < pavail_ents; i++) {
1316 #ifdef CONFIG_DEBUG_BOOTMEM
1317                 prom_printf("free_bootmem(pavail:%d): base[%lx] size[%lx]\n",
1318                             i, pavail[i].phys_addr, pavail[i].reg_size);
1319 #endif
1320                 free_bootmem(pavail[i].phys_addr, pavail[i].reg_size);
1321         }
1322
1323 #ifdef CONFIG_BLK_DEV_INITRD
1324         if (initrd_start) {
1325                 size = initrd_end - initrd_start;
1326
1327                 /* Resert the initrd image area. */
1328 #ifdef CONFIG_DEBUG_BOOTMEM
1329                 prom_printf("reserve_bootmem(initrd): base[%llx] size[%lx]\n",
1330                         initrd_start, initrd_end);
1331 #endif
1332                 reserve_bootmem(initrd_start, size);
1333                 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
1334
1335                 initrd_start += PAGE_OFFSET;
1336                 initrd_end += PAGE_OFFSET;
1337         }
1338 #endif
1339         /* Reserve the kernel text/data/bss. */
1340 #ifdef CONFIG_DEBUG_BOOTMEM
1341         prom_printf("reserve_bootmem(kernel): base[%lx] size[%lx]\n", kern_base, kern_size);
1342 #endif
1343         reserve_bootmem(kern_base, kern_size);
1344         *pages_avail -= PAGE_ALIGN(kern_size) >> PAGE_SHIFT;
1345
1346         /* Reserve the bootmem map.   We do not account for it
1347          * in pages_avail because we will release that memory
1348          * in free_all_bootmem.
1349          */
1350         size = bootmap_size;
1351 #ifdef CONFIG_DEBUG_BOOTMEM
1352         prom_printf("reserve_bootmem(bootmap): base[%lx] size[%lx]\n",
1353                     (bootmap_pfn << PAGE_SHIFT), size);
1354 #endif
1355         reserve_bootmem((bootmap_pfn << PAGE_SHIFT), size);
1356         *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
1357
1358         return end_pfn;
1359 }
1360
1361 #ifdef CONFIG_DEBUG_PAGEALLOC
1362 static unsigned long kernel_map_range(unsigned long pstart, unsigned long pend, pgprot_t prot)
1363 {
1364         unsigned long vstart = PAGE_OFFSET + pstart;
1365         unsigned long vend = PAGE_OFFSET + pend;
1366         unsigned long alloc_bytes = 0UL;
1367
1368         if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1369                 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1370                             vstart, vend);
1371                 prom_halt();
1372         }
1373
1374         while (vstart < vend) {
1375                 unsigned long this_end, paddr = __pa(vstart);
1376                 pgd_t *pgd = pgd_offset_k(vstart);
1377                 pud_t *pud;
1378                 pmd_t *pmd;
1379                 pte_t *pte;
1380
1381                 pud = pud_offset(pgd, vstart);
1382                 if (pud_none(*pud)) {
1383                         pmd_t *new;
1384
1385                         new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1386                         alloc_bytes += PAGE_SIZE;
1387                         pud_populate(&init_mm, pud, new);
1388                 }
1389
1390                 pmd = pmd_offset(pud, vstart);
1391                 if (!pmd_present(*pmd)) {
1392                         pte_t *new;
1393
1394                         new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1395                         alloc_bytes += PAGE_SIZE;
1396                         pmd_populate_kernel(&init_mm, pmd, new);
1397                 }
1398
1399                 pte = pte_offset_kernel(pmd, vstart);
1400                 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1401                 if (this_end > vend)
1402                         this_end = vend;
1403
1404                 while (vstart < this_end) {
1405                         pte_val(*pte) = (paddr | pgprot_val(prot));
1406
1407                         vstart += PAGE_SIZE;
1408                         paddr += PAGE_SIZE;
1409                         pte++;
1410                 }
1411         }
1412
1413         return alloc_bytes;
1414 }
1415
1416 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1417 static int pall_ents __initdata;
1418
1419 extern unsigned int kvmap_linear_patch[1];
1420
1421 static void __init kernel_physical_mapping_init(void)
1422 {
1423         unsigned long i, mem_alloced = 0UL;
1424
1425         read_obp_memory("reg", &pall[0], &pall_ents);
1426
1427         for (i = 0; i < pall_ents; i++) {
1428                 unsigned long phys_start, phys_end;
1429
1430                 phys_start = pall[i].phys_addr;
1431                 phys_end = phys_start + pall[i].reg_size;
1432                 mem_alloced += kernel_map_range(phys_start, phys_end,
1433                                                 PAGE_KERNEL);
1434         }
1435
1436         printk("Allocated %ld bytes for kernel page tables.\n",
1437                mem_alloced);
1438
1439         kvmap_linear_patch[0] = 0x01000000; /* nop */
1440         flushi(&kvmap_linear_patch[0]);
1441
1442         __flush_tlb_all();
1443 }
1444
1445 void kernel_map_pages(struct page *page, int numpages, int enable)
1446 {
1447         unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1448         unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1449
1450         kernel_map_range(phys_start, phys_end,
1451                          (enable ? PAGE_KERNEL : __pgprot(0)));
1452
1453         /* we should perform an IPI and flush all tlbs,
1454          * but that can deadlock->flush only current cpu.
1455          */
1456         __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1457                                  PAGE_OFFSET + phys_end);
1458 }
1459 #endif
1460
1461 unsigned long __init find_ecache_flush_span(unsigned long size)
1462 {
1463         int i;
1464
1465         for (i = 0; i < pavail_ents; i++) {
1466                 if (pavail[i].reg_size >= size)
1467                         return pavail[i].phys_addr;
1468         }
1469
1470         return ~0UL;
1471 }
1472
1473 /* paging_init() sets up the page tables */
1474
1475 extern void cheetah_ecache_flush_init(void);
1476
1477 static unsigned long last_valid_pfn;
1478 pgd_t swapper_pg_dir[2048];
1479
1480 void __init paging_init(void)
1481 {
1482         unsigned long end_pfn, pages_avail, shift;
1483         unsigned long real_end, i;
1484
1485         /* Find available physical memory... */
1486         read_obp_memory("available", &pavail[0], &pavail_ents);
1487
1488         phys_base = 0xffffffffffffffffUL;
1489         for (i = 0; i < pavail_ents; i++)
1490                 phys_base = min(phys_base, pavail[i].phys_addr);
1491
1492         pfn_base = phys_base >> PAGE_SHIFT;
1493
1494         kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1495         kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1496
1497         set_bit(0, mmu_context_bmap);
1498
1499         shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1500
1501         real_end = (unsigned long)_end;
1502         if ((real_end > ((unsigned long)KERNBASE + 0x400000)))
1503                 bigkernel = 1;
1504         if ((real_end > ((unsigned long)KERNBASE + 0x800000))) {
1505                 prom_printf("paging_init: Kernel > 8MB, too large.\n");
1506                 prom_halt();
1507         }
1508
1509         /* Set kernel pgd to upper alias so physical page computations
1510          * work.
1511          */
1512         init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1513
1514         memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1515
1516         /* Now can init the kernel/bad page tables. */
1517         pud_set(pud_offset(&swapper_pg_dir[0], 0),
1518                 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1519
1520         swapper_pgd_zero = pgd_val(swapper_pg_dir[0]);
1521
1522         inherit_prom_mappings_pre();
1523
1524         /* Ok, we can use our TLB miss and window trap handlers safely.
1525          * We need to do a quick peek here to see if we are on StarFire
1526          * or not, so setup_tba can setup the IRQ globals correctly (it
1527          * needs to get the hard smp processor id correctly).
1528          */
1529         {
1530                 extern void setup_tba(int);
1531                 setup_tba(this_is_starfire);
1532         }
1533         __flush_tlb_all();
1534
1535         /* Everything from this point forward, until we are done with
1536          * inherit_prom_mappings_post(), must complete successfully
1537          * without calling into the firmware.  The firwmare page tables
1538          * have not been built, but we are running on the Linux kernel's
1539          * trap table.
1540          */
1541
1542         /* Setup bootmem... */
1543         pages_avail = 0;
1544         last_valid_pfn = end_pfn = bootmem_init(&pages_avail);
1545
1546         inherit_prom_mappings_post();
1547
1548         inherit_locked_prom_mappings(1);
1549
1550 #ifdef CONFIG_DEBUG_PAGEALLOC
1551         kernel_physical_mapping_init();
1552 #endif
1553
1554         {
1555                 unsigned long zones_size[MAX_NR_ZONES];
1556                 unsigned long zholes_size[MAX_NR_ZONES];
1557                 unsigned long npages;
1558                 int znum;
1559
1560                 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1561                         zones_size[znum] = zholes_size[znum] = 0;
1562
1563                 npages = end_pfn - pfn_base;
1564                 zones_size[ZONE_DMA] = npages;
1565                 zholes_size[ZONE_DMA] = npages - pages_avail;
1566
1567                 free_area_init_node(0, &contig_page_data, zones_size,
1568                                     phys_base >> PAGE_SHIFT, zholes_size);
1569         }
1570
1571         device_scan();
1572 }
1573
1574 static void __init taint_real_pages(void)
1575 {
1576         int i;
1577
1578         read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
1579
1580         /* Find changes discovered in the physmem available rescan and
1581          * reserve the lost portions in the bootmem maps.
1582          */
1583         for (i = 0; i < pavail_ents; i++) {
1584                 unsigned long old_start, old_end;
1585
1586                 old_start = pavail[i].phys_addr;
1587                 old_end = old_start +
1588                         pavail[i].reg_size;
1589                 while (old_start < old_end) {
1590                         int n;
1591
1592                         for (n = 0; pavail_rescan_ents; n++) {
1593                                 unsigned long new_start, new_end;
1594
1595                                 new_start = pavail_rescan[n].phys_addr;
1596                                 new_end = new_start +
1597                                         pavail_rescan[n].reg_size;
1598
1599                                 if (new_start <= old_start &&
1600                                     new_end >= (old_start + PAGE_SIZE)) {
1601                                         set_bit(old_start >> 22,
1602                                                 sparc64_valid_addr_bitmap);
1603                                         goto do_next_page;
1604                                 }
1605                         }
1606                         reserve_bootmem(old_start, PAGE_SIZE);
1607
1608                 do_next_page:
1609                         old_start += PAGE_SIZE;
1610                 }
1611         }
1612 }
1613
1614 void __init mem_init(void)
1615 {
1616         unsigned long codepages, datapages, initpages;
1617         unsigned long addr, last;
1618         int i;
1619
1620         i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1621         i += 1;
1622         sparc64_valid_addr_bitmap = (unsigned long *) alloc_bootmem(i << 3);
1623         if (sparc64_valid_addr_bitmap == NULL) {
1624                 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1625                 prom_halt();
1626         }
1627         memset(sparc64_valid_addr_bitmap, 0, i << 3);
1628
1629         addr = PAGE_OFFSET + kern_base;
1630         last = PAGE_ALIGN(kern_size) + addr;
1631         while (addr < last) {
1632                 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1633                 addr += PAGE_SIZE;
1634         }
1635
1636         taint_real_pages();
1637
1638         max_mapnr = last_valid_pfn - pfn_base;
1639         high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1640
1641 #ifdef CONFIG_DEBUG_BOOTMEM
1642         prom_printf("mem_init: Calling free_all_bootmem().\n");
1643 #endif
1644         totalram_pages = num_physpages = free_all_bootmem() - 1;
1645
1646         /*
1647          * Set up the zero page, mark it reserved, so that page count
1648          * is not manipulated when freeing the page from user ptes.
1649          */
1650         mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1651         if (mem_map_zero == NULL) {
1652                 prom_printf("paging_init: Cannot alloc zero page.\n");
1653                 prom_halt();
1654         }
1655         SetPageReserved(mem_map_zero);
1656
1657         codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1658         codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1659         datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1660         datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1661         initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1662         initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1663
1664         printk("Memory: %uk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1665                nr_free_pages() << (PAGE_SHIFT-10),
1666                codepages << (PAGE_SHIFT-10),
1667                datapages << (PAGE_SHIFT-10),
1668                initpages << (PAGE_SHIFT-10),
1669                PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1670
1671         if (tlb_type == cheetah || tlb_type == cheetah_plus)
1672                 cheetah_ecache_flush_init();
1673 }
1674
1675 void free_initmem(void)
1676 {
1677         unsigned long addr, initend;
1678
1679         /*
1680          * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1681          */
1682         addr = PAGE_ALIGN((unsigned long)(__init_begin));
1683         initend = (unsigned long)(__init_end) & PAGE_MASK;
1684         for (; addr < initend; addr += PAGE_SIZE) {
1685                 unsigned long page;
1686                 struct page *p;
1687
1688                 page = (addr +
1689                         ((unsigned long) __va(kern_base)) -
1690                         ((unsigned long) KERNBASE));
1691                 memset((void *)addr, 0xcc, PAGE_SIZE);
1692                 p = virt_to_page(page);
1693
1694                 ClearPageReserved(p);
1695                 set_page_count(p, 1);
1696                 __free_page(p);
1697                 num_physpages++;
1698                 totalram_pages++;
1699         }
1700 }
1701
1702 #ifdef CONFIG_BLK_DEV_INITRD
1703 void free_initrd_mem(unsigned long start, unsigned long end)
1704 {
1705         if (start < end)
1706                 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
1707         for (; start < end; start += PAGE_SIZE) {
1708                 struct page *p = virt_to_page(start);
1709
1710                 ClearPageReserved(p);
1711                 set_page_count(p, 1);
1712                 __free_page(p);
1713                 num_physpages++;
1714                 totalram_pages++;
1715         }
1716 }
1717 #endif