2 * Definitions for the new Marvell Yukon / SysKonenct driver.
7 /* PCI config registers */
8 #define PCI_DEV_REG1 0x40
9 #define PCI_DEV_REG2 0x44
10 #define PCI_REV_DESC 0x4
12 #define PCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \
13 PCI_STATUS_SIG_SYSTEM_ERROR | \
14 PCI_STATUS_REC_MASTER_ABORT | \
15 PCI_STATUS_REC_TARGET_ABORT | \
22 B0_POWER_CTRL = 0x0007,
30 B0_XM1_PHY_ADDR = 0x0030,
31 B0_XM1_PHY_DATA = 0x0034,
34 B0_XM2_PHY_ADDR = 0x0050,
35 B0_XM2_PHY_DATA = 0x0054,
64 B2_IRQM_CTRL = 0x0148,
65 B2_IRQM_TEST = 0x0149,
67 B2_IRQM_HWE_MSK = 0x0150,
68 B2_TST_CTRL1 = 0x0158,
69 B2_TST_CTRL2 = 0x0159,
82 B3_RAM_DATA_LO = 0x0184,
83 B3_RAM_DATA_HI = 0x0188,
84 B3_RI_WTO_R1 = 0x0190,
85 B3_RI_WTO_XA1 = 0x0191,
86 B3_RI_WTO_XS1 = 0x0192,
87 B3_RI_RTO_R1 = 0x0193,
88 B3_RI_RTO_XA1 = 0x0194,
89 B3_RI_RTO_XS1 = 0x0195,
90 B3_RI_WTO_R2 = 0x0196,
91 B3_RI_WTO_XA2 = 0x0197,
92 B3_RI_WTO_XS2 = 0x0198,
93 B3_RI_RTO_R2 = 0x0199,
94 B3_RI_RTO_XA2 = 0x019a,
95 B3_RI_RTO_XS2 = 0x019b,
96 B3_RI_TO_VAL = 0x019c,
99 B3_MA_TOINI_RX1 = 0x01b0,
100 B3_MA_TOINI_RX2 = 0x01b1,
101 B3_MA_TOINI_TX1 = 0x01b2,
102 B3_MA_TOINI_TX2 = 0x01b3,
103 B3_MA_TOVAL_RX1 = 0x01b4,
104 B3_MA_TOVAL_RX2 = 0x01b5,
105 B3_MA_TOVAL_TX1 = 0x01b6,
106 B3_MA_TOVAL_TX2 = 0x01b7,
107 B3_MA_TO_CTRL = 0x01b8,
108 B3_MA_TO_TEST = 0x01ba,
109 B3_MA_RCINI_RX1 = 0x01c0,
110 B3_MA_RCINI_RX2 = 0x01c1,
111 B3_MA_RCINI_TX1 = 0x01c2,
112 B3_MA_RCINI_TX2 = 0x01c3,
113 B3_MA_RCVAL_RX1 = 0x01c4,
114 B3_MA_RCVAL_RX2 = 0x01c5,
115 B3_MA_RCVAL_TX1 = 0x01c6,
116 B3_MA_RCVAL_TX2 = 0x01c7,
117 B3_MA_RC_CTRL = 0x01c8,
118 B3_MA_RC_TEST = 0x01ca,
119 B3_PA_TOINI_RX1 = 0x01d0,
120 B3_PA_TOINI_RX2 = 0x01d4,
121 B3_PA_TOINI_TX1 = 0x01d8,
122 B3_PA_TOINI_TX2 = 0x01dc,
123 B3_PA_TOVAL_RX1 = 0x01e0,
124 B3_PA_TOVAL_RX2 = 0x01e4,
125 B3_PA_TOVAL_TX1 = 0x01e8,
126 B3_PA_TOVAL_TX2 = 0x01ec,
131 /* B0_CTST 16 bit Control/Status register */
133 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
134 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
135 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
136 CS_VAUX_AVAIL = 1<<10,/* VAUX available (YUKON only) */
137 CS_BUS_CLOCK = 1<<9, /* Bus Clock 0/1 = 33/66 MHz */
138 CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */
139 CS_ST_SW_IRQ = 1<<7, /* Set IRQ SW Request */
140 CS_CL_SW_IRQ = 1<<6, /* Clear IRQ SW Request */
141 CS_STOP_DONE = 1<<5, /* Stop Master is finished */
142 CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
143 CS_MRST_CLR = 1<<3, /* Clear Master reset */
144 CS_MRST_SET = 1<<2, /* Set Master reset */
145 CS_RST_CLR = 1<<1, /* Clear Software reset */
146 CS_RST_SET = 1, /* Set Software reset */
148 /* B0_LED 8 Bit LED register */
149 /* Bit 7.. 2: reserved */
150 LED_STAT_ON = 1<<1, /* Status LED on */
151 LED_STAT_OFF = 1, /* Status LED off */
153 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
154 PC_VAUX_ENA = 1<<7, /* Switch VAUX Enable */
155 PC_VAUX_DIS = 1<<6, /* Switch VAUX Disable */
156 PC_VCC_ENA = 1<<5, /* Switch VCC Enable */
157 PC_VCC_DIS = 1<<4, /* Switch VCC Disable */
158 PC_VAUX_ON = 1<<3, /* Switch VAUX On */
159 PC_VAUX_OFF = 1<<2, /* Switch VAUX Off */
160 PC_VCC_ON = 1<<1, /* Switch VCC On */
161 PC_VCC_OFF = 1<<0, /* Switch VCC Off */
164 /* B2_IRQM_MSK 32 bit IRQ Moderation Mask */
166 IS_ALL_MSK = 0xbffffffful, /* All Interrupt bits */
167 IS_HW_ERR = 1<<31, /* Interrupt HW Error */
168 /* Bit 30: reserved */
169 IS_PA_TO_RX1 = 1<<29, /* Packet Arb Timeout Rx1 */
170 IS_PA_TO_RX2 = 1<<28, /* Packet Arb Timeout Rx2 */
171 IS_PA_TO_TX1 = 1<<27, /* Packet Arb Timeout Tx1 */
172 IS_PA_TO_TX2 = 1<<26, /* Packet Arb Timeout Tx2 */
173 IS_I2C_READY = 1<<25, /* IRQ on end of I2C Tx */
174 IS_IRQ_SW = 1<<24, /* SW forced IRQ */
175 IS_EXT_REG = 1<<23, /* IRQ from LM80 or PHY (GENESIS only) */
176 /* IRQ from PHY (YUKON only) */
177 IS_TIMINT = 1<<22, /* IRQ from Timer */
178 IS_MAC1 = 1<<21, /* IRQ from MAC 1 */
179 IS_LNK_SYNC_M1 = 1<<20, /* Link Sync Cnt wrap MAC 1 */
180 IS_MAC2 = 1<<19, /* IRQ from MAC 2 */
181 IS_LNK_SYNC_M2 = 1<<18, /* Link Sync Cnt wrap MAC 2 */
182 /* Receive Queue 1 */
183 IS_R1_B = 1<<17, /* Q_R1 End of Buffer */
184 IS_R1_F = 1<<16, /* Q_R1 End of Frame */
185 IS_R1_C = 1<<15, /* Q_R1 Encoding Error */
186 /* Receive Queue 2 */
187 IS_R2_B = 1<<14, /* Q_R2 End of Buffer */
188 IS_R2_F = 1<<13, /* Q_R2 End of Frame */
189 IS_R2_C = 1<<12, /* Q_R2 Encoding Error */
190 /* Synchronous Transmit Queue 1 */
191 IS_XS1_B = 1<<11, /* Q_XS1 End of Buffer */
192 IS_XS1_F = 1<<10, /* Q_XS1 End of Frame */
193 IS_XS1_C = 1<<9, /* Q_XS1 Encoding Error */
194 /* Asynchronous Transmit Queue 1 */
195 IS_XA1_B = 1<<8, /* Q_XA1 End of Buffer */
196 IS_XA1_F = 1<<7, /* Q_XA1 End of Frame */
197 IS_XA1_C = 1<<6, /* Q_XA1 Encoding Error */
198 /* Synchronous Transmit Queue 2 */
199 IS_XS2_B = 1<<5, /* Q_XS2 End of Buffer */
200 IS_XS2_F = 1<<4, /* Q_XS2 End of Frame */
201 IS_XS2_C = 1<<3, /* Q_XS2 Encoding Error */
202 /* Asynchronous Transmit Queue 2 */
203 IS_XA2_B = 1<<2, /* Q_XA2 End of Buffer */
204 IS_XA2_F = 1<<1, /* Q_XA2 End of Frame */
205 IS_XA2_C = 1<<0, /* Q_XA2 Encoding Error */
207 IS_TO_PORT1 = IS_PA_TO_RX1 | IS_PA_TO_TX1,
208 IS_TO_PORT2 = IS_PA_TO_RX2 | IS_PA_TO_TX2,
210 IS_PORT_1 = IS_XA1_F| IS_R1_F | IS_TO_PORT1 | IS_MAC1,
211 IS_PORT_2 = IS_XA2_F| IS_R2_F | IS_TO_PORT2 | IS_MAC2,
215 /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
217 IS_ERR_MSK = 0x00003fff,/* All Error bits */
219 IS_IRQ_TIST_OV = 1<<13, /* Time Stamp Timer Overflow (YUKON only) */
220 IS_IRQ_SENSOR = 1<<12, /* IRQ from Sensor (YUKON only) */
221 IS_IRQ_MST_ERR = 1<<11, /* IRQ master error detected */
222 IS_IRQ_STAT = 1<<10, /* IRQ status exception */
223 IS_NO_STAT_M1 = 1<<9, /* No Rx Status from MAC 1 */
224 IS_NO_STAT_M2 = 1<<8, /* No Rx Status from MAC 2 */
225 IS_NO_TIST_M1 = 1<<7, /* No Time Stamp from MAC 1 */
226 IS_NO_TIST_M2 = 1<<6, /* No Time Stamp from MAC 2 */
227 IS_RAM_RD_PAR = 1<<5, /* RAM Read Parity Error */
228 IS_RAM_WR_PAR = 1<<4, /* RAM Write Parity Error */
229 IS_M1_PAR_ERR = 1<<3, /* MAC 1 Parity Error */
230 IS_M2_PAR_ERR = 1<<2, /* MAC 2 Parity Error */
231 IS_R1_PAR_ERR = 1<<1, /* Queue R1 Parity Error */
232 IS_R2_PAR_ERR = 1<<0, /* Queue R2 Parity Error */
235 /* B2_TST_CTRL1 8 bit Test Control Register 1 */
237 TST_FRC_DPERR_MR = 1<<7, /* force DATAPERR on MST RD */
238 TST_FRC_DPERR_MW = 1<<6, /* force DATAPERR on MST WR */
239 TST_FRC_DPERR_TR = 1<<5, /* force DATAPERR on TRG RD */
240 TST_FRC_DPERR_TW = 1<<4, /* force DATAPERR on TRG WR */
241 TST_FRC_APERR_M = 1<<3, /* force ADDRPERR on MST */
242 TST_FRC_APERR_T = 1<<2, /* force ADDRPERR on TRG */
243 TST_CFG_WRITE_ON = 1<<1, /* Enable Config Reg WR */
244 TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */
247 /* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */
249 CFG_CHIP_R_MSK = 0xf<<4, /* Bit 7.. 4: Chip Revision */
250 /* Bit 3.. 2: reserved */
251 CFG_DIS_M2_CLK = 1<<1, /* Disable Clock for 2nd MAC */
252 CFG_SNG_MAC = 1<<0, /* MAC Config: 0=2 MACs / 1=1 MAC*/
255 /* B2_CHIP_ID 8 bit Chip Identification Number */
257 CHIP_ID_GENESIS = 0x0a, /* Chip ID for GENESIS */
258 CHIP_ID_YUKON = 0xb0, /* Chip ID for YUKON */
259 CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
260 CHIP_ID_YUKON_LP = 0xb2, /* Chip ID for YUKON-LP */
261 CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */
262 CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */
263 CHIP_ID_YUKON_FE = 0xb7, /* Chip ID for YUKON-2 FE */
265 CHIP_REV_YU_LITE_A1 = 3, /* Chip Rev. for YUKON-Lite A1,A2 */
266 CHIP_REV_YU_LITE_A3 = 7, /* Chip Rev. for YUKON-Lite A3 */
269 /* B2_TI_CTRL 8 bit Timer control */
270 /* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */
272 TIM_START = 1<<2, /* Start Timer */
273 TIM_STOP = 1<<1, /* Stop Timer */
274 TIM_CLR_IRQ = 1<<0, /* Clear Timer IRQ (!IRQM) */
277 /* B2_TI_TEST 8 Bit Timer Test */
278 /* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */
279 /* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */
281 TIM_T_ON = 1<<2, /* Test mode on */
282 TIM_T_OFF = 1<<1, /* Test mode off */
283 TIM_T_STEP = 1<<0, /* Test step */
286 /* B2_GP_IO 32 bit General Purpose I/O Register */
288 GP_DIR_9 = 1<<25, /* IO_9 direct, 0=In/1=Out */
289 GP_DIR_8 = 1<<24, /* IO_8 direct, 0=In/1=Out */
290 GP_DIR_7 = 1<<23, /* IO_7 direct, 0=In/1=Out */
291 GP_DIR_6 = 1<<22, /* IO_6 direct, 0=In/1=Out */
292 GP_DIR_5 = 1<<21, /* IO_5 direct, 0=In/1=Out */
293 GP_DIR_4 = 1<<20, /* IO_4 direct, 0=In/1=Out */
294 GP_DIR_3 = 1<<19, /* IO_3 direct, 0=In/1=Out */
295 GP_DIR_2 = 1<<18, /* IO_2 direct, 0=In/1=Out */
296 GP_DIR_1 = 1<<17, /* IO_1 direct, 0=In/1=Out */
297 GP_DIR_0 = 1<<16, /* IO_0 direct, 0=In/1=Out */
299 GP_IO_9 = 1<<9, /* IO_9 pin */
300 GP_IO_8 = 1<<8, /* IO_8 pin */
301 GP_IO_7 = 1<<7, /* IO_7 pin */
302 GP_IO_6 = 1<<6, /* IO_6 pin */
303 GP_IO_5 = 1<<5, /* IO_5 pin */
304 GP_IO_4 = 1<<4, /* IO_4 pin */
305 GP_IO_3 = 1<<3, /* IO_3 pin */
306 GP_IO_2 = 1<<2, /* IO_2 pin */
307 GP_IO_1 = 1<<1, /* IO_1 pin */
308 GP_IO_0 = 1<<0, /* IO_0 pin */
311 /* Descriptor Bit Definition */
312 /* TxCtrl Transmit Buffer Control Field */
313 /* RxCtrl Receive Buffer Control Field */
315 BMU_OWN = 1<<31, /* OWN bit: 0=host/1=BMU */
316 BMU_STF = 1<<30, /* Start of Frame */
317 BMU_EOF = 1<<29, /* End of Frame */
318 BMU_IRQ_EOB = 1<<28, /* Req "End of Buffer" IRQ */
319 BMU_IRQ_EOF = 1<<27, /* Req "End of Frame" IRQ */
320 /* TxCtrl specific bits */
321 BMU_STFWD = 1<<26, /* (Tx) Store & Forward Frame */
322 BMU_NO_FCS = 1<<25, /* (Tx) Disable MAC FCS (CRC) generation */
323 BMU_SW = 1<<24, /* (Tx) 1 bit res. for SW use */
324 /* RxCtrl specific bits */
325 BMU_DEV_0 = 1<<26, /* (Rx) Transfer data to Dev0 */
326 BMU_STAT_VAL = 1<<25, /* (Rx) Rx Status Valid */
327 BMU_TIST_VAL = 1<<24, /* (Rx) Rx TimeStamp Valid */
328 /* Bit 23..16: BMU Check Opcodes */
329 BMU_CHECK = 0x55<<16, /* Default BMU check */
330 BMU_TCP_CHECK = 0x56<<16, /* Descr with TCP ext */
331 BMU_UDP_CHECK = 0x57<<16, /* Descr with UDP ext (YUKON only) */
332 BMU_BBC = 0xffffL, /* Bit 15.. 0: Buffer Byte Counter */
335 /* B2_BSC_CTRL 8 bit Blink Source Counter Control */
337 BSC_START = 1<<1, /* Start Blink Source Counter */
338 BSC_STOP = 1<<0, /* Stop Blink Source Counter */
341 /* B2_BSC_STAT 8 bit Blink Source Counter Status */
343 BSC_SRC = 1<<0, /* Blink Source, 0=Off / 1=On */
346 /* B2_BSC_TST 16 bit Blink Source Counter Test Reg */
348 BSC_T_ON = 1<<2, /* Test mode on */
349 BSC_T_OFF = 1<<1, /* Test mode off */
350 BSC_T_STEP = 1<<0, /* Test step */
353 /* B3_RAM_ADDR 32 bit RAM Address, to read or write */
354 /* Bit 31..19: reserved */
355 #define RAM_ADR_RAN 0x0007ffffL /* Bit 18.. 0: RAM Address Range */
356 /* RAM Interface Registers */
358 /* B3_RI_CTRL 16 bit RAM Iface Control Register */
360 RI_CLR_RD_PERR = 1<<9, /* Clear IRQ RAM Read Parity Err */
361 RI_CLR_WR_PERR = 1<<8, /* Clear IRQ RAM Write Parity Err*/
363 RI_RST_CLR = 1<<1, /* Clear RAM Interface Reset */
364 RI_RST_SET = 1<<0, /* Set RAM Interface Reset */
367 /* MAC Arbiter Registers */
368 /* B3_MA_TO_CTRL 16 bit MAC Arbiter Timeout Ctrl Reg */
370 MA_FOE_ON = 1<<3, /* XMAC Fast Output Enable ON */
371 MA_FOE_OFF = 1<<2, /* XMAC Fast Output Enable OFF */
372 MA_RST_CLR = 1<<1, /* Clear MAC Arbiter Reset */
373 MA_RST_SET = 1<<0, /* Set MAC Arbiter Reset */
378 #define SK_MAC_TO_53 72 /* MAC arbiter timeout */
379 #define SK_PKT_TO_53 0x2000 /* Packet arbiter timeout */
380 #define SK_PKT_TO_MAX 0xffff /* Maximum value */
381 #define SK_RI_TO_53 36 /* RAM interface timeout */
383 /* Packet Arbiter Registers */
384 /* B3_PA_CTRL 16 bit Packet Arbiter Ctrl Register */
386 PA_CLR_TO_TX2 = 1<<13, /* Clear IRQ Packet Timeout TX2 */
387 PA_CLR_TO_TX1 = 1<<12, /* Clear IRQ Packet Timeout TX1 */
388 PA_CLR_TO_RX2 = 1<<11, /* Clear IRQ Packet Timeout RX2 */
389 PA_CLR_TO_RX1 = 1<<10, /* Clear IRQ Packet Timeout RX1 */
390 PA_ENA_TO_TX2 = 1<<9, /* Enable Timeout Timer TX2 */
391 PA_DIS_TO_TX2 = 1<<8, /* Disable Timeout Timer TX2 */
392 PA_ENA_TO_TX1 = 1<<7, /* Enable Timeout Timer TX1 */
393 PA_DIS_TO_TX1 = 1<<6, /* Disable Timeout Timer TX1 */
394 PA_ENA_TO_RX2 = 1<<5, /* Enable Timeout Timer RX2 */
395 PA_DIS_TO_RX2 = 1<<4, /* Disable Timeout Timer RX2 */
396 PA_ENA_TO_RX1 = 1<<3, /* Enable Timeout Timer RX1 */
397 PA_DIS_TO_RX1 = 1<<2, /* Disable Timeout Timer RX1 */
398 PA_RST_CLR = 1<<1, /* Clear MAC Arbiter Reset */
399 PA_RST_SET = 1<<0, /* Set MAC Arbiter Reset */
402 #define PA_ENA_TO_ALL (PA_ENA_TO_RX1 | PA_ENA_TO_RX2 |\
403 PA_ENA_TO_TX1 | PA_ENA_TO_TX2)
406 /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
407 /* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */
408 /* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */
409 /* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */
410 /* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */
412 #define TXA_MAX_VAL 0x00ffffffUL /* Bit 23.. 0: Max TXA Timer/Cnt Val */
414 /* TXA_CTRL 8 bit Tx Arbiter Control Register */
416 TXA_ENA_FSYNC = 1<<7, /* Enable force of sync Tx queue */
417 TXA_DIS_FSYNC = 1<<6, /* Disable force of sync Tx queue */
418 TXA_ENA_ALLOC = 1<<5, /* Enable alloc of free bandwidth */
419 TXA_DIS_ALLOC = 1<<4, /* Disable alloc of free bandwidth */
420 TXA_START_RC = 1<<3, /* Start sync Rate Control */
421 TXA_STOP_RC = 1<<2, /* Stop sync Rate Control */
422 TXA_ENA_ARB = 1<<1, /* Enable Tx Arbiter */
423 TXA_DIS_ARB = 1<<0, /* Disable Tx Arbiter */
429 /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
431 TXA_ITI_INI = 0x0200,/* 32 bit Tx Arb Interval Timer Init Val*/
432 TXA_ITI_VAL = 0x0204,/* 32 bit Tx Arb Interval Timer Value */
433 TXA_LIM_INI = 0x0208,/* 32 bit Tx Arb Limit Counter Init Val */
434 TXA_LIM_VAL = 0x020c,/* 32 bit Tx Arb Limit Counter Value */
435 TXA_CTRL = 0x0210,/* 8 bit Tx Arbiter Control Register */
436 TXA_TEST = 0x0211,/* 8 bit Tx Arbiter Test Register */
437 TXA_STAT = 0x0212,/* 8 bit Tx Arbiter Status Register */
442 B6_EXT_REG = 0x0300,/* External registers (GENESIS only) */
443 B7_CFG_SPC = 0x0380,/* copy of the Configuration register */
444 B8_RQ1_REGS = 0x0400,/* Receive Queue 1 */
445 B8_RQ2_REGS = 0x0480,/* Receive Queue 2 */
446 B8_TS1_REGS = 0x0600,/* Transmit sync queue 1 */
447 B8_TA1_REGS = 0x0680,/* Transmit async queue 1 */
448 B8_TS2_REGS = 0x0700,/* Transmit sync queue 2 */
449 B8_TA2_REGS = 0x0780,/* Transmit sync queue 2 */
450 B16_RAM_REGS = 0x0800,/* RAM Buffer Registers */
453 /* Queue Register Offsets, use Q_ADDR() to access */
455 B8_Q_REGS = 0x0400, /* base of Queue registers */
456 Q_D = 0x00, /* 8*32 bit Current Descriptor */
457 Q_DA_L = 0x20, /* 32 bit Current Descriptor Address Low dWord */
458 Q_DA_H = 0x24, /* 32 bit Current Descriptor Address High dWord */
459 Q_AC_L = 0x28, /* 32 bit Current Address Counter Low dWord */
460 Q_AC_H = 0x2c, /* 32 bit Current Address Counter High dWord */
461 Q_BC = 0x30, /* 32 bit Current Byte Counter */
462 Q_CSR = 0x34, /* 32 bit BMU Control/Status Register */
463 Q_F = 0x38, /* 32 bit Flag Register */
464 Q_T1 = 0x3c, /* 32 bit Test Register 1 */
465 Q_T1_TR = 0x3c, /* 8 bit Test Register 1 Transfer SM */
466 Q_T1_WR = 0x3d, /* 8 bit Test Register 1 Write Descriptor SM */
467 Q_T1_RD = 0x3e, /* 8 bit Test Register 1 Read Descriptor SM */
468 Q_T1_SV = 0x3f, /* 8 bit Test Register 1 Supervisor SM */
469 Q_T2 = 0x40, /* 32 bit Test Register 2 */
470 Q_T3 = 0x44, /* 32 bit Test Register 3 */
473 Q_DONE = 0x24, /* 16 bit Done Index (Yukon-2 only) */
474 Q_WM = 0x40, /* 16 bit FIFO Watermark */
475 Q_AL = 0x42, /* 8 bit FIFO Alignment */
476 Q_RSP = 0x44, /* 16 bit FIFO Read Shadow Pointer */
477 Q_RSL = 0x46, /* 8 bit FIFO Read Shadow Level */
478 Q_RP = 0x48, /* 8 bit FIFO Read Pointer */
479 Q_RL = 0x4a, /* 8 bit FIFO Read Level */
480 Q_WP = 0x4c, /* 8 bit FIFO Write Pointer */
481 Q_WSP = 0x4d, /* 8 bit FIFO Write Shadow Pointer */
482 Q_WL = 0x4e, /* 8 bit FIFO Write Level */
483 Q_WSL = 0x4f, /* 8 bit FIFO Write Shadow Level */
485 #define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs))
487 /* RAM Buffer Register Offsets */
490 RB_START = 0x00,/* 32 bit RAM Buffer Start Address */
491 RB_END = 0x04,/* 32 bit RAM Buffer End Address */
492 RB_WP = 0x08,/* 32 bit RAM Buffer Write Pointer */
493 RB_RP = 0x0c,/* 32 bit RAM Buffer Read Pointer */
494 RB_RX_UTPP = 0x10,/* 32 bit Rx Upper Threshold, Pause Packet */
495 RB_RX_LTPP = 0x14,/* 32 bit Rx Lower Threshold, Pause Packet */
496 RB_RX_UTHP = 0x18,/* 32 bit Rx Upper Threshold, High Prio */
497 RB_RX_LTHP = 0x1c,/* 32 bit Rx Lower Threshold, High Prio */
498 /* 0x10 - 0x1f: reserved at Tx RAM Buffer Registers */
499 RB_PC = 0x20,/* 32 bit RAM Buffer Packet Counter */
500 RB_LEV = 0x24,/* 32 bit RAM Buffer Level Register */
501 RB_CTRL = 0x28,/* 32 bit RAM Buffer Control Register */
502 RB_TST1 = 0x29,/* 8 bit RAM Buffer Test Register 1 */
503 RB_TST2 = 0x2a,/* 8 bit RAM Buffer Test Register 2 */
506 /* Receive and Transmit Queues */
508 Q_R1 = 0x0000, /* Receive Queue 1 */
509 Q_R2 = 0x0080, /* Receive Queue 2 */
510 Q_XS1 = 0x0200, /* Synchronous Transmit Queue 1 */
511 Q_XA1 = 0x0280, /* Asynchronous Transmit Queue 1 */
512 Q_XS2 = 0x0300, /* Synchronous Transmit Queue 2 */
513 Q_XA2 = 0x0380, /* Asynchronous Transmit Queue 2 */
516 /* Different MAC Types */
518 SK_MAC_XMAC = 0, /* Xaqti XMAC II */
519 SK_MAC_GMAC = 1, /* Marvell GMAC */
522 /* Different PHY Types */
524 SK_PHY_XMAC = 0,/* integrated in XMAC II */
525 SK_PHY_BCOM = 1,/* Broadcom BCM5400 */
526 SK_PHY_LONE = 2,/* Level One LXT1000 [not supported]*/
527 SK_PHY_NAT = 3,/* National DP83891 [not supported] */
528 SK_PHY_MARV_COPPER= 4,/* Marvell 88E1011S */
529 SK_PHY_MARV_FIBER = 5,/* Marvell 88E1011S working on fiber */
532 /* PHY addresses (bits 12..8 of PHY address reg) */
534 PHY_ADDR_XMAC = 0<<8,
535 PHY_ADDR_BCOM = 1<<8,
537 /* GPHY address (bits 15..11 of SMI control reg) */
541 #define RB_ADDR(offs, queue) (B16_RAM_REGS + (queue) + (offs))
543 /* Receive MAC FIFO, Receive LED, and Link_Sync regs (GENESIS only) */
545 RX_MFF_EA = 0x0c00,/* 32 bit Receive MAC FIFO End Address */
546 RX_MFF_WP = 0x0c04,/* 32 bit Receive MAC FIFO Write Pointer */
548 RX_MFF_RP = 0x0c0c,/* 32 bit Receive MAC FIFO Read Pointer */
549 RX_MFF_PC = 0x0c10,/* 32 bit Receive MAC FIFO Packet Cnt */
550 RX_MFF_LEV = 0x0c14,/* 32 bit Receive MAC FIFO Level */
551 RX_MFF_CTRL1 = 0x0c18,/* 16 bit Receive MAC FIFO Control Reg 1*/
552 RX_MFF_STAT_TO = 0x0c1a,/* 8 bit Receive MAC Status Timeout */
553 RX_MFF_TIST_TO = 0x0c1b,/* 8 bit Receive MAC Time Stamp Timeout */
554 RX_MFF_CTRL2 = 0x0c1c,/* 8 bit Receive MAC FIFO Control Reg 2*/
555 RX_MFF_TST1 = 0x0c1d,/* 8 bit Receive MAC FIFO Test Reg 1 */
556 RX_MFF_TST2 = 0x0c1e,/* 8 bit Receive MAC FIFO Test Reg 2 */
558 RX_LED_INI = 0x0c20,/* 32 bit Receive LED Cnt Init Value */
559 RX_LED_VAL = 0x0c24,/* 32 bit Receive LED Cnt Current Value */
560 RX_LED_CTRL = 0x0c28,/* 8 bit Receive LED Cnt Control Reg */
561 RX_LED_TST = 0x0c29,/* 8 bit Receive LED Cnt Test Register */
563 LNK_SYNC_INI = 0x0c30,/* 32 bit Link Sync Cnt Init Value */
564 LNK_SYNC_VAL = 0x0c34,/* 32 bit Link Sync Cnt Current Value */
565 LNK_SYNC_CTRL = 0x0c38,/* 8 bit Link Sync Cnt Control Register */
566 LNK_SYNC_TST = 0x0c39,/* 8 bit Link Sync Cnt Test Register */
567 LNK_LED_REG = 0x0c3c,/* 8 bit Link LED Register */
570 /* Receive and Transmit MAC FIFO Registers (GENESIS only) */
571 /* RX_MFF_CTRL1 16 bit Receive MAC FIFO Control Reg 1 */
573 MFF_ENA_RDY_PAT = 1<<13, /* Enable Ready Patch */
574 MFF_DIS_RDY_PAT = 1<<12, /* Disable Ready Patch */
575 MFF_ENA_TIM_PAT = 1<<11, /* Enable Timing Patch */
576 MFF_DIS_TIM_PAT = 1<<10, /* Disable Timing Patch */
577 MFF_ENA_ALM_FUL = 1<<9, /* Enable AlmostFull Sign */
578 MFF_DIS_ALM_FUL = 1<<8, /* Disable AlmostFull Sign */
579 MFF_ENA_PAUSE = 1<<7, /* Enable Pause Signaling */
580 MFF_DIS_PAUSE = 1<<6, /* Disable Pause Signaling */
581 MFF_ENA_FLUSH = 1<<5, /* Enable Frame Flushing */
582 MFF_DIS_FLUSH = 1<<4, /* Disable Frame Flushing */
583 MFF_ENA_TIST = 1<<3, /* Enable Time Stamp Gener */
584 MFF_DIS_TIST = 1<<2, /* Disable Time Stamp Gener */
585 MFF_CLR_INTIST = 1<<1, /* Clear IRQ No Time Stamp */
586 MFF_CLR_INSTAT = 1<<0, /* Clear IRQ No Status */
587 #define MFF_RX_CTRL_DEF MFF_ENA_TIM_PAT
590 /* TX_MFF_CTRL1 16 bit Transmit MAC FIFO Control Reg 1 */
592 MFF_CLR_PERR = 1<<15, /* Clear Parity Error IRQ */
593 /* Bit 14: reserved */
594 MFF_ENA_PKT_REC = 1<<13, /* Enable Packet Recovery */
595 MFF_DIS_PKT_REC = 1<<12, /* Disable Packet Recovery */
597 MFF_ENA_W4E = 1<<7, /* Enable Wait for Empty */
598 MFF_DIS_W4E = 1<<6, /* Disable Wait for Empty */
600 MFF_ENA_LOOPB = 1<<3, /* Enable Loopback */
601 MFF_DIS_LOOPB = 1<<2, /* Disable Loopback */
602 MFF_CLR_MAC_RST = 1<<1, /* Clear XMAC Reset */
603 MFF_SET_MAC_RST = 1<<0, /* Set XMAC Reset */
606 #define MFF_TX_CTRL_DEF (MFF_ENA_PKT_REC | MFF_ENA_TIM_PAT | MFF_ENA_FLUSH)
608 /* RX_MFF_TST2 8 bit Receive MAC FIFO Test Register 2 */
609 /* TX_MFF_TST2 8 bit Transmit MAC FIFO Test Register 2 */
611 MFF_WSP_T_ON = 1<<6, /* Tx: Write Shadow Ptr TestOn */
612 MFF_WSP_T_OFF = 1<<5, /* Tx: Write Shadow Ptr TstOff */
613 MFF_WSP_INC = 1<<4, /* Tx: Write Shadow Ptr Increment */
614 MFF_PC_DEC = 1<<3, /* Packet Counter Decrement */
615 MFF_PC_T_ON = 1<<2, /* Packet Counter Test On */
616 MFF_PC_T_OFF = 1<<1, /* Packet Counter Test Off */
617 MFF_PC_INC = 1<<0, /* Packet Counter Increment */
620 /* RX_MFF_TST1 8 bit Receive MAC FIFO Test Register 1 */
621 /* TX_MFF_TST1 8 bit Transmit MAC FIFO Test Register 1 */
623 MFF_WP_T_ON = 1<<6, /* Write Pointer Test On */
624 MFF_WP_T_OFF = 1<<5, /* Write Pointer Test Off */
625 MFF_WP_INC = 1<<4, /* Write Pointer Increm */
627 MFF_RP_T_ON = 1<<2, /* Read Pointer Test On */
628 MFF_RP_T_OFF = 1<<1, /* Read Pointer Test Off */
629 MFF_RP_DEC = 1<<0, /* Read Pointer Decrement */
632 /* RX_MFF_CTRL2 8 bit Receive MAC FIFO Control Reg 2 */
633 /* TX_MFF_CTRL2 8 bit Transmit MAC FIFO Control Reg 2 */
635 MFF_ENA_OP_MD = 1<<3, /* Enable Operation Mode */
636 MFF_DIS_OP_MD = 1<<2, /* Disable Operation Mode */
637 MFF_RST_CLR = 1<<1, /* Clear MAC FIFO Reset */
638 MFF_RST_SET = 1<<0, /* Set MAC FIFO Reset */
642 /* Link LED Counter Registers (GENESIS only) */
644 /* RX_LED_CTRL 8 bit Receive LED Cnt Control Reg */
645 /* TX_LED_CTRL 8 bit Transmit LED Cnt Control Reg */
646 /* LNK_SYNC_CTRL 8 bit Link Sync Cnt Control Register */
648 LED_START = 1<<2, /* Start Timer */
649 LED_STOP = 1<<1, /* Stop Timer */
650 LED_STATE = 1<<0, /* Rx/Tx: LED State, 1=LED on */
653 /* RX_LED_TST 8 bit Receive LED Cnt Test Register */
654 /* TX_LED_TST 8 bit Transmit LED Cnt Test Register */
655 /* LNK_SYNC_TST 8 bit Link Sync Cnt Test Register */
657 LED_T_ON = 1<<2, /* LED Counter Test mode On */
658 LED_T_OFF = 1<<1, /* LED Counter Test mode Off */
659 LED_T_STEP = 1<<0, /* LED Counter Step */
662 /* LNK_LED_REG 8 bit Link LED Register */
664 LED_BLK_ON = 1<<5, /* Link LED Blinking On */
665 LED_BLK_OFF = 1<<4, /* Link LED Blinking Off */
666 LED_SYNC_ON = 1<<3, /* Use Sync Wire to switch LED */
667 LED_SYNC_OFF = 1<<2, /* Disable Sync Wire Input */
668 LED_ON = 1<<1, /* switch LED on */
669 LED_OFF = 1<<0, /* switch LED off */
672 /* Receive GMAC FIFO (YUKON and Yukon-2) */
674 RX_GMF_EA = 0x0c40,/* 32 bit Rx GMAC FIFO End Address */
675 RX_GMF_AF_THR = 0x0c44,/* 32 bit Rx GMAC FIFO Almost Full Thresh. */
676 RX_GMF_CTRL_T = 0x0c48,/* 32 bit Rx GMAC FIFO Control/Test */
677 RX_GMF_FL_MSK = 0x0c4c,/* 32 bit Rx GMAC FIFO Flush Mask */
678 RX_GMF_FL_THR = 0x0c50,/* 32 bit Rx GMAC FIFO Flush Threshold */
679 RX_GMF_TR_THR = 0x0c54,/* 32 bit Rx Truncation Threshold (Yukon-2) */
681 RX_GMF_VLAN = 0x0c5c,/* 32 bit Rx VLAN Type Register (Yukon-2) */
682 RX_GMF_WP = 0x0c60,/* 32 bit Rx GMAC FIFO Write Pointer */
684 RX_GMF_WLEV = 0x0c68,/* 32 bit Rx GMAC FIFO Write Level */
686 RX_GMF_RP = 0x0c70,/* 32 bit Rx GMAC FIFO Read Pointer */
688 RX_GMF_RLEV = 0x0c78,/* 32 bit Rx GMAC FIFO Read Level */
692 /* TXA_TEST 8 bit Tx Arbiter Test Register */
694 TXA_INT_T_ON = 1<<5, /* Tx Arb Interval Timer Test On */
695 TXA_INT_T_OFF = 1<<4, /* Tx Arb Interval Timer Test Off */
696 TXA_INT_T_STEP = 1<<3, /* Tx Arb Interval Timer Step */
697 TXA_LIM_T_ON = 1<<2, /* Tx Arb Limit Timer Test On */
698 TXA_LIM_T_OFF = 1<<1, /* Tx Arb Limit Timer Test Off */
699 TXA_LIM_T_STEP = 1<<0, /* Tx Arb Limit Timer Step */
702 /* TXA_STAT 8 bit Tx Arbiter Status Register */
704 TXA_PRIO_XS = 1<<0, /* sync queue has prio to send */
708 /* Q_BC 32 bit Current Byte Counter */
710 /* BMU Control Status Registers */
711 /* B0_R1_CSR 32 bit BMU Ctrl/Stat Rx Queue 1 */
712 /* B0_R2_CSR 32 bit BMU Ctrl/Stat Rx Queue 2 */
713 /* B0_XA1_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 1 */
714 /* B0_XS1_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 1 */
715 /* B0_XA2_CSR 32 bit BMU Ctrl/Stat Sync Tx Queue 2 */
716 /* B0_XS2_CSR 32 bit BMU Ctrl/Stat Async Tx Queue 2 */
717 /* Q_CSR 32 bit BMU Control/Status Register */
720 CSR_SV_IDLE = 1<<24, /* BMU SM Idle */
722 CSR_DESC_CLR = 1<<21, /* Clear Reset for Descr */
723 CSR_DESC_SET = 1<<20, /* Set Reset for Descr */
724 CSR_FIFO_CLR = 1<<19, /* Clear Reset for FIFO */
725 CSR_FIFO_SET = 1<<18, /* Set Reset for FIFO */
726 CSR_HPI_RUN = 1<<17, /* Release HPI SM */
727 CSR_HPI_RST = 1<<16, /* Reset HPI SM to Idle */
728 CSR_SV_RUN = 1<<15, /* Release Supervisor SM */
729 CSR_SV_RST = 1<<14, /* Reset Supervisor SM */
730 CSR_DREAD_RUN = 1<<13, /* Release Descr Read SM */
731 CSR_DREAD_RST = 1<<12, /* Reset Descr Read SM */
732 CSR_DWRITE_RUN = 1<<11, /* Release Descr Write SM */
733 CSR_DWRITE_RST = 1<<10, /* Reset Descr Write SM */
734 CSR_TRANS_RUN = 1<<9, /* Release Transfer SM */
735 CSR_TRANS_RST = 1<<8, /* Reset Transfer SM */
736 CSR_ENA_POL = 1<<7, /* Enable Descr Polling */
737 CSR_DIS_POL = 1<<6, /* Disable Descr Polling */
738 CSR_STOP = 1<<5, /* Stop Rx/Tx Queue */
739 CSR_START = 1<<4, /* Start Rx/Tx Queue */
740 CSR_IRQ_CL_P = 1<<3, /* (Rx) Clear Parity IRQ */
741 CSR_IRQ_CL_B = 1<<2, /* Clear EOB IRQ */
742 CSR_IRQ_CL_F = 1<<1, /* Clear EOF IRQ */
743 CSR_IRQ_CL_C = 1<<0, /* Clear ERR IRQ */
746 #define CSR_SET_RESET (CSR_DESC_SET | CSR_FIFO_SET | CSR_HPI_RST |\
747 CSR_SV_RST | CSR_DREAD_RST | CSR_DWRITE_RST |\
749 #define CSR_CLR_RESET (CSR_DESC_CLR | CSR_FIFO_CLR | CSR_HPI_RUN |\
750 CSR_SV_RUN | CSR_DREAD_RUN | CSR_DWRITE_RUN |\
753 /* Q_F 32 bit Flag Register */
755 F_ALM_FULL = 1<<27, /* Rx FIFO: almost full */
756 F_EMPTY = 1<<27, /* Tx FIFO: empty flag */
757 F_FIFO_EOF = 1<<26, /* Tag (EOF Flag) bit in FIFO */
758 F_WM_REACHED = 1<<25, /* Watermark reached */
760 F_FIFO_LEVEL = 0x1fL<<16, /* Bit 23..16: # of Qwords in FIFO */
761 F_WATER_MARK = 0x0007ffL, /* Bit 10.. 0: Watermark */
764 /* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */
765 /* RB_START 32 bit RAM Buffer Start Address */
766 /* RB_END 32 bit RAM Buffer End Address */
767 /* RB_WP 32 bit RAM Buffer Write Pointer */
768 /* RB_RP 32 bit RAM Buffer Read Pointer */
769 /* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */
770 /* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */
771 /* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */
772 /* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */
773 /* RB_PC 32 bit RAM Buffer Packet Counter */
774 /* RB_LEV 32 bit RAM Buffer Level Register */
776 #define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */
777 /* RB_TST2 8 bit RAM Buffer Test Register 2 */
778 /* RB_TST1 8 bit RAM Buffer Test Register 1 */
780 /* RB_CTRL 8 bit RAM Buffer Control Register */
782 RB_ENA_STFWD = 1<<5, /* Enable Store & Forward */
783 RB_DIS_STFWD = 1<<4, /* Disable Store & Forward */
784 RB_ENA_OP_MD = 1<<3, /* Enable Operation Mode */
785 RB_DIS_OP_MD = 1<<2, /* Disable Operation Mode */
786 RB_RST_CLR = 1<<1, /* Clear RAM Buf STM Reset */
787 RB_RST_SET = 1<<0, /* Set RAM Buf STM Reset */
790 /* Transmit MAC FIFO and Transmit LED Registers (GENESIS only), */
792 TX_MFF_EA = 0x0d00,/* 32 bit Transmit MAC FIFO End Address */
793 TX_MFF_WP = 0x0d04,/* 32 bit Transmit MAC FIFO WR Pointer */
794 TX_MFF_WSP = 0x0d08,/* 32 bit Transmit MAC FIFO WR Shadow Ptr */
795 TX_MFF_RP = 0x0d0c,/* 32 bit Transmit MAC FIFO RD Pointer */
796 TX_MFF_PC = 0x0d10,/* 32 bit Transmit MAC FIFO Packet Cnt */
797 TX_MFF_LEV = 0x0d14,/* 32 bit Transmit MAC FIFO Level */
798 TX_MFF_CTRL1 = 0x0d18,/* 16 bit Transmit MAC FIFO Ctrl Reg 1 */
799 TX_MFF_WAF = 0x0d1a,/* 8 bit Transmit MAC Wait after flush */
801 TX_MFF_CTRL2 = 0x0d1c,/* 8 bit Transmit MAC FIFO Ctrl Reg 2 */
802 TX_MFF_TST1 = 0x0d1d,/* 8 bit Transmit MAC FIFO Test Reg 1 */
803 TX_MFF_TST2 = 0x0d1e,/* 8 bit Transmit MAC FIFO Test Reg 2 */
805 TX_LED_INI = 0x0d20,/* 32 bit Transmit LED Cnt Init Value */
806 TX_LED_VAL = 0x0d24,/* 32 bit Transmit LED Cnt Current Val */
807 TX_LED_CTRL = 0x0d28,/* 8 bit Transmit LED Cnt Control Reg */
808 TX_LED_TST = 0x0d29,/* 8 bit Transmit LED Cnt Test Reg */
811 /* Counter and Timer constants, for a host clock of 62.5 MHz */
812 #define SK_XMIT_DUR 0x002faf08UL /* 50 ms */
813 #define SK_BLK_DUR 0x01dcd650UL /* 500 ms */
815 #define SK_DPOLL_DEF 0x00ee6b28UL /* 250 ms at 62.5 MHz */
817 #define SK_DPOLL_MAX 0x00ffffffUL /* 268 ms at 62.5 MHz */
818 /* 215 ms at 78.12 MHz */
820 #define SK_FACT_62 100 /* is given in percent */
821 #define SK_FACT_53 85 /* on GENESIS: 53.12 MHz */
822 #define SK_FACT_78 125 /* on YUKON: 78.12 MHz */
825 /* Transmit GMAC FIFO (YUKON only) */
827 TX_GMF_EA = 0x0d40,/* 32 bit Tx GMAC FIFO End Address */
828 TX_GMF_AE_THR = 0x0d44,/* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/
829 TX_GMF_CTRL_T = 0x0d48,/* 32 bit Tx GMAC FIFO Control/Test */
831 TX_GMF_WP = 0x0d60,/* 32 bit Tx GMAC FIFO Write Pointer */
832 TX_GMF_WSP = 0x0d64,/* 32 bit Tx GMAC FIFO Write Shadow Ptr. */
833 TX_GMF_WLEV = 0x0d68,/* 32 bit Tx GMAC FIFO Write Level */
835 TX_GMF_RP = 0x0d70,/* 32 bit Tx GMAC FIFO Read Pointer */
836 TX_GMF_RSTP = 0x0d74,/* 32 bit Tx GMAC FIFO Restart Pointer */
837 TX_GMF_RLEV = 0x0d78,/* 32 bit Tx GMAC FIFO Read Level */
839 /* Descriptor Poll Timer Registers */
840 B28_DPT_INI = 0x0e00,/* 24 bit Descriptor Poll Timer Init Val */
841 B28_DPT_VAL = 0x0e04,/* 24 bit Descriptor Poll Timer Curr Val */
842 B28_DPT_CTRL = 0x0e08,/* 8 bit Descriptor Poll Timer Ctrl Reg */
844 B28_DPT_TST = 0x0e0a,/* 8 bit Descriptor Poll Timer Test Reg */
846 /* Time Stamp Timer Registers (YUKON only) */
847 GMAC_TI_ST_VAL = 0x0e14,/* 32 bit Time Stamp Timer Curr Val */
848 GMAC_TI_ST_CTRL = 0x0e18,/* 8 bit Time Stamp Timer Ctrl Reg */
849 GMAC_TI_ST_TST = 0x0e1a,/* 8 bit Time Stamp Timer Test Reg */
852 /* Status BMU Registers (Yukon-2 only)*/
854 STAT_CTRL = 0x0e80,/* 32 bit Status BMU Control Reg */
855 STAT_LAST_IDX = 0x0e84,/* 16 bit Status BMU Last Index */
856 /* 0x0e85 - 0x0e86: reserved */
857 STAT_LIST_ADDR_LO = 0x0e88,/* 32 bit Status List Start Addr (low) */
858 STAT_LIST_ADDR_HI = 0x0e8c,/* 32 bit Status List Start Addr (high) */
859 STAT_TXA1_RIDX = 0x0e90,/* 16 bit Status TxA1 Report Index Reg */
860 STAT_TXS1_RIDX = 0x0e92,/* 16 bit Status TxS1 Report Index Reg */
861 STAT_TXA2_RIDX = 0x0e94,/* 16 bit Status TxA2 Report Index Reg */
862 STAT_TXS2_RIDX = 0x0e96,/* 16 bit Status TxS2 Report Index Reg */
863 STAT_TX_IDX_TH = 0x0e98,/* 16 bit Status Tx Index Threshold Reg */
864 STAT_PUT_IDX = 0x0e9c,/* 16 bit Status Put Index Reg */
866 /* FIFO Control/Status Registers (Yukon-2 only)*/
867 STAT_FIFO_WP = 0x0ea0,/* 8 bit Status FIFO Write Pointer Reg */
868 STAT_FIFO_RP = 0x0ea4,/* 8 bit Status FIFO Read Pointer Reg */
869 STAT_FIFO_RSP = 0x0ea6,/* 8 bit Status FIFO Read Shadow Ptr */
870 STAT_FIFO_LEVEL = 0x0ea8,/* 8 bit Status FIFO Level Reg */
871 STAT_FIFO_SHLVL = 0x0eaa,/* 8 bit Status FIFO Shadow Level Reg */
872 STAT_FIFO_WM = 0x0eac,/* 8 bit Status FIFO Watermark Reg */
873 STAT_FIFO_ISR_WM = 0x0ead,/* 8 bit Status FIFO ISR Watermark Reg */
875 /* Level and ISR Timer Registers (Yukon-2 only)*/
876 STAT_LEV_TIMER_INI = 0x0eb0,/* 32 bit Level Timer Init. Value Reg */
877 STAT_LEV_TIMER_CNT = 0x0eb4,/* 32 bit Level Timer Counter Reg */
878 STAT_LEV_TIMER_CTRL = 0x0eb8,/* 8 bit Level Timer Control Reg */
879 STAT_LEV_TIMER_TEST = 0x0eb9,/* 8 bit Level Timer Test Reg */
880 STAT_TX_TIMER_INI = 0x0ec0,/* 32 bit Tx Timer Init. Value Reg */
881 STAT_TX_TIMER_CNT = 0x0ec4,/* 32 bit Tx Timer Counter Reg */
882 STAT_TX_TIMER_CTRL = 0x0ec8,/* 8 bit Tx Timer Control Reg */
883 STAT_TX_TIMER_TEST = 0x0ec9,/* 8 bit Tx Timer Test Reg */
884 STAT_ISR_TIMER_INI = 0x0ed0,/* 32 bit ISR Timer Init. Value Reg */
885 STAT_ISR_TIMER_CNT = 0x0ed4,/* 32 bit ISR Timer Counter Reg */
886 STAT_ISR_TIMER_CTRL = 0x0ed8,/* 8 bit ISR Timer Control Reg */
887 STAT_ISR_TIMER_TEST = 0x0ed9,/* 8 bit ISR Timer Test Reg */
889 ST_LAST_IDX_MASK = 0x007f,/* Last Index Mask */
890 ST_TXRP_IDX_MASK = 0x0fff,/* Tx Report Index Mask */
891 ST_TXTH_IDX_MASK = 0x0fff,/* Tx Threshold Index Mask */
892 ST_WM_IDX_MASK = 0x3f,/* FIFO Watermark Index Mask */
898 LINKLED_LINKSYNC_OFF = 0x04,
899 LINKLED_LINKSYNC_ON = 0x08,
900 LINKLED_BLINK_OFF = 0x10,
901 LINKLED_BLINK_ON = 0x20,
904 /* GMAC and GPHY Control Registers (YUKON only) */
906 GMAC_CTRL = 0x0f00,/* 32 bit GMAC Control Reg */
907 GPHY_CTRL = 0x0f04,/* 32 bit GPHY Control Reg */
908 GMAC_IRQ_SRC = 0x0f08,/* 8 bit GMAC Interrupt Source Reg */
909 GMAC_IRQ_MSK = 0x0f0c,/* 8 bit GMAC Interrupt Mask Reg */
910 GMAC_LINK_CTRL = 0x0f10,/* 16 bit Link Control Reg */
912 /* Wake-up Frame Pattern Match Control Registers (YUKON only) */
914 WOL_REG_OFFS = 0x20,/* HW-Bug: Address is + 0x20 against spec. */
916 WOL_CTRL_STAT = 0x0f20,/* 16 bit WOL Control/Status Reg */
917 WOL_MATCH_CTL = 0x0f22,/* 8 bit WOL Match Control Reg */
918 WOL_MATCH_RES = 0x0f23,/* 8 bit WOL Match Result Reg */
919 WOL_MAC_ADDR = 0x0f24,/* 32 bit WOL MAC Address */
920 WOL_PATT_PME = 0x0f2a,/* 8 bit WOL PME Match Enable (Yukon-2) */
921 WOL_PATT_ASFM = 0x0f2b,/* 8 bit WOL ASF Match Enable (Yukon-2) */
922 WOL_PATT_RPTR = 0x0f2c,/* 8 bit WOL Pattern Read Pointer */
924 /* WOL Pattern Length Registers (YUKON only) */
926 WOL_PATT_LEN_LO = 0x0f30,/* 32 bit WOL Pattern Length 3..0 */
927 WOL_PATT_LEN_HI = 0x0f34,/* 24 bit WOL Pattern Length 6..4 */
929 /* WOL Pattern Counter Registers (YUKON only) */
931 WOL_PATT_CNT_0 = 0x0f38,/* 32 bit WOL Pattern Counter 3..0 */
932 WOL_PATT_CNT_4 = 0x0f3c,/* 24 bit WOL Pattern Counter 6..4 */
936 WOL_PATT_RAM_1 = 0x1000,/* WOL Pattern RAM Link 1 */
937 WOL_PATT_RAM_2 = 0x1400,/* WOL Pattern RAM Link 2 */
941 BASE_XMAC_1 = 0x2000,/* XMAC 1 registers */
942 BASE_GMAC_1 = 0x2800,/* GMAC 1 registers */
943 BASE_XMAC_2 = 0x3000,/* XMAC 2 registers */
944 BASE_GMAC_2 = 0x3800,/* GMAC 2 registers */
948 * Receive Frame Status Encoding
951 XMR_FS_LEN = 0x3fff<<18, /* Bit 31..18: Rx Frame Length */
952 XMR_FS_2L_VLAN = 1<<17, /* Bit 17: tagged wh 2Lev VLAN ID*/
953 XMR_FS_1_VLAN = 1<<16, /* Bit 16: tagged wh 1ev VLAN ID*/
954 XMR_FS_BC = 1<<15, /* Bit 15: Broadcast Frame */
955 XMR_FS_MC = 1<<14, /* Bit 14: Multicast Frame */
956 XMR_FS_UC = 1<<13, /* Bit 13: Unicast Frame */
958 XMR_FS_BURST = 1<<11, /* Bit 11: Burst Mode */
959 XMR_FS_CEX_ERR = 1<<10, /* Bit 10: Carrier Ext. Error */
960 XMR_FS_802_3 = 1<<9, /* Bit 9: 802.3 Frame */
961 XMR_FS_COL_ERR = 1<<8, /* Bit 8: Collision Error */
962 XMR_FS_CAR_ERR = 1<<7, /* Bit 7: Carrier Event Error */
963 XMR_FS_LEN_ERR = 1<<6, /* Bit 6: In-Range Length Error */
964 XMR_FS_FRA_ERR = 1<<5, /* Bit 5: Framing Error */
965 XMR_FS_RUNT = 1<<4, /* Bit 4: Runt Frame */
966 XMR_FS_LNG_ERR = 1<<3, /* Bit 3: Giant (Jumbo) Frame */
967 XMR_FS_FCS_ERR = 1<<2, /* Bit 2: Frame Check Sequ Err */
968 XMR_FS_ERR = 1<<1, /* Bit 1: Frame Error */
969 XMR_FS_MCTRL = 1<<0, /* Bit 0: MAC Control Packet */
972 * XMR_FS_ERR will be set if
973 * XMR_FS_FCS_ERR, XMR_FS_LNG_ERR, XMR_FS_RUNT,
974 * XMR_FS_FRA_ERR, XMR_FS_LEN_ERR, or XMR_FS_CEX_ERR
975 * is set. XMR_FS_LNG_ERR and XMR_FS_LEN_ERR will issue
976 * XMR_FS_ERR unless the corresponding bit in the Receive Command
982 ,* XMAC-PHY Registers, indirect addressed over the XMAC
985 PHY_XMAC_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
986 PHY_XMAC_STAT = 0x01,/* 16 bit r/w PHY Status Register */
987 PHY_XMAC_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
988 PHY_XMAC_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
989 PHY_XMAC_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
990 PHY_XMAC_AUNE_LP = 0x05,/* 16 bit r/o Link Partner Abi Reg */
991 PHY_XMAC_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
992 PHY_XMAC_NEPG = 0x07,/* 16 bit r/w Next Page Register */
993 PHY_XMAC_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
995 PHY_XMAC_EXT_STAT = 0x0f,/* 16 bit r/o Ext Status Register */
996 PHY_XMAC_RES_ABI = 0x10,/* 16 bit r/o PHY Resolved Ability */
999 * Broadcom-PHY Registers, indirect addressed over XMAC
1002 PHY_BCOM_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
1003 PHY_BCOM_STAT = 0x01,/* 16 bit r/o PHY Status Register */
1004 PHY_BCOM_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
1005 PHY_BCOM_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
1006 PHY_BCOM_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
1007 PHY_BCOM_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */
1008 PHY_BCOM_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
1009 PHY_BCOM_NEPG = 0x07,/* 16 bit r/w Next Page Register */
1010 PHY_BCOM_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
1011 /* Broadcom-specific registers */
1012 PHY_BCOM_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
1013 PHY_BCOM_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
1014 PHY_BCOM_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */
1015 PHY_BCOM_P_EXT_CTRL = 0x10,/* 16 bit r/w PHY Extended Ctrl Reg */
1016 PHY_BCOM_P_EXT_STAT = 0x11,/* 16 bit r/o PHY Extended Stat Reg */
1017 PHY_BCOM_RE_CTR = 0x12,/* 16 bit r/w Receive Error Counter */
1018 PHY_BCOM_FC_CTR = 0x13,/* 16 bit r/w False Carrier Sense Cnt */
1019 PHY_BCOM_RNO_CTR = 0x14,/* 16 bit r/w Receiver NOT_OK Cnt */
1021 PHY_BCOM_AUX_CTRL = 0x18,/* 16 bit r/w Auxiliary Control Reg */
1022 PHY_BCOM_AUX_STAT = 0x19,/* 16 bit r/o Auxiliary Stat Summary */
1023 PHY_BCOM_INT_STAT = 0x1a,/* 16 bit r/o Interrupt Status Reg */
1024 PHY_BCOM_INT_MASK = 0x1b,/* 16 bit r/w Interrupt Mask Reg */
1028 * Marvel-PHY Registers, indirect addressed over GMAC
1031 PHY_MARV_CTRL = 0x00,/* 16 bit r/w PHY Control Register */
1032 PHY_MARV_STAT = 0x01,/* 16 bit r/o PHY Status Register */
1033 PHY_MARV_ID0 = 0x02,/* 16 bit r/o PHY ID0 Register */
1034 PHY_MARV_ID1 = 0x03,/* 16 bit r/o PHY ID1 Register */
1035 PHY_MARV_AUNE_ADV = 0x04,/* 16 bit r/w Auto-Neg. Advertisement */
1036 PHY_MARV_AUNE_LP = 0x05,/* 16 bit r/o Link Part Ability Reg */
1037 PHY_MARV_AUNE_EXP = 0x06,/* 16 bit r/o Auto-Neg. Expansion Reg */
1038 PHY_MARV_NEPG = 0x07,/* 16 bit r/w Next Page Register */
1039 PHY_MARV_NEPG_LP = 0x08,/* 16 bit r/o Next Page Link Partner */
1040 /* Marvel-specific registers */
1041 PHY_MARV_1000T_CTRL = 0x09,/* 16 bit r/w 1000Base-T Control Reg */
1042 PHY_MARV_1000T_STAT = 0x0a,/* 16 bit r/o 1000Base-T Status Reg */
1043 PHY_MARV_EXT_STAT = 0x0f,/* 16 bit r/o Extended Status Reg */
1044 PHY_MARV_PHY_CTRL = 0x10,/* 16 bit r/w PHY Specific Ctrl Reg */
1045 PHY_MARV_PHY_STAT = 0x11,/* 16 bit r/o PHY Specific Stat Reg */
1046 PHY_MARV_INT_MASK = 0x12,/* 16 bit r/w Interrupt Mask Reg */
1047 PHY_MARV_INT_STAT = 0x13,/* 16 bit r/o Interrupt Status Reg */
1048 PHY_MARV_EXT_CTRL = 0x14,/* 16 bit r/w Ext. PHY Specific Ctrl */
1049 PHY_MARV_RXE_CNT = 0x15,/* 16 bit r/w Receive Error Counter */
1050 PHY_MARV_EXT_ADR = 0x16,/* 16 bit r/w Ext. Ad. for Cable Diag. */
1051 PHY_MARV_PORT_IRQ = 0x17,/* 16 bit r/o Port 0 IRQ (88E1111 only) */
1052 PHY_MARV_LED_CTRL = 0x18,/* 16 bit r/w LED Control Reg */
1053 PHY_MARV_LED_OVER = 0x19,/* 16 bit r/w Manual LED Override Reg */
1054 PHY_MARV_EXT_CTRL_2 = 0x1a,/* 16 bit r/w Ext. PHY Specific Ctrl 2 */
1055 PHY_MARV_EXT_P_STAT = 0x1b,/* 16 bit r/w Ext. PHY Spec. Stat Reg */
1056 PHY_MARV_CABLE_DIAG = 0x1c,/* 16 bit r/o Cable Diagnostic Reg */
1057 PHY_MARV_PAGE_ADDR = 0x1d,/* 16 bit r/w Extended Page Address Reg */
1058 PHY_MARV_PAGE_DATA = 0x1e,/* 16 bit r/w Extended Page Data Reg */
1060 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1061 PHY_MARV_FE_LED_PAR = 0x16,/* 16 bit r/w LED Parallel Select Reg. */
1062 PHY_MARV_FE_LED_SER = 0x17,/* 16 bit r/w LED Stream Select S. LED */
1063 PHY_MARV_FE_VCT_TX = 0x1a,/* 16 bit r/w VCT Reg. for TXP/N Pins */
1064 PHY_MARV_FE_VCT_RX = 0x1b,/* 16 bit r/o VCT Reg. for RXP/N Pins */
1065 PHY_MARV_FE_SPEC_2 = 0x1c,/* 16 bit r/w Specific Control Reg. 2 */
1069 PHY_CT_RESET = 1<<15, /* Bit 15: (sc) clear all PHY related regs */
1070 PHY_CT_LOOP = 1<<14, /* Bit 14: enable Loopback over PHY */
1071 PHY_CT_SPS_LSB = 1<<13, /* Bit 13: Speed select, lower bit */
1072 PHY_CT_ANE = 1<<12, /* Bit 12: Auto-Negotiation Enabled */
1073 PHY_CT_PDOWN = 1<<11, /* Bit 11: Power Down Mode */
1074 PHY_CT_ISOL = 1<<10, /* Bit 10: Isolate Mode */
1075 PHY_CT_RE_CFG = 1<<9, /* Bit 9: (sc) Restart Auto-Negotiation */
1076 PHY_CT_DUP_MD = 1<<8, /* Bit 8: Duplex Mode */
1077 PHY_CT_COL_TST = 1<<7, /* Bit 7: Collision Test enabled */
1078 PHY_CT_SPS_MSB = 1<<6, /* Bit 6: Speed select, upper bit */
1082 PHY_CT_SP1000 = PHY_CT_SPS_MSB, /* enable speed of 1000 Mbps */
1083 PHY_CT_SP100 = PHY_CT_SPS_LSB, /* enable speed of 100 Mbps */
1084 PHY_CT_SP10 = 0, /* enable speed of 10 Mbps */
1088 PHY_ST_EXT_ST = 1<<8, /* Bit 8: Extended Status Present */
1090 PHY_ST_PRE_SUP = 1<<6, /* Bit 6: Preamble Suppression */
1091 PHY_ST_AN_OVER = 1<<5, /* Bit 5: Auto-Negotiation Over */
1092 PHY_ST_REM_FLT = 1<<4, /* Bit 4: Remote Fault Condition Occured */
1093 PHY_ST_AN_CAP = 1<<3, /* Bit 3: Auto-Negotiation Capability */
1094 PHY_ST_LSYNC = 1<<2, /* Bit 2: Link Synchronized */
1095 PHY_ST_JAB_DET = 1<<1, /* Bit 1: Jabber Detected */
1096 PHY_ST_EXT_REG = 1<<0, /* Bit 0: Extended Register available */
1100 PHY_I1_OUI_MSK = 0x3f<<10, /* Bit 15..10: Organization Unique ID */
1101 PHY_I1_MOD_NUM = 0x3f<<4, /* Bit 9.. 4: Model Number */
1102 PHY_I1_REV_MSK = 0xf, /* Bit 3.. 0: Revision Number */
1105 /* different Broadcom PHY Ids */
1107 PHY_BCOM_ID1_A1 = 0x6041,
1108 PHY_BCOM_ID1_B2 = 0x6043,
1109 PHY_BCOM_ID1_C0 = 0x6044,
1110 PHY_BCOM_ID1_C5 = 0x6047,
1113 /* different Marvell PHY Ids */
1115 PHY_MARV_ID0_VAL= 0x0141, /* Marvell Unique Identifier */
1116 PHY_MARV_ID1_B0 = 0x0C23, /* Yukon (PHY 88E1011) */
1117 PHY_MARV_ID1_B2 = 0x0C25, /* Yukon-Plus (PHY 88E1011) */
1118 PHY_MARV_ID1_C2 = 0x0CC2, /* Yukon-EC (PHY 88E1111) */
1119 PHY_MARV_ID1_Y2 = 0x0C91, /* Yukon-2 (PHY 88E1112) */
1122 /* Advertisement register bits */
1124 PHY_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */
1125 PHY_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */
1126 PHY_AN_RF = 1<<13, /* Bit 13: Remote Fault Bits */
1128 PHY_AN_PAUSE_ASYM = 1<<11,/* Bit 11: Try for asymmetric */
1129 PHY_AN_PAUSE_CAP = 1<<10, /* Bit 10: Try for pause */
1130 PHY_AN_100BASE4 = 1<<9, /* Bit 9: Try for 100mbps 4k packets */
1131 PHY_AN_100FULL = 1<<8, /* Bit 8: Try for 100mbps full-duplex */
1132 PHY_AN_100HALF = 1<<7, /* Bit 7: Try for 100mbps half-duplex */
1133 PHY_AN_10FULL = 1<<6, /* Bit 6: Try for 10mbps full-duplex */
1134 PHY_AN_10HALF = 1<<5, /* Bit 5: Try for 10mbps half-duplex */
1135 PHY_AN_CSMA = 1<<0, /* Bit 0: Only selector supported */
1136 PHY_AN_SEL = 0x1f, /* Bit 4..0: Selector Field, 00001=Ethernet*/
1137 PHY_AN_FULL = PHY_AN_100FULL | PHY_AN_10FULL | PHY_AN_CSMA,
1138 PHY_AN_ALL = PHY_AN_10HALF | PHY_AN_10FULL |
1139 PHY_AN_100HALF | PHY_AN_100FULL,
1144 PHY_X_AN_NXT_PG = 1<<15, /* Bit 15: Request Next Page */
1145 PHY_X_AN_ACK = 1<<14, /* Bit 14: (ro) Acknowledge Received */
1146 PHY_X_AN_RFB = 3<<12,/* Bit 13..12: Remote Fault Bits */
1148 PHY_X_AN_PAUSE = 3<<7,/* Bit 8.. 7: Pause Bits */
1149 PHY_X_AN_HD = 1<<6, /* Bit 6: Half Duplex */
1150 PHY_X_AN_FD = 1<<5, /* Bit 5: Full Duplex */
1153 /* Pause Bits (PHY_X_AN_PAUSE and PHY_X_RS_PAUSE) encoding */
1155 PHY_X_P_NO_PAUSE = 0<<7,/* Bit 8..7: no Pause Mode */
1156 PHY_X_P_SYM_MD = 1<<7, /* Bit 8..7: symmetric Pause Mode */
1157 PHY_X_P_ASYM_MD = 2<<7,/* Bit 8..7: asymmetric Pause Mode */
1158 PHY_X_P_BOTH_MD = 3<<7,/* Bit 8..7: both Pause Mode */
1162 /* Broadcom-Specific */
1163 /***** PHY_BCOM_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1165 PHY_B_1000C_TEST = 7<<13,/* Bit 15..13: Test Modes */
1166 PHY_B_1000C_MSE = 1<<12, /* Bit 12: Master/Slave Enable */
1167 PHY_B_1000C_MSC = 1<<11, /* Bit 11: M/S Configuration */
1168 PHY_B_1000C_RD = 1<<10, /* Bit 10: Repeater/DTE */
1169 PHY_B_1000C_AFD = 1<<9, /* Bit 9: Advertise Full Duplex */
1170 PHY_B_1000C_AHD = 1<<8, /* Bit 8: Advertise Half Duplex */
1173 /***** PHY_BCOM_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1174 /***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1176 PHY_B_1000S_MSF = 1<<15, /* Bit 15: Master/Slave Fault */
1177 PHY_B_1000S_MSR = 1<<14, /* Bit 14: Master/Slave Result */
1178 PHY_B_1000S_LRS = 1<<13, /* Bit 13: Local Receiver Status */
1179 PHY_B_1000S_RRS = 1<<12, /* Bit 12: Remote Receiver Status */
1180 PHY_B_1000S_LP_FD = 1<<11, /* Bit 11: Link Partner can FD */
1181 PHY_B_1000S_LP_HD = 1<<10, /* Bit 10: Link Partner can HD */
1182 /* Bit 9..8: reserved */
1183 PHY_B_1000S_IEC = 0xff, /* Bit 7..0: Idle Error Count */
1186 /***** PHY_BCOM_EXT_STAT 16 bit r/o Extended Status Register *****/
1188 PHY_B_ES_X_FD_CAP = 1<<15, /* Bit 15: 1000Base-X FD capable */
1189 PHY_B_ES_X_HD_CAP = 1<<14, /* Bit 14: 1000Base-X HD capable */
1190 PHY_B_ES_T_FD_CAP = 1<<13, /* Bit 13: 1000Base-T FD capable */
1191 PHY_B_ES_T_HD_CAP = 1<<12, /* Bit 12: 1000Base-T HD capable */
1194 /***** PHY_BCOM_P_EXT_CTRL 16 bit r/w PHY Extended Control Reg *****/
1196 PHY_B_PEC_MAC_PHY = 1<<15, /* Bit 15: 10BIT/GMI-Interface */
1197 PHY_B_PEC_DIS_CROSS = 1<<14, /* Bit 14: Disable MDI Crossover */
1198 PHY_B_PEC_TX_DIS = 1<<13, /* Bit 13: Tx output Disabled */
1199 PHY_B_PEC_INT_DIS = 1<<12, /* Bit 12: Interrupts Disabled */
1200 PHY_B_PEC_F_INT = 1<<11, /* Bit 11: Force Interrupt */
1201 PHY_B_PEC_BY_45 = 1<<10, /* Bit 10: Bypass 4B5B-Decoder */
1202 PHY_B_PEC_BY_SCR = 1<<9, /* Bit 9: Bypass Scrambler */
1203 PHY_B_PEC_BY_MLT3 = 1<<8, /* Bit 8: Bypass MLT3 Encoder */
1204 PHY_B_PEC_BY_RXA = 1<<7, /* Bit 7: Bypass Rx Alignm. */
1205 PHY_B_PEC_RES_SCR = 1<<6, /* Bit 6: Reset Scrambler */
1206 PHY_B_PEC_EN_LTR = 1<<5, /* Bit 5: Ena LED Traffic Mode */
1207 PHY_B_PEC_LED_ON = 1<<4, /* Bit 4: Force LED's on */
1208 PHY_B_PEC_LED_OFF = 1<<3, /* Bit 3: Force LED's off */
1209 PHY_B_PEC_EX_IPG = 1<<2, /* Bit 2: Extend Tx IPG Mode */
1210 PHY_B_PEC_3_LED = 1<<1, /* Bit 1: Three Link LED mode */
1211 PHY_B_PEC_HIGH_LA = 1<<0, /* Bit 0: GMII FIFO Elasticy */
1214 /***** PHY_BCOM_P_EXT_STAT 16 bit r/o PHY Extended Status Reg *****/
1216 PHY_B_PES_CROSS_STAT = 1<<13, /* Bit 13: MDI Crossover Status */
1217 PHY_B_PES_INT_STAT = 1<<12, /* Bit 12: Interrupt Status */
1218 PHY_B_PES_RRS = 1<<11, /* Bit 11: Remote Receiver Stat. */
1219 PHY_B_PES_LRS = 1<<10, /* Bit 10: Local Receiver Stat. */
1220 PHY_B_PES_LOCKED = 1<<9, /* Bit 9: Locked */
1221 PHY_B_PES_LS = 1<<8, /* Bit 8: Link Status */
1222 PHY_B_PES_RF = 1<<7, /* Bit 7: Remote Fault */
1223 PHY_B_PES_CE_ER = 1<<6, /* Bit 6: Carrier Ext Error */
1224 PHY_B_PES_BAD_SSD = 1<<5, /* Bit 5: Bad SSD */
1225 PHY_B_PES_BAD_ESD = 1<<4, /* Bit 4: Bad ESD */
1226 PHY_B_PES_RX_ER = 1<<3, /* Bit 3: Receive Error */
1227 PHY_B_PES_TX_ER = 1<<2, /* Bit 2: Transmit Error */
1228 PHY_B_PES_LOCK_ER = 1<<1, /* Bit 1: Lock Error */
1229 PHY_B_PES_MLT3_ER = 1<<0, /* Bit 0: MLT3 code Error */
1232 /* PHY_BCOM_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/
1233 /* PHY_BCOM_AUNE_LP 16 bit r/o Link Partner Ability Reg *****/
1235 PHY_B_AN_RF = 1<<13, /* Bit 13: Remote Fault */
1237 PHY_B_AN_ASP = 1<<11, /* Bit 11: Asymmetric Pause */
1238 PHY_B_AN_PC = 1<<10, /* Bit 10: Pause Capable */
1242 /***** PHY_BCOM_FC_CTR 16 bit r/w False Carrier Counter *****/
1244 PHY_B_FC_CTR = 0xff, /* Bit 7..0: False Carrier Counter */
1246 /***** PHY_BCOM_RNO_CTR 16 bit r/w Receive NOT_OK Counter *****/
1247 PHY_B_RC_LOC_MSK = 0xff00, /* Bit 15..8: Local Rx NOT_OK cnt */
1248 PHY_B_RC_REM_MSK = 0x00ff, /* Bit 7..0: Remote Rx NOT_OK cnt */
1250 /***** PHY_BCOM_AUX_CTRL 16 bit r/w Auxiliary Control Reg *****/
1251 PHY_B_AC_L_SQE = 1<<15, /* Bit 15: Low Squelch */
1252 PHY_B_AC_LONG_PACK = 1<<14, /* Bit 14: Rx Long Packets */
1253 PHY_B_AC_ER_CTRL = 3<<12,/* Bit 13..12: Edgerate Control */
1254 /* Bit 11: reserved */
1255 PHY_B_AC_TX_TST = 1<<10, /* Bit 10: Tx test bit, always 1 */
1256 /* Bit 9.. 8: reserved */
1257 PHY_B_AC_DIS_PRF = 1<<7, /* Bit 7: dis part resp filter */
1258 /* Bit 6: reserved */
1259 PHY_B_AC_DIS_PM = 1<<5, /* Bit 5: dis power management */
1260 /* Bit 4: reserved */
1261 PHY_B_AC_DIAG = 1<<3, /* Bit 3: Diagnostic Mode */
1264 /***** PHY_BCOM_AUX_STAT 16 bit r/o Auxiliary Status Reg *****/
1266 PHY_B_AS_AN_C = 1<<15, /* Bit 15: AutoNeg complete */
1267 PHY_B_AS_AN_CA = 1<<14, /* Bit 14: AN Complete Ack */
1268 PHY_B_AS_ANACK_D = 1<<13, /* Bit 13: AN Ack Detect */
1269 PHY_B_AS_ANAB_D = 1<<12, /* Bit 12: AN Ability Detect */
1270 PHY_B_AS_NPW = 1<<11, /* Bit 11: AN Next Page Wait */
1271 PHY_B_AS_AN_RES_MSK = 7<<8,/* Bit 10..8: AN HDC */
1272 PHY_B_AS_PDF = 1<<7, /* Bit 7: Parallel Detect. Fault */
1273 PHY_B_AS_RF = 1<<6, /* Bit 6: Remote Fault */
1274 PHY_B_AS_ANP_R = 1<<5, /* Bit 5: AN Page Received */
1275 PHY_B_AS_LP_ANAB = 1<<4, /* Bit 4: LP AN Ability */
1276 PHY_B_AS_LP_NPAB = 1<<3, /* Bit 3: LP Next Page Ability */
1277 PHY_B_AS_LS = 1<<2, /* Bit 2: Link Status */
1278 PHY_B_AS_PRR = 1<<1, /* Bit 1: Pause Resolution-Rx */
1279 PHY_B_AS_PRT = 1<<0, /* Bit 0: Pause Resolution-Tx */
1281 #define PHY_B_AS_PAUSE_MSK (PHY_B_AS_PRR | PHY_B_AS_PRT)
1283 /***** PHY_BCOM_INT_STAT 16 bit r/o Interrupt Status Reg *****/
1284 /***** PHY_BCOM_INT_MASK 16 bit r/w Interrupt Mask Reg *****/
1286 PHY_B_IS_PSE = 1<<14, /* Bit 14: Pair Swap Error */
1287 PHY_B_IS_MDXI_SC = 1<<13, /* Bit 13: MDIX Status Change */
1288 PHY_B_IS_HCT = 1<<12, /* Bit 12: counter above 32k */
1289 PHY_B_IS_LCT = 1<<11, /* Bit 11: counter above 128 */
1290 PHY_B_IS_AN_PR = 1<<10, /* Bit 10: Page Received */
1291 PHY_B_IS_NO_HDCL = 1<<9, /* Bit 9: No HCD Link */
1292 PHY_B_IS_NO_HDC = 1<<8, /* Bit 8: No HCD */
1293 PHY_B_IS_NEG_USHDC = 1<<7, /* Bit 7: Negotiated Unsup. HCD */
1294 PHY_B_IS_SCR_S_ER = 1<<6, /* Bit 6: Scrambler Sync Error */
1295 PHY_B_IS_RRS_CHANGE = 1<<5, /* Bit 5: Remote Rx Stat Change */
1296 PHY_B_IS_LRS_CHANGE = 1<<4, /* Bit 4: Local Rx Stat Change */
1297 PHY_B_IS_DUP_CHANGE = 1<<3, /* Bit 3: Duplex Mode Change */
1298 PHY_B_IS_LSP_CHANGE = 1<<2, /* Bit 2: Link Speed Change */
1299 PHY_B_IS_LST_CHANGE = 1<<1, /* Bit 1: Link Status Changed */
1300 PHY_B_IS_CRC_ER = 1<<0, /* Bit 0: CRC Error */
1302 #define PHY_B_DEF_MSK \
1303 (~(PHY_B_IS_PSE | PHY_B_IS_AN_PR | PHY_B_IS_DUP_CHANGE | \
1304 PHY_B_IS_LSP_CHANGE | PHY_B_IS_LST_CHANGE))
1306 /* Pause Bits (PHY_B_AN_ASP and PHY_B_AN_PC) encoding */
1308 PHY_B_P_NO_PAUSE = 0<<10,/* Bit 11..10: no Pause Mode */
1309 PHY_B_P_SYM_MD = 1<<10, /* Bit 11..10: symmetric Pause Mode */
1310 PHY_B_P_ASYM_MD = 2<<10,/* Bit 11..10: asymmetric Pause Mode */
1311 PHY_B_P_BOTH_MD = 3<<10,/* Bit 11..10: both Pause Mode */
1314 * Resolved Duplex mode and Capabilities (Aux Status Summary Reg)
1317 PHY_B_RES_1000FD = 7<<8,/* Bit 10..8: 1000Base-T Full Dup. */
1318 PHY_B_RES_1000HD = 6<<8,/* Bit 10..8: 1000Base-T Half Dup. */
1321 /** Marvell-Specific */
1323 PHY_M_AN_NXT_PG = 1<<15, /* Request Next Page */
1324 PHY_M_AN_ACK = 1<<14, /* (ro) Acknowledge Received */
1325 PHY_M_AN_RF = 1<<13, /* Remote Fault */
1327 PHY_M_AN_ASP = 1<<11, /* Asymmetric Pause */
1328 PHY_M_AN_PC = 1<<10, /* MAC Pause implemented */
1329 PHY_M_AN_100_T4 = 1<<9, /* Not cap. 100Base-T4 (always 0) */
1330 PHY_M_AN_100_FD = 1<<8, /* Advertise 100Base-TX Full Duplex */
1331 PHY_M_AN_100_HD = 1<<7, /* Advertise 100Base-TX Half Duplex */
1332 PHY_M_AN_10_FD = 1<<6, /* Advertise 10Base-TX Full Duplex */
1333 PHY_M_AN_10_HD = 1<<5, /* Advertise 10Base-TX Half Duplex */
1334 PHY_M_AN_SEL_MSK =0x1f<<4, /* Bit 4.. 0: Selector Field Mask */
1337 /* special defines for FIBER (88E1011S only) */
1339 PHY_M_AN_ASP_X = 1<<8, /* Asymmetric Pause */
1340 PHY_M_AN_PC_X = 1<<7, /* MAC Pause implemented */
1341 PHY_M_AN_1000X_AHD = 1<<6, /* Advertise 10000Base-X Half Duplex */
1342 PHY_M_AN_1000X_AFD = 1<<5, /* Advertise 10000Base-X Full Duplex */
1345 /* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */
1347 PHY_M_P_NO_PAUSE_X = 0<<7,/* Bit 8.. 7: no Pause Mode */
1348 PHY_M_P_SYM_MD_X = 1<<7, /* Bit 8.. 7: symmetric Pause Mode */
1349 PHY_M_P_ASYM_MD_X = 2<<7,/* Bit 8.. 7: asymmetric Pause Mode */
1350 PHY_M_P_BOTH_MD_X = 3<<7,/* Bit 8.. 7: both Pause Mode */
1353 /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1355 PHY_M_1000C_TEST = 7<<13,/* Bit 15..13: Test Modes */
1356 PHY_M_1000C_MSE = 1<<12, /* Manual Master/Slave Enable */
1357 PHY_M_1000C_MSC = 1<<11, /* M/S Configuration (1=Master) */
1358 PHY_M_1000C_MPD = 1<<10, /* Multi-Port Device */
1359 PHY_M_1000C_AFD = 1<<9, /* Advertise Full Duplex */
1360 PHY_M_1000C_AHD = 1<<8, /* Advertise Half Duplex */
1363 /***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/
1365 PHY_M_PC_TX_FFD_MSK = 3<<14,/* Bit 15..14: Tx FIFO Depth Mask */
1366 PHY_M_PC_RX_FFD_MSK = 3<<12,/* Bit 13..12: Rx FIFO Depth Mask */
1367 PHY_M_PC_ASS_CRS_TX = 1<<11, /* Assert CRS on Transmit */
1368 PHY_M_PC_FL_GOOD = 1<<10, /* Force Link Good */
1369 PHY_M_PC_EN_DET_MSK = 3<<8,/* Bit 9.. 8: Energy Detect Mask */
1370 PHY_M_PC_ENA_EXT_D = 1<<7, /* Enable Ext. Distance (10BT) */
1371 PHY_M_PC_MDIX_MSK = 3<<5,/* Bit 6.. 5: MDI/MDIX Config. Mask */
1372 PHY_M_PC_DIS_125CLK = 1<<4, /* Disable 125 CLK */
1373 PHY_M_PC_MAC_POW_UP = 1<<3, /* MAC Power up */
1374 PHY_M_PC_SQE_T_ENA = 1<<2, /* SQE Test Enabled */
1375 PHY_M_PC_POL_R_DIS = 1<<1, /* Polarity Reversal Disabled */
1376 PHY_M_PC_DIS_JABBER = 1<<0, /* Disable Jabber */
1380 PHY_M_PC_EN_DET = 2<<8, /* Energy Detect (Mode 1) */
1381 PHY_M_PC_EN_DET_PLUS = 3<<8, /* Energy Detect Plus (Mode 2) */
1384 #define PHY_M_PC_MDI_XMODE(x) (((x)<<5) & PHY_M_PC_MDIX_MSK)
1387 PHY_M_PC_MAN_MDI = 0, /* 00 = Manual MDI configuration */
1388 PHY_M_PC_MAN_MDIX = 1, /* 01 = Manual MDIX configuration */
1389 PHY_M_PC_ENA_AUTO = 3, /* 11 = Enable Automatic Crossover */
1392 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1394 PHY_M_PC_ENA_DTE_DT = 1<<15, /* Enable Data Terminal Equ. (DTE) Detect */
1395 PHY_M_PC_ENA_ENE_DT = 1<<14, /* Enable Energy Detect (sense & pulse) */
1396 PHY_M_PC_DIS_NLP_CK = 1<<13, /* Disable Normal Link Puls (NLP) Check */
1397 PHY_M_PC_ENA_LIP_NP = 1<<12, /* Enable Link Partner Next Page Reg. */
1398 PHY_M_PC_DIS_NLP_GN = 1<<11, /* Disable Normal Link Puls Generation */
1400 PHY_M_PC_DIS_SCRAMB = 1<<9, /* Disable Scrambler */
1401 PHY_M_PC_DIS_FEFI = 1<<8, /* Disable Far End Fault Indic. (FEFI) */
1403 PHY_M_PC_SH_TP_SEL = 1<<6, /* Shielded Twisted Pair Select */
1404 PHY_M_PC_RX_FD_MSK = 3<<2,/* Bit 3.. 2: Rx FIFO Depth Mask */
1407 /***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/
1409 PHY_M_PS_SPEED_MSK = 3<<14, /* Bit 15..14: Speed Mask */
1410 PHY_M_PS_SPEED_1000 = 1<<15, /* 10 = 1000 Mbps */
1411 PHY_M_PS_SPEED_100 = 1<<14, /* 01 = 100 Mbps */
1412 PHY_M_PS_SPEED_10 = 0, /* 00 = 10 Mbps */
1413 PHY_M_PS_FULL_DUP = 1<<13, /* Full Duplex */
1414 PHY_M_PS_PAGE_REC = 1<<12, /* Page Received */
1415 PHY_M_PS_SPDUP_RES = 1<<11, /* Speed & Duplex Resolved */
1416 PHY_M_PS_LINK_UP = 1<<10, /* Link Up */
1417 PHY_M_PS_CABLE_MSK = 7<<7, /* Bit 9.. 7: Cable Length Mask */
1418 PHY_M_PS_MDI_X_STAT = 1<<6, /* MDI Crossover Stat (1=MDIX) */
1419 PHY_M_PS_DOWNS_STAT = 1<<5, /* Downshift Status (1=downsh.) */
1420 PHY_M_PS_ENDET_STAT = 1<<4, /* Energy Detect Status (1=act) */
1421 PHY_M_PS_TX_P_EN = 1<<3, /* Tx Pause Enabled */
1422 PHY_M_PS_RX_P_EN = 1<<2, /* Rx Pause Enabled */
1423 PHY_M_PS_POL_REV = 1<<1, /* Polarity Reversed */
1424 PHY_M_PS_JABBER = 1<<0, /* Jabber */
1427 #define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN)
1429 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1431 PHY_M_PS_DTE_DETECT = 1<<15, /* Data Terminal Equipment (DTE) Detected */
1432 PHY_M_PS_RES_SPEED = 1<<14, /* Resolved Speed (1=100 Mbps, 0=10 Mbps */
1436 PHY_M_IS_AN_ERROR = 1<<15, /* Auto-Negotiation Error */
1437 PHY_M_IS_LSP_CHANGE = 1<<14, /* Link Speed Changed */
1438 PHY_M_IS_DUP_CHANGE = 1<<13, /* Duplex Mode Changed */
1439 PHY_M_IS_AN_PR = 1<<12, /* Page Received */
1440 PHY_M_IS_AN_COMPL = 1<<11, /* Auto-Negotiation Completed */
1441 PHY_M_IS_LST_CHANGE = 1<<10, /* Link Status Changed */
1442 PHY_M_IS_SYMB_ERROR = 1<<9, /* Symbol Error */
1443 PHY_M_IS_FALSE_CARR = 1<<8, /* False Carrier */
1444 PHY_M_IS_FIFO_ERROR = 1<<7, /* FIFO Overflow/Underrun Error */
1445 PHY_M_IS_MDI_CHANGE = 1<<6, /* MDI Crossover Changed */
1446 PHY_M_IS_DOWNSH_DET = 1<<5, /* Downshift Detected */
1447 PHY_M_IS_END_CHANGE = 1<<4, /* Energy Detect Changed */
1449 PHY_M_IS_DTE_CHANGE = 1<<2, /* DTE Power Det. Status Changed */
1450 PHY_M_IS_POL_CHANGE = 1<<1, /* Polarity Changed */
1451 PHY_M_IS_JABBER = 1<<0, /* Jabber */
1453 PHY_M_IS_DEF_MSK = PHY_M_IS_AN_ERROR | PHY_M_IS_LSP_CHANGE |
1454 PHY_M_IS_LST_CHANGE | PHY_M_IS_FIFO_ERROR,
1456 PHY_M_IS_AN_MSK = PHY_M_IS_AN_ERROR | PHY_M_IS_AN_COMPL,
1459 /***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/
1461 PHY_M_EC_ENA_BC_EXT = 1<<15, /* Enable Block Carr. Ext. (88E1111 only) */
1462 PHY_M_EC_ENA_LIN_LB = 1<<14, /* Enable Line Loopback (88E1111 only) */
1464 PHY_M_EC_DIS_LINK_P = 1<<12, /* Disable Link Pulses (88E1111 only) */
1465 PHY_M_EC_M_DSC_MSK = 3<<10, /* Bit 11..10: Master Downshift Counter */
1466 /* (88E1011 only) */
1467 PHY_M_EC_S_DSC_MSK = 3<<8,/* Bit 9.. 8: Slave Downshift Counter */
1468 /* (88E1011 only) */
1469 PHY_M_EC_M_DSC_MSK2 = 7<<9,/* Bit 11.. 9: Master Downshift Counter */
1470 /* (88E1111 only) */
1471 PHY_M_EC_DOWN_S_ENA = 1<<8, /* Downshift Enable (88E1111 only) */
1472 /* !!! Errata in spec. (1 = disable) */
1473 PHY_M_EC_RX_TIM_CT = 1<<7, /* RGMII Rx Timing Control*/
1474 PHY_M_EC_MAC_S_MSK = 7<<4,/* Bit 6.. 4: Def. MAC interface speed */
1475 PHY_M_EC_FIB_AN_ENA = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */
1476 PHY_M_EC_DTE_D_ENA = 1<<2, /* DTE Detect Enable (88E1111 only) */
1477 PHY_M_EC_TX_TIM_CT = 1<<1, /* RGMII Tx Timing Control */
1478 PHY_M_EC_TRANS_DIS = 1<<0, /* Transmitter Disable (88E1111 only) */};
1480 #define PHY_M_EC_M_DSC(x) ((x)<<10) /* 00=1x; 01=2x; 10=3x; 11=4x */
1481 #define PHY_M_EC_S_DSC(x) ((x)<<8) /* 00=dis; 01=1x; 10=2x; 11=3x */
1482 #define PHY_M_EC_MAC_S(x) ((x)<<4) /* 01X=0; 110=2.5; 111=25 (MHz) */
1484 #define PHY_M_EC_M_DSC_2(x) ((x)<<9) /* 000=1x; 001=2x; 010=3x; 011=4x */
1485 /* 100=5x; 101=6x; 110=7x; 111=8x */
1487 MAC_TX_CLK_0_MHZ = 2,
1488 MAC_TX_CLK_2_5_MHZ = 6,
1489 MAC_TX_CLK_25_MHZ = 7,
1492 /***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/
1494 PHY_M_LEDC_DIS_LED = 1<<15, /* Disable LED */
1495 PHY_M_LEDC_PULS_MSK = 7<<12,/* Bit 14..12: Pulse Stretch Mask */
1496 PHY_M_LEDC_F_INT = 1<<11, /* Force Interrupt */
1497 PHY_M_LEDC_BL_R_MSK = 7<<8,/* Bit 10.. 8: Blink Rate Mask */
1498 PHY_M_LEDC_DP_C_LSB = 1<<7, /* Duplex Control (LSB, 88E1111 only) */
1499 PHY_M_LEDC_TX_C_LSB = 1<<6, /* Tx Control (LSB, 88E1111 only) */
1500 PHY_M_LEDC_LK_C_MSK = 7<<3,/* Bit 5.. 3: Link Control Mask */
1501 /* (88E1111 only) */
1505 PHY_M_LEDC_LINK_MSK = 3<<3,/* Bit 4.. 3: Link Control Mask */
1506 /* (88E1011 only) */
1507 PHY_M_LEDC_DP_CTRL = 1<<2, /* Duplex Control */
1508 PHY_M_LEDC_DP_C_MSB = 1<<2, /* Duplex Control (MSB, 88E1111 only) */
1509 PHY_M_LEDC_RX_CTRL = 1<<1, /* Rx Activity / Link */
1510 PHY_M_LEDC_TX_CTRL = 1<<0, /* Tx Activity / Link */
1511 PHY_M_LEDC_TX_C_MSB = 1<<0, /* Tx Control (MSB, 88E1111 only) */
1514 #define PHY_M_LED_PULS_DUR(x) (((x)<<12) & PHY_M_LEDC_PULS_MSK)
1517 PULS_NO_STR = 0,/* no pulse stretching */
1518 PULS_21MS = 1,/* 21 ms to 42 ms */
1519 PULS_42MS = 2,/* 42 ms to 84 ms */
1520 PULS_84MS = 3,/* 84 ms to 170 ms */
1521 PULS_170MS = 4,/* 170 ms to 340 ms */
1522 PULS_340MS = 5,/* 340 ms to 670 ms */
1523 PULS_670MS = 6,/* 670 ms to 1.3 s */
1524 PULS_1300MS = 7,/* 1.3 s to 2.7 s */
1527 #define PHY_M_LED_BLINK_RT(x) (((x)<<8) & PHY_M_LEDC_BL_R_MSK)
1530 BLINK_42MS = 0,/* 42 ms */
1531 BLINK_84MS = 1,/* 84 ms */
1532 BLINK_170MS = 2,/* 170 ms */
1533 BLINK_340MS = 3,/* 340 ms */
1534 BLINK_670MS = 4,/* 670 ms */
1537 /***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/
1538 #define PHY_M_LED_MO_SGMII(x) ((x)<<14) /* Bit 15..14: SGMII AN Timer */
1539 /* Bit 13..12: reserved */
1540 #define PHY_M_LED_MO_DUP(x) ((x)<<10) /* Bit 11..10: Duplex */
1541 #define PHY_M_LED_MO_10(x) ((x)<<8) /* Bit 9.. 8: Link 10 */
1542 #define PHY_M_LED_MO_100(x) ((x)<<6) /* Bit 7.. 6: Link 100 */
1543 #define PHY_M_LED_MO_1000(x) ((x)<<4) /* Bit 5.. 4: Link 1000 */
1544 #define PHY_M_LED_MO_RX(x) ((x)<<2) /* Bit 3.. 2: Rx */
1545 #define PHY_M_LED_MO_TX(x) ((x)<<0) /* Bit 1.. 0: Tx */
1554 /***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/
1556 PHY_M_EC2_FI_IMPED = 1<<6, /* Fiber Input Impedance */
1557 PHY_M_EC2_FO_IMPED = 1<<5, /* Fiber Output Impedance */
1558 PHY_M_EC2_FO_M_CLK = 1<<4, /* Fiber Mode Clock Enable */
1559 PHY_M_EC2_FO_BOOST = 1<<3, /* Fiber Output Boost */
1560 PHY_M_EC2_FO_AM_MSK = 7,/* Bit 2.. 0: Fiber Output Amplitude */
1563 /***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/
1565 PHY_M_FC_AUTO_SEL = 1<<15, /* Fiber/Copper Auto Sel. Dis. */
1566 PHY_M_FC_AN_REG_ACC = 1<<14, /* Fiber/Copper AN Reg. Access */
1567 PHY_M_FC_RESOLUTION = 1<<13, /* Fiber/Copper Resolution */
1568 PHY_M_SER_IF_AN_BP = 1<<12, /* Ser. IF AN Bypass Enable */
1569 PHY_M_SER_IF_BP_ST = 1<<11, /* Ser. IF AN Bypass Status */
1570 PHY_M_IRQ_POLARITY = 1<<10, /* IRQ polarity */
1571 PHY_M_DIS_AUT_MED = 1<<9, /* Disable Aut. Medium Reg. Selection */
1572 /* (88E1111 only) */
1573 /* Bit 9.. 4: reserved (88E1011 only) */
1574 PHY_M_UNDOC1 = 1<<7, /* undocumented bit !! */
1575 PHY_M_DTE_POW_STAT = 1<<4, /* DTE Power Status (88E1111 only) */
1576 PHY_M_MODE_MASK = 0xf, /* Bit 3.. 0: copy of HWCFG MODE[3:0] */
1579 /***** PHY_MARV_CABLE_DIAG 16 bit r/o Cable Diagnostic Reg *****/
1581 PHY_M_CABD_ENA_TEST = 1<<15, /* Enable Test (Page 0) */
1582 PHY_M_CABD_DIS_WAIT = 1<<15, /* Disable Waiting Period (Page 1) */
1583 /* (88E1111 only) */
1584 PHY_M_CABD_STAT_MSK = 3<<13, /* Bit 14..13: Status Mask */
1585 PHY_M_CABD_AMPL_MSK = 0x1f<<8,/* Bit 12.. 8: Amplitude Mask */
1586 /* (88E1111 only) */
1587 PHY_M_CABD_DIST_MSK = 0xff, /* Bit 7.. 0: Distance Mask */
1590 /* values for Cable Diagnostic Status (11=fail; 00=OK; 10=open; 01=short) */
1592 CABD_STAT_NORMAL= 0,
1593 CABD_STAT_SHORT = 1,
1598 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1599 /***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/
1600 /* Bit 15..12: reserved (used internally) */
1602 PHY_M_FELP_LED2_MSK = 0xf<<8, /* Bit 11.. 8: LED2 Mask (LINK) */
1603 PHY_M_FELP_LED1_MSK = 0xf<<4, /* Bit 7.. 4: LED1 Mask (ACT) */
1604 PHY_M_FELP_LED0_MSK = 0xf, /* Bit 3.. 0: LED0 Mask (SPEED) */
1607 #define PHY_M_FELP_LED2_CTRL(x) (((x)<<8) & PHY_M_FELP_LED2_MSK)
1608 #define PHY_M_FELP_LED1_CTRL(x) (((x)<<4) & PHY_M_FELP_LED1_MSK)
1609 #define PHY_M_FELP_LED0_CTRL(x) (((x)<<0) & PHY_M_FELP_LED0_MSK)
1612 LED_PAR_CTRL_COLX = 0x00,
1613 LED_PAR_CTRL_ERROR = 0x01,
1614 LED_PAR_CTRL_DUPLEX = 0x02,
1615 LED_PAR_CTRL_DP_COL = 0x03,
1616 LED_PAR_CTRL_SPEED = 0x04,
1617 LED_PAR_CTRL_LINK = 0x05,
1618 LED_PAR_CTRL_TX = 0x06,
1619 LED_PAR_CTRL_RX = 0x07,
1620 LED_PAR_CTRL_ACT = 0x08,
1621 LED_PAR_CTRL_LNK_RX = 0x09,
1622 LED_PAR_CTRL_LNK_AC = 0x0a,
1623 LED_PAR_CTRL_ACT_BL = 0x0b,
1624 LED_PAR_CTRL_TX_BL = 0x0c,
1625 LED_PAR_CTRL_RX_BL = 0x0d,
1626 LED_PAR_CTRL_COL_BL = 0x0e,
1627 LED_PAR_CTRL_INACT = 0x0f
1630 /*****,PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/
1632 PHY_M_FESC_DIS_WAIT = 1<<2, /* Disable TDR Waiting Period */
1633 PHY_M_FESC_ENA_MCLK = 1<<1, /* Enable MAC Rx Clock in sleep mode */
1634 PHY_M_FESC_SEL_CL_A = 1<<0, /* Select Class A driver (100B-TX) */
1637 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1638 /***** PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl *****/
1640 PHY_M_MAC_MD_MSK = 7<<7, /* Bit 9.. 7: Mode Select Mask */
1641 PHY_M_MAC_MD_AUTO = 3,/* Auto Copper/1000Base-X */
1642 PHY_M_MAC_MD_COPPER = 5,/* Copper only */
1643 PHY_M_MAC_MD_1000BX = 7,/* 1000Base-X only */
1645 #define PHY_M_MAC_MODE_SEL(x) (((x)<<7) & PHY_M_MAC_MD_MSK)
1647 /***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/
1649 PHY_M_LEDC_LOS_MSK = 0xf<<12,/* Bit 15..12: LOS LED Ctrl. Mask */
1650 PHY_M_LEDC_INIT_MSK = 0xf<<8, /* Bit 11.. 8: INIT LED Ctrl. Mask */
1651 PHY_M_LEDC_STA1_MSK = 0xf<<4,/* Bit 7.. 4: STAT1 LED Ctrl. Mask */
1652 PHY_M_LEDC_STA0_MSK = 0xf, /* Bit 3.. 0: STAT0 LED Ctrl. Mask */
1655 #define PHY_M_LEDC_LOS_CTRL(x) (((x)<<12) & PHY_M_LEDC_LOS_MSK)
1656 #define PHY_M_LEDC_INIT_CTRL(x) (((x)<<8) & PHY_M_LEDC_INIT_MSK)
1657 #define PHY_M_LEDC_STA1_CTRL(x) (((x)<<4) & PHY_M_LEDC_STA1_MSK)
1658 #define PHY_M_LEDC_STA0_CTRL(x) (((x)<<0) & PHY_M_LEDC_STA0_MSK)
1660 /* GMAC registers */
1661 /* Port Registers */
1663 GM_GP_STAT = 0x0000, /* 16 bit r/o General Purpose Status */
1664 GM_GP_CTRL = 0x0004, /* 16 bit r/w General Purpose Control */
1665 GM_TX_CTRL = 0x0008, /* 16 bit r/w Transmit Control Reg. */
1666 GM_RX_CTRL = 0x000c, /* 16 bit r/w Receive Control Reg. */
1667 GM_TX_FLOW_CTRL = 0x0010, /* 16 bit r/w Transmit Flow-Control */
1668 GM_TX_PARAM = 0x0014, /* 16 bit r/w Transmit Parameter Reg. */
1669 GM_SERIAL_MODE = 0x0018, /* 16 bit r/w Serial Mode Register */
1670 /* Source Address Registers */
1671 GM_SRC_ADDR_1L = 0x001c, /* 16 bit r/w Source Address 1 (low) */
1672 GM_SRC_ADDR_1M = 0x0020, /* 16 bit r/w Source Address 1 (middle) */
1673 GM_SRC_ADDR_1H = 0x0024, /* 16 bit r/w Source Address 1 (high) */
1674 GM_SRC_ADDR_2L = 0x0028, /* 16 bit r/w Source Address 2 (low) */
1675 GM_SRC_ADDR_2M = 0x002c, /* 16 bit r/w Source Address 2 (middle) */
1676 GM_SRC_ADDR_2H = 0x0030, /* 16 bit r/w Source Address 2 (high) */
1678 /* Multicast Address Hash Registers */
1679 GM_MC_ADDR_H1 = 0x0034, /* 16 bit r/w Multicast Address Hash 1 */
1680 GM_MC_ADDR_H2 = 0x0038, /* 16 bit r/w Multicast Address Hash 2 */
1681 GM_MC_ADDR_H3 = 0x003c, /* 16 bit r/w Multicast Address Hash 3 */
1682 GM_MC_ADDR_H4 = 0x0040, /* 16 bit r/w Multicast Address Hash 4 */
1684 /* Interrupt Source Registers */
1685 GM_TX_IRQ_SRC = 0x0044, /* 16 bit r/o Tx Overflow IRQ Source */
1686 GM_RX_IRQ_SRC = 0x0048, /* 16 bit r/o Rx Overflow IRQ Source */
1687 GM_TR_IRQ_SRC = 0x004c, /* 16 bit r/o Tx/Rx Over. IRQ Source */
1689 /* Interrupt Mask Registers */
1690 GM_TX_IRQ_MSK = 0x0050, /* 16 bit r/w Tx Overflow IRQ Mask */
1691 GM_RX_IRQ_MSK = 0x0054, /* 16 bit r/w Rx Overflow IRQ Mask */
1692 GM_TR_IRQ_MSK = 0x0058, /* 16 bit r/w Tx/Rx Over. IRQ Mask */
1694 /* Serial Management Interface (SMI) Registers */
1695 GM_SMI_CTRL = 0x0080, /* 16 bit r/w SMI Control Register */
1696 GM_SMI_DATA = 0x0084, /* 16 bit r/w SMI Data Register */
1697 GM_PHY_ADDR = 0x0088, /* 16 bit r/w GPHY Address Register */
1701 #define GM_MIB_CNT_BASE 0x0100 /* Base Address of MIB Counters */
1702 #define GM_MIB_CNT_SIZE 44 /* Number of MIB Counters */
1705 * MIB Counters base address definitions (low word) -
1706 * use offset 4 for access to high word (32 bit r/o)
1709 GM_RXF_UC_OK = GM_MIB_CNT_BASE + 0, /* Unicast Frames Received OK */
1710 GM_RXF_BC_OK = GM_MIB_CNT_BASE + 8, /* Broadcast Frames Received OK */
1711 GM_RXF_MPAUSE = GM_MIB_CNT_BASE + 16, /* Pause MAC Ctrl Frames Received */
1712 GM_RXF_MC_OK = GM_MIB_CNT_BASE + 24, /* Multicast Frames Received OK */
1713 GM_RXF_FCS_ERR = GM_MIB_CNT_BASE + 32, /* Rx Frame Check Seq. Error */
1714 /* GM_MIB_CNT_BASE + 40: reserved */
1715 GM_RXO_OK_LO = GM_MIB_CNT_BASE + 48, /* Octets Received OK Low */
1716 GM_RXO_OK_HI = GM_MIB_CNT_BASE + 56, /* Octets Received OK High */
1717 GM_RXO_ERR_LO = GM_MIB_CNT_BASE + 64, /* Octets Received Invalid Low */
1718 GM_RXO_ERR_HI = GM_MIB_CNT_BASE + 72, /* Octets Received Invalid High */
1719 GM_RXF_SHT = GM_MIB_CNT_BASE + 80, /* Frames <64 Byte Received OK */
1720 GM_RXE_FRAG = GM_MIB_CNT_BASE + 88, /* Frames <64 Byte Received with FCS Err */
1721 GM_RXF_64B = GM_MIB_CNT_BASE + 96, /* 64 Byte Rx Frame */
1722 GM_RXF_127B = GM_MIB_CNT_BASE + 104, /* 65-127 Byte Rx Frame */
1723 GM_RXF_255B = GM_MIB_CNT_BASE + 112, /* 128-255 Byte Rx Frame */
1724 GM_RXF_511B = GM_MIB_CNT_BASE + 120, /* 256-511 Byte Rx Frame */
1725 GM_RXF_1023B = GM_MIB_CNT_BASE + 128, /* 512-1023 Byte Rx Frame */
1726 GM_RXF_1518B = GM_MIB_CNT_BASE + 136, /* 1024-1518 Byte Rx Frame */
1727 GM_RXF_MAX_SZ = GM_MIB_CNT_BASE + 144, /* 1519-MaxSize Byte Rx Frame */
1728 GM_RXF_LNG_ERR = GM_MIB_CNT_BASE + 152, /* Rx Frame too Long Error */
1729 GM_RXF_JAB_PKT = GM_MIB_CNT_BASE + 160, /* Rx Jabber Packet Frame */
1730 /* GM_MIB_CNT_BASE + 168: reserved */
1731 GM_RXE_FIFO_OV = GM_MIB_CNT_BASE + 176, /* Rx FIFO overflow Event */
1732 /* GM_MIB_CNT_BASE + 184: reserved */
1733 GM_TXF_UC_OK = GM_MIB_CNT_BASE + 192, /* Unicast Frames Xmitted OK */
1734 GM_TXF_BC_OK = GM_MIB_CNT_BASE + 200, /* Broadcast Frames Xmitted OK */
1735 GM_TXF_MPAUSE = GM_MIB_CNT_BASE + 208, /* Pause MAC Ctrl Frames Xmitted */
1736 GM_TXF_MC_OK = GM_MIB_CNT_BASE + 216, /* Multicast Frames Xmitted OK */
1737 GM_TXO_OK_LO = GM_MIB_CNT_BASE + 224, /* Octets Transmitted OK Low */
1738 GM_TXO_OK_HI = GM_MIB_CNT_BASE + 232, /* Octets Transmitted OK High */
1739 GM_TXF_64B = GM_MIB_CNT_BASE + 240, /* 64 Byte Tx Frame */
1740 GM_TXF_127B = GM_MIB_CNT_BASE + 248, /* 65-127 Byte Tx Frame */
1741 GM_TXF_255B = GM_MIB_CNT_BASE + 256, /* 128-255 Byte Tx Frame */
1742 GM_TXF_511B = GM_MIB_CNT_BASE + 264, /* 256-511 Byte Tx Frame */
1743 GM_TXF_1023B = GM_MIB_CNT_BASE + 272, /* 512-1023 Byte Tx Frame */
1744 GM_TXF_1518B = GM_MIB_CNT_BASE + 280, /* 1024-1518 Byte Tx Frame */
1745 GM_TXF_MAX_SZ = GM_MIB_CNT_BASE + 288, /* 1519-MaxSize Byte Tx Frame */
1747 GM_TXF_COL = GM_MIB_CNT_BASE + 304, /* Tx Collision */
1748 GM_TXF_LAT_COL = GM_MIB_CNT_BASE + 312, /* Tx Late Collision */
1749 GM_TXF_ABO_COL = GM_MIB_CNT_BASE + 320, /* Tx aborted due to Exces. Col. */
1750 GM_TXF_MUL_COL = GM_MIB_CNT_BASE + 328, /* Tx Multiple Collision */
1751 GM_TXF_SNG_COL = GM_MIB_CNT_BASE + 336, /* Tx Single Collision */
1752 GM_TXE_FIFO_UR = GM_MIB_CNT_BASE + 344, /* Tx FIFO Underrun Event */
1755 /* GMAC Bit Definitions */
1756 /* GM_GP_STAT 16 bit r/o General Purpose Status Register */
1758 GM_GPSR_SPEED = 1<<15, /* Bit 15: Port Speed (1 = 100 Mbps) */
1759 GM_GPSR_DUPLEX = 1<<14, /* Bit 14: Duplex Mode (1 = Full) */
1760 GM_GPSR_FC_TX_DIS = 1<<13, /* Bit 13: Tx Flow-Control Mode Disabled */
1761 GM_GPSR_LINK_UP = 1<<12, /* Bit 12: Link Up Status */
1762 GM_GPSR_PAUSE = 1<<11, /* Bit 11: Pause State */
1763 GM_GPSR_TX_ACTIVE = 1<<10, /* Bit 10: Tx in Progress */
1764 GM_GPSR_EXC_COL = 1<<9, /* Bit 9: Excessive Collisions Occured */
1765 GM_GPSR_LAT_COL = 1<<8, /* Bit 8: Late Collisions Occured */
1767 GM_GPSR_PHY_ST_CH = 1<<5, /* Bit 5: PHY Status Change */
1768 GM_GPSR_GIG_SPEED = 1<<4, /* Bit 4: Gigabit Speed (1 = 1000 Mbps) */
1769 GM_GPSR_PART_MODE = 1<<3, /* Bit 3: Partition mode */
1770 GM_GPSR_FC_RX_DIS = 1<<2, /* Bit 2: Rx Flow-Control Mode Disabled */
1771 GM_GPSR_PROM_EN = 1<<1, /* Bit 1: Promiscuous Mode Enabled */
1774 /* GM_GP_CTRL 16 bit r/w General Purpose Control Register */
1776 GM_GPCR_PROM_ENA = 1<<14, /* Bit 14: Enable Promiscuous Mode */
1777 GM_GPCR_FC_TX_DIS = 1<<13, /* Bit 13: Disable Tx Flow-Control Mode */
1778 GM_GPCR_TX_ENA = 1<<12, /* Bit 12: Enable Transmit */
1779 GM_GPCR_RX_ENA = 1<<11, /* Bit 11: Enable Receive */
1780 GM_GPCR_BURST_ENA = 1<<10, /* Bit 10: Enable Burst Mode */
1781 GM_GPCR_LOOP_ENA = 1<<9, /* Bit 9: Enable MAC Loopback Mode */
1782 GM_GPCR_PART_ENA = 1<<8, /* Bit 8: Enable Partition Mode */
1783 GM_GPCR_GIGS_ENA = 1<<7, /* Bit 7: Gigabit Speed (1000 Mbps) */
1784 GM_GPCR_FL_PASS = 1<<6, /* Bit 6: Force Link Pass */
1785 GM_GPCR_DUP_FULL = 1<<5, /* Bit 5: Full Duplex Mode */
1786 GM_GPCR_FC_RX_DIS = 1<<4, /* Bit 4: Disable Rx Flow-Control Mode */
1787 GM_GPCR_SPEED_100 = 1<<3, /* Bit 3: Port Speed 100 Mbps */
1788 GM_GPCR_AU_DUP_DIS = 1<<2, /* Bit 2: Disable Auto-Update Duplex */
1789 GM_GPCR_AU_FCT_DIS = 1<<1, /* Bit 1: Disable Auto-Update Flow-C. */
1790 GM_GPCR_AU_SPD_DIS = 1<<0, /* Bit 0: Disable Auto-Update Speed */
1793 #define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100)
1794 #define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS|GM_GPCR_AU_SPD_DIS)
1796 /* GM_TX_CTRL 16 bit r/w Transmit Control Register */
1798 GM_TXCR_FORCE_JAM = 1<<15, /* Bit 15: Force Jam / Flow-Control */
1799 GM_TXCR_CRC_DIS = 1<<14, /* Bit 14: Disable insertion of CRC */
1800 GM_TXCR_PAD_DIS = 1<<13, /* Bit 13: Disable padding of packets */
1801 GM_TXCR_COL_THR_MSK = 1<<10, /* Bit 12..10: Collision Threshold */
1804 #define TX_COL_THR(x) (((x)<<10) & GM_TXCR_COL_THR_MSK)
1805 #define TX_COL_DEF 0x04
1807 /* GM_RX_CTRL 16 bit r/w Receive Control Register */
1809 GM_RXCR_UCF_ENA = 1<<15, /* Bit 15: Enable Unicast filtering */
1810 GM_RXCR_MCF_ENA = 1<<14, /* Bit 14: Enable Multicast filtering */
1811 GM_RXCR_CRC_DIS = 1<<13, /* Bit 13: Remove 4-byte CRC */
1812 GM_RXCR_PASS_FC = 1<<12, /* Bit 12: Pass FC packets to FIFO */
1815 /* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */
1817 GM_TXPA_JAMLEN_MSK = 0x03<<14, /* Bit 15..14: Jam Length */
1818 GM_TXPA_JAMIPG_MSK = 0x1f<<9, /* Bit 13..9: Jam IPG */
1819 GM_TXPA_JAMDAT_MSK = 0x1f<<4, /* Bit 8..4: IPG Jam to Data */
1821 TX_JAM_LEN_DEF = 0x03,
1822 TX_JAM_IPG_DEF = 0x0b,
1823 TX_IPG_JAM_DEF = 0x1c,
1826 #define TX_JAM_LEN_VAL(x) (((x)<<14) & GM_TXPA_JAMLEN_MSK)
1827 #define TX_JAM_IPG_VAL(x) (((x)<<9) & GM_TXPA_JAMIPG_MSK)
1828 #define TX_IPG_JAM_DATA(x) (((x)<<4) & GM_TXPA_JAMDAT_MSK)
1831 /* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */
1833 GM_SMOD_DATABL_MSK = 0x1f<<11, /* Bit 15..11: Data Blinder (r/o) */
1834 GM_SMOD_LIMIT_4 = 1<<10, /* Bit 10: 4 consecutive Tx trials */
1835 GM_SMOD_VLAN_ENA = 1<<9, /* Bit 9: Enable VLAN (Max. Frame Len) */
1836 GM_SMOD_JUMBO_ENA = 1<<8, /* Bit 8: Enable Jumbo (Max. Frame Len) */
1837 GM_SMOD_IPG_MSK = 0x1f /* Bit 4..0: Inter-Packet Gap (IPG) */
1840 #define DATA_BLIND_VAL(x) (((x)<<11) & GM_SMOD_DATABL_MSK)
1841 #define DATA_BLIND_DEF 0x04
1843 #define IPG_DATA_VAL(x) (x & GM_SMOD_IPG_MSK)
1844 #define IPG_DATA_DEF 0x1e
1846 /* GM_SMI_CTRL 16 bit r/w SMI Control Register */
1848 GM_SMI_CT_PHY_A_MSK = 0x1f<<11,/* Bit 15..11: PHY Device Address */
1849 GM_SMI_CT_REG_A_MSK = 0x1f<<6,/* Bit 10.. 6: PHY Register Address */
1850 GM_SMI_CT_OP_RD = 1<<5, /* Bit 5: OpCode Read (0=Write)*/
1851 GM_SMI_CT_RD_VAL = 1<<4, /* Bit 4: Read Valid (Read completed) */
1852 GM_SMI_CT_BUSY = 1<<3, /* Bit 3: Busy (Operation in progress) */
1855 #define GM_SMI_CT_PHY_AD(x) (((x)<<11) & GM_SMI_CT_PHY_A_MSK)
1856 #define GM_SMI_CT_REG_AD(x) (((x)<<6) & GM_SMI_CT_REG_A_MSK)
1858 /* GM_PHY_ADDR 16 bit r/w GPHY Address Register */
1860 GM_PAR_MIB_CLR = 1<<5, /* Bit 5: Set MIB Clear Counter Mode */
1861 GM_PAR_MIB_TST = 1<<4, /* Bit 4: MIB Load Counter (Test Mode) */
1864 /* Receive Frame Status Encoding */
1866 GMR_FS_LEN = 0xffff<<16, /* Bit 31..16: Rx Frame Length */
1867 GMR_FS_VLAN = 1<<13, /* Bit 13: VLAN Packet */
1868 GMR_FS_JABBER = 1<<12, /* Bit 12: Jabber Packet */
1869 GMR_FS_UN_SIZE = 1<<11, /* Bit 11: Undersize Packet */
1870 GMR_FS_MC = 1<<10, /* Bit 10: Multicast Packet */
1871 GMR_FS_BC = 1<<9, /* Bit 9: Broadcast Packet */
1872 GMR_FS_RX_OK = 1<<8, /* Bit 8: Receive OK (Good Packet) */
1873 GMR_FS_GOOD_FC = 1<<7, /* Bit 7: Good Flow-Control Packet */
1874 GMR_FS_BAD_FC = 1<<6, /* Bit 6: Bad Flow-Control Packet */
1875 GMR_FS_MII_ERR = 1<<5, /* Bit 5: MII Error */
1876 GMR_FS_LONG_ERR = 1<<4, /* Bit 4: Too Long Packet */
1877 GMR_FS_FRAGMENT = 1<<3, /* Bit 3: Fragment */
1879 GMR_FS_CRC_ERR = 1<<1, /* Bit 1: CRC Error */
1880 GMR_FS_RX_FF_OV = 1<<0, /* Bit 0: Rx FIFO Overflow */
1883 * GMR_FS_ANY_ERR (analogous to XMR_FS_ANY_ERR)
1885 GMR_FS_ANY_ERR = GMR_FS_CRC_ERR | GMR_FS_LONG_ERR |
1886 GMR_FS_MII_ERR | GMR_FS_BAD_FC | GMR_FS_GOOD_FC |
1888 /* Rx GMAC FIFO Flush Mask (default) */
1889 RX_FF_FL_DEF_MSK = GMR_FS_CRC_ERR | GMR_FS_RX_FF_OV |GMR_FS_MII_ERR |
1890 GMR_FS_BAD_FC | GMR_FS_GOOD_FC | GMR_FS_UN_SIZE |
1894 /* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */
1896 GMF_WP_TST_ON = 1<<14, /* Write Pointer Test On */
1897 GMF_WP_TST_OFF = 1<<13, /* Write Pointer Test Off */
1898 GMF_WP_STEP = 1<<12, /* Write Pointer Step/Increment */
1900 GMF_RP_TST_ON = 1<<10, /* Read Pointer Test On */
1901 GMF_RP_TST_OFF = 1<<9, /* Read Pointer Test Off */
1902 GMF_RP_STEP = 1<<8, /* Read Pointer Step/Increment */
1903 GMF_RX_F_FL_ON = 1<<7, /* Rx FIFO Flush Mode On */
1904 GMF_RX_F_FL_OFF = 1<<6, /* Rx FIFO Flush Mode Off */
1905 GMF_CLI_RX_FO = 1<<5, /* Clear IRQ Rx FIFO Overrun */
1906 GMF_CLI_RX_FC = 1<<4, /* Clear IRQ Rx Frame Complete */
1907 GMF_OPER_ON = 1<<3, /* Operational Mode On */
1908 GMF_OPER_OFF = 1<<2, /* Operational Mode Off */
1909 GMF_RST_CLR = 1<<1, /* Clear GMAC FIFO Reset */
1910 GMF_RST_SET = 1<<0, /* Set GMAC FIFO Reset */
1912 RX_GMF_FL_THR_DEF = 0xa, /* flush threshold (default) */
1916 /* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test */
1918 GMF_WSP_TST_ON = 1<<18,/* Write Shadow Pointer Test On */
1919 GMF_WSP_TST_OFF = 1<<17,/* Write Shadow Pointer Test Off */
1920 GMF_WSP_STEP = 1<<16,/* Write Shadow Pointer Step/Increment */
1922 GMF_CLI_TX_FU = 1<<6, /* Clear IRQ Tx FIFO Underrun */
1923 GMF_CLI_TX_FC = 1<<5, /* Clear IRQ Tx Frame Complete */
1924 GMF_CLI_TX_PE = 1<<4, /* Clear IRQ Tx Parity Error */
1927 /* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */
1929 GMT_ST_START = 1<<2, /* Start Time Stamp Timer */
1930 GMT_ST_STOP = 1<<1, /* Stop Time Stamp Timer */
1931 GMT_ST_CLR_IRQ = 1<<0, /* Clear Time Stamp Timer IRQ */
1934 /* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */
1936 GMC_H_BURST_ON = 1<<7, /* Half Duplex Burst Mode On */
1937 GMC_H_BURST_OFF = 1<<6, /* Half Duplex Burst Mode Off */
1938 GMC_F_LOOPB_ON = 1<<5, /* FIFO Loopback On */
1939 GMC_F_LOOPB_OFF = 1<<4, /* FIFO Loopback Off */
1940 GMC_PAUSE_ON = 1<<3, /* Pause On */
1941 GMC_PAUSE_OFF = 1<<2, /* Pause Off */
1942 GMC_RST_CLR = 1<<1, /* Clear GMAC Reset */
1943 GMC_RST_SET = 1<<0, /* Set GMAC Reset */
1946 /* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */
1948 GPC_SEL_BDT = 1<<28, /* Select Bi-Dir. Transfer for MDC/MDIO */
1949 GPC_INT_POL_HI = 1<<27, /* IRQ Polarity is Active HIGH */
1950 GPC_75_OHM = 1<<26, /* Use 75 Ohm Termination instead of 50 */
1951 GPC_DIS_FC = 1<<25, /* Disable Automatic Fiber/Copper Detection */
1952 GPC_DIS_SLEEP = 1<<24, /* Disable Energy Detect */
1953 GPC_HWCFG_M_3 = 1<<23, /* HWCFG_MODE[3] */
1954 GPC_HWCFG_M_2 = 1<<22, /* HWCFG_MODE[2] */
1955 GPC_HWCFG_M_1 = 1<<21, /* HWCFG_MODE[1] */
1956 GPC_HWCFG_M_0 = 1<<20, /* HWCFG_MODE[0] */
1957 GPC_ANEG_0 = 1<<19, /* ANEG[0] */
1958 GPC_ENA_XC = 1<<18, /* Enable MDI crossover */
1959 GPC_DIS_125 = 1<<17, /* Disable 125 MHz clock */
1960 GPC_ANEG_3 = 1<<16, /* ANEG[3] */
1961 GPC_ANEG_2 = 1<<15, /* ANEG[2] */
1962 GPC_ANEG_1 = 1<<14, /* ANEG[1] */
1963 GPC_ENA_PAUSE = 1<<13, /* Enable Pause (SYM_OR_REM) */
1964 GPC_PHYADDR_4 = 1<<12, /* Bit 4 of Phy Addr */
1965 GPC_PHYADDR_3 = 1<<11, /* Bit 3 of Phy Addr */
1966 GPC_PHYADDR_2 = 1<<10, /* Bit 2 of Phy Addr */
1967 GPC_PHYADDR_1 = 1<<9, /* Bit 1 of Phy Addr */
1968 GPC_PHYADDR_0 = 1<<8, /* Bit 0 of Phy Addr */
1969 /* Bits 7..2: reserved */
1970 GPC_RST_CLR = 1<<1, /* Clear GPHY Reset */
1971 GPC_RST_SET = 1<<0, /* Set GPHY Reset */
1974 #define GPC_HWCFG_GMII_COP (GPC_HWCFG_M_3|GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0)
1975 #define GPC_HWCFG_GMII_FIB (GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0)
1976 #define GPC_ANEG_ADV_ALL_M (GPC_ANEG_3 | GPC_ANEG_2 | GPC_ANEG_1 | GPC_ANEG_0)
1978 /* forced speed and duplex mode (don't mix with other ANEG bits) */
1979 #define GPC_FRC10MBIT_HALF 0
1980 #define GPC_FRC10MBIT_FULL GPC_ANEG_0
1981 #define GPC_FRC100MBIT_HALF GPC_ANEG_1
1982 #define GPC_FRC100MBIT_FULL (GPC_ANEG_0 | GPC_ANEG_1)
1984 /* auto-negotiation with limited advertised speeds */
1985 /* mix only with master/slave settings (for copper) */
1986 #define GPC_ADV_1000_HALF GPC_ANEG_2
1987 #define GPC_ADV_1000_FULL GPC_ANEG_3
1988 #define GPC_ADV_ALL (GPC_ANEG_2 | GPC_ANEG_3)
1990 /* master/slave settings */
1991 /* only for copper with 1000 Mbps */
1992 #define GPC_FORCE_MASTER 0
1993 #define GPC_FORCE_SLAVE GPC_ANEG_0
1994 #define GPC_PREF_MASTER GPC_ANEG_1
1995 #define GPC_PREF_SLAVE (GPC_ANEG_1 | GPC_ANEG_0)
1997 /* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */
1998 /* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */
2000 GM_IS_TX_CO_OV = 1<<5, /* Transmit Counter Overflow IRQ */
2001 GM_IS_RX_CO_OV = 1<<4, /* Receive Counter Overflow IRQ */
2002 GM_IS_TX_FF_UR = 1<<3, /* Transmit FIFO Underrun */
2003 GM_IS_TX_COMPL = 1<<2, /* Frame Transmission Complete */
2004 GM_IS_RX_FF_OR = 1<<1, /* Receive FIFO Overrun */
2005 GM_IS_RX_COMPL = 1<<0, /* Frame Reception Complete */
2007 #define GMAC_DEF_MSK (GM_IS_TX_CO_OV | GM_IS_RX_CO_OV | GM_IS_TX_FF_UR)
2009 /* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */
2010 /* Bits 15.. 2: reserved */
2011 GMLC_RST_CLR = 1<<1, /* Clear GMAC Link Reset */
2012 GMLC_RST_SET = 1<<0, /* Set GMAC Link Reset */
2015 /* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */
2016 WOL_CTL_LINK_CHG_OCC = 1<<15,
2017 WOL_CTL_MAGIC_PKT_OCC = 1<<14,
2018 WOL_CTL_PATTERN_OCC = 1<<13,
2019 WOL_CTL_CLEAR_RESULT = 1<<12,
2020 WOL_CTL_ENA_PME_ON_LINK_CHG = 1<<11,
2021 WOL_CTL_DIS_PME_ON_LINK_CHG = 1<<10,
2022 WOL_CTL_ENA_PME_ON_MAGIC_PKT = 1<<9,
2023 WOL_CTL_DIS_PME_ON_MAGIC_PKT = 1<<8,
2024 WOL_CTL_ENA_PME_ON_PATTERN = 1<<7,
2025 WOL_CTL_DIS_PME_ON_PATTERN = 1<<6,
2026 WOL_CTL_ENA_LINK_CHG_UNIT = 1<<5,
2027 WOL_CTL_DIS_LINK_CHG_UNIT = 1<<4,
2028 WOL_CTL_ENA_MAGIC_PKT_UNIT = 1<<3,
2029 WOL_CTL_DIS_MAGIC_PKT_UNIT = 1<<2,
2030 WOL_CTL_ENA_PATTERN_UNIT = 1<<1,
2031 WOL_CTL_DIS_PATTERN_UNIT = 1<<0,
2034 #define WOL_CTL_DEFAULT \
2035 (WOL_CTL_DIS_PME_ON_LINK_CHG | \
2036 WOL_CTL_DIS_PME_ON_PATTERN | \
2037 WOL_CTL_DIS_PME_ON_MAGIC_PKT | \
2038 WOL_CTL_DIS_LINK_CHG_UNIT | \
2039 WOL_CTL_DIS_PATTERN_UNIT | \
2040 WOL_CTL_DIS_MAGIC_PKT_UNIT)
2042 /* WOL_MATCH_CTL 8 bit WOL Match Control Reg */
2043 #define WOL_CTL_PATT_ENA(x) (1 << (x))
2046 /* XMAC II registers */
2048 XM_MMU_CMD = 0x0000, /* 16 bit r/w MMU Command Register */
2049 XM_POFF = 0x0008, /* 32 bit r/w Packet Offset Register */
2050 XM_BURST = 0x000c, /* 32 bit r/w Burst Register for half duplex*/
2051 XM_1L_VLAN_TAG = 0x0010, /* 16 bit r/w One Level VLAN Tag ID */
2052 XM_2L_VLAN_TAG = 0x0014, /* 16 bit r/w Two Level VLAN Tag ID */
2053 XM_TX_CMD = 0x0020, /* 16 bit r/w Transmit Command Register */
2054 XM_TX_RT_LIM = 0x0024, /* 16 bit r/w Transmit Retry Limit Register */
2055 XM_TX_STIME = 0x0028, /* 16 bit r/w Transmit Slottime Register */
2056 XM_TX_IPG = 0x002c, /* 16 bit r/w Transmit Inter Packet Gap */
2057 XM_RX_CMD = 0x0030, /* 16 bit r/w Receive Command Register */
2058 XM_PHY_ADDR = 0x0034, /* 16 bit r/w PHY Address Register */
2059 XM_PHY_DATA = 0x0038, /* 16 bit r/w PHY Data Register */
2060 XM_GP_PORT = 0x0040, /* 32 bit r/w General Purpose Port Register */
2061 XM_IMSK = 0x0044, /* 16 bit r/w Interrupt Mask Register */
2062 XM_ISRC = 0x0048, /* 16 bit r/o Interrupt Status Register */
2063 XM_HW_CFG = 0x004c, /* 16 bit r/w Hardware Config Register */
2064 XM_TX_LO_WM = 0x0060, /* 16 bit r/w Tx FIFO Low Water Mark */
2065 XM_TX_HI_WM = 0x0062, /* 16 bit r/w Tx FIFO High Water Mark */
2066 XM_TX_THR = 0x0064, /* 16 bit r/w Tx Request Threshold */
2067 XM_HT_THR = 0x0066, /* 16 bit r/w Host Request Threshold */
2068 XM_PAUSE_DA = 0x0068, /* NA reg r/w Pause Destination Address */
2069 XM_CTL_PARA = 0x0070, /* 32 bit r/w Control Parameter Register */
2070 XM_MAC_OPCODE = 0x0074, /* 16 bit r/w Opcode for MAC control frames */
2071 XM_MAC_PTIME = 0x0076, /* 16 bit r/w Pause time for MAC ctrl frames*/
2072 XM_TX_STAT = 0x0078, /* 32 bit r/o Tx Status LIFO Register */
2074 XM_EXM_START = 0x0080, /* r/w Start Address of the EXM Regs */
2075 #define XM_EXM(reg) (XM_EXM_START + ((reg) << 3))
2079 XM_SRC_CHK = 0x0100, /* NA reg r/w Source Check Address Register */
2080 XM_SA = 0x0108, /* NA reg r/w Station Address Register */
2081 XM_HSM = 0x0110, /* 64 bit r/w Hash Match Address Registers */
2082 XM_RX_LO_WM = 0x0118, /* 16 bit r/w Receive Low Water Mark */
2083 XM_RX_HI_WM = 0x011a, /* 16 bit r/w Receive High Water Mark */
2084 XM_RX_THR = 0x011c, /* 32 bit r/w Receive Request Threshold */
2085 XM_DEV_ID = 0x0120, /* 32 bit r/o Device ID Register */
2086 XM_MODE = 0x0124, /* 32 bit r/w Mode Register */
2087 XM_LSA = 0x0128, /* NA reg r/o Last Source Register */
2088 XM_TS_READ = 0x0130, /* 32 bit r/o Time Stamp Read Register */
2089 XM_TS_LOAD = 0x0134, /* 32 bit r/o Time Stamp Load Value */
2090 XM_STAT_CMD = 0x0200, /* 16 bit r/w Statistics Command Register */
2091 XM_RX_CNT_EV = 0x0204, /* 32 bit r/o Rx Counter Event Register */
2092 XM_TX_CNT_EV = 0x0208, /* 32 bit r/o Tx Counter Event Register */
2093 XM_RX_EV_MSK = 0x020c, /* 32 bit r/w Rx Counter Event Mask */
2094 XM_TX_EV_MSK = 0x0210, /* 32 bit r/w Tx Counter Event Mask */
2095 XM_TXF_OK = 0x0280, /* 32 bit r/o Frames Transmitted OK Conuter */
2096 XM_TXO_OK_HI = 0x0284, /* 32 bit r/o Octets Transmitted OK High Cnt*/
2097 XM_TXO_OK_LO = 0x0288, /* 32 bit r/o Octets Transmitted OK Low Cnt */
2098 XM_TXF_BC_OK = 0x028c, /* 32 bit r/o Broadcast Frames Xmitted OK */
2099 XM_TXF_MC_OK = 0x0290, /* 32 bit r/o Multicast Frames Xmitted OK */
2100 XM_TXF_UC_OK = 0x0294, /* 32 bit r/o Unicast Frames Xmitted OK */
2101 XM_TXF_LONG = 0x0298, /* 32 bit r/o Tx Long Frame Counter */
2102 XM_TXE_BURST = 0x029c, /* 32 bit r/o Tx Burst Event Counter */
2103 XM_TXF_MPAUSE = 0x02a0, /* 32 bit r/o Tx Pause MAC Ctrl Frame Cnt */
2104 XM_TXF_MCTRL = 0x02a4, /* 32 bit r/o Tx MAC Ctrl Frame Counter */
2105 XM_TXF_SNG_COL = 0x02a8, /* 32 bit r/o Tx Single Collision Counter */
2106 XM_TXF_MUL_COL = 0x02ac, /* 32 bit r/o Tx Multiple Collision Counter */
2107 XM_TXF_ABO_COL = 0x02b0, /* 32 bit r/o Tx aborted due to Exces. Col. */
2108 XM_TXF_LAT_COL = 0x02b4, /* 32 bit r/o Tx Late Collision Counter */
2109 XM_TXF_DEF = 0x02b8, /* 32 bit r/o Tx Deferred Frame Counter */
2110 XM_TXF_EX_DEF = 0x02bc, /* 32 bit r/o Tx Excessive Deferall Counter */
2111 XM_TXE_FIFO_UR = 0x02c0, /* 32 bit r/o Tx FIFO Underrun Event Cnt */
2112 XM_TXE_CS_ERR = 0x02c4, /* 32 bit r/o Tx Carrier Sense Error Cnt */
2113 XM_TXP_UTIL = 0x02c8, /* 32 bit r/o Tx Utilization in % */
2114 XM_TXF_64B = 0x02d0, /* 32 bit r/o 64 Byte Tx Frame Counter */
2115 XM_TXF_127B = 0x02d4, /* 32 bit r/o 65-127 Byte Tx Frame Counter */
2116 XM_TXF_255B = 0x02d8, /* 32 bit r/o 128-255 Byte Tx Frame Counter */
2117 XM_TXF_511B = 0x02dc, /* 32 bit r/o 256-511 Byte Tx Frame Counter */
2118 XM_TXF_1023B = 0x02e0, /* 32 bit r/o 512-1023 Byte Tx Frame Counter*/
2119 XM_TXF_MAX_SZ = 0x02e4, /* 32 bit r/o 1024-MaxSize Byte Tx Frame Cnt*/
2120 XM_RXF_OK = 0x0300, /* 32 bit r/o Frames Received OK */
2121 XM_RXO_OK_HI = 0x0304, /* 32 bit r/o Octets Received OK High Cnt */
2122 XM_RXO_OK_LO = 0x0308, /* 32 bit r/o Octets Received OK Low Counter*/
2123 XM_RXF_BC_OK = 0x030c, /* 32 bit r/o Broadcast Frames Received OK */
2124 XM_RXF_MC_OK = 0x0310, /* 32 bit r/o Multicast Frames Received OK */
2125 XM_RXF_UC_OK = 0x0314, /* 32 bit r/o Unicast Frames Received OK */
2126 XM_RXF_MPAUSE = 0x0318, /* 32 bit r/o Rx Pause MAC Ctrl Frame Cnt */
2127 XM_RXF_MCTRL = 0x031c, /* 32 bit r/o Rx MAC Ctrl Frame Counter */
2128 XM_RXF_INV_MP = 0x0320, /* 32 bit r/o Rx invalid Pause Frame Cnt */
2129 XM_RXF_INV_MOC = 0x0324, /* 32 bit r/o Rx Frames with inv. MAC Opcode*/
2130 XM_RXE_BURST = 0x0328, /* 32 bit r/o Rx Burst Event Counter */
2131 XM_RXE_FMISS = 0x032c, /* 32 bit r/o Rx Missed Frames Event Cnt */
2132 XM_RXF_FRA_ERR = 0x0330, /* 32 bit r/o Rx Framing Error Counter */
2133 XM_RXE_FIFO_OV = 0x0334, /* 32 bit r/o Rx FIFO overflow Event Cnt */
2134 XM_RXF_JAB_PKT = 0x0338, /* 32 bit r/o Rx Jabber Packet Frame Cnt */
2135 XM_RXE_CAR_ERR = 0x033c, /* 32 bit r/o Rx Carrier Event Error Cnt */
2136 XM_RXF_LEN_ERR = 0x0340, /* 32 bit r/o Rx in Range Length Error */
2137 XM_RXE_SYM_ERR = 0x0344, /* 32 bit r/o Rx Symbol Error Counter */
2138 XM_RXE_SHT_ERR = 0x0348, /* 32 bit r/o Rx Short Event Error Cnt */
2139 XM_RXE_RUNT = 0x034c, /* 32 bit r/o Rx Runt Event Counter */
2140 XM_RXF_LNG_ERR = 0x0350, /* 32 bit r/o Rx Frame too Long Error Cnt */
2141 XM_RXF_FCS_ERR = 0x0354, /* 32 bit r/o Rx Frame Check Seq. Error Cnt */
2142 XM_RXF_CEX_ERR = 0x035c, /* 32 bit r/o Rx Carrier Ext Error Frame Cnt*/
2143 XM_RXP_UTIL = 0x0360, /* 32 bit r/o Rx Utilization in % */
2144 XM_RXF_64B = 0x0368, /* 32 bit r/o 64 Byte Rx Frame Counter */
2145 XM_RXF_127B = 0x036c, /* 32 bit r/o 65-127 Byte Rx Frame Counter */
2146 XM_RXF_255B = 0x0370, /* 32 bit r/o 128-255 Byte Rx Frame Counter */
2147 XM_RXF_511B = 0x0374, /* 32 bit r/o 256-511 Byte Rx Frame Counter */
2148 XM_RXF_1023B = 0x0378, /* 32 bit r/o 512-1023 Byte Rx Frame Counter*/
2149 XM_RXF_MAX_SZ = 0x037c, /* 32 bit r/o 1024-MaxSize Byte Rx Frame Cnt*/
2152 /* XM_MMU_CMD 16 bit r/w MMU Command Register */
2154 XM_MMU_PHY_RDY = 1<<12,/* Bit 12: PHY Read Ready */
2155 XM_MMU_PHY_BUSY = 1<<11,/* Bit 11: PHY Busy */
2156 XM_MMU_IGN_PF = 1<<10,/* Bit 10: Ignore Pause Frame */
2157 XM_MMU_MAC_LB = 1<<9, /* Bit 9: Enable MAC Loopback */
2158 XM_MMU_FRC_COL = 1<<7, /* Bit 7: Force Collision */
2159 XM_MMU_SIM_COL = 1<<6, /* Bit 6: Simulate Collision */
2160 XM_MMU_NO_PRE = 1<<5, /* Bit 5: No MDIO Preamble */
2161 XM_MMU_GMII_FD = 1<<4, /* Bit 4: GMII uses Full Duplex */
2162 XM_MMU_RAT_CTRL = 1<<3, /* Bit 3: Enable Rate Control */
2163 XM_MMU_GMII_LOOP= 1<<2, /* Bit 2: PHY is in Loopback Mode */
2164 XM_MMU_ENA_RX = 1<<1, /* Bit 1: Enable Receiver */
2165 XM_MMU_ENA_TX = 1<<0, /* Bit 0: Enable Transmitter */
2169 /* XM_TX_CMD 16 bit r/w Transmit Command Register */
2171 XM_TX_BK2BK = 1<<6, /* Bit 6: Ignor Carrier Sense (Tx Bk2Bk)*/
2172 XM_TX_ENC_BYP = 1<<5, /* Bit 5: Set Encoder in Bypass Mode */
2173 XM_TX_SAM_LINE = 1<<4, /* Bit 4: (sc) Start utilization calculation */
2174 XM_TX_NO_GIG_MD = 1<<3, /* Bit 3: Disable Carrier Extension */
2175 XM_TX_NO_PRE = 1<<2, /* Bit 2: Disable Preamble Generation */
2176 XM_TX_NO_CRC = 1<<1, /* Bit 1: Disable CRC Generation */
2177 XM_TX_AUTO_PAD = 1<<0, /* Bit 0: Enable Automatic Padding */
2180 /* XM_TX_RT_LIM 16 bit r/w Transmit Retry Limit Register */
2181 #define XM_RT_LIM_MSK 0x1f /* Bit 4..0: Tx Retry Limit */
2184 /* XM_TX_STIME 16 bit r/w Transmit Slottime Register */
2185 #define XM_STIME_MSK 0x7f /* Bit 6..0: Tx Slottime bits */
2188 /* XM_TX_IPG 16 bit r/w Transmit Inter Packet Gap */
2189 #define XM_IPG_MSK 0xff /* Bit 7..0: IPG value bits */
2192 /* XM_RX_CMD 16 bit r/w Receive Command Register */
2194 XM_RX_LENERR_OK = 1<<8, /* Bit 8 don't set Rx Err bit for */
2195 /* inrange error packets */
2196 XM_RX_BIG_PK_OK = 1<<7, /* Bit 7 don't set Rx Err bit for */
2198 XM_RX_IPG_CAP = 1<<6, /* Bit 6 repl. type field with IPG */
2199 XM_RX_TP_MD = 1<<5, /* Bit 5: Enable transparent Mode */
2200 XM_RX_STRIP_FCS = 1<<4, /* Bit 4: Enable FCS Stripping */
2201 XM_RX_SELF_RX = 1<<3, /* Bit 3: Enable Rx of own packets */
2202 XM_RX_SAM_LINE = 1<<2, /* Bit 2: (sc) Start utilization calculation */
2203 XM_RX_STRIP_PAD = 1<<1, /* Bit 1: Strip pad bytes of Rx frames */
2204 XM_RX_DIS_CEXT = 1<<0, /* Bit 0: Disable carrier ext. check */
2208 /* XM_GP_PORT 32 bit r/w General Purpose Port Register */
2210 XM_GP_ANIP = 1<<6, /* Bit 6: (ro) Auto-Neg. in progress */
2211 XM_GP_FRC_INT = 1<<5, /* Bit 5: (sc) Force Interrupt */
2212 XM_GP_RES_MAC = 1<<3, /* Bit 3: (sc) Reset MAC and FIFOs */
2213 XM_GP_RES_STAT = 1<<2, /* Bit 2: (sc) Reset the statistics module */
2214 XM_GP_INP_ASS = 1<<0, /* Bit 0: (ro) GP Input Pin asserted */
2218 /* XM_IMSK 16 bit r/w Interrupt Mask Register */
2219 /* XM_ISRC 16 bit r/o Interrupt Status Register */
2221 XM_IS_LNK_AE = 1<<14, /* Bit 14: Link Asynchronous Event */
2222 XM_IS_TX_ABORT = 1<<13, /* Bit 13: Transmit Abort, late Col. etc */
2223 XM_IS_FRC_INT = 1<<12, /* Bit 12: Force INT bit set in GP */
2224 XM_IS_INP_ASS = 1<<11, /* Bit 11: Input Asserted, GP bit 0 set */
2225 XM_IS_LIPA_RC = 1<<10, /* Bit 10: Link Partner requests config */
2226 XM_IS_RX_PAGE = 1<<9, /* Bit 9: Page Received */
2227 XM_IS_TX_PAGE = 1<<8, /* Bit 8: Next Page Loaded for Transmit */
2228 XM_IS_AND = 1<<7, /* Bit 7: Auto-Negotiation Done */
2229 XM_IS_TSC_OV = 1<<6, /* Bit 6: Time Stamp Counter Overflow */
2230 XM_IS_RXC_OV = 1<<5, /* Bit 5: Rx Counter Event Overflow */
2231 XM_IS_TXC_OV = 1<<4, /* Bit 4: Tx Counter Event Overflow */
2232 XM_IS_RXF_OV = 1<<3, /* Bit 3: Receive FIFO Overflow */
2233 XM_IS_TXF_UR = 1<<2, /* Bit 2: Transmit FIFO Underrun */
2234 XM_IS_TX_COMP = 1<<1, /* Bit 1: Frame Tx Complete */
2235 XM_IS_RX_COMP = 1<<0, /* Bit 0: Frame Rx Complete */
2238 #define XM_DEF_MSK (~(XM_IS_INP_ASS | XM_IS_LIPA_RC | XM_IS_RX_PAGE | \
2239 XM_IS_AND | XM_IS_RXC_OV | XM_IS_TXC_OV | \
2240 XM_IS_RXF_OV | XM_IS_TXF_UR))
2243 /* XM_HW_CFG 16 bit r/w Hardware Config Register */
2245 XM_HW_GEN_EOP = 1<<3, /* Bit 3: generate End of Packet pulse */
2246 XM_HW_COM4SIG = 1<<2, /* Bit 2: use Comma Detect for Sig. Det.*/
2247 XM_HW_GMII_MD = 1<<0, /* Bit 0: GMII Interface selected */
2251 /* XM_TX_LO_WM 16 bit r/w Tx FIFO Low Water Mark */
2252 /* XM_TX_HI_WM 16 bit r/w Tx FIFO High Water Mark */
2253 #define XM_TX_WM_MSK 0x01ff /* Bit 9.. 0 Tx FIFO Watermark bits */
2255 /* XM_TX_THR 16 bit r/w Tx Request Threshold */
2256 /* XM_HT_THR 16 bit r/w Host Request Threshold */
2257 /* XM_RX_THR 16 bit r/w Rx Request Threshold */
2258 #define XM_THR_MSK 0x03ff /* Bit 10.. 0 Rx/Tx Request Threshold bits */
2261 /* XM_TX_STAT 32 bit r/o Tx Status LIFO Register */
2263 XM_ST_VALID = (1UL<<31), /* Bit 31: Status Valid */
2264 XM_ST_BYTE_CNT = (0x3fffL<<17), /* Bit 30..17: Tx frame Length */
2265 XM_ST_RETRY_CNT = (0x1fL<<12), /* Bit 16..12: Retry Count */
2266 XM_ST_EX_COL = 1<<11, /* Bit 11: Excessive Collisions */
2267 XM_ST_EX_DEF = 1<<10, /* Bit 10: Excessive Deferral */
2268 XM_ST_BURST = 1<<9, /* Bit 9: p. xmitted in burst md*/
2269 XM_ST_DEFER = 1<<8, /* Bit 8: packet was defered */
2270 XM_ST_BC = 1<<7, /* Bit 7: Broadcast packet */
2271 XM_ST_MC = 1<<6, /* Bit 6: Multicast packet */
2272 XM_ST_UC = 1<<5, /* Bit 5: Unicast packet */
2273 XM_ST_TX_UR = 1<<4, /* Bit 4: FIFO Underrun occured */
2274 XM_ST_CS_ERR = 1<<3, /* Bit 3: Carrier Sense Error */
2275 XM_ST_LAT_COL = 1<<2, /* Bit 2: Late Collision Error */
2276 XM_ST_MUL_COL = 1<<1, /* Bit 1: Multiple Collisions */
2277 XM_ST_SGN_COL = 1<<0, /* Bit 0: Single Collision */
2280 /* XM_RX_LO_WM 16 bit r/w Receive Low Water Mark */
2281 /* XM_RX_HI_WM 16 bit r/w Receive High Water Mark */
2282 #define XM_RX_WM_MSK 0x03ff /* Bit 11.. 0: Rx FIFO Watermark bits */
2285 /* XM_DEV_ID 32 bit r/o Device ID Register */
2286 #define XM_DEV_OUI (0x00ffffffUL<<8) /* Bit 31..8: Device OUI */
2287 #define XM_DEV_REV (0x07L << 5) /* Bit 7..5: Chip Rev Num */
2290 /* XM_MODE 32 bit r/w Mode Register */
2292 XM_MD_ENA_REJ = 1<<26, /* Bit 26: Enable Frame Reject */
2293 XM_MD_SPOE_E = 1<<25, /* Bit 25: Send Pause on Edge */
2294 /* extern generated */
2295 XM_MD_TX_REP = 1<<24, /* Bit 24: Transmit Repeater Mode */
2296 XM_MD_SPOFF_I = 1<<23, /* Bit 23: Send Pause on FIFO full */
2297 /* intern generated */
2298 XM_MD_LE_STW = 1<<22, /* Bit 22: Rx Stat Word in Little Endian */
2299 XM_MD_TX_CONT = 1<<21, /* Bit 21: Send Continuous */
2300 XM_MD_TX_PAUSE = 1<<20, /* Bit 20: (sc) Send Pause Frame */
2301 XM_MD_ATS = 1<<19, /* Bit 19: Append Time Stamp */
2302 XM_MD_SPOL_I = 1<<18, /* Bit 18: Send Pause on Low */
2303 /* intern generated */
2304 XM_MD_SPOH_I = 1<<17, /* Bit 17: Send Pause on High */
2305 /* intern generated */
2306 XM_MD_CAP = 1<<16, /* Bit 16: Check Address Pair */
2307 XM_MD_ENA_HASH = 1<<15, /* Bit 15: Enable Hashing */
2308 XM_MD_CSA = 1<<14, /* Bit 14: Check Station Address */
2309 XM_MD_CAA = 1<<13, /* Bit 13: Check Address Array */
2310 XM_MD_RX_MCTRL = 1<<12, /* Bit 12: Rx MAC Control Frame */
2311 XM_MD_RX_RUNT = 1<<11, /* Bit 11: Rx Runt Frames */
2312 XM_MD_RX_IRLE = 1<<10, /* Bit 10: Rx in Range Len Err Frame */
2313 XM_MD_RX_LONG = 1<<9, /* Bit 9: Rx Long Frame */
2314 XM_MD_RX_CRCE = 1<<8, /* Bit 8: Rx CRC Error Frame */
2315 XM_MD_RX_ERR = 1<<7, /* Bit 7: Rx Error Frame */
2316 XM_MD_DIS_UC = 1<<6, /* Bit 6: Disable Rx Unicast */
2317 XM_MD_DIS_MC = 1<<5, /* Bit 5: Disable Rx Multicast */
2318 XM_MD_DIS_BC = 1<<4, /* Bit 4: Disable Rx Broadcast */
2319 XM_MD_ENA_PROM = 1<<3, /* Bit 3: Enable Promiscuous */
2320 XM_MD_ENA_BE = 1<<2, /* Bit 2: Enable Big Endian */
2321 XM_MD_FTF = 1<<1, /* Bit 1: (sc) Flush Tx FIFO */
2322 XM_MD_FRF = 1<<0, /* Bit 0: (sc) Flush Rx FIFO */
2325 #define XM_PAUSE_MODE (XM_MD_SPOE_E | XM_MD_SPOL_I | XM_MD_SPOH_I)
2326 #define XM_DEF_MODE (XM_MD_RX_RUNT | XM_MD_RX_IRLE | XM_MD_RX_LONG |\
2327 XM_MD_RX_CRCE | XM_MD_RX_ERR | XM_MD_CSA)
2329 /* XM_STAT_CMD 16 bit r/w Statistics Command Register */
2331 XM_SC_SNP_RXC = 1<<5, /* Bit 5: (sc) Snap Rx Counters */
2332 XM_SC_SNP_TXC = 1<<4, /* Bit 4: (sc) Snap Tx Counters */
2333 XM_SC_CP_RXC = 1<<3, /* Bit 3: Copy Rx Counters Continuously */
2334 XM_SC_CP_TXC = 1<<2, /* Bit 2: Copy Tx Counters Continuously */
2335 XM_SC_CLR_RXC = 1<<1, /* Bit 1: (sc) Clear Rx Counters */
2336 XM_SC_CLR_TXC = 1<<0, /* Bit 0: (sc) Clear Tx Counters */
2340 /* XM_RX_CNT_EV 32 bit r/o Rx Counter Event Register */
2341 /* XM_RX_EV_MSK 32 bit r/w Rx Counter Event Mask */
2343 XMR_MAX_SZ_OV = 1<<31, /* Bit 31: 1024-MaxSize Rx Cnt Ov*/
2344 XMR_1023B_OV = 1<<30, /* Bit 30: 512-1023Byte Rx Cnt Ov*/
2345 XMR_511B_OV = 1<<29, /* Bit 29: 256-511 Byte Rx Cnt Ov*/
2346 XMR_255B_OV = 1<<28, /* Bit 28: 128-255 Byte Rx Cnt Ov*/
2347 XMR_127B_OV = 1<<27, /* Bit 27: 65-127 Byte Rx Cnt Ov */
2348 XMR_64B_OV = 1<<26, /* Bit 26: 64 Byte Rx Cnt Ov */
2349 XMR_UTIL_OV = 1<<25, /* Bit 25: Rx Util Cnt Overflow */
2350 XMR_UTIL_UR = 1<<24, /* Bit 24: Rx Util Cnt Underrun */
2351 XMR_CEX_ERR_OV = 1<<23, /* Bit 23: CEXT Err Cnt Ov */
2352 XMR_FCS_ERR_OV = 1<<21, /* Bit 21: Rx FCS Error Cnt Ov */
2353 XMR_LNG_ERR_OV = 1<<20, /* Bit 20: Rx too Long Err Cnt Ov*/
2354 XMR_RUNT_OV = 1<<19, /* Bit 19: Runt Event Cnt Ov */
2355 XMR_SHT_ERR_OV = 1<<18, /* Bit 18: Rx Short Ev Err Cnt Ov*/
2356 XMR_SYM_ERR_OV = 1<<17, /* Bit 17: Rx Sym Err Cnt Ov */
2357 XMR_CAR_ERR_OV = 1<<15, /* Bit 15: Rx Carr Ev Err Cnt Ov */
2358 XMR_JAB_PKT_OV = 1<<14, /* Bit 14: Rx Jabb Packet Cnt Ov */
2359 XMR_FIFO_OV = 1<<13, /* Bit 13: Rx FIFO Ov Ev Cnt Ov */
2360 XMR_FRA_ERR_OV = 1<<12, /* Bit 12: Rx Framing Err Cnt Ov */
2361 XMR_FMISS_OV = 1<<11, /* Bit 11: Rx Missed Ev Cnt Ov */
2362 XMR_BURST = 1<<10, /* Bit 10: Rx Burst Event Cnt Ov */
2363 XMR_INV_MOC = 1<<9, /* Bit 9: Rx with inv. MAC OC Ov*/
2364 XMR_INV_MP = 1<<8, /* Bit 8: Rx inv Pause Frame Ov */
2365 XMR_MCTRL_OV = 1<<7, /* Bit 7: Rx MAC Ctrl-F Cnt Ov */
2366 XMR_MPAUSE_OV = 1<<6, /* Bit 6: Rx Pause MAC Ctrl-F Ov*/
2367 XMR_UC_OK_OV = 1<<5, /* Bit 5: Rx Unicast Frame CntOv*/
2368 XMR_MC_OK_OV = 1<<4, /* Bit 4: Rx Multicast Cnt Ov */
2369 XMR_BC_OK_OV = 1<<3, /* Bit 3: Rx Broadcast Cnt Ov */
2370 XMR_OK_LO_OV = 1<<2, /* Bit 2: Octets Rx OK Low CntOv*/
2371 XMR_OK_HI_OV = 1<<1, /* Bit 1: Octets Rx OK Hi Cnt Ov*/
2372 XMR_OK_OV = 1<<0, /* Bit 0: Frames Received Ok Ov */
2375 #define XMR_DEF_MSK (XMR_OK_LO_OV | XMR_OK_HI_OV)
2377 /* XM_TX_CNT_EV 32 bit r/o Tx Counter Event Register */
2378 /* XM_TX_EV_MSK 32 bit r/w Tx Counter Event Mask */
2380 XMT_MAX_SZ_OV = 1<<25, /* Bit 25: 1024-MaxSize Tx Cnt Ov*/
2381 XMT_1023B_OV = 1<<24, /* Bit 24: 512-1023Byte Tx Cnt Ov*/
2382 XMT_511B_OV = 1<<23, /* Bit 23: 256-511 Byte Tx Cnt Ov*/
2383 XMT_255B_OV = 1<<22, /* Bit 22: 128-255 Byte Tx Cnt Ov*/
2384 XMT_127B_OV = 1<<21, /* Bit 21: 65-127 Byte Tx Cnt Ov */
2385 XMT_64B_OV = 1<<20, /* Bit 20: 64 Byte Tx Cnt Ov */
2386 XMT_UTIL_OV = 1<<19, /* Bit 19: Tx Util Cnt Overflow */
2387 XMT_UTIL_UR = 1<<18, /* Bit 18: Tx Util Cnt Underrun */
2388 XMT_CS_ERR_OV = 1<<17, /* Bit 17: Tx Carr Sen Err Cnt Ov*/
2389 XMT_FIFO_UR_OV = 1<<16, /* Bit 16: Tx FIFO Ur Ev Cnt Ov */
2390 XMT_EX_DEF_OV = 1<<15, /* Bit 15: Tx Ex Deferall Cnt Ov */
2391 XMT_DEF = 1<<14, /* Bit 14: Tx Deferred Cnt Ov */
2392 XMT_LAT_COL_OV = 1<<13, /* Bit 13: Tx Late Col Cnt Ov */
2393 XMT_ABO_COL_OV = 1<<12, /* Bit 12: Tx abo dueto Ex Col Ov*/
2394 XMT_MUL_COL_OV = 1<<11, /* Bit 11: Tx Mult Col Cnt Ov */
2395 XMT_SNG_COL = 1<<10, /* Bit 10: Tx Single Col Cnt Ov */
2396 XMT_MCTRL_OV = 1<<9, /* Bit 9: Tx MAC Ctrl Counter Ov*/
2397 XMT_MPAUSE = 1<<8, /* Bit 8: Tx Pause MAC Ctrl-F Ov*/
2398 XMT_BURST = 1<<7, /* Bit 7: Tx Burst Event Cnt Ov */
2399 XMT_LONG = 1<<6, /* Bit 6: Tx Long Frame Cnt Ov */
2400 XMT_UC_OK_OV = 1<<5, /* Bit 5: Tx Unicast Cnt Ov */
2401 XMT_MC_OK_OV = 1<<4, /* Bit 4: Tx Multicast Cnt Ov */
2402 XMT_BC_OK_OV = 1<<3, /* Bit 3: Tx Broadcast Cnt Ov */
2403 XMT_OK_LO_OV = 1<<2, /* Bit 2: Octets Tx OK Low CntOv*/
2404 XMT_OK_HI_OV = 1<<1, /* Bit 1: Octets Tx OK Hi Cnt Ov*/
2405 XMT_OK_OV = 1<<0, /* Bit 0: Frames Tx Ok Ov */
2408 #define XMT_DEF_MSK (XMT_OK_LO_OV | XMT_OK_HI_OV)
2410 struct skge_rx_desc {
2423 struct skge_tx_desc {
2435 struct skge_element {
2436 struct skge_element *next;
2438 struct sk_buff *skb;
2439 DECLARE_PCI_UNMAP_ADDR(mapaddr);
2440 DECLARE_PCI_UNMAP_LEN(maplen);
2444 struct skge_element *to_clean;
2445 struct skge_element *to_use;
2446 struct skge_element *start;
2447 unsigned long count;
2453 struct pci_dev *pdev;
2455 struct net_device *dev[2];
2467 struct tasklet_struct ext_tasklet;
2468 spinlock_t phy_lock;
2472 static inline int iscopper(const struct skge_hw *hw)
2474 return (hw->pmd_type == 'T');
2478 FLOW_MODE_NONE = 0, /* No Flow-Control */
2479 FLOW_MODE_LOC_SEND = 1, /* Local station sends PAUSE */
2480 FLOW_MODE_REM_SEND = 2, /* Symmetric or just remote */
2481 FLOW_MODE_SYMMETRIC = 3, /* Both stations may send PAUSE */
2487 struct net_device *netdev;
2492 struct skge_ring tx_ring;
2493 struct skge_ring rx_ring;
2495 struct net_device_stats net_stats;
2501 u8 autoneg; /* AUTONEG_ENABLE, AUTONEG_DISABLE */
2502 u8 duplex; /* DUPLEX_HALF, DUPLEX_FULL */
2503 u16 speed; /* SPEED_1000, SPEED_100, ... */
2506 void *mem; /* PCI memory for rings */
2508 unsigned long mem_size;
2509 unsigned int rx_buf_size;
2513 /* Register accessor for memory mapped device */
2514 static inline u32 skge_read32(const struct skge_hw *hw, int reg)
2516 return readl(hw->regs + reg);
2519 static inline u16 skge_read16(const struct skge_hw *hw, int reg)
2521 return readw(hw->regs + reg);
2524 static inline u8 skge_read8(const struct skge_hw *hw, int reg)
2526 return readb(hw->regs + reg);
2529 static inline void skge_write32(const struct skge_hw *hw, int reg, u32 val)
2531 writel(val, hw->regs + reg);
2534 static inline void skge_write16(const struct skge_hw *hw, int reg, u16 val)
2536 writew(val, hw->regs + reg);
2539 static inline void skge_write8(const struct skge_hw *hw, int reg, u8 val)
2541 writeb(val, hw->regs + reg);
2544 /* MAC Related Registers inside the device. */
2545 #define SK_REG(port,reg) (((port)<<7)+(reg))
2546 #define SK_XMAC_REG(port, reg) \
2547 ((BASE_XMAC_1 + (port) * (BASE_XMAC_2 - BASE_XMAC_1)) | (reg) << 1)
2549 static inline u32 xm_read32(const struct skge_hw *hw, int port, int reg)
2552 v = skge_read16(hw, SK_XMAC_REG(port, reg));
2553 v |= (u32)skge_read16(hw, SK_XMAC_REG(port, reg+2)) << 16;
2557 static inline u16 xm_read16(const struct skge_hw *hw, int port, int reg)
2559 return skge_read16(hw, SK_XMAC_REG(port,reg));
2562 static inline void xm_write32(const struct skge_hw *hw, int port, int r, u32 v)
2564 skge_write16(hw, SK_XMAC_REG(port,r), v & 0xffff);
2565 skge_write16(hw, SK_XMAC_REG(port,r+2), v >> 16);
2568 static inline void xm_write16(const struct skge_hw *hw, int port, int r, u16 v)
2570 skge_write16(hw, SK_XMAC_REG(port,r), v);
2573 static inline void xm_outhash(const struct skge_hw *hw, int port, int reg,
2576 xm_write16(hw, port, reg, (u16)hash[0] | ((u16)hash[1] << 8));
2577 xm_write16(hw, port, reg+2, (u16)hash[2] | ((u16)hash[3] << 8));
2578 xm_write16(hw, port, reg+4, (u16)hash[4] | ((u16)hash[5] << 8));
2579 xm_write16(hw, port, reg+6, (u16)hash[6] | ((u16)hash[7] << 8));
2582 static inline void xm_outaddr(const struct skge_hw *hw, int port, int reg,
2585 xm_write16(hw, port, reg, (u16)addr[0] | ((u16)addr[1] << 8));
2586 xm_write16(hw, port, reg+2, (u16)addr[2] | ((u16)addr[3] << 8));
2587 xm_write16(hw, port, reg+4, (u16)addr[4] | ((u16)addr[5] << 8));
2590 #define SK_GMAC_REG(port,reg) \
2591 (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg))
2593 static inline u16 gma_read16(const struct skge_hw *hw, int port, int reg)
2595 return skge_read16(hw, SK_GMAC_REG(port,reg));
2598 static inline u32 gma_read32(const struct skge_hw *hw, int port, int reg)
2600 return (u32) skge_read16(hw, SK_GMAC_REG(port,reg))
2601 | ((u32)skge_read16(hw, SK_GMAC_REG(port,reg+4)) << 16);
2604 static inline void gma_write16(const struct skge_hw *hw, int port, int r, u16 v)
2606 skge_write16(hw, SK_GMAC_REG(port,r), v);
2609 static inline void gma_set_addr(struct skge_hw *hw, int port, int reg,
2612 gma_write16(hw, port, reg, (u16) addr[0] | ((u16) addr[1] << 8));
2613 gma_write16(hw, port, reg+4,(u16) addr[2] | ((u16) addr[3] << 8));
2614 gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8));
projects / linux-2.6 / blob