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   1 /*
   2  * TI OMAP I2C master mode driver
   3  *
   4  * Copyright (C) 2003 MontaVista Software, Inc.
   5  * Copyright (C) 2004 Texas Instruments.
   6  *
   7  * Updated to work with multiple I2C interfaces on 24xx by
   8  * Tony Lindgren <tony@atomide.com> and Imre Deak <imre.deak@nokia.com>
   9  * Copyright (C) 2005 Nokia Corporation
  10  *
  11  * Cleaned up by Juha Yrjölä <juha.yrjola@nokia.com>
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2 of the License, or
  16  * (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  26  */
  27
  28 #include <linux/module.h>
  29 #include <linux/delay.h>
  30 #include <linux/i2c.h>
  31 #include <linux/err.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/completion.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/clk.h>
  36
  37 #include <asm/io.h>
  38
  39 /* timeout waiting for the controller to respond */
  40 #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
  41
  42 #define OMAP_I2C_REV_REG                0x00
  43 #define OMAP_I2C_IE_REG                 0x04
  44 #define OMAP_I2C_STAT_REG               0x08
  45 #define OMAP_I2C_IV_REG                 0x0c
  46 #define OMAP_I2C_SYSS_REG               0x10
  47 #define OMAP_I2C_BUF_REG                0x14
  48 #define OMAP_I2C_CNT_REG                0x18
  49 #define OMAP_I2C_DATA_REG               0x1c
  50 #define OMAP_I2C_SYSC_REG               0x20
  51 #define OMAP_I2C_CON_REG                0x24
  52 #define OMAP_I2C_OA_REG                 0x28
  53 #define OMAP_I2C_SA_REG                 0x2c
  54 #define OMAP_I2C_PSC_REG                0x30
  55 #define OMAP_I2C_SCLL_REG               0x34
  56 #define OMAP_I2C_SCLH_REG               0x38
  57 #define OMAP_I2C_SYSTEST_REG            0x3c
  58
  59 /* I2C Interrupt Enable Register (OMAP_I2C_IE): */
  60 #define OMAP_I2C_IE_XRDY        (1 << 4)        /* TX data ready int enable */
  61 #define OMAP_I2C_IE_RRDY        (1 << 3)        /* RX data ready int enable */
  62 #define OMAP_I2C_IE_ARDY        (1 << 2)        /* Access ready int enable */
  63 #define OMAP_I2C_IE_NACK        (1 << 1)        /* No ack interrupt enable */
  64 #define OMAP_I2C_IE_AL          (1 << 0)        /* Arbitration lost int ena */
  65
  66 /* I2C Status Register (OMAP_I2C_STAT): */
  67 #define OMAP_I2C_STAT_SBD       (1 << 15)       /* Single byte data */
  68 #define OMAP_I2C_STAT_BB        (1 << 12)       /* Bus busy */
  69 #define OMAP_I2C_STAT_ROVR      (1 << 11)       /* Receive overrun */
  70 #define OMAP_I2C_STAT_XUDF      (1 << 10)       /* Transmit underflow */
  71 #define OMAP_I2C_STAT_AAS       (1 << 9)        /* Address as slave */
  72 #define OMAP_I2C_STAT_AD0       (1 << 8)        /* Address zero */
  73 #define OMAP_I2C_STAT_XRDY      (1 << 4)        /* Transmit data ready */
  74 #define OMAP_I2C_STAT_RRDY      (1 << 3)        /* Receive data ready */
  75 #define OMAP_I2C_STAT_ARDY      (1 << 2)        /* Register access ready */
  76 #define OMAP_I2C_STAT_NACK      (1 << 1)        /* No ack interrupt enable */
  77 #define OMAP_I2C_STAT_AL        (1 << 0)        /* Arbitration lost int ena */
  78
  79 /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
  80 #define OMAP_I2C_BUF_RDMA_EN    (1 << 15)       /* RX DMA channel enable */
  81 #define OMAP_I2C_BUF_XDMA_EN    (1 << 7)        /* TX DMA channel enable */
  82
  83 /* I2C Configuration Register (OMAP_I2C_CON): */
  84 #define OMAP_I2C_CON_EN         (1 << 15)       /* I2C module enable */
  85 #define OMAP_I2C_CON_BE         (1 << 14)       /* Big endian mode */
  86 #define OMAP_I2C_CON_STB        (1 << 11)       /* Start byte mode (master) */
  87 #define OMAP_I2C_CON_MST        (1 << 10)       /* Master/slave mode */
  88 #define OMAP_I2C_CON_TRX        (1 << 9)        /* TX/RX mode (master only) */
  89 #define OMAP_I2C_CON_XA         (1 << 8)        /* Expand address */
  90 #define OMAP_I2C_CON_RM         (1 << 2)        /* Repeat mode (master only) */
  91 #define OMAP_I2C_CON_STP        (1 << 1)        /* Stop cond (master only) */
  92 #define OMAP_I2C_CON_STT        (1 << 0)        /* Start condition (master) */
  93
  94 /* I2C System Test Register (OMAP_I2C_SYSTEST): */
  95 #ifdef DEBUG
  96 #define OMAP_I2C_SYSTEST_ST_EN          (1 << 15)       /* System test enable */
  97 #define OMAP_I2C_SYSTEST_FREE           (1 << 14)       /* Free running mode */
  98 #define OMAP_I2C_SYSTEST_TMODE_MASK     (3 << 12)       /* Test mode select */
  99 #define OMAP_I2C_SYSTEST_TMODE_SHIFT    (12)            /* Test mode select */
 100 #define OMAP_I2C_SYSTEST_SCL_I          (1 << 3)        /* SCL line sense in */
 101 #define OMAP_I2C_SYSTEST_SCL_O          (1 << 2)        /* SCL line drive out */
 102 #define OMAP_I2C_SYSTEST_SDA_I          (1 << 1)        /* SDA line sense in */
 103 #define OMAP_I2C_SYSTEST_SDA_O          (1 << 0)        /* SDA line drive out */
 104 #endif
 105
 106 /* I2C System Status register (OMAP_I2C_SYSS): */
 107 #define OMAP_I2C_SYSS_RDONE             (1 << 0)        /* Reset Done */
 108
 109 /* I2C System Configuration Register (OMAP_I2C_SYSC): */
 110 #define OMAP_I2C_SYSC_SRST              (1 << 1)        /* Soft Reset */
 111
 112 /* REVISIT: Use platform_data instead of module parameters */
 113 /* Fast Mode = 400 kHz, Standard = 100 kHz */
 114 static int clock = 100; /* Default: 100 kHz */
 115 module_param(clock, int, 0);
 116 MODULE_PARM_DESC(clock, "Set I2C clock in kHz: 400=fast mode (default == 100)");
 117
 118 struct omap_i2c_dev {
 119         struct device           *dev;
 120         void __iomem            *base;          /* virtual */
 121         int                     irq;
 122         struct clk              *iclk;          /* Interface clock */
 123         struct clk              *fclk;          /* Functional clock */
 124         struct completion       cmd_complete;
 125         struct resource         *ioarea;
 126         u16                     cmd_err;
 127         u8                      *buf;
 128         size_t                  buf_len;
 129         struct i2c_adapter      adapter;
 130         unsigned                rev1:1;
 131 };
 132
 133 static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
 134                                       int reg, u16 val)
 135 {
 136         __raw_writew(val, i2c_dev->base + reg);
 137 }
 138
 139 static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
 140 {
 141         return __raw_readw(i2c_dev->base + reg);
 142 }
 143
 144 static int omap_i2c_get_clocks(struct omap_i2c_dev *dev)
 145 {
 146         if (cpu_is_omap16xx() || cpu_is_omap24xx()) {
 147                 dev->iclk = clk_get(dev->dev, "i2c_ick");
 148                 if (IS_ERR(dev->iclk)) {
 149                         dev->iclk = NULL;
 150                         return -ENODEV;
 151                 }
 152         }
 153
 154         dev->fclk = clk_get(dev->dev, "i2c_fck");
 155         if (IS_ERR(dev->fclk)) {
 156                 if (dev->iclk != NULL) {
 157                         clk_put(dev->iclk);
 158                         dev->iclk = NULL;
 159                 }
 160                 dev->fclk = NULL;
 161                 return -ENODEV;
 162         }
 163
 164         return 0;
 165 }
 166
 167 static void omap_i2c_put_clocks(struct omap_i2c_dev *dev)
 168 {
 169         clk_put(dev->fclk);
 170         dev->fclk = NULL;
 171         if (dev->iclk != NULL) {
 172                 clk_put(dev->iclk);
 173                 dev->iclk = NULL;
 174         }
 175 }
 176
 177 static void omap_i2c_enable_clocks(struct omap_i2c_dev *dev)
 178 {
 179         if (dev->iclk != NULL)
 180                 clk_enable(dev->iclk);
 181         clk_enable(dev->fclk);
 182 }
 183
 184 static void omap_i2c_disable_clocks(struct omap_i2c_dev *dev)
 185 {
 186         if (dev->iclk != NULL)
 187                 clk_disable(dev->iclk);
 188         clk_disable(dev->fclk);
 189 }
 190
 191 static int omap_i2c_init(struct omap_i2c_dev *dev)
 192 {
 193         u16 psc = 0;
 194         unsigned long fclk_rate = 12000000;
 195         unsigned long timeout;
 196
 197         if (!dev->rev1) {
 198                 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, OMAP_I2C_SYSC_SRST);
 199                 /* For some reason we need to set the EN bit before the
 200                  * reset done bit gets set. */
 201                 timeout = jiffies + OMAP_I2C_TIMEOUT;
 202                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
 203                 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
 204                          OMAP_I2C_SYSS_RDONE)) {
 205                         if (time_after(jiffies, timeout)) {
 206                                 dev_warn(dev->dev, "timeout waiting "
 207                                                 "for controller reset\n");
 208                                 return -ETIMEDOUT;
 209                         }
 210                         msleep(1);
 211                 }
 212         }
 213         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 214
 215         if (cpu_class_is_omap1()) {
 216                 struct clk *armxor_ck;
 217
 218                 armxor_ck = clk_get(NULL, "armxor_ck");
 219                 if (IS_ERR(armxor_ck))
 220                         dev_warn(dev->dev, "Could not get armxor_ck\n");
 221                 else {
 222                         fclk_rate = clk_get_rate(armxor_ck);
 223                         clk_put(armxor_ck);
 224                 }
 225                 /* TRM for 5912 says the I2C clock must be prescaled to be
 226                  * between 7 - 12 MHz. The XOR input clock is typically
 227                  * 12, 13 or 19.2 MHz. So we should have code that produces:
 228                  *
 229                  * XOR MHz      Divider         Prescaler
 230                  * 12           1               0
 231                  * 13           2               1
 232                  * 19.2         2               1
 233                  */
 234                 if (fclk_rate > 12000000)
 235                         psc = fclk_rate / 12000000;
 236         }
 237
 238         /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
 239         omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
 240
 241         /* Program desired operating rate */
 242         fclk_rate /= (psc + 1) * 1000;
 243         if (psc > 2)
 244                 psc = 2;
 245
 246         omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG,
 247                            fclk_rate / (clock * 2) - 7 + psc);
 248         omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG,
 249                            fclk_rate / (clock * 2) - 7 + psc);
 250
 251         /* Take the I2C module out of reset: */
 252         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
 253
 254         /* Enable interrupts */
 255         omap_i2c_write_reg(dev, OMAP_I2C_IE_REG,
 256                            (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
 257                             OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
 258                             OMAP_I2C_IE_AL));
 259         return 0;
 260 }
 261
 262 /*
 263  * Waiting on Bus Busy
 264  */
 265 static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
 266 {
 267         unsigned long timeout;
 268
 269         timeout = jiffies + OMAP_I2C_TIMEOUT;
 270         while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
 271                 if (time_after(jiffies, timeout)) {
 272                         dev_warn(dev->dev, "timeout waiting for bus ready\n");
 273                         return -ETIMEDOUT;
 274                 }
 275                 msleep(1);
 276         }
 277
 278         return 0;
 279 }
 280
 281 /*
 282  * Low level master read/write transaction.
 283  */
 284 static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
 285                              struct i2c_msg *msg, int stop)
 286 {
 287         struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
 288         int r;
 289         u16 w;
 290
 291         dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
 292                 msg->addr, msg->len, msg->flags, stop);
 293
 294         if (msg->len == 0)
 295                 return -EINVAL;
 296
 297         omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
 298
 299         /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
 300         dev->buf = msg->buf;
 301         dev->buf_len = msg->len;
 302
 303         omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
 304
 305         init_completion(&dev->cmd_complete);
 306         dev->cmd_err = 0;
 307
 308         w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
 309         if (msg->flags & I2C_M_TEN)
 310                 w |= OMAP_I2C_CON_XA;
 311         if (!(msg->flags & I2C_M_RD))
 312                 w |= OMAP_I2C_CON_TRX;
 313         if (stop)
 314                 w |= OMAP_I2C_CON_STP;
 315         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
 316
 317         r = wait_for_completion_interruptible_timeout(&dev->cmd_complete,
 318                                                       OMAP_I2C_TIMEOUT);
 319         dev->buf_len = 0;
 320         if (r < 0)
 321                 return r;
 322         if (r == 0) {
 323                 dev_err(dev->dev, "controller timed out\n");
 324                 omap_i2c_init(dev);
 325                 return -ETIMEDOUT;
 326         }
 327
 328         if (likely(!dev->cmd_err))
 329                 return 0;
 330
 331         /* We have an error */
 332         if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
 333                             OMAP_I2C_STAT_XUDF)) {
 334                 omap_i2c_init(dev);
 335                 return -EIO;
 336         }
 337
 338         if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
 339                 if (msg->flags & I2C_M_IGNORE_NAK)
 340                         return 0;
 341                 if (stop) {
 342                         w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
 343                         w |= OMAP_I2C_CON_STP;
 344                         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
 345                 }
 346                 return -EREMOTEIO;
 347         }
 348         return -EIO;
 349 }
 350
 351
 352 /*
 353  * Prepare controller for a transaction and call omap_i2c_xfer_msg
 354  * to do the work during IRQ processing.
 355  */
 356 static int
 357 omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 358 {
 359         struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
 360         int i;
 361         int r;
 362
 363         omap_i2c_enable_clocks(dev);
 364
 365         if ((r = omap_i2c_wait_for_bb(dev)) < 0)
 366                 goto out;
 367
 368         for (i = 0; i < num; i++) {
 369                 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
 370                 if (r != 0)
 371                         break;
 372         }
 373
 374         if (r == 0)
 375                 r = num;
 376 out:
 377         omap_i2c_disable_clocks(dev);
 378         return r;
 379 }
 380
 381 static u32
 382 omap_i2c_func(struct i2c_adapter *adap)
 383 {
 384         return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
 385 }
 386
 387 static inline void
 388 omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
 389 {
 390         dev->cmd_err |= err;
 391         complete(&dev->cmd_complete);
 392 }
 393
 394 static inline void
 395 omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
 396 {
 397         omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
 398 }
 399
 400 static irqreturn_t
 401 omap_i2c_rev1_isr(int this_irq, void *dev_id)
 402 {
 403         struct omap_i2c_dev *dev = dev_id;
 404         u16 iv, w;
 405
 406         iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
 407         switch (iv) {
 408         case 0x00:      /* None */
 409                 break;
 410         case 0x01:      /* Arbitration lost */
 411                 dev_err(dev->dev, "Arbitration lost\n");
 412                 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
 413                 break;
 414         case 0x02:      /* No acknowledgement */
 415                 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
 416                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
 417                 break;
 418         case 0x03:      /* Register access ready */
 419                 omap_i2c_complete_cmd(dev, 0);
 420                 break;
 421         case 0x04:      /* Receive data ready */
 422                 if (dev->buf_len) {
 423                         w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
 424                         *dev->buf++ = w;
 425                         dev->buf_len--;
 426                         if (dev->buf_len) {
 427                                 *dev->buf++ = w >> 8;
 428                                 dev->buf_len--;
 429                         }
 430                 } else
 431                         dev_err(dev->dev, "RRDY IRQ while no data requested\n");
 432                 break;
 433         case 0x05:      /* Transmit data ready */
 434                 if (dev->buf_len) {
 435                         w = *dev->buf++;
 436                         dev->buf_len--;
 437                         if (dev->buf_len) {
 438                                 w |= *dev->buf++ << 8;
 439                                 dev->buf_len--;
 440                         }
 441                         omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
 442                 } else
 443                         dev_err(dev->dev, "XRDY IRQ while no data to send\n");
 444                 break;
 445         default:
 446                 return IRQ_NONE;
 447         }
 448
 449         return IRQ_HANDLED;
 450 }
 451
 452 static irqreturn_t
 453 omap_i2c_isr(int this_irq, void *dev_id)
 454 {
 455         struct omap_i2c_dev *dev = dev_id;
 456         u16 bits;
 457         u16 stat, w;
 458         int count = 0;
 459
 460         bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
 461         while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) {
 462                 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
 463                 if (count++ == 100) {
 464                         dev_warn(dev->dev, "Too much work in one IRQ\n");
 465                         break;
 466                 }
 467
 468                 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
 469
 470                 if (stat & OMAP_I2C_STAT_ARDY) {
 471                         omap_i2c_complete_cmd(dev, 0);
 472                         continue;
 473                 }
 474                 if (stat & OMAP_I2C_STAT_RRDY) {
 475                         w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
 476                         if (dev->buf_len) {
 477                                 *dev->buf++ = w;
 478                                 dev->buf_len--;
 479                                 if (dev->buf_len) {
 480                                         *dev->buf++ = w >> 8;
 481                                         dev->buf_len--;
 482                                 }
 483                         } else
 484                                 dev_err(dev->dev, "RRDY IRQ while no data "
 485                                                 "requested\n");
 486                         omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RRDY);
 487                         continue;
 488                 }
 489                 if (stat & OMAP_I2C_STAT_XRDY) {
 490                         w = 0;
 491                         if (dev->buf_len) {
 492                                 w = *dev->buf++;
 493                                 dev->buf_len--;
 494                                 if (dev->buf_len) {
 495                                         w |= *dev->buf++ << 8;
 496                                         dev->buf_len--;
 497                                 }
 498                         } else
 499                                 dev_err(dev->dev, "XRDY IRQ while no "
 500                                         "data to send\n");
 501                         omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
 502                         omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XRDY);
 503                         continue;
 504                 }
 505                 if (stat & OMAP_I2C_STAT_ROVR) {
 506                         dev_err(dev->dev, "Receive overrun\n");
 507                         dev->cmd_err |= OMAP_I2C_STAT_ROVR;
 508                 }
 509                 if (stat & OMAP_I2C_STAT_XUDF) {
 510                         dev_err(dev->dev, "Transmit overflow\n");
 511                         dev->cmd_err |= OMAP_I2C_STAT_XUDF;
 512                 }
 513                 if (stat & OMAP_I2C_STAT_NACK) {
 514                         omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
 515                         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
 516                                            OMAP_I2C_CON_STP);
 517                 }
 518                 if (stat & OMAP_I2C_STAT_AL) {
 519                         dev_err(dev->dev, "Arbitration lost\n");
 520                         omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
 521                 }
 522         }
 523
 524         return count ? IRQ_HANDLED : IRQ_NONE;
 525 }
 526
 527 static const struct i2c_algorithm omap_i2c_algo = {
 528         .master_xfer    = omap_i2c_xfer,
 529         .functionality  = omap_i2c_func,
 530 };
 531
 532 static int
 533 omap_i2c_probe(struct platform_device *pdev)
 534 {
 535         struct omap_i2c_dev     *dev;
 536         struct i2c_adapter      *adap;
 537         struct resource         *mem, *irq, *ioarea;
 538         int r;
 539
 540         /* NOTE: driver uses the static register mapping */
 541         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 542         if (!mem) {
 543                 dev_err(&pdev->dev, "no mem resource?\n");
 544                 return -ENODEV;
 545         }
 546         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 547         if (!irq) {
 548                 dev_err(&pdev->dev, "no irq resource?\n");
 549                 return -ENODEV;
 550         }
 551
 552         ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
 553                         pdev->name);
 554         if (!ioarea) {
 555                 dev_err(&pdev->dev, "I2C region already claimed\n");
 556                 return -EBUSY;
 557         }
 558
 559         if (clock > 200)
 560                 clock = 400;    /* Fast mode */
 561         else
 562                 clock = 100;    /* Standard mode */
 563
 564         dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL);
 565         if (!dev) {
 566                 r = -ENOMEM;
 567                 goto err_release_region;
 568         }
 569
 570         dev->dev = &pdev->dev;
 571         dev->irq = irq->start;
 572         dev->base = (void __iomem *) IO_ADDRESS(mem->start);
 573         platform_set_drvdata(pdev, dev);
 574
 575         if ((r = omap_i2c_get_clocks(dev)) != 0)
 576                 goto err_free_mem;
 577
 578         omap_i2c_enable_clocks(dev);
 579
 580         if (cpu_is_omap15xx())
 581                 dev->rev1 = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) < 0x20;
 582
 583         /* reset ASAP, clearing any IRQs */
 584         omap_i2c_init(dev);
 585
 586         r = request_irq(dev->irq, dev->rev1 ? omap_i2c_rev1_isr : omap_i2c_isr,
 587                         0, pdev->name, dev);
 588
 589         if (r) {
 590                 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
 591                 goto err_unuse_clocks;
 592         }
 593         r = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
 594         dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n",
 595                  pdev->id, r >> 4, r & 0xf, clock);
 596
 597         adap = &dev->adapter;
 598         i2c_set_adapdata(adap, dev);
 599         adap->owner = THIS_MODULE;
 600         adap->class = I2C_CLASS_HWMON;
 601         strncpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
 602         adap->algo = &omap_i2c_algo;
 603         adap->dev.parent = &pdev->dev;
 604
 605         /* i2c device drivers may be active on return from add_adapter() */
 606         adap->nr = pdev->id;
 607         r = i2c_add_numbered_adapter(adap);
 608         if (r) {
 609                 dev_err(dev->dev, "failure adding adapter\n");
 610                 goto err_free_irq;
 611         }
 612
 613         omap_i2c_disable_clocks(dev);
 614
 615         return 0;
 616
 617 err_free_irq:
 618         free_irq(dev->irq, dev);
 619 err_unuse_clocks:
 620         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 621         omap_i2c_disable_clocks(dev);
 622         omap_i2c_put_clocks(dev);
 623 err_free_mem:
 624         platform_set_drvdata(pdev, NULL);
 625         kfree(dev);
 626 err_release_region:
 627         release_mem_region(mem->start, (mem->end - mem->start) + 1);
 628
 629         return r;
 630 }
 631
 632 static int
 633 omap_i2c_remove(struct platform_device *pdev)
 634 {
 635         struct omap_i2c_dev     *dev = platform_get_drvdata(pdev);
 636         struct resource         *mem;
 637
 638         platform_set_drvdata(pdev, NULL);
 639
 640         free_irq(dev->irq, dev);
 641         i2c_del_adapter(&dev->adapter);
 642         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 643         omap_i2c_put_clocks(dev);
 644         kfree(dev);
 645         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 646         release_mem_region(mem->start, (mem->end - mem->start) + 1);
 647         return 0;
 648 }
 649
 650 static struct platform_driver omap_i2c_driver = {
 651         .probe          = omap_i2c_probe,
 652         .remove         = omap_i2c_remove,
 653         .driver         = {
 654                 .name   = "i2c_omap",
 655                 .owner  = THIS_MODULE,
 656         },
 657 };
 658
 659 /* I2C may be needed to bring up other drivers */
 660 static int __init
 661 omap_i2c_init_driver(void)
 662 {
 663         return platform_driver_register(&omap_i2c_driver);
 664 }
 665 subsys_initcall(omap_i2c_init_driver);
 666
 667 static void __exit omap_i2c_exit_driver(void)
 668 {
 669         platform_driver_unregister(&omap_i2c_driver);
 670 }
 671 module_exit(omap_i2c_exit_driver);
 672
 673 MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
 674 MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
 675 MODULE_LICENSE("GPL");