2 * Driver for the Conexant CX23885 PCIe bridge
4 * Copyright (c) 2006 Steven Toth <stoth@hauppauge.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 #include <linux/init.h>
23 #include <linux/list.h>
24 #include <linux/module.h>
25 #include <linux/moduleparam.h>
26 #include <linux/kmod.h>
27 #include <linux/kernel.h>
28 #include <linux/slab.h>
29 #include <linux/interrupt.h>
30 #include <linux/delay.h>
31 #include <asm/div64.h>
35 MODULE_DESCRIPTION("Driver for cx23885 based TV cards");
36 MODULE_AUTHOR("Steven Toth <stoth@hauppauge.com>");
37 MODULE_LICENSE("GPL");
39 static unsigned int debug;
40 module_param(debug,int,0644);
41 MODULE_PARM_DESC(debug,"enable debug messages");
43 static unsigned int card[] = {[0 ... (CX23885_MAXBOARDS - 1)] = UNSET };
44 module_param_array(card, int, NULL, 0444);
45 MODULE_PARM_DESC(card,"card type");
47 #define dprintk(level, fmt, arg...)\
48 do { if (debug >= level)\
49 printk(KERN_DEBUG "%s/0: " fmt, dev->name, ## arg);\
52 static unsigned int cx23885_devcount;
54 static DEFINE_MUTEX(devlist);
55 LIST_HEAD(cx23885_devlist);
57 #define NO_SYNC_LINE (-1U)
61 * 1 line = 16 bytes of CDT
63 * cdt size = 16 * linesize
68 * 0x00000000 0x00008fff FIFO clusters
69 * 0x00010000 0x000104af Channel Management Data Structures
70 * 0x000104b0 0x000104ff Free
71 * 0x00010500 0x000108bf 15 channels * iqsize
72 * 0x000108c0 0x000108ff Free
73 * 0x00010900 0x00010e9f IQ's + Cluster Descriptor Tables
74 * 15 channels * (iqsize + (maxlines * linesize))
75 * 0x00010ea0 0x00010xxx Free
78 static struct sram_channel cx23885_sram_channels[] = {
81 .cmds_start = 0x10000,
82 .ctrl_start = 0x105b0,
86 .ptr1_reg = DMA1_PTR1,
87 .ptr2_reg = DMA1_PTR2,
88 .cnt1_reg = DMA1_CNT1,
89 .cnt2_reg = DMA1_CNT2,
99 .ptr1_reg = DMA2_PTR1,
100 .ptr2_reg = DMA2_PTR2,
101 .cnt1_reg = DMA2_CNT1,
102 .cnt2_reg = DMA2_CNT2,
106 .cmds_start = 0x100A0,
107 .ctrl_start = 0x10630,
109 .fifo_start = 0x5000,
111 .ptr1_reg = DMA3_PTR1,
112 .ptr2_reg = DMA3_PTR2,
113 .cnt1_reg = DMA3_CNT1,
114 .cnt2_reg = DMA3_CNT2,
123 .ptr1_reg = DMA4_PTR1,
124 .ptr2_reg = DMA4_PTR2,
125 .cnt1_reg = DMA4_CNT1,
126 .cnt2_reg = DMA4_CNT2,
135 .ptr1_reg = DMA5_PTR1,
136 .ptr2_reg = DMA5_PTR2,
137 .cnt1_reg = DMA5_CNT1,
138 .cnt2_reg = DMA5_CNT2,
142 .cmds_start = 0x10140,
143 .ctrl_start = 0x10680,
145 .fifo_start = 0x6000,
147 .ptr1_reg = DMA5_PTR1,
148 .ptr2_reg = DMA5_PTR2,
149 .cnt1_reg = DMA5_CNT1,
150 .cnt2_reg = DMA5_CNT2,
159 .ptr1_reg = DMA6_PTR1,
160 .ptr2_reg = DMA6_PTR2,
161 .cnt1_reg = DMA6_CNT1,
162 .cnt2_reg = DMA6_CNT2,
171 .ptr1_reg = DMA7_PTR1,
172 .ptr2_reg = DMA7_PTR2,
173 .cnt1_reg = DMA7_CNT1,
174 .cnt2_reg = DMA7_CNT2,
183 .ptr1_reg = DMA8_PTR1,
184 .ptr2_reg = DMA8_PTR2,
185 .cnt1_reg = DMA8_CNT1,
186 .cnt2_reg = DMA8_CNT2,
190 /* FIXME, these allocations will change when
191 * analog arrives. The be reviewed.
192 * CX23887 Assumptions
193 * 1 line = 16 bytes of CDT
195 * cdt size = 16 * linesize
200 * 0x00000000 0x00008fff FIFO clusters
201 * 0x00010000 0x000104af Channel Management Data Structures
202 * 0x000104b0 0x000104ff Free
203 * 0x00010500 0x000108bf 15 channels * iqsize
204 * 0x000108c0 0x000108ff Free
205 * 0x00010900 0x00010e9f IQ's + Cluster Descriptor Tables
206 * 15 channels * (iqsize + (maxlines * linesize))
207 * 0x00010ea0 0x00010xxx Free
210 static struct sram_channel cx23887_sram_channels[] = {
213 .cmds_start = 0x10000,
214 .ctrl_start = 0x105b0,
218 .ptr1_reg = DMA1_PTR1,
219 .ptr2_reg = DMA1_PTR2,
220 .cnt1_reg = DMA1_CNT1,
221 .cnt2_reg = DMA1_CNT2,
230 .ptr1_reg = DMA2_PTR1,
231 .ptr2_reg = DMA2_PTR2,
232 .cnt1_reg = DMA2_CNT1,
233 .cnt2_reg = DMA2_CNT2,
237 .cmds_start = 0x100A0,
238 .ctrl_start = 0x10780,
240 .fifo_start = 0x5000,
242 .ptr1_reg = DMA3_PTR1,
243 .ptr2_reg = DMA3_PTR2,
244 .cnt1_reg = DMA3_CNT1,
245 .cnt2_reg = DMA3_CNT2,
254 .ptr1_reg = DMA4_PTR1,
255 .ptr2_reg = DMA4_PTR2,
256 .cnt1_reg = DMA4_CNT1,
257 .cnt2_reg = DMA4_CNT2,
266 .ptr1_reg = DMA5_PTR1,
267 .ptr2_reg = DMA5_PTR2,
268 .cnt1_reg = DMA5_CNT1,
269 .cnt2_reg = DMA5_CNT2,
273 .cmds_start = 0x10140,
274 .ctrl_start = 0x10680,
276 .fifo_start = 0x6000,
278 .ptr1_reg = DMA5_PTR1,
279 .ptr2_reg = DMA5_PTR2,
280 .cnt1_reg = DMA5_CNT1,
281 .cnt2_reg = DMA5_CNT2,
290 .ptr1_reg = DMA6_PTR1,
291 .ptr2_reg = DMA6_PTR2,
292 .cnt1_reg = DMA6_CNT1,
293 .cnt2_reg = DMA6_CNT2,
302 .ptr1_reg = DMA7_PTR1,
303 .ptr2_reg = DMA7_PTR2,
304 .cnt1_reg = DMA7_CNT1,
305 .cnt2_reg = DMA7_CNT2,
314 .ptr1_reg = DMA8_PTR1,
315 .ptr2_reg = DMA8_PTR2,
316 .cnt1_reg = DMA8_CNT1,
317 .cnt2_reg = DMA8_CNT2,
321 static int cx23885_risc_decode(u32 risc)
323 static char *instr[16] = {
324 [ RISC_SYNC >> 28 ] = "sync",
325 [ RISC_WRITE >> 28 ] = "write",
326 [ RISC_WRITEC >> 28 ] = "writec",
327 [ RISC_READ >> 28 ] = "read",
328 [ RISC_READC >> 28 ] = "readc",
329 [ RISC_JUMP >> 28 ] = "jump",
330 [ RISC_SKIP >> 28 ] = "skip",
331 [ RISC_WRITERM >> 28 ] = "writerm",
332 [ RISC_WRITECM >> 28 ] = "writecm",
333 [ RISC_WRITECR >> 28 ] = "writecr",
335 static int incr[16] = {
336 [ RISC_WRITE >> 28 ] = 3,
337 [ RISC_JUMP >> 28 ] = 3,
338 [ RISC_SKIP >> 28 ] = 1,
339 [ RISC_SYNC >> 28 ] = 1,
340 [ RISC_WRITERM >> 28 ] = 3,
341 [ RISC_WRITECM >> 28 ] = 3,
342 [ RISC_WRITECR >> 28 ] = 4,
344 static char *bits[] = {
345 "12", "13", "14", "resync",
346 "cnt0", "cnt1", "18", "19",
347 "20", "21", "22", "23",
348 "irq1", "irq2", "eol", "sol",
352 printk("0x%08x [ %s", risc,
353 instr[risc >> 28] ? instr[risc >> 28] : "INVALID");
354 for (i = ARRAY_SIZE(bits) - 1; i >= 0; i--)
355 if (risc & (1 << (i + 12)))
356 printk(" %s", bits[i]);
357 printk(" count=%d ]\n", risc & 0xfff);
358 return incr[risc >> 28] ? incr[risc >> 28] : 1;
361 void cx23885_wakeup(struct cx23885_tsport *port,
362 struct cx23885_dmaqueue *q, u32 count)
364 struct cx23885_dev *dev = port->dev;
365 struct cx23885_buffer *buf;
368 for (bc = 0;; bc++) {
369 if (list_empty(&q->active))
371 buf = list_entry(q->active.next,
372 struct cx23885_buffer, vb.queue);
374 /* count comes from the hw and is is 16bit wide --
375 * this trick handles wrap-arounds correctly for
376 * up to 32767 buffers in flight... */
377 if ((s16) (count - buf->count) < 0)
380 do_gettimeofday(&buf->vb.ts);
381 dprintk(2, "[%p/%d] wakeup reg=%d buf=%d\n", buf, buf->vb.i,
383 buf->vb.state = VIDEOBUF_DONE;
384 list_del(&buf->vb.queue);
385 wake_up(&buf->vb.done);
387 if (list_empty(&q->active)) {
388 del_timer(&q->timeout);
390 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
393 printk("%s: %d buffers handled (should be 1)\n",
397 int cx23885_sram_channel_setup(struct cx23885_dev *dev,
398 struct sram_channel *ch,
399 unsigned int bpl, u32 risc)
401 unsigned int i, lines;
404 if (ch->cmds_start == 0)
406 dprintk(1, "%s() Erasing channel [%s]\n", __FUNCTION__,
408 cx_write(ch->ptr1_reg, 0);
409 cx_write(ch->ptr2_reg, 0);
410 cx_write(ch->cnt2_reg, 0);
411 cx_write(ch->cnt1_reg, 0);
414 dprintk(1, "%s() Configuring channel [%s]\n", __FUNCTION__,
418 bpl = (bpl + 7) & ~7; /* alignment */
420 lines = ch->fifo_size / bpl;
425 cx_write(8 + 0, cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC) );
426 cx_write(8 + 4, cpu_to_le32(8) );
427 cx_write(8 + 8, cpu_to_le32(0) );
430 for (i = 0; i < lines; i++) {
431 dprintk(2, "%s() 0x%08x <- 0x%08x\n", __FUNCTION__, cdt + 16*i,
432 ch->fifo_start + bpl*i);
433 cx_write(cdt + 16*i, ch->fifo_start + bpl*i);
434 cx_write(cdt + 16*i + 4, 0);
435 cx_write(cdt + 16*i + 8, 0);
436 cx_write(cdt + 16*i + 12, 0);
441 cx_write(ch->cmds_start + 0, 8);
443 cx_write(ch->cmds_start + 0, risc);
444 cx_write(ch->cmds_start + 4, 0); /* 64 bits 63-32 */
445 cx_write(ch->cmds_start + 8, cdt);
446 cx_write(ch->cmds_start + 12, (lines*16) >> 3);
447 cx_write(ch->cmds_start + 16, ch->ctrl_start);
449 cx_write(ch->cmds_start + 20, 0x80000000 | (64 >> 2) );
451 cx_write(ch->cmds_start + 20, 64 >> 2);
452 for (i = 24; i < 80; i += 4)
453 cx_write(ch->cmds_start + i, 0);
456 cx_write(ch->ptr1_reg, ch->fifo_start);
457 cx_write(ch->ptr2_reg, cdt);
458 cx_write(ch->cnt2_reg, (lines*16) >> 3);
459 cx_write(ch->cnt1_reg, (bpl >> 3) -1);
461 dprintk(2,"[bridge %d] sram setup %s: bpl=%d lines=%d\n",
470 void cx23885_sram_channel_dump(struct cx23885_dev *dev,
471 struct sram_channel *ch)
473 static char *name[] = {
490 unsigned int i, j, n;
492 printk("%s: %s - dma channel status dump\n",
493 dev->name, ch->name);
494 for (i = 0; i < ARRAY_SIZE(name); i++)
495 printk("%s: cmds: %-15s: 0x%08x\n",
497 cx_read(ch->cmds_start + 4*i));
499 for (i = 0; i < 4; i++) {
500 risc = cx_read(ch->cmds_start + 4 * (i + 14));
501 printk("%s: risc%d: ", dev->name, i);
502 cx23885_risc_decode(risc);
504 for (i = 0; i < (64 >> 2); i += n) {
505 risc = cx_read(ch->ctrl_start + 4 * i);
506 /* No consideration for bits 63-32 */
508 printk("%s: (0x%08x) iq %x: ", dev->name,
509 ch->ctrl_start + 4 * i, i);
510 n = cx23885_risc_decode(risc);
511 for (j = 1; j < n; j++) {
512 risc = cx_read(ch->ctrl_start + 4 * (i + j));
513 printk("%s: iq %x: 0x%08x [ arg #%d ]\n",
514 dev->name, i+j, risc, j);
518 printk("%s: fifo: 0x%08x -> 0x%x\n",
519 dev->name, ch->fifo_start, ch->fifo_start+ch->fifo_size);
520 printk("%s: ctrl: 0x%08x -> 0x%x\n",
521 dev->name, ch->ctrl_start, ch->ctrl_start + 6*16);
522 printk("%s: ptr1_reg: 0x%08x\n",
523 dev->name, cx_read(ch->ptr1_reg));
524 printk("%s: ptr2_reg: 0x%08x\n",
525 dev->name, cx_read(ch->ptr2_reg));
526 printk("%s: cnt1_reg: 0x%08x\n",
527 dev->name, cx_read(ch->cnt1_reg));
528 printk("%s: cnt2_reg: 0x%08x\n",
529 dev->name, cx_read(ch->cnt2_reg));
532 static void cx23885_risc_disasm(struct cx23885_tsport *port,
533 struct btcx_riscmem *risc)
535 struct cx23885_dev *dev = port->dev;
536 unsigned int i, j, n;
538 printk("%s: risc disasm: %p [dma=0x%08lx]\n",
539 dev->name, risc->cpu, (unsigned long)risc->dma);
540 for (i = 0; i < (risc->size >> 2); i += n) {
541 printk("%s: %04d: ", dev->name, i);
542 n = cx23885_risc_decode(risc->cpu[i]);
543 for (j = 1; j < n; j++)
544 printk("%s: %04d: 0x%08x [ arg #%d ]\n",
545 dev->name, i + j, risc->cpu[i + j], j);
546 if (risc->cpu[i] == RISC_JUMP)
551 static void cx23885_shutdown(struct cx23885_dev *dev)
553 /* disable RISC controller */
554 cx_write(DEV_CNTRL2, 0);
556 /* Disable all IR activity */
557 cx_write(IR_CNTRL_REG, 0);
559 /* Disable Video A/B activity */
560 cx_write(VID_A_DMA_CTL, 0);
561 cx_write(VID_B_DMA_CTL, 0);
562 cx_write(VID_C_DMA_CTL, 0);
564 /* Disable Audio activity */
565 cx_write(AUD_INT_DMA_CTL, 0);
566 cx_write(AUD_EXT_DMA_CTL, 0);
568 /* Disable Serial port */
569 cx_write(UART_CTL, 0);
571 /* Disable Interrupts */
572 cx_write(PCI_INT_MSK, 0);
573 cx_write(VID_A_INT_MSK, 0);
574 cx_write(VID_B_INT_MSK, 0);
575 cx_write(VID_C_INT_MSK, 0);
576 cx_write(AUDIO_INT_INT_MSK, 0);
577 cx_write(AUDIO_EXT_INT_MSK, 0);
581 static void cx23885_reset(struct cx23885_dev *dev)
583 dprintk(1, "%s()\n", __FUNCTION__);
585 cx23885_shutdown(dev);
587 cx_write(PCI_INT_STAT, 0xffffffff);
588 cx_write(VID_A_INT_STAT, 0xffffffff);
589 cx_write(VID_B_INT_STAT, 0xffffffff);
590 cx_write(VID_C_INT_STAT, 0xffffffff);
591 cx_write(AUDIO_INT_INT_STAT, 0xffffffff);
592 cx_write(AUDIO_EXT_INT_STAT, 0xffffffff);
593 cx_write(CLK_DELAY, cx_read(CLK_DELAY) & 0x80000000);
597 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH01],
599 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH02], 128, 0);
600 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH03],
602 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH04], 128, 0);
603 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH05], 128, 0);
604 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH06],
606 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH07], 128, 0);
607 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH08], 128, 0);
608 cx23885_sram_channel_setup(dev, &dev->sram_channels[SRAM_CH09], 128, 0);
610 cx23885_gpio_setup(dev);
614 static int cx23885_pci_quirks(struct cx23885_dev *dev)
616 dprintk(1, "%s()\n", __FUNCTION__);
618 /* The cx23885 bridge has a weird bug which causes NMI to be asserted
619 * when DMA begins if RDR_TLCTL0 bit4 is not cleared. It does not
620 * occur on the cx23887 bridge.
622 if(dev->bridge == CX23885_BRIDGE_885)
623 cx_clear(RDR_TLCTL0, 1 << 4);
628 static int get_resources(struct cx23885_dev *dev)
630 if (request_mem_region(pci_resource_start(dev->pci,0),
631 pci_resource_len(dev->pci,0),
635 printk(KERN_ERR "%s: can't get MMIO memory @ 0x%llx\n",
636 dev->name, (unsigned long long)pci_resource_start(dev->pci,0));
641 static void cx23885_timeout(unsigned long data);
642 int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
643 u32 reg, u32 mask, u32 value);
645 static int cx23885_init_tsport(struct cx23885_dev *dev, struct cx23885_tsport *port, int portno)
647 dprintk(1, "%s(portno=%d)\n", __FUNCTION__, portno);
649 /* Transport bus init dma queue - Common settings */
650 port->dma_ctl_val = 0x11; /* Enable RISC controller and Fifo */
651 port->ts_int_msk_val = 0x1111; /* TS port bits for RISC */
653 spin_lock_init(&port->slock);
657 INIT_LIST_HEAD(&port->mpegq.active);
658 INIT_LIST_HEAD(&port->mpegq.queued);
659 port->mpegq.timeout.function = cx23885_timeout;
660 port->mpegq.timeout.data = (unsigned long)port;
661 init_timer(&port->mpegq.timeout);
665 port->reg_gpcnt = VID_B_GPCNT;
666 port->reg_gpcnt_ctl = VID_B_GPCNT_CTL;
667 port->reg_dma_ctl = VID_B_DMA_CTL;
668 port->reg_lngth = VID_B_LNGTH;
669 port->reg_hw_sop_ctrl = VID_B_HW_SOP_CTL;
670 port->reg_gen_ctrl = VID_B_GEN_CTL;
671 port->reg_bd_pkt_status = VID_B_BD_PKT_STATUS;
672 port->reg_sop_status = VID_B_SOP_STATUS;
673 port->reg_fifo_ovfl_stat = VID_B_FIFO_OVFL_STAT;
674 port->reg_vld_misc = VID_B_VLD_MISC;
675 port->reg_ts_clk_en = VID_B_TS_CLK_EN;
676 port->reg_src_sel = VID_B_SRC_SEL;
677 port->reg_ts_int_msk = VID_B_INT_MSK;
678 port->reg_ts_int_stat = VID_B_INT_STAT;
679 port->sram_chno = SRAM_CH03; /* VID_B */
680 port->pci_irqmask = 0x02; /* VID_B bit1 */
683 port->reg_gpcnt = VID_C_GPCNT;
684 port->reg_gpcnt_ctl = VID_C_GPCNT_CTL;
685 port->reg_dma_ctl = VID_C_DMA_CTL;
686 port->reg_lngth = VID_C_LNGTH;
687 port->reg_hw_sop_ctrl = VID_C_HW_SOP_CTL;
688 port->reg_gen_ctrl = VID_C_GEN_CTL;
689 port->reg_bd_pkt_status = VID_C_BD_PKT_STATUS;
690 port->reg_sop_status = VID_C_SOP_STATUS;
691 port->reg_fifo_ovfl_stat = VID_C_FIFO_OVFL_STAT;
692 port->reg_vld_misc = VID_C_VLD_MISC;
693 port->reg_ts_clk_en = VID_C_TS_CLK_EN;
694 port->reg_src_sel = 0;
695 port->reg_ts_int_msk = VID_C_INT_MSK;
696 port->reg_ts_int_stat = VID_C_INT_STAT;
697 port->sram_chno = SRAM_CH06; /* VID_C */
698 port->pci_irqmask = 0x04; /* VID_C bit2 */
704 cx23885_risc_stopper(dev->pci, &port->mpegq.stopper,
705 port->reg_dma_ctl, port->dma_ctl_val, 0x00);
710 static void cx23885_dev_checkrevision(struct cx23885_dev *dev)
712 switch (cx_read(RDR_CFG2) & 0xff) {
715 dev->hwrevision = 0xa0;
719 dev->hwrevision = 0xa1;
723 dev->hwrevision = 0xb0;
727 dev->hwrevision = 0xc0;
731 dev->hwrevision = 0xc0;
734 dev->hwrevision = 0xb1;
737 printk(KERN_ERR "%s() New hardware revision found 0x%x\n",
738 __FUNCTION__, dev->hwrevision);
741 printk(KERN_INFO "%s() Hardware revision = 0x%02x\n",
742 __FUNCTION__, dev->hwrevision);
744 printk(KERN_ERR "%s() Hardware revision unknown 0x%x\n",
745 __FUNCTION__, dev->hwrevision);
748 static int cx23885_dev_setup(struct cx23885_dev *dev)
752 mutex_init(&dev->lock);
754 atomic_inc(&dev->refcount);
756 dev->nr = cx23885_devcount++;
757 sprintf(dev->name, "cx23885[%d]", dev->nr);
759 mutex_lock(&devlist);
760 list_add_tail(&dev->devlist, &cx23885_devlist);
761 mutex_unlock(&devlist);
763 /* Configure the internal memory */
764 if(dev->pci->device == 0x8880) {
765 dev->bridge = CX23885_BRIDGE_887;
766 dev->sram_channels = cx23887_sram_channels;
767 /* Apply a sensible clock frequency for the PCIe bridge */
768 dev->clk_freq = 25000000;
770 if(dev->pci->device == 0x8852) {
771 dev->bridge = CX23885_BRIDGE_885;
772 dev->sram_channels = cx23885_sram_channels;
773 /* Apply a sensible clock frequency for the PCIe bridge */
774 dev->clk_freq = 28000000;
778 dprintk(1, "%s() Memory configured for PCIe bridge type %d\n",
779 __FUNCTION__, dev->bridge);
783 if (card[dev->nr] < cx23885_bcount)
784 dev->board = card[dev->nr];
785 for (i = 0; UNSET == dev->board && i < cx23885_idcount; i++)
786 if (dev->pci->subsystem_vendor == cx23885_subids[i].subvendor &&
787 dev->pci->subsystem_device == cx23885_subids[i].subdevice)
788 dev->board = cx23885_subids[i].card;
789 if (UNSET == dev->board) {
790 dev->board = CX23885_BOARD_UNKNOWN;
791 cx23885_card_list(dev);
794 /* If the user specific a clk freq override, apply it */
795 if (cx23885_boards[dev->board].clk_freq > 0)
796 dev->clk_freq = cx23885_boards[dev->board].clk_freq;
798 dev->pci_bus = dev->pci->bus->number;
799 dev->pci_slot = PCI_SLOT(dev->pci->devfn);
800 dev->pci_irqmask = 0x001f00;
802 /* External Master 1 Bus */
803 dev->i2c_bus[0].nr = 0;
804 dev->i2c_bus[0].dev = dev;
805 dev->i2c_bus[0].reg_stat = I2C1_STAT;
806 dev->i2c_bus[0].reg_ctrl = I2C1_CTRL;
807 dev->i2c_bus[0].reg_addr = I2C1_ADDR;
808 dev->i2c_bus[0].reg_rdata = I2C1_RDATA;
809 dev->i2c_bus[0].reg_wdata = I2C1_WDATA;
810 dev->i2c_bus[0].i2c_period = (0x9d << 24); /* 100kHz */
812 /* External Master 2 Bus */
813 dev->i2c_bus[1].nr = 1;
814 dev->i2c_bus[1].dev = dev;
815 dev->i2c_bus[1].reg_stat = I2C2_STAT;
816 dev->i2c_bus[1].reg_ctrl = I2C2_CTRL;
817 dev->i2c_bus[1].reg_addr = I2C2_ADDR;
818 dev->i2c_bus[1].reg_rdata = I2C2_RDATA;
819 dev->i2c_bus[1].reg_wdata = I2C2_WDATA;
820 dev->i2c_bus[1].i2c_period = (0x9d << 24); /* 100kHz */
822 /* Internal Master 3 Bus */
823 dev->i2c_bus[2].nr = 2;
824 dev->i2c_bus[2].dev = dev;
825 dev->i2c_bus[2].reg_stat = I2C3_STAT;
826 dev->i2c_bus[2].reg_ctrl = I2C3_CTRL;
827 dev->i2c_bus[2].reg_addr = I2C3_ADDR;
828 dev->i2c_bus[2].reg_rdata = I2C3_RDATA;
829 dev->i2c_bus[2].reg_wdata = I2C3_WDATA;
830 dev->i2c_bus[2].i2c_period = (0x07 << 24); /* 1.95MHz */
832 if(cx23885_boards[dev->board].portb == CX23885_MPEG_DVB)
833 cx23885_init_tsport(dev, &dev->ts1, 1);
835 if(cx23885_boards[dev->board].portc == CX23885_MPEG_DVB)
836 cx23885_init_tsport(dev, &dev->ts2, 2);
838 if (get_resources(dev) < 0) {
839 printk(KERN_ERR "CORE %s No more PCIe resources for "
840 "subsystem: %04x:%04x\n",
841 dev->name, dev->pci->subsystem_vendor,
842 dev->pci->subsystem_device);
849 dev->lmmio = ioremap(pci_resource_start(dev->pci,0),
850 pci_resource_len(dev->pci,0));
852 dev->bmmio = (u8 __iomem *)dev->lmmio;
854 printk(KERN_INFO "CORE %s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n",
855 dev->name, dev->pci->subsystem_vendor,
856 dev->pci->subsystem_device, cx23885_boards[dev->board].name,
857 dev->board, card[dev->nr] == dev->board ?
858 "insmod option" : "autodetected");
860 cx23885_pci_quirks(dev);
862 /* Assume some sensible defaults */
863 dev->tuner_type = cx23885_boards[dev->board].tuner_type;
864 dev->tuner_addr = cx23885_boards[dev->board].tuner_addr;
865 dev->radio_type = cx23885_boards[dev->board].radio_type;
866 dev->radio_addr = cx23885_boards[dev->board].radio_addr;
868 dprintk(1, "%s() tuner_type = 0x%x tuner_addr = 0x%x\n",
869 __FUNCTION__, dev->tuner_type, dev->tuner_addr);
870 dprintk(1, "%s() radio_type = 0x%x radio_addr = 0x%x\n",
871 __FUNCTION__, dev->radio_type, dev->radio_addr);
876 cx23885_i2c_register(&dev->i2c_bus[0]);
877 cx23885_i2c_register(&dev->i2c_bus[1]);
878 cx23885_i2c_register(&dev->i2c_bus[2]);
879 cx23885_call_i2c_clients (&dev->i2c_bus[0], TUNER_SET_STANDBY, NULL);
880 cx23885_card_setup(dev);
881 cx23885_ir_init(dev);
883 if (cx23885_boards[dev->board].porta == CX23885_ANALOG_VIDEO) {
884 if (cx23885_video_register(dev) < 0) {
885 printk(KERN_ERR "%s() Failed to register analog "
886 "video adapters on VID_A\n", __FUNCTION__);
890 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) {
891 if (cx23885_dvb_register(&dev->ts1) < 0) {
892 printk(KERN_ERR "%s() Failed to register dvb adapters on VID_B\n",
897 if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) {
898 if (cx23885_dvb_register(&dev->ts2) < 0) {
899 printk(KERN_ERR "%s() Failed to register dvb adapters on VID_C\n",
904 cx23885_dev_checkrevision(dev);
909 static void cx23885_dev_unregister(struct cx23885_dev *dev)
911 release_mem_region(pci_resource_start(dev->pci,0),
912 pci_resource_len(dev->pci,0));
914 if (!atomic_dec_and_test(&dev->refcount))
917 if (cx23885_boards[dev->board].porta == CX23885_ANALOG_VIDEO)
918 cx23885_video_unregister(dev);
920 if(cx23885_boards[dev->board].portb == CX23885_MPEG_DVB)
921 cx23885_dvb_unregister(&dev->ts1);
923 if(cx23885_boards[dev->board].portc == CX23885_MPEG_DVB)
924 cx23885_dvb_unregister(&dev->ts2);
926 cx23885_i2c_unregister(&dev->i2c_bus[2]);
927 cx23885_i2c_unregister(&dev->i2c_bus[1]);
928 cx23885_i2c_unregister(&dev->i2c_bus[0]);
933 static u32* cx23885_risc_field(u32 *rp, struct scatterlist *sglist,
934 unsigned int offset, u32 sync_line,
935 unsigned int bpl, unsigned int padding,
938 struct scatterlist *sg;
939 unsigned int line, todo;
941 /* sync instruction */
942 if (sync_line != NO_SYNC_LINE)
943 *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
947 for (line = 0; line < lines; line++) {
948 while (offset && offset >= sg_dma_len(sg)) {
949 offset -= sg_dma_len(sg);
952 if (bpl <= sg_dma_len(sg)-offset) {
953 /* fits into current chunk */
954 *(rp++)=cpu_to_le32(RISC_WRITE|RISC_SOL|RISC_EOL|bpl);
955 *(rp++)=cpu_to_le32(sg_dma_address(sg)+offset);
956 *(rp++)=cpu_to_le32(0); /* bits 63-32 */
959 /* scanline needs to be split */
961 *(rp++)=cpu_to_le32(RISC_WRITE|RISC_SOL|
962 (sg_dma_len(sg)-offset));
963 *(rp++)=cpu_to_le32(sg_dma_address(sg)+offset);
964 *(rp++)=cpu_to_le32(0); /* bits 63-32 */
965 todo -= (sg_dma_len(sg)-offset);
968 while (todo > sg_dma_len(sg)) {
969 *(rp++)=cpu_to_le32(RISC_WRITE|
971 *(rp++)=cpu_to_le32(sg_dma_address(sg));
972 *(rp++)=cpu_to_le32(0); /* bits 63-32 */
973 todo -= sg_dma_len(sg);
976 *(rp++)=cpu_to_le32(RISC_WRITE|RISC_EOL|todo);
977 *(rp++)=cpu_to_le32(sg_dma_address(sg));
978 *(rp++)=cpu_to_le32(0); /* bits 63-32 */
987 int cx23885_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc,
988 struct scatterlist *sglist, unsigned int top_offset,
989 unsigned int bottom_offset, unsigned int bpl,
990 unsigned int padding, unsigned int lines)
992 u32 instructions, fields;
997 if (UNSET != top_offset)
999 if (UNSET != bottom_offset)
1002 /* estimate risc mem: worst case is one write per page border +
1003 one write per scan line + syncs + jump (all 2 dwords). Padding
1004 can cause next bpl to start close to a page border. First DMA
1005 region may be smaller than PAGE_SIZE */
1006 /* write and jump need and extra dword */
1007 instructions = fields * (1 + ((bpl + padding) * lines) / PAGE_SIZE + lines);
1009 if ((rc = btcx_riscmem_alloc(pci,risc,instructions*12)) < 0)
1012 /* write risc instructions */
1014 if (UNSET != top_offset)
1015 rp = cx23885_risc_field(rp, sglist, top_offset, 0,
1016 bpl, padding, lines);
1017 if (UNSET != bottom_offset)
1018 rp = cx23885_risc_field(rp, sglist, bottom_offset, 0x200,
1019 bpl, padding, lines);
1021 /* save pointer to jmp instruction address */
1023 BUG_ON((risc->jmp - risc->cpu + 2) * sizeof (*risc->cpu) > risc->size);
1027 static int cx23885_risc_databuffer(struct pci_dev *pci,
1028 struct btcx_riscmem *risc,
1029 struct scatterlist *sglist,
1037 /* estimate risc mem: worst case is one write per page border +
1038 one write per scan line + syncs + jump (all 2 dwords). Here
1039 there is no padding and no sync. First DMA region may be smaller
1041 /* Jump and write need an extra dword */
1042 instructions = 1 + (bpl * lines) / PAGE_SIZE + lines;
1045 if ((rc = btcx_riscmem_alloc(pci,risc,instructions*12)) < 0)
1048 /* write risc instructions */
1050 rp = cx23885_risc_field(rp, sglist, 0, NO_SYNC_LINE, bpl, 0, lines);
1052 /* save pointer to jmp instruction address */
1054 BUG_ON((risc->jmp - risc->cpu + 2) * sizeof (*risc->cpu) > risc->size);
1058 int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
1059 u32 reg, u32 mask, u32 value)
1064 if ((rc = btcx_riscmem_alloc(pci, risc, 4*16)) < 0)
1067 /* write risc instructions */
1069 *(rp++) = cpu_to_le32(RISC_WRITECR | RISC_IRQ2);
1070 *(rp++) = cpu_to_le32(reg);
1071 *(rp++) = cpu_to_le32(value);
1072 *(rp++) = cpu_to_le32(mask);
1073 *(rp++) = cpu_to_le32(RISC_JUMP);
1074 *(rp++) = cpu_to_le32(risc->dma);
1075 *(rp++) = cpu_to_le32(0); /* bits 63-32 */
1079 void cx23885_free_buffer(struct videobuf_queue *q, struct cx23885_buffer *buf)
1081 struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
1083 BUG_ON(in_interrupt());
1084 videobuf_waiton(&buf->vb, 0, 0);
1085 videobuf_dma_unmap(q, dma);
1086 videobuf_dma_free(dma);
1087 btcx_riscmem_free((struct pci_dev *)q->dev, &buf->risc);
1088 buf->vb.state = VIDEOBUF_NEEDS_INIT;
1091 static void cx23885_tsport_reg_dump(struct cx23885_tsport *port)
1093 struct cx23885_dev *dev = port->dev;
1095 dprintk(1, "%s() Register Dump\n", __FUNCTION__);
1096 dprintk(1, "%s() DEV_CNTRL2 0x%08X\n", __FUNCTION__,
1097 cx_read(DEV_CNTRL2));
1098 dprintk(1, "%s() PCI_INT_MSK 0x%08X\n", __FUNCTION__,
1099 cx_read(PCI_INT_MSK));
1100 dprintk(1, "%s() AUD_INT_INT_MSK 0x%08X\n", __FUNCTION__,
1101 cx_read(AUDIO_INT_INT_MSK));
1102 dprintk(1, "%s() AUD_INT_DMA_CTL 0x%08X\n", __FUNCTION__,
1103 cx_read(AUD_INT_DMA_CTL));
1104 dprintk(1, "%s() AUD_EXT_INT_MSK 0x%08X\n", __FUNCTION__,
1105 cx_read(AUDIO_EXT_INT_MSK));
1106 dprintk(1, "%s() AUD_EXT_DMA_CTL 0x%08X\n", __FUNCTION__,
1107 cx_read(AUD_EXT_DMA_CTL));
1108 dprintk(1, "%s() PAD_CTRL 0x%08X\n", __FUNCTION__,
1110 dprintk(1, "%s() ALT_PIN_OUT_SEL 0x%08X\n", __FUNCTION__,
1111 cx_read(ALT_PIN_OUT_SEL));
1112 dprintk(1, "%s() GPIO2 0x%08X\n", __FUNCTION__,
1114 dprintk(1, "%s() gpcnt(0x%08X) 0x%08X\n", __FUNCTION__,
1115 port->reg_gpcnt, cx_read(port->reg_gpcnt));
1116 dprintk(1, "%s() gpcnt_ctl(0x%08X) 0x%08x\n", __FUNCTION__,
1117 port->reg_gpcnt_ctl, cx_read(port->reg_gpcnt_ctl));
1118 dprintk(1, "%s() dma_ctl(0x%08X) 0x%08x\n", __FUNCTION__,
1119 port->reg_dma_ctl, cx_read(port->reg_dma_ctl));
1120 dprintk(1, "%s() src_sel(0x%08X) 0x%08x\n", __FUNCTION__,
1121 port->reg_src_sel, cx_read(port->reg_src_sel));
1122 dprintk(1, "%s() lngth(0x%08X) 0x%08x\n", __FUNCTION__,
1123 port->reg_lngth, cx_read(port->reg_lngth));
1124 dprintk(1, "%s() hw_sop_ctrl(0x%08X) 0x%08x\n", __FUNCTION__,
1125 port->reg_hw_sop_ctrl, cx_read(port->reg_hw_sop_ctrl));
1126 dprintk(1, "%s() gen_ctrl(0x%08X) 0x%08x\n", __FUNCTION__,
1127 port->reg_gen_ctrl, cx_read(port->reg_gen_ctrl));
1128 dprintk(1, "%s() bd_pkt_status(0x%08X) 0x%08x\n", __FUNCTION__,
1129 port->reg_bd_pkt_status, cx_read(port->reg_bd_pkt_status));
1130 dprintk(1, "%s() sop_status(0x%08X) 0x%08x\n", __FUNCTION__,
1131 port->reg_sop_status, cx_read(port->reg_sop_status));
1132 dprintk(1, "%s() fifo_ovfl_stat(0x%08X) 0x%08x\n", __FUNCTION__,
1133 port->reg_fifo_ovfl_stat, cx_read(port->reg_fifo_ovfl_stat));
1134 dprintk(1, "%s() vld_misc(0x%08X) 0x%08x\n", __FUNCTION__,
1135 port->reg_vld_misc, cx_read(port->reg_vld_misc));
1136 dprintk(1, "%s() ts_clk_en(0x%08X) 0x%08x\n", __FUNCTION__,
1137 port->reg_ts_clk_en, cx_read(port->reg_ts_clk_en));
1138 dprintk(1, "%s() ts_int_msk(0x%08X) 0x%08x\n", __FUNCTION__,
1139 port->reg_ts_int_msk, cx_read(port->reg_ts_int_msk));
1142 static int cx23885_start_dma(struct cx23885_tsport *port,
1143 struct cx23885_dmaqueue *q,
1144 struct cx23885_buffer *buf)
1146 struct cx23885_dev *dev = port->dev;
1148 dprintk(1, "%s() w: %d, h: %d, f: %d\n", __FUNCTION__,
1149 buf->vb.width, buf->vb.height, buf->vb.field);
1151 /* setup fifo + format */
1152 cx23885_sram_channel_setup(dev,
1153 &dev->sram_channels[ port->sram_chno ],
1154 port->ts_packet_size, buf->risc.dma);
1156 cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ] );
1157 cx23885_risc_disasm(port, &buf->risc);
1160 /* write TS length to chip */
1161 cx_write(port->reg_lngth, buf->vb.width);
1163 if ( (!(cx23885_boards[dev->board].portb & CX23885_MPEG_DVB)) &&
1164 (!(cx23885_boards[dev->board].portc & CX23885_MPEG_DVB)) ) {
1165 printk( "%s() Failed. Unsupported value in .portb/c (0x%08x)/(0x%08x)\n",
1167 cx23885_boards[dev->board].portb,
1168 cx23885_boards[dev->board].portc );
1174 /* If the port supports SRC SELECT, configure it */
1175 if(port->reg_src_sel)
1176 cx_write(port->reg_src_sel, port->src_sel_val);
1178 cx_write(port->reg_hw_sop_ctrl, 0x47 << 16 | 188 << 4);
1179 cx_write(port->reg_ts_clk_en, port->ts_clk_en_val);
1180 cx_write(port->reg_vld_misc, 0x00);
1181 cx_write(port->reg_gen_ctrl, port->gen_ctrl_val);
1184 // NOTE: this is 2 (reserved) for portb, does it matter?
1185 /* reset counter to zero */
1186 cx_write(port->reg_gpcnt_ctl, 3);
1189 switch(dev->bridge) {
1190 case CX23885_BRIDGE_885:
1191 case CX23885_BRIDGE_887:
1193 dprintk(1, "%s() enabling TS int's and DMA\n", __FUNCTION__ );
1194 cx_set(port->reg_ts_int_msk, port->ts_int_msk_val);
1195 cx_set(port->reg_dma_ctl, port->dma_ctl_val);
1196 cx_set(PCI_INT_MSK, dev->pci_irqmask | port->pci_irqmask);
1202 cx_set(DEV_CNTRL2, (1<<5)); /* Enable RISC controller */
1205 cx23885_tsport_reg_dump(port);
1210 static int cx23885_stop_dma(struct cx23885_tsport *port)
1212 struct cx23885_dev *dev = port->dev;
1213 dprintk(1, "%s()\n", __FUNCTION__);
1215 /* Stop interrupts and DMA */
1216 cx_clear(port->reg_ts_int_msk, port->ts_int_msk_val);
1217 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1222 int cx23885_restart_queue(struct cx23885_tsport *port,
1223 struct cx23885_dmaqueue *q)
1225 struct cx23885_dev *dev = port->dev;
1226 struct cx23885_buffer *buf;
1228 dprintk(5, "%s()\n", __FUNCTION__);
1229 if (list_empty(&q->active))
1231 struct cx23885_buffer *prev;
1234 dprintk(5, "%s() queue is empty\n", __FUNCTION__);
1237 if (list_empty(&q->queued))
1239 buf = list_entry(q->queued.next, struct cx23885_buffer,
1242 list_del(&buf->vb.queue);
1243 list_add_tail(&buf->vb.queue, &q->active);
1244 cx23885_start_dma(port, q, buf);
1245 buf->vb.state = VIDEOBUF_ACTIVE;
1246 buf->count = q->count++;
1247 mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT);
1248 dprintk(5, "[%p/%d] restart_queue - first active\n",
1251 } else if (prev->vb.width == buf->vb.width &&
1252 prev->vb.height == buf->vb.height &&
1253 prev->fmt == buf->fmt) {
1254 list_del(&buf->vb.queue);
1255 list_add_tail(&buf->vb.queue, &q->active);
1256 buf->vb.state = VIDEOBUF_ACTIVE;
1257 buf->count = q->count++;
1258 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
1259 prev->risc.jmp[2] = cpu_to_le32(0); /* 64 bit bits 63-32 */
1260 dprintk(5,"[%p/%d] restart_queue - move to active\n",
1270 buf = list_entry(q->active.next, struct cx23885_buffer, vb.queue);
1271 dprintk(2, "restart_queue [%p/%d]: restart dma\n",
1273 cx23885_start_dma(port, q, buf);
1274 list_for_each_entry(buf, &q->active, vb.queue)
1275 buf->count = q->count++;
1276 mod_timer(&q->timeout, jiffies + BUFFER_TIMEOUT);
1280 /* ------------------------------------------------------------------ */
1282 int cx23885_buf_prepare(struct videobuf_queue *q, struct cx23885_tsport *port,
1283 struct cx23885_buffer *buf, enum v4l2_field field)
1285 struct cx23885_dev *dev = port->dev;
1286 int size = port->ts_packet_size * port->ts_packet_count;
1289 dprintk(1, "%s: %p\n", __FUNCTION__, buf);
1290 if (0 != buf->vb.baddr && buf->vb.bsize < size)
1293 if (VIDEOBUF_NEEDS_INIT == buf->vb.state) {
1294 buf->vb.width = port->ts_packet_size;
1295 buf->vb.height = port->ts_packet_count;
1296 buf->vb.size = size;
1297 buf->vb.field = field /*V4L2_FIELD_TOP*/;
1299 if (0 != (rc = videobuf_iolock(q, &buf->vb, NULL)))
1301 cx23885_risc_databuffer(dev->pci, &buf->risc,
1302 videobuf_to_dma(&buf->vb)->sglist,
1303 buf->vb.width, buf->vb.height);
1305 buf->vb.state = VIDEOBUF_PREPARED;
1309 cx23885_free_buffer(q, buf);
1313 void cx23885_buf_queue(struct cx23885_tsport *port, struct cx23885_buffer *buf)
1315 struct cx23885_buffer *prev;
1316 struct cx23885_dev *dev = port->dev;
1317 struct cx23885_dmaqueue *cx88q = &port->mpegq;
1319 /* add jump to stopper */
1320 buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
1321 buf->risc.jmp[1] = cpu_to_le32(cx88q->stopper.dma);
1322 buf->risc.jmp[2] = cpu_to_le32(0); /* bits 63-32 */
1324 if (list_empty(&cx88q->active)) {
1325 dprintk( 1, "queue is empty - first active\n" );
1326 list_add_tail(&buf->vb.queue, &cx88q->active);
1327 cx23885_start_dma(port, cx88q, buf);
1328 buf->vb.state = VIDEOBUF_ACTIVE;
1329 buf->count = cx88q->count++;
1330 mod_timer(&cx88q->timeout, jiffies + BUFFER_TIMEOUT);
1331 dprintk(1, "[%p/%d] %s - first active\n",
1332 buf, buf->vb.i, __FUNCTION__);
1334 dprintk( 1, "queue is not empty - append to active\n" );
1335 prev = list_entry(cx88q->active.prev, struct cx23885_buffer,
1337 list_add_tail(&buf->vb.queue, &cx88q->active);
1338 buf->vb.state = VIDEOBUF_ACTIVE;
1339 buf->count = cx88q->count++;
1340 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
1341 prev->risc.jmp[2] = cpu_to_le32(0); /* 64 bit bits 63-32 */
1342 dprintk( 1, "[%p/%d] %s - append to active\n",
1343 buf, buf->vb.i, __FUNCTION__);
1347 /* ----------------------------------------------------------- */
1349 static void do_cancel_buffers(struct cx23885_tsport *port, char *reason,
1352 struct cx23885_dev *dev = port->dev;
1353 struct cx23885_dmaqueue *q = &port->mpegq;
1354 struct cx23885_buffer *buf;
1355 unsigned long flags;
1357 spin_lock_irqsave(&port->slock, flags);
1358 while (!list_empty(&q->active)) {
1359 buf = list_entry(q->active.next, struct cx23885_buffer,
1361 list_del(&buf->vb.queue);
1362 buf->vb.state = VIDEOBUF_ERROR;
1363 wake_up(&buf->vb.done);
1364 dprintk(1, "[%p/%d] %s - dma=0x%08lx\n",
1365 buf, buf->vb.i, reason, (unsigned long)buf->risc.dma);
1368 dprintk(1, "restarting queue\n" );
1369 cx23885_restart_queue(port, q);
1371 spin_unlock_irqrestore(&port->slock, flags);
1375 static void cx23885_timeout(unsigned long data)
1377 struct cx23885_tsport *port = (struct cx23885_tsport *)data;
1378 struct cx23885_dev *dev = port->dev;
1380 dprintk(1, "%s()\n",__FUNCTION__);
1383 cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ]);
1385 cx23885_stop_dma(port);
1386 do_cancel_buffers(port, "timeout", 1);
1389 static int cx23885_irq_ts(struct cx23885_tsport *port, u32 status)
1391 struct cx23885_dev *dev = port->dev;
1395 if ( (status & VID_BC_MSK_OPC_ERR) ||
1396 (status & VID_BC_MSK_BAD_PKT) ||
1397 (status & VID_BC_MSK_SYNC) ||
1398 (status & VID_BC_MSK_OF))
1400 if (status & VID_BC_MSK_OPC_ERR)
1401 dprintk(7, " (VID_BC_MSK_OPC_ERR 0x%08x)\n", VID_BC_MSK_OPC_ERR);
1402 if (status & VID_BC_MSK_BAD_PKT)
1403 dprintk(7, " (VID_BC_MSK_BAD_PKT 0x%08x)\n", VID_BC_MSK_BAD_PKT);
1404 if (status & VID_BC_MSK_SYNC)
1405 dprintk(7, " (VID_BC_MSK_SYNC 0x%08x)\n", VID_BC_MSK_SYNC);
1406 if (status & VID_BC_MSK_OF)
1407 dprintk(7, " (VID_BC_MSK_OF 0x%08x)\n", VID_BC_MSK_OF);
1409 printk(KERN_ERR "%s: mpeg risc op code error\n", dev->name);
1411 cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
1412 cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ]);
1414 } else if (status & VID_BC_MSK_RISCI1) {
1416 dprintk(7, " (RISCI1 0x%08x)\n", VID_BC_MSK_RISCI1);
1418 spin_lock(&port->slock);
1419 count = cx_read(port->reg_gpcnt);
1420 cx23885_wakeup(port, &port->mpegq, count);
1421 spin_unlock(&port->slock);
1423 } else if (status & VID_BC_MSK_RISCI2) {
1425 dprintk(7, " (RISCI2 0x%08x)\n", VID_BC_MSK_RISCI2);
1427 spin_lock(&port->slock);
1428 cx23885_restart_queue(port, &port->mpegq);
1429 spin_unlock(&port->slock);
1433 cx_write(port->reg_ts_int_stat, status);
1440 static irqreturn_t cx23885_irq(int irq, void *dev_id)
1442 struct cx23885_dev *dev = dev_id;
1443 struct cx23885_tsport *ts1 = &dev->ts1;
1444 struct cx23885_tsport *ts2 = &dev->ts2;
1445 u32 pci_status, pci_mask;
1446 u32 vida_status, vida_mask;
1447 u32 ts1_status, ts1_mask;
1448 u32 ts2_status, ts2_mask;
1449 int vida_count = 0, ts1_count = 0, ts2_count = 0, handled = 0;
1451 pci_status = cx_read(PCI_INT_STAT);
1452 pci_mask = cx_read(PCI_INT_MSK);
1453 vida_status = cx_read(VID_A_INT_STAT);
1454 vida_mask = cx_read(VID_A_INT_MSK);
1455 ts1_status = cx_read(VID_B_INT_STAT);
1456 ts1_mask = cx_read(VID_B_INT_MSK);
1457 ts2_status = cx_read(VID_C_INT_STAT);
1458 ts2_mask = cx_read(VID_C_INT_MSK);
1460 if ( (pci_status == 0) && (ts2_status == 0) && (ts1_status == 0) )
1463 vida_count = cx_read(VID_A_GPCNT);
1464 ts1_count = cx_read(ts1->reg_gpcnt);
1465 ts2_count = cx_read(ts2->reg_gpcnt);
1466 dprintk(7, "pci_status: 0x%08x pci_mask: 0x%08x\n",
1467 pci_status, pci_mask);
1468 dprintk(7, "vida_status: 0x%08x vida_mask: 0x%08x count: 0x%x\n",
1469 vida_status, vida_mask, vida_count);
1470 dprintk(7, "ts1_status: 0x%08x ts1_mask: 0x%08x count: 0x%x\n",
1471 ts1_status, ts1_mask, ts1_count);
1472 dprintk(7, "ts2_status: 0x%08x ts2_mask: 0x%08x count: 0x%x\n",
1473 ts2_status, ts2_mask, ts2_count);
1475 if ( (pci_status & PCI_MSK_RISC_RD) ||
1476 (pci_status & PCI_MSK_RISC_WR) ||
1477 (pci_status & PCI_MSK_AL_RD) ||
1478 (pci_status & PCI_MSK_AL_WR) ||
1479 (pci_status & PCI_MSK_APB_DMA) ||
1480 (pci_status & PCI_MSK_VID_C) ||
1481 (pci_status & PCI_MSK_VID_B) ||
1482 (pci_status & PCI_MSK_VID_A) ||
1483 (pci_status & PCI_MSK_AUD_INT) ||
1484 (pci_status & PCI_MSK_AUD_EXT) )
1487 if (pci_status & PCI_MSK_RISC_RD)
1488 dprintk(7, " (PCI_MSK_RISC_RD 0x%08x)\n", PCI_MSK_RISC_RD);
1489 if (pci_status & PCI_MSK_RISC_WR)
1490 dprintk(7, " (PCI_MSK_RISC_WR 0x%08x)\n", PCI_MSK_RISC_WR);
1491 if (pci_status & PCI_MSK_AL_RD)
1492 dprintk(7, " (PCI_MSK_AL_RD 0x%08x)\n", PCI_MSK_AL_RD);
1493 if (pci_status & PCI_MSK_AL_WR)
1494 dprintk(7, " (PCI_MSK_AL_WR 0x%08x)\n", PCI_MSK_AL_WR);
1495 if (pci_status & PCI_MSK_APB_DMA)
1496 dprintk(7, " (PCI_MSK_APB_DMA 0x%08x)\n", PCI_MSK_APB_DMA);
1497 if (pci_status & PCI_MSK_VID_C)
1498 dprintk(7, " (PCI_MSK_VID_C 0x%08x)\n", PCI_MSK_VID_C);
1499 if (pci_status & PCI_MSK_VID_B)
1500 dprintk(7, " (PCI_MSK_VID_B 0x%08x)\n", PCI_MSK_VID_B);
1501 if (pci_status & PCI_MSK_VID_A)
1502 dprintk(7, " (PCI_MSK_VID_A 0x%08x)\n", PCI_MSK_VID_A);
1503 if (pci_status & PCI_MSK_AUD_INT)
1504 dprintk(7, " (PCI_MSK_AUD_INT 0x%08x)\n", PCI_MSK_AUD_INT);
1505 if (pci_status & PCI_MSK_AUD_EXT)
1506 dprintk(7, " (PCI_MSK_AUD_EXT 0x%08x)\n", PCI_MSK_AUD_EXT);
1511 if (cx23885_boards[dev->board].portb == CX23885_MPEG_DVB)
1512 handled += cx23885_irq_ts(ts1, ts1_status);
1516 if (cx23885_boards[dev->board].portc == CX23885_MPEG_DVB)
1517 handled += cx23885_irq_ts(ts2, ts2_status);
1521 handled += cx23885_video_irq(dev, vida_status);
1524 cx_write(PCI_INT_STAT, pci_status);
1526 return IRQ_RETVAL(handled);
1529 static int __devinit cx23885_initdev(struct pci_dev *pci_dev,
1530 const struct pci_device_id *pci_id)
1532 struct cx23885_dev *dev;
1535 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1541 if (pci_enable_device(pci_dev)) {
1546 if (cx23885_dev_setup(dev) < 0) {
1551 /* print pci info */
1552 pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev);
1553 pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat);
1554 printk(KERN_INFO "%s/0: found at %s, rev: %d, irq: %d, "
1555 "latency: %d, mmio: 0x%llx\n", dev->name,
1556 pci_name(pci_dev), dev->pci_rev, pci_dev->irq,
1557 dev->pci_lat, (unsigned long long)pci_resource_start(pci_dev,0));
1559 pci_set_master(pci_dev);
1560 if (!pci_dma_supported(pci_dev, 0xffffffff)) {
1561 printk("%s/0: Oops: no 32bit PCI DMA ???\n", dev->name);
1566 err = request_irq(pci_dev->irq, cx23885_irq,
1567 IRQF_SHARED | IRQF_DISABLED, dev->name, dev);
1569 printk(KERN_ERR "%s: can't get IRQ %d\n",
1570 dev->name, pci_dev->irq);
1574 pci_set_drvdata(pci_dev, dev);
1578 cx23885_dev_unregister(dev);
1584 static void __devexit cx23885_finidev(struct pci_dev *pci_dev)
1586 struct cx23885_dev *dev = pci_get_drvdata(pci_dev);
1588 cx23885_shutdown(dev);
1590 pci_disable_device(pci_dev);
1592 /* unregister stuff */
1593 free_irq(pci_dev->irq, dev);
1594 pci_set_drvdata(pci_dev, NULL);
1596 mutex_lock(&devlist);
1597 list_del(&dev->devlist);
1598 mutex_unlock(&devlist);
1600 cx23885_dev_unregister(dev);
1604 static struct pci_device_id cx23885_pci_tbl[] = {
1609 .subvendor = PCI_ANY_ID,
1610 .subdevice = PCI_ANY_ID,
1615 .subvendor = PCI_ANY_ID,
1616 .subdevice = PCI_ANY_ID,
1618 /* --- end of list --- */
1621 MODULE_DEVICE_TABLE(pci, cx23885_pci_tbl);
1623 static struct pci_driver cx23885_pci_driver = {
1625 .id_table = cx23885_pci_tbl,
1626 .probe = cx23885_initdev,
1627 .remove = __devexit_p(cx23885_finidev),
1633 static int cx23885_init(void)
1635 printk(KERN_INFO "cx23885 driver version %d.%d.%d loaded\n",
1636 (CX23885_VERSION_CODE >> 16) & 0xff,
1637 (CX23885_VERSION_CODE >> 8) & 0xff,
1638 CX23885_VERSION_CODE & 0xff);
1640 printk(KERN_INFO "cx23885: snapshot date %04d-%02d-%02d\n",
1641 SNAPSHOT/10000, (SNAPSHOT/100)%100, SNAPSHOT%100);
1643 return pci_register_driver(&cx23885_pci_driver);
1646 static void cx23885_fini(void)
1648 pci_unregister_driver(&cx23885_pci_driver);
1651 module_init(cx23885_init);
1652 module_exit(cx23885_fini);
1654 /* ----------------------------------------------------------- */
1659 * kate: eol "unix"; indent-width 3; remove-trailing-space on; replace-trailing-space-save on; tab-width 8; replace-tabs off; space-indent off; mixed-indent off