2 * drivers/net/mv643xx_eth.c - Driver for MV643XX ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 rabeeh@galileo.co.il
8 * Copyright (C) 2003 PMC-Sierra, Inc.,
9 * written by Manish Lachwani
11 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 * Copyright (C) 2004-2005 MontaVista Software, Inc.
14 * Dale Farnsworth <dale@farnsworth.org>
16 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
17 * <sjhill@realitydiluted.com>
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version 2
22 * of the License, or (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
33 #include <linux/init.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/tcp.h>
36 #include <linux/udp.h>
37 #include <linux/etherdevice.h>
41 #include <linux/bitops.h>
42 #include <linux/delay.h>
43 #include <linux/ethtool.h>
44 #include <linux/platform_device.h>
47 #include <asm/types.h>
48 #include <asm/pgtable.h>
49 #include <asm/system.h>
50 #include <asm/delay.h>
51 #include "mv643xx_eth.h"
54 * The first part is the high level driver of the gigE ethernet ports.
60 #define DMA_ALIGN 8 /* hw requires 8-byte alignment */
61 #define HW_IP_ALIGN 2 /* hw aligns IP header */
62 #define WRAP HW_IP_ALIGN + ETH_HLEN + VLAN_HLEN + FCS_LEN
63 #define RX_SKB_SIZE ((dev->mtu + WRAP + 7) & ~0x7)
65 #define INT_CAUSE_UNMASK_ALL 0x0007ffff
66 #define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff
67 #define INT_CAUSE_MASK_ALL 0x00000000
68 #define INT_CAUSE_MASK_ALL_EXT 0x00000000
69 #define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL
70 #define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT
72 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
73 #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
75 #define MAX_DESCS_PER_SKB 1
78 #define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */
79 #define PHY_WAIT_MICRO_SECONDS 10
81 /* Static function declarations */
82 static int eth_port_link_is_up(unsigned int eth_port_num);
83 static void eth_port_uc_addr_get(struct net_device *dev,
84 unsigned char *MacAddr);
85 static void eth_port_set_multicast_list(struct net_device *);
86 static int mv643xx_eth_real_open(struct net_device *);
87 static int mv643xx_eth_real_stop(struct net_device *);
88 static int mv643xx_eth_change_mtu(struct net_device *, int);
89 static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *);
90 static void eth_port_init_mac_tables(unsigned int eth_port_num);
92 static int mv643xx_poll(struct net_device *dev, int *budget);
94 static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);
95 static int ethernet_phy_detect(unsigned int eth_port_num);
96 static struct ethtool_ops mv643xx_ethtool_ops;
98 static char mv643xx_driver_name[] = "mv643xx_eth";
99 static char mv643xx_driver_version[] = "1.0";
101 static void __iomem *mv643xx_eth_shared_base;
103 /* used to protect MV643XX_ETH_SMI_REG, which is shared across ports */
104 static DEFINE_SPINLOCK(mv643xx_eth_phy_lock);
106 static inline u32 mv_read(int offset)
108 void __iomem *reg_base;
110 reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS;
112 return readl(reg_base + offset);
115 static inline void mv_write(int offset, u32 data)
117 void __iomem *reg_base;
119 reg_base = mv643xx_eth_shared_base - MV643XX_ETH_SHARED_REGS;
120 writel(data, reg_base + offset);
124 * Changes MTU (maximum transfer unit) of the gigabit ethenret port
126 * Input : pointer to ethernet interface network device structure
128 * Output : 0 upon success, -EINVAL upon failure
130 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
132 struct mv643xx_private *mp = netdev_priv(dev);
135 spin_lock_irqsave(&mp->lock, flags);
137 if ((new_mtu > 9500) || (new_mtu < 64)) {
138 spin_unlock_irqrestore(&mp->lock, flags);
144 * Stop then re-open the interface. This will allocate RX skb's with
146 * There is a possible danger that the open will not successed, due
147 * to memory is full, which might fail the open function.
149 if (netif_running(dev)) {
150 if (mv643xx_eth_real_stop(dev))
152 "%s: Fatal error on stopping device\n",
154 if (mv643xx_eth_real_open(dev))
156 "%s: Fatal error on opening device\n",
160 spin_unlock_irqrestore(&mp->lock, flags);
165 * mv643xx_eth_rx_task
167 * Fills / refills RX queue on a certain gigabit ethernet port
169 * Input : pointer to ethernet interface network device structure
172 static void mv643xx_eth_rx_task(void *data)
174 struct net_device *dev = (struct net_device *)data;
175 struct mv643xx_private *mp = netdev_priv(dev);
176 struct pkt_info pkt_info;
180 if (test_and_set_bit(0, &mp->rx_task_busy))
181 panic("%s: Error in test_set_bit / clear_bit", dev->name);
183 while (mp->rx_ring_skbs < (mp->rx_ring_size - 5)) {
184 skb = dev_alloc_skb(RX_SKB_SIZE + DMA_ALIGN);
188 unaligned = (u32)skb->data & (DMA_ALIGN - 1);
190 skb_reserve(skb, DMA_ALIGN - unaligned);
191 pkt_info.cmd_sts = ETH_RX_ENABLE_INTERRUPT;
192 pkt_info.byte_cnt = RX_SKB_SIZE;
193 pkt_info.buf_ptr = dma_map_single(NULL, skb->data, RX_SKB_SIZE,
195 pkt_info.return_info = skb;
196 if (eth_rx_return_buff(mp, &pkt_info) != ETH_OK) {
198 "%s: Error allocating RX Ring\n", dev->name);
201 skb_reserve(skb, HW_IP_ALIGN);
203 clear_bit(0, &mp->rx_task_busy);
205 * If RX ring is empty of SKB, set a timer to try allocating
206 * again in a later time .
208 if ((mp->rx_ring_skbs == 0) && (mp->rx_timer_flag == 0)) {
209 printk(KERN_INFO "%s: Rx ring is empty\n", dev->name);
211 mp->timeout.expires = jiffies + (HZ / 10);
212 add_timer(&mp->timeout);
213 mp->rx_timer_flag = 1;
215 #ifdef MV643XX_RX_QUEUE_FILL_ON_TASK
217 /* Return interrupts */
218 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(mp->port_num),
219 INT_CAUSE_UNMASK_ALL);
225 * mv643xx_eth_rx_task_timer_wrapper
227 * Timer routine to wake up RX queue filling task. This function is
228 * used only in case the RX queue is empty, and all alloc_skb has
229 * failed (due to out of memory event).
231 * Input : pointer to ethernet interface network device structure
234 static void mv643xx_eth_rx_task_timer_wrapper(unsigned long data)
236 struct net_device *dev = (struct net_device *)data;
237 struct mv643xx_private *mp = netdev_priv(dev);
239 mp->rx_timer_flag = 0;
240 mv643xx_eth_rx_task((void *)data);
244 * mv643xx_eth_update_mac_address
246 * Update the MAC address of the port in the address table
248 * Input : pointer to ethernet interface network device structure
251 static void mv643xx_eth_update_mac_address(struct net_device *dev)
253 struct mv643xx_private *mp = netdev_priv(dev);
254 unsigned int port_num = mp->port_num;
256 eth_port_init_mac_tables(port_num);
257 memcpy(mp->port_mac_addr, dev->dev_addr, 6);
258 eth_port_uc_addr_set(port_num, mp->port_mac_addr);
262 * mv643xx_eth_set_rx_mode
264 * Change from promiscuos to regular rx mode
266 * Input : pointer to ethernet interface network device structure
269 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
271 struct mv643xx_private *mp = netdev_priv(dev);
273 if (dev->flags & IFF_PROMISC)
274 mp->port_config |= (u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE;
276 mp->port_config &= ~(u32) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE;
278 mv_write(MV643XX_ETH_PORT_CONFIG_REG(mp->port_num), mp->port_config);
280 eth_port_set_multicast_list(dev);
284 * mv643xx_eth_set_mac_address
286 * Change the interface's mac address.
287 * No special hardware thing should be done because interface is always
288 * put in promiscuous mode.
290 * Input : pointer to ethernet interface network device structure and
291 * a pointer to the designated entry to be added to the cache.
292 * Output : zero upon success, negative upon failure
294 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
298 for (i = 0; i < 6; i++)
299 /* +2 is for the offset of the HW addr type */
300 dev->dev_addr[i] = ((unsigned char *)addr)[i + 2];
301 mv643xx_eth_update_mac_address(dev);
306 * mv643xx_eth_tx_timeout
308 * Called upon a timeout on transmitting a packet
310 * Input : pointer to ethernet interface network device structure.
313 static void mv643xx_eth_tx_timeout(struct net_device *dev)
315 struct mv643xx_private *mp = netdev_priv(dev);
317 printk(KERN_INFO "%s: TX timeout ", dev->name);
319 /* Do the reset outside of interrupt context */
320 schedule_work(&mp->tx_timeout_task);
324 * mv643xx_eth_tx_timeout_task
326 * Actual routine to reset the adapter when a timeout on Tx has occurred
328 static void mv643xx_eth_tx_timeout_task(struct net_device *dev)
330 struct mv643xx_private *mp = netdev_priv(dev);
332 netif_device_detach(dev);
333 eth_port_reset(mp->port_num);
335 netif_device_attach(dev);
339 * mv643xx_eth_free_tx_queue
341 * Input : dev - a pointer to the required interface
343 * Output : 0 if was able to release skb , nonzero otherwise
345 static int mv643xx_eth_free_tx_queue(struct net_device *dev,
346 unsigned int eth_int_cause_ext)
348 struct mv643xx_private *mp = netdev_priv(dev);
349 struct net_device_stats *stats = &mp->stats;
350 struct pkt_info pkt_info;
353 if (!(eth_int_cause_ext & (BIT0 | BIT8)))
356 spin_lock(&mp->lock);
358 /* Check only queue 0 */
359 while (eth_tx_return_desc(mp, &pkt_info) == ETH_OK) {
360 if (pkt_info.cmd_sts & BIT0) {
361 printk("%s: Error in TX\n", dev->name);
365 if (pkt_info.cmd_sts & ETH_TX_FIRST_DESC)
366 dma_unmap_single(NULL, pkt_info.buf_ptr,
370 dma_unmap_page(NULL, pkt_info.buf_ptr,
374 if (pkt_info.return_info) {
375 dev_kfree_skb_irq(pkt_info.return_info);
380 spin_unlock(&mp->lock);
386 * mv643xx_eth_receive
388 * This function is forward packets that are received from the port's
389 * queues toward kernel core or FastRoute them to another interface.
391 * Input : dev - a pointer to the required interface
392 * max - maximum number to receive (0 means unlimted)
394 * Output : number of served packets
397 static int mv643xx_eth_receive_queue(struct net_device *dev, int budget)
399 static int mv643xx_eth_receive_queue(struct net_device *dev)
402 struct mv643xx_private *mp = netdev_priv(dev);
403 struct net_device_stats *stats = &mp->stats;
404 unsigned int received_packets = 0;
406 struct pkt_info pkt_info;
409 while (budget-- > 0 && eth_port_receive(mp, &pkt_info) == ETH_OK) {
411 while (eth_port_receive(mp, &pkt_info) == ETH_OK) {
416 /* Update statistics. Note byte count includes 4 byte CRC count */
418 stats->rx_bytes += pkt_info.byte_cnt;
419 skb = pkt_info.return_info;
421 * In case received a packet without first / last bits on OR
422 * the error summary bit is on, the packets needs to be dropeed.
424 if (((pkt_info.cmd_sts
425 & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
426 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
427 || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
429 if ((pkt_info.cmd_sts & (ETH_RX_FIRST_DESC |
430 ETH_RX_LAST_DESC)) !=
431 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) {
434 "%s: Received packet spread "
435 "on multiple descriptors\n",
438 if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)
441 dev_kfree_skb_irq(skb);
444 * The -4 is for the CRC in the trailer of the
447 skb_put(skb, pkt_info.byte_cnt - 4);
450 if (pkt_info.cmd_sts & ETH_LAYER_4_CHECKSUM_OK) {
451 skb->ip_summed = CHECKSUM_UNNECESSARY;
453 (pkt_info.cmd_sts & 0x0007fff8) >> 3);
455 skb->protocol = eth_type_trans(skb, dev);
457 netif_receive_skb(skb);
464 return received_packets;
468 * mv643xx_eth_int_handler
470 * Main interrupt handler for the gigbit ethernet ports
472 * Input : irq - irq number (not used)
473 * dev_id - a pointer to the required interface's data structure
478 static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id,
479 struct pt_regs *regs)
481 struct net_device *dev = (struct net_device *)dev_id;
482 struct mv643xx_private *mp = netdev_priv(dev);
483 u32 eth_int_cause, eth_int_cause_ext = 0;
484 unsigned int port_num = mp->port_num;
486 /* Read interrupt cause registers */
487 eth_int_cause = mv_read(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num)) &
488 INT_CAUSE_UNMASK_ALL;
490 if (eth_int_cause & BIT1)
491 eth_int_cause_ext = mv_read(
492 MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num)) &
493 INT_CAUSE_UNMASK_ALL_EXT;
496 if (!(eth_int_cause & 0x0007fffd)) {
497 /* Dont ack the Rx interrupt */
500 * Clear specific ethernet port intrerrupt registers by
501 * acknowleding relevant bits.
503 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num),
505 if (eth_int_cause_ext != 0x0)
506 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG
507 (port_num), ~eth_int_cause_ext);
509 /* UDP change : We may need this */
510 if ((eth_int_cause_ext & 0x0000ffff) &&
511 (mv643xx_eth_free_tx_queue(dev, eth_int_cause_ext) == 0) &&
512 (mp->tx_ring_size > mp->tx_ring_skbs + MAX_DESCS_PER_SKB))
513 netif_wake_queue(dev);
516 if (netif_rx_schedule_prep(dev)) {
517 /* Mask all the interrupts */
518 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), 0);
519 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG
521 __netif_rx_schedule(dev);
524 if (eth_int_cause & (BIT2 | BIT11))
525 mv643xx_eth_receive_queue(dev, 0);
528 * After forwarded received packets to upper layer, add a task
529 * in an interrupts enabled context that refills the RX ring
532 #ifdef MV643XX_RX_QUEUE_FILL_ON_TASK
533 /* Unmask all interrupts on ethernet port */
534 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
536 queue_task(&mp->rx_task, &tq_immediate);
537 mark_bh(IMMEDIATE_BH);
539 mp->rx_task.func(dev);
543 /* PHY status changed */
544 if (eth_int_cause_ext & (BIT16 | BIT20)) {
545 if (eth_port_link_is_up(port_num)) {
546 netif_carrier_on(dev);
547 netif_wake_queue(dev);
549 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG
552 netif_carrier_off(dev);
553 netif_stop_queue(dev);
558 * If no real interrupt occured, exit.
559 * This can happen when using gigE interrupt coalescing mechanism.
561 if ((eth_int_cause == 0x0) && (eth_int_cause_ext == 0x0))
570 * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
573 * This routine sets the RX coalescing interrupt mechanism parameter.
574 * This parameter is a timeout counter, that counts in 64 t_clk
575 * chunks ; that when timeout event occurs a maskable interrupt
577 * The parameter is calculated using the tClk of the MV-643xx chip
578 * , and the required delay of the interrupt in usec.
581 * unsigned int eth_port_num Ethernet port number
582 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
583 * unsigned int delay Delay in usec
586 * Interrupt coalescing mechanism value is set in MV-643xx chip.
589 * The interrupt coalescing value set in the gigE port.
592 static unsigned int eth_port_set_rx_coal(unsigned int eth_port_num,
593 unsigned int t_clk, unsigned int delay)
595 unsigned int coal = ((t_clk / 1000000) * delay) / 64;
597 /* Set RX Coalescing mechanism */
598 mv_write(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num),
599 ((coal & 0x3fff) << 8) |
600 (mv_read(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num))
608 * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
611 * This routine sets the TX coalescing interrupt mechanism parameter.
612 * This parameter is a timeout counter, that counts in 64 t_clk
613 * chunks ; that when timeout event occurs a maskable interrupt
615 * The parameter is calculated using the t_cLK frequency of the
616 * MV-643xx chip and the required delay in the interrupt in uSec
619 * unsigned int eth_port_num Ethernet port number
620 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
621 * unsigned int delay Delay in uSeconds
624 * Interrupt coalescing mechanism value is set in MV-643xx chip.
627 * The interrupt coalescing value set in the gigE port.
630 static unsigned int eth_port_set_tx_coal(unsigned int eth_port_num,
631 unsigned int t_clk, unsigned int delay)
634 coal = ((t_clk / 1000000) * delay) / 64;
635 /* Set TX Coalescing mechanism */
636 mv_write(MV643XX_ETH_TX_FIFO_URGENT_THRESHOLD_REG(eth_port_num),
644 * This function is called when openning the network device. The function
645 * should initialize all the hardware, initialize cyclic Rx/Tx
646 * descriptors chain and buffers and allocate an IRQ to the network
649 * Input : a pointer to the network device structure
651 * Output : zero of success , nonzero if fails.
654 static int mv643xx_eth_open(struct net_device *dev)
656 struct mv643xx_private *mp = netdev_priv(dev);
657 unsigned int port_num = mp->port_num;
660 spin_lock_irq(&mp->lock);
662 err = request_irq(dev->irq, mv643xx_eth_int_handler,
663 SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
666 printk(KERN_ERR "Can not assign IRQ number to MV643XX_eth%d\n",
672 if (mv643xx_eth_real_open(dev)) {
673 printk("%s: Error opening interface\n", dev->name);
678 spin_unlock_irq(&mp->lock);
683 free_irq(dev->irq, dev);
686 spin_unlock_irq(&mp->lock);
692 * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
695 * This function prepares a Rx chained list of descriptors and packet
696 * buffers in a form of a ring. The routine must be called after port
697 * initialization routine and before port start routine.
698 * The Ethernet SDMA engine uses CPU bus addresses to access the various
699 * devices in the system (i.e. DRAM). This function uses the ethernet
700 * struct 'virtual to physical' routine (set by the user) to set the ring
701 * with physical addresses.
704 * struct mv643xx_private *mp Ethernet Port Control srtuct.
707 * The routine updates the Ethernet port control struct with information
708 * regarding the Rx descriptors and buffers.
713 static void ether_init_rx_desc_ring(struct mv643xx_private *mp)
715 volatile struct eth_rx_desc *p_rx_desc;
716 int rx_desc_num = mp->rx_ring_size;
719 /* initialize the next_desc_ptr links in the Rx descriptors ring */
720 p_rx_desc = (struct eth_rx_desc *)mp->p_rx_desc_area;
721 for (i = 0; i < rx_desc_num; i++) {
722 p_rx_desc[i].next_desc_ptr = mp->rx_desc_dma +
723 ((i + 1) % rx_desc_num) * sizeof(struct eth_rx_desc);
726 /* Save Rx desc pointer to driver struct. */
727 mp->rx_curr_desc_q = 0;
728 mp->rx_used_desc_q = 0;
730 mp->rx_desc_area_size = rx_desc_num * sizeof(struct eth_rx_desc);
732 /* Add the queue to the list of RX queues of this port */
733 mp->port_rx_queue_command |= 1;
737 * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
740 * This function prepares a Tx chained list of descriptors and packet
741 * buffers in a form of a ring. The routine must be called after port
742 * initialization routine and before port start routine.
743 * The Ethernet SDMA engine uses CPU bus addresses to access the various
744 * devices in the system (i.e. DRAM). This function uses the ethernet
745 * struct 'virtual to physical' routine (set by the user) to set the ring
746 * with physical addresses.
749 * struct mv643xx_private *mp Ethernet Port Control srtuct.
752 * The routine updates the Ethernet port control struct with information
753 * regarding the Tx descriptors and buffers.
758 static void ether_init_tx_desc_ring(struct mv643xx_private *mp)
760 int tx_desc_num = mp->tx_ring_size;
761 struct eth_tx_desc *p_tx_desc;
764 /* Initialize the next_desc_ptr links in the Tx descriptors ring */
765 p_tx_desc = (struct eth_tx_desc *)mp->p_tx_desc_area;
766 for (i = 0; i < tx_desc_num; i++) {
767 p_tx_desc[i].next_desc_ptr = mp->tx_desc_dma +
768 ((i + 1) % tx_desc_num) * sizeof(struct eth_tx_desc);
771 mp->tx_curr_desc_q = 0;
772 mp->tx_used_desc_q = 0;
773 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
774 mp->tx_first_desc_q = 0;
777 mp->tx_desc_area_size = tx_desc_num * sizeof(struct eth_tx_desc);
779 /* Add the queue to the list of Tx queues of this port */
780 mp->port_tx_queue_command |= 1;
783 /* Helper function for mv643xx_eth_open */
784 static int mv643xx_eth_real_open(struct net_device *dev)
786 struct mv643xx_private *mp = netdev_priv(dev);
787 unsigned int port_num = mp->port_num;
791 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num), 0x0000ff00);
793 /* Clear the ethernet port interrupts */
794 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
795 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
797 /* Unmask RX buffer and TX end interrupt */
798 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
799 INT_CAUSE_UNMASK_ALL);
801 /* Unmask phy and link status changes interrupts */
802 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
803 INT_CAUSE_UNMASK_ALL_EXT);
805 /* Set the MAC Address */
806 memcpy(mp->port_mac_addr, dev->dev_addr, 6);
810 INIT_WORK(&mp->rx_task, (void (*)(void *))mv643xx_eth_rx_task, dev);
812 memset(&mp->timeout, 0, sizeof(struct timer_list));
813 mp->timeout.function = mv643xx_eth_rx_task_timer_wrapper;
814 mp->timeout.data = (unsigned long)dev;
816 mp->rx_task_busy = 0;
817 mp->rx_timer_flag = 0;
819 /* Allocate RX and TX skb rings */
820 mp->rx_skb = kmalloc(sizeof(*mp->rx_skb) * mp->rx_ring_size,
823 printk(KERN_ERR "%s: Cannot allocate Rx skb ring\n", dev->name);
826 mp->tx_skb = kmalloc(sizeof(*mp->tx_skb) * mp->tx_ring_size,
829 printk(KERN_ERR "%s: Cannot allocate Tx skb ring\n", dev->name);
834 /* Allocate TX ring */
835 mp->tx_ring_skbs = 0;
836 size = mp->tx_ring_size * sizeof(struct eth_tx_desc);
837 mp->tx_desc_area_size = size;
839 if (mp->tx_sram_size) {
840 mp->p_tx_desc_area = ioremap(mp->tx_sram_addr,
842 mp->tx_desc_dma = mp->tx_sram_addr;
844 mp->p_tx_desc_area = dma_alloc_coherent(NULL, size,
848 if (!mp->p_tx_desc_area) {
849 printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n",
855 BUG_ON((u32) mp->p_tx_desc_area & 0xf); /* check 16-byte alignment */
856 memset((void *)mp->p_tx_desc_area, 0, mp->tx_desc_area_size);
858 ether_init_tx_desc_ring(mp);
860 /* Allocate RX ring */
861 mp->rx_ring_skbs = 0;
862 size = mp->rx_ring_size * sizeof(struct eth_rx_desc);
863 mp->rx_desc_area_size = size;
865 if (mp->rx_sram_size) {
866 mp->p_rx_desc_area = ioremap(mp->rx_sram_addr,
868 mp->rx_desc_dma = mp->rx_sram_addr;
870 mp->p_rx_desc_area = dma_alloc_coherent(NULL, size,
874 if (!mp->p_rx_desc_area) {
875 printk(KERN_ERR "%s: Cannot allocate Rx ring (size %d bytes)\n",
877 printk(KERN_ERR "%s: Freeing previously allocated TX queues...",
879 if (mp->rx_sram_size)
880 iounmap(mp->p_tx_desc_area);
882 dma_free_coherent(NULL, mp->tx_desc_area_size,
883 mp->p_tx_desc_area, mp->tx_desc_dma);
888 memset((void *)mp->p_rx_desc_area, 0, size);
890 ether_init_rx_desc_ring(mp);
892 mv643xx_eth_rx_task(dev); /* Fill RX ring with skb's */
896 /* Interrupt Coalescing */
900 eth_port_set_rx_coal(port_num, 133000000, MV643XX_RX_COAL);
904 eth_port_set_tx_coal(port_num, 133000000, MV643XX_TX_COAL);
906 netif_start_queue(dev);
911 static void mv643xx_eth_free_tx_rings(struct net_device *dev)
913 struct mv643xx_private *mp = netdev_priv(dev);
914 unsigned int port_num = mp->port_num;
918 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num), 0x0000ff00);
920 /* Free outstanding skb's on TX rings */
921 for (curr = 0; mp->tx_ring_skbs && curr < mp->tx_ring_size; curr++) {
922 if (mp->tx_skb[curr]) {
923 dev_kfree_skb(mp->tx_skb[curr]);
927 if (mp->tx_ring_skbs)
928 printk("%s: Error on Tx descriptor free - could not free %d"
929 " descriptors\n", dev->name, mp->tx_ring_skbs);
932 if (mp->tx_sram_size)
933 iounmap(mp->p_tx_desc_area);
935 dma_free_coherent(NULL, mp->tx_desc_area_size,
936 mp->p_tx_desc_area, mp->tx_desc_dma);
939 static void mv643xx_eth_free_rx_rings(struct net_device *dev)
941 struct mv643xx_private *mp = netdev_priv(dev);
942 unsigned int port_num = mp->port_num;
946 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num), 0x0000ff00);
948 /* Free preallocated skb's on RX rings */
949 for (curr = 0; mp->rx_ring_skbs && curr < mp->rx_ring_size; curr++) {
950 if (mp->rx_skb[curr]) {
951 dev_kfree_skb(mp->rx_skb[curr]);
956 if (mp->rx_ring_skbs)
958 "%s: Error in freeing Rx Ring. %d skb's still"
959 " stuck in RX Ring - ignoring them\n", dev->name,
962 if (mp->rx_sram_size)
963 iounmap(mp->p_rx_desc_area);
965 dma_free_coherent(NULL, mp->rx_desc_area_size,
966 mp->p_rx_desc_area, mp->rx_desc_dma);
972 * This function is used when closing the network device.
973 * It updates the hardware,
974 * release all memory that holds buffers and descriptors and release the IRQ.
975 * Input : a pointer to the device structure
976 * Output : zero if success , nonzero if fails
979 /* Helper function for mv643xx_eth_stop */
981 static int mv643xx_eth_real_stop(struct net_device *dev)
983 struct mv643xx_private *mp = netdev_priv(dev);
984 unsigned int port_num = mp->port_num;
986 netif_carrier_off(dev);
987 netif_stop_queue(dev);
989 mv643xx_eth_free_tx_rings(dev);
990 mv643xx_eth_free_rx_rings(dev);
992 eth_port_reset(mp->port_num);
994 /* Disable ethernet port interrupts */
995 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
996 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
998 /* Mask RX buffer and TX end interrupt */
999 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num), 0);
1001 /* Mask phy and link status changes interrupts */
1002 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num), 0);
1007 static int mv643xx_eth_stop(struct net_device *dev)
1009 struct mv643xx_private *mp = netdev_priv(dev);
1011 spin_lock_irq(&mp->lock);
1013 mv643xx_eth_real_stop(dev);
1015 free_irq(dev->irq, dev);
1016 spin_unlock_irq(&mp->lock);
1022 static void mv643xx_tx(struct net_device *dev)
1024 struct mv643xx_private *mp = netdev_priv(dev);
1025 struct pkt_info pkt_info;
1027 while (eth_tx_return_desc(mp, &pkt_info) == ETH_OK) {
1028 if (pkt_info.cmd_sts & ETH_TX_FIRST_DESC)
1029 dma_unmap_single(NULL, pkt_info.buf_ptr,
1033 dma_unmap_page(NULL, pkt_info.buf_ptr,
1037 if (pkt_info.return_info)
1038 dev_kfree_skb_irq(pkt_info.return_info);
1041 if (netif_queue_stopped(dev) &&
1042 mp->tx_ring_size > mp->tx_ring_skbs + MAX_DESCS_PER_SKB)
1043 netif_wake_queue(dev);
1049 * This function is used in case of NAPI
1051 static int mv643xx_poll(struct net_device *dev, int *budget)
1053 struct mv643xx_private *mp = netdev_priv(dev);
1054 int done = 1, orig_budget, work_done;
1055 unsigned int port_num = mp->port_num;
1056 unsigned long flags;
1058 #ifdef MV643XX_TX_FAST_REFILL
1059 if (++mp->tx_clean_threshold > 5) {
1060 spin_lock_irqsave(&mp->lock, flags);
1062 mp->tx_clean_threshold = 0;
1063 spin_unlock_irqrestore(&mp->lock, flags);
1067 if ((mv_read(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num)))
1068 != (u32) mp->rx_used_desc_q) {
1069 orig_budget = *budget;
1070 if (orig_budget > dev->quota)
1071 orig_budget = dev->quota;
1072 work_done = mv643xx_eth_receive_queue(dev, orig_budget);
1073 mp->rx_task.func(dev);
1074 *budget -= work_done;
1075 dev->quota -= work_done;
1076 if (work_done >= orig_budget)
1081 spin_lock_irqsave(&mp->lock, flags);
1082 __netif_rx_complete(dev);
1083 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num), 0);
1084 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
1085 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
1086 INT_CAUSE_UNMASK_ALL);
1087 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
1088 INT_CAUSE_UNMASK_ALL_EXT);
1089 spin_unlock_irqrestore(&mp->lock, flags);
1092 return done ? 0 : 1;
1096 /* Hardware can't handle unaligned fragments smaller than 9 bytes.
1097 * This helper function detects that case.
1100 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1105 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1106 fragp = &skb_shinfo(skb)->frags[frag];
1107 if (fragp->size <= 8 && fragp->page_offset & 0x7)
1116 * mv643xx_eth_start_xmit
1118 * This function is queues a packet in the Tx descriptor for
1121 * Input : skb - a pointer to socket buffer
1122 * dev - a pointer to the required port
1124 * Output : zero upon success
1126 static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev)
1128 struct mv643xx_private *mp = netdev_priv(dev);
1129 struct net_device_stats *stats = &mp->stats;
1130 ETH_FUNC_RET_STATUS status;
1131 unsigned long flags;
1132 struct pkt_info pkt_info;
1134 if (netif_queue_stopped(dev)) {
1136 "%s: Tried sending packet when interface is stopped\n",
1141 /* This is a hard error, log it. */
1142 if ((mp->tx_ring_size - mp->tx_ring_skbs) <=
1143 (skb_shinfo(skb)->nr_frags + 1)) {
1144 netif_stop_queue(dev);
1146 "%s: Bug in mv643xx_eth - Trying to transmit when"
1147 " queue full !\n", dev->name);
1151 /* Paranoid check - this shouldn't happen */
1153 stats->tx_dropped++;
1154 printk(KERN_ERR "mv64320_eth paranoid check failed\n");
1158 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1159 if (has_tiny_unaligned_frags(skb)) {
1160 if ((skb_linearize(skb, GFP_ATOMIC) != 0)) {
1161 stats->tx_dropped++;
1162 printk(KERN_DEBUG "%s: failed to linearize tiny "
1163 "unaligned fragment\n", dev->name);
1168 spin_lock_irqsave(&mp->lock, flags);
1170 if (!skb_shinfo(skb)->nr_frags) {
1171 if (skb->ip_summed != CHECKSUM_HW) {
1172 /* Errata BTS #50, IHL must be 5 if no HW checksum */
1173 pkt_info.cmd_sts = ETH_TX_ENABLE_INTERRUPT |
1176 5 << ETH_TX_IHL_SHIFT;
1177 pkt_info.l4i_chk = 0;
1180 pkt_info.cmd_sts = ETH_TX_ENABLE_INTERRUPT |
1183 ETH_GEN_TCP_UDP_CHECKSUM |
1184 ETH_GEN_IP_V_4_CHECKSUM |
1185 skb->nh.iph->ihl << ETH_TX_IHL_SHIFT;
1186 /* CPU already calculated pseudo header checksum. */
1187 if (skb->nh.iph->protocol == IPPROTO_UDP) {
1188 pkt_info.cmd_sts |= ETH_UDP_FRAME;
1189 pkt_info.l4i_chk = skb->h.uh->check;
1190 } else if (skb->nh.iph->protocol == IPPROTO_TCP)
1191 pkt_info.l4i_chk = skb->h.th->check;
1194 "%s: chksum proto != TCP or UDP\n",
1196 spin_unlock_irqrestore(&mp->lock, flags);
1200 pkt_info.byte_cnt = skb->len;
1201 pkt_info.buf_ptr = dma_map_single(NULL, skb->data, skb->len,
1203 pkt_info.return_info = skb;
1204 status = eth_port_send(mp, &pkt_info);
1205 if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL))
1206 printk(KERN_ERR "%s: Error on transmitting packet\n",
1208 stats->tx_bytes += pkt_info.byte_cnt;
1212 /* first frag which is skb header */
1213 pkt_info.byte_cnt = skb_headlen(skb);
1214 pkt_info.buf_ptr = dma_map_single(NULL, skb->data,
1217 pkt_info.l4i_chk = 0;
1218 pkt_info.return_info = 0;
1220 if (skb->ip_summed != CHECKSUM_HW)
1221 /* Errata BTS #50, IHL must be 5 if no HW checksum */
1222 pkt_info.cmd_sts = ETH_TX_FIRST_DESC |
1223 5 << ETH_TX_IHL_SHIFT;
1225 pkt_info.cmd_sts = ETH_TX_FIRST_DESC |
1226 ETH_GEN_TCP_UDP_CHECKSUM |
1227 ETH_GEN_IP_V_4_CHECKSUM |
1228 skb->nh.iph->ihl << ETH_TX_IHL_SHIFT;
1229 /* CPU already calculated pseudo header checksum. */
1230 if (skb->nh.iph->protocol == IPPROTO_UDP) {
1231 pkt_info.cmd_sts |= ETH_UDP_FRAME;
1232 pkt_info.l4i_chk = skb->h.uh->check;
1233 } else if (skb->nh.iph->protocol == IPPROTO_TCP)
1234 pkt_info.l4i_chk = skb->h.th->check;
1237 "%s: chksum proto != TCP or UDP\n",
1239 spin_unlock_irqrestore(&mp->lock, flags);
1244 status = eth_port_send(mp, &pkt_info);
1245 if (status != ETH_OK) {
1246 if ((status == ETH_ERROR))
1248 "%s: Error on transmitting packet\n",
1250 if (status == ETH_QUEUE_FULL)
1251 printk("Error on Queue Full \n");
1252 if (status == ETH_QUEUE_LAST_RESOURCE)
1253 printk("Tx resource error \n");
1255 stats->tx_bytes += pkt_info.byte_cnt;
1257 /* Check for the remaining frags */
1258 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1259 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
1260 pkt_info.l4i_chk = 0x0000;
1261 pkt_info.cmd_sts = 0x00000000;
1263 /* Last Frag enables interrupt and frees the skb */
1264 if (frag == (skb_shinfo(skb)->nr_frags - 1)) {
1265 pkt_info.cmd_sts |= ETH_TX_ENABLE_INTERRUPT |
1267 pkt_info.return_info = skb;
1269 pkt_info.return_info = 0;
1271 pkt_info.l4i_chk = 0;
1272 pkt_info.byte_cnt = this_frag->size;
1274 pkt_info.buf_ptr = dma_map_page(NULL, this_frag->page,
1275 this_frag->page_offset,
1279 status = eth_port_send(mp, &pkt_info);
1281 if (status != ETH_OK) {
1282 if ((status == ETH_ERROR))
1283 printk(KERN_ERR "%s: Error on "
1284 "transmitting packet\n",
1287 if (status == ETH_QUEUE_LAST_RESOURCE)
1288 printk("Tx resource error \n");
1290 if (status == ETH_QUEUE_FULL)
1291 printk("Queue is full \n");
1293 stats->tx_bytes += pkt_info.byte_cnt;
1297 spin_lock_irqsave(&mp->lock, flags);
1299 pkt_info.cmd_sts = ETH_TX_ENABLE_INTERRUPT | ETH_TX_FIRST_DESC |
1301 pkt_info.l4i_chk = 0;
1302 pkt_info.byte_cnt = skb->len;
1303 pkt_info.buf_ptr = dma_map_single(NULL, skb->data, skb->len,
1305 pkt_info.return_info = skb;
1306 status = eth_port_send(mp, &pkt_info);
1307 if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL))
1308 printk(KERN_ERR "%s: Error on transmitting packet\n",
1310 stats->tx_bytes += pkt_info.byte_cnt;
1313 /* Check if TX queue can handle another skb. If not, then
1314 * signal higher layers to stop requesting TX
1316 if (mp->tx_ring_size <= (mp->tx_ring_skbs + MAX_DESCS_PER_SKB))
1318 * Stop getting skb's from upper layers.
1319 * Getting skb's from upper layers will be enabled again after
1320 * packets are released.
1322 netif_stop_queue(dev);
1324 /* Update statistics and start of transmittion time */
1325 stats->tx_packets++;
1326 dev->trans_start = jiffies;
1328 spin_unlock_irqrestore(&mp->lock, flags);
1330 return 0; /* success */
1334 * mv643xx_eth_get_stats
1336 * Returns a pointer to the interface statistics.
1338 * Input : dev - a pointer to the required interface
1340 * Output : a pointer to the interface's statistics
1343 static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1345 struct mv643xx_private *mp = netdev_priv(dev);
1350 #ifdef CONFIG_NET_POLL_CONTROLLER
1351 static inline void mv643xx_enable_irq(struct mv643xx_private *mp)
1353 int port_num = mp->port_num;
1354 unsigned long flags;
1356 spin_lock_irqsave(&mp->lock, flags);
1357 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
1358 INT_CAUSE_UNMASK_ALL);
1359 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
1360 INT_CAUSE_UNMASK_ALL_EXT);
1361 spin_unlock_irqrestore(&mp->lock, flags);
1364 static inline void mv643xx_disable_irq(struct mv643xx_private *mp)
1366 int port_num = mp->port_num;
1367 unsigned long flags;
1369 spin_lock_irqsave(&mp->lock, flags);
1370 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num),
1371 INT_CAUSE_MASK_ALL);
1372 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num),
1373 INT_CAUSE_MASK_ALL_EXT);
1374 spin_unlock_irqrestore(&mp->lock, flags);
1377 static void mv643xx_netpoll(struct net_device *netdev)
1379 struct mv643xx_private *mp = netdev_priv(netdev);
1381 mv643xx_disable_irq(mp);
1382 mv643xx_eth_int_handler(netdev->irq, netdev, NULL);
1383 mv643xx_enable_irq(mp);
1390 * First function called after registering the network device.
1391 * It's purpose is to initialize the device as an ethernet device,
1392 * fill the ethernet device structure with pointers * to functions,
1393 * and set the MAC address of the interface
1395 * Input : struct device *
1396 * Output : -ENOMEM if failed , 0 if success
1398 static int mv643xx_eth_probe(struct platform_device *pdev)
1400 struct mv643xx_eth_platform_data *pd;
1401 int port_num = pdev->id;
1402 struct mv643xx_private *mp;
1403 struct net_device *dev;
1405 struct resource *res;
1408 dev = alloc_etherdev(sizeof(struct mv643xx_private));
1412 platform_set_drvdata(pdev, dev);
1414 mp = netdev_priv(dev);
1416 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1418 dev->irq = res->start;
1420 mp->port_num = port_num;
1422 dev->open = mv643xx_eth_open;
1423 dev->stop = mv643xx_eth_stop;
1424 dev->hard_start_xmit = mv643xx_eth_start_xmit;
1425 dev->get_stats = mv643xx_eth_get_stats;
1426 dev->set_mac_address = mv643xx_eth_set_mac_address;
1427 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
1429 /* No need to Tx Timeout */
1430 dev->tx_timeout = mv643xx_eth_tx_timeout;
1432 dev->poll = mv643xx_poll;
1436 #ifdef CONFIG_NET_POLL_CONTROLLER
1437 dev->poll_controller = mv643xx_netpoll;
1440 dev->watchdog_timeo = 2 * HZ;
1441 dev->tx_queue_len = mp->tx_ring_size;
1443 dev->change_mtu = mv643xx_eth_change_mtu;
1444 SET_ETHTOOL_OPS(dev, &mv643xx_ethtool_ops);
1446 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1447 #ifdef MAX_SKB_FRAGS
1449 * Zero copy can only work if we use Discovery II memory. Else, we will
1450 * have to map the buffers to ISA memory which is only 16 MB
1452 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_HW_CSUM;
1456 /* Configure the timeout task */
1457 INIT_WORK(&mp->tx_timeout_task,
1458 (void (*)(void *))mv643xx_eth_tx_timeout_task, dev);
1460 spin_lock_init(&mp->lock);
1462 /* set default config values */
1463 eth_port_uc_addr_get(dev, dev->dev_addr);
1464 mp->port_config = MV643XX_ETH_PORT_CONFIG_DEFAULT_VALUE;
1465 mp->port_config_extend = MV643XX_ETH_PORT_CONFIG_EXTEND_DEFAULT_VALUE;
1466 mp->port_sdma_config = MV643XX_ETH_PORT_SDMA_CONFIG_DEFAULT_VALUE;
1467 mp->port_serial_control = MV643XX_ETH_PORT_SERIAL_CONTROL_DEFAULT_VALUE;
1468 mp->rx_ring_size = MV643XX_ETH_PORT_DEFAULT_RECEIVE_QUEUE_SIZE;
1469 mp->tx_ring_size = MV643XX_ETH_PORT_DEFAULT_TRANSMIT_QUEUE_SIZE;
1471 pd = pdev->dev.platform_data;
1473 if (pd->mac_addr != NULL)
1474 memcpy(dev->dev_addr, pd->mac_addr, 6);
1476 if (pd->phy_addr || pd->force_phy_addr)
1477 ethernet_phy_set(port_num, pd->phy_addr);
1479 if (pd->port_config || pd->force_port_config)
1480 mp->port_config = pd->port_config;
1482 if (pd->port_config_extend || pd->force_port_config_extend)
1483 mp->port_config_extend = pd->port_config_extend;
1485 if (pd->port_sdma_config || pd->force_port_sdma_config)
1486 mp->port_sdma_config = pd->port_sdma_config;
1488 if (pd->port_serial_control || pd->force_port_serial_control)
1489 mp->port_serial_control = pd->port_serial_control;
1491 if (pd->rx_queue_size)
1492 mp->rx_ring_size = pd->rx_queue_size;
1494 if (pd->tx_queue_size)
1495 mp->tx_ring_size = pd->tx_queue_size;
1497 if (pd->tx_sram_size) {
1498 mp->tx_sram_size = pd->tx_sram_size;
1499 mp->tx_sram_addr = pd->tx_sram_addr;
1502 if (pd->rx_sram_size) {
1503 mp->rx_sram_size = pd->rx_sram_size;
1504 mp->rx_sram_addr = pd->rx_sram_addr;
1508 err = ethernet_phy_detect(port_num);
1510 pr_debug("MV643xx ethernet port %d: "
1511 "No PHY detected at addr %d\n",
1512 port_num, ethernet_phy_get(port_num));
1516 err = register_netdev(dev);
1522 "%s: port %d with MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
1523 dev->name, port_num, p[0], p[1], p[2], p[3], p[4], p[5]);
1525 if (dev->features & NETIF_F_SG)
1526 printk(KERN_NOTICE "%s: Scatter Gather Enabled\n", dev->name);
1528 if (dev->features & NETIF_F_IP_CSUM)
1529 printk(KERN_NOTICE "%s: TX TCP/IP Checksumming Supported\n",
1532 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1533 printk(KERN_NOTICE "%s: RX TCP/UDP Checksum Offload ON \n", dev->name);
1537 printk(KERN_NOTICE "%s: TX and RX Interrupt Coalescing ON \n",
1542 printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name);
1545 if (mp->tx_sram_size > 0)
1546 printk(KERN_NOTICE "%s: Using SRAM\n", dev->name);
1556 static int mv643xx_eth_remove(struct platform_device *pdev)
1558 struct net_device *dev = platform_get_drvdata(pdev);
1560 unregister_netdev(dev);
1561 flush_scheduled_work();
1564 platform_set_drvdata(pdev, NULL);
1568 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
1570 struct resource *res;
1572 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
1574 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1578 mv643xx_eth_shared_base = ioremap(res->start,
1579 MV643XX_ETH_SHARED_REGS_SIZE);
1580 if (mv643xx_eth_shared_base == NULL)
1587 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
1589 iounmap(mv643xx_eth_shared_base);
1590 mv643xx_eth_shared_base = NULL;
1595 static struct platform_driver mv643xx_eth_driver = {
1596 .probe = mv643xx_eth_probe,
1597 .remove = mv643xx_eth_remove,
1599 .name = MV643XX_ETH_NAME,
1603 static struct platform_driver mv643xx_eth_shared_driver = {
1604 .probe = mv643xx_eth_shared_probe,
1605 .remove = mv643xx_eth_shared_remove,
1607 .name = MV643XX_ETH_SHARED_NAME,
1612 * mv643xx_init_module
1614 * Registers the network drivers into the Linux kernel
1620 static int __init mv643xx_init_module(void)
1624 rc = platform_driver_register(&mv643xx_eth_shared_driver);
1626 rc = platform_driver_register(&mv643xx_eth_driver);
1628 platform_driver_unregister(&mv643xx_eth_shared_driver);
1634 * mv643xx_cleanup_module
1636 * Registers the network drivers into the Linux kernel
1642 static void __exit mv643xx_cleanup_module(void)
1644 platform_driver_unregister(&mv643xx_eth_driver);
1645 platform_driver_unregister(&mv643xx_eth_shared_driver);
1648 module_init(mv643xx_init_module);
1649 module_exit(mv643xx_cleanup_module);
1651 MODULE_LICENSE("GPL");
1652 MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani"
1653 " and Dale Farnsworth");
1654 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
1657 * The second part is the low level driver of the gigE ethernet ports.
1661 * Marvell's Gigabit Ethernet controller low level driver
1664 * This file introduce low level API to Marvell's Gigabit Ethernet
1665 * controller. This Gigabit Ethernet Controller driver API controls
1666 * 1) Operations (i.e. port init, start, reset etc').
1667 * 2) Data flow (i.e. port send, receive etc').
1668 * Each Gigabit Ethernet port is controlled via
1669 * struct mv643xx_private.
1670 * This struct includes user configuration information as well as
1671 * driver internal data needed for its operations.
1673 * Supported Features:
1674 * - This low level driver is OS independent. Allocating memory for
1675 * the descriptor rings and buffers are not within the scope of
1677 * - The user is free from Rx/Tx queue managing.
1678 * - This low level driver introduce functionality API that enable
1679 * the to operate Marvell's Gigabit Ethernet Controller in a
1681 * - Simple Gigabit Ethernet port operation API.
1682 * - Simple Gigabit Ethernet port data flow API.
1683 * - Data flow and operation API support per queue functionality.
1684 * - Support cached descriptors for better performance.
1685 * - Enable access to all four DRAM banks and internal SRAM memory
1687 * - PHY access and control API.
1688 * - Port control register configuration API.
1689 * - Full control over Unicast and Multicast MAC configurations.
1693 * Initialization phase
1694 * This phase complete the initialization of the the
1695 * mv643xx_private struct.
1696 * User information regarding port configuration has to be set
1697 * prior to calling the port initialization routine.
1699 * In this phase any port Tx/Rx activity is halted, MIB counters
1700 * are cleared, PHY address is set according to user parameter and
1701 * access to DRAM and internal SRAM memory spaces.
1703 * Driver ring initialization
1704 * Allocating memory for the descriptor rings and buffers is not
1705 * within the scope of this driver. Thus, the user is required to
1706 * allocate memory for the descriptors ring and buffers. Those
1707 * memory parameters are used by the Rx and Tx ring initialization
1708 * routines in order to curve the descriptor linked list in a form
1710 * Note: Pay special attention to alignment issues when using
1711 * cached descriptors/buffers. In this phase the driver store
1712 * information in the mv643xx_private struct regarding each queue
1716 * This phase prepares the Ethernet port for Rx and Tx activity.
1717 * It uses the information stored in the mv643xx_private struct to
1718 * initialize the various port registers.
1721 * All packet references to/from the driver are done using
1723 * This struct is a unified struct used with Rx and Tx operations.
1724 * This way the user is not required to be familiar with neither
1725 * Tx nor Rx descriptors structures.
1726 * The driver's descriptors rings are management by indexes.
1727 * Those indexes controls the ring resources and used to indicate
1728 * a SW resource error:
1730 * This index points to the current available resource for use. For
1731 * example in Rx process this index will point to the descriptor
1732 * that will be passed to the user upon calling the receive
1733 * routine. In Tx process, this index will point to the descriptor
1734 * that will be assigned with the user packet info and transmitted.
1736 * This index points to the descriptor that need to restore its
1737 * resources. For example in Rx process, using the Rx buffer return
1738 * API will attach the buffer returned in packet info to the
1739 * descriptor pointed by 'used'. In Tx process, using the Tx
1740 * descriptor return will merely return the user packet info with
1741 * the command status of the transmitted buffer pointed by the
1742 * 'used' index. Nevertheless, it is essential to use this routine
1743 * to update the 'used' index.
1745 * This index supports Tx Scatter-Gather. It points to the first
1746 * descriptor of a packet assembled of multiple buffers. For
1747 * example when in middle of Such packet we have a Tx resource
1748 * error the 'curr' index get the value of 'first' to indicate
1749 * that the ring returned to its state before trying to transmit
1752 * Receive operation:
1753 * The eth_port_receive API set the packet information struct,
1754 * passed by the caller, with received information from the
1755 * 'current' SDMA descriptor.
1756 * It is the user responsibility to return this resource back
1757 * to the Rx descriptor ring to enable the reuse of this source.
1758 * Return Rx resource is done using the eth_rx_return_buff API.
1760 * Transmit operation:
1761 * The eth_port_send API supports Scatter-Gather which enables to
1762 * send a packet spanned over multiple buffers. This means that
1763 * for each packet info structure given by the user and put into
1764 * the Tx descriptors ring, will be transmitted only if the 'LAST'
1765 * bit will be set in the packet info command status field. This
1766 * API also consider restriction regarding buffer alignments and
1768 * The user must return a Tx resource after ensuring the buffer
1769 * has been transmitted to enable the Tx ring indexes to update.
1772 * This device is on-board. No jumper diagram is necessary.
1774 * EXTERNAL INTERFACE
1776 * Prior to calling the initialization routine eth_port_init() the user
1777 * must set the following fields under mv643xx_private struct:
1778 * port_num User Ethernet port number.
1779 * port_mac_addr[6] User defined port MAC address.
1780 * port_config User port configuration value.
1781 * port_config_extend User port config extend value.
1782 * port_sdma_config User port SDMA config value.
1783 * port_serial_control User port serial control value.
1785 * This driver data flow is done using the struct pkt_info which
1786 * is a unified struct for Rx and Tx operations:
1788 * byte_cnt Tx/Rx descriptor buffer byte count.
1789 * l4i_chk CPU provided TCP Checksum. For Tx operation
1791 * cmd_sts Tx/Rx descriptor command status.
1792 * buf_ptr Tx/Rx descriptor buffer pointer.
1793 * return_info Tx/Rx user resource return information.
1797 /* SDMA command macros */
1798 #define ETH_ENABLE_TX_QUEUE(eth_port) \
1799 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), 1)
1804 static int ethernet_phy_get(unsigned int eth_port_num);
1805 static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);
1807 /* Ethernet Port routines */
1808 static int eth_port_uc_addr(unsigned int eth_port_num, unsigned char uc_nibble,
1812 * eth_port_init - Initialize the Ethernet port driver
1815 * This function prepares the ethernet port to start its activity:
1816 * 1) Completes the ethernet port driver struct initialization toward port
1818 * 2) Resets the device to a quiescent state in case of warm reboot.
1819 * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
1820 * 4) Clean MAC tables. The reset status of those tables is unknown.
1821 * 5) Set PHY address.
1822 * Note: Call this routine prior to eth_port_start routine and after
1823 * setting user values in the user fields of Ethernet port control
1827 * struct mv643xx_private *mp Ethernet port control struct
1835 static void eth_port_init(struct mv643xx_private *mp)
1837 mp->port_rx_queue_command = 0;
1838 mp->port_tx_queue_command = 0;
1840 mp->rx_resource_err = 0;
1841 mp->tx_resource_err = 0;
1843 eth_port_reset(mp->port_num);
1845 eth_port_init_mac_tables(mp->port_num);
1847 ethernet_phy_reset(mp->port_num);
1851 * eth_port_start - Start the Ethernet port activity.
1854 * This routine prepares the Ethernet port for Rx and Tx activity:
1855 * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
1856 * has been initialized a descriptor's ring (using
1857 * ether_init_tx_desc_ring for Tx and ether_init_rx_desc_ring for Rx)
1858 * 2. Initialize and enable the Ethernet configuration port by writing to
1859 * the port's configuration and command registers.
1860 * 3. Initialize and enable the SDMA by writing to the SDMA's
1861 * configuration and command registers. After completing these steps,
1862 * the ethernet port SDMA can starts to perform Rx and Tx activities.
1864 * Note: Each Rx and Tx queue descriptor's list must be initialized prior
1865 * to calling this function (use ether_init_tx_desc_ring for Tx queues
1866 * and ether_init_rx_desc_ring for Rx queues).
1869 * struct mv643xx_private *mp Ethernet port control struct
1872 * Ethernet port is ready to receive and transmit.
1877 static void eth_port_start(struct mv643xx_private *mp)
1879 unsigned int port_num = mp->port_num;
1880 int tx_curr_desc, rx_curr_desc;
1882 /* Assignment of Tx CTRP of given queue */
1883 tx_curr_desc = mp->tx_curr_desc_q;
1884 mv_write(MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port_num),
1885 (u32)((struct eth_tx_desc *)mp->tx_desc_dma + tx_curr_desc));
1887 /* Assignment of Rx CRDP of given queue */
1888 rx_curr_desc = mp->rx_curr_desc_q;
1889 mv_write(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num),
1890 (u32)((struct eth_rx_desc *)mp->rx_desc_dma + rx_curr_desc));
1892 /* Add the assigned Ethernet address to the port's address table */
1893 eth_port_uc_addr_set(port_num, mp->port_mac_addr);
1895 /* Assign port configuration and command. */
1896 mv_write(MV643XX_ETH_PORT_CONFIG_REG(port_num), mp->port_config);
1898 mv_write(MV643XX_ETH_PORT_CONFIG_EXTEND_REG(port_num),
1899 mp->port_config_extend);
1902 /* Increase the Rx side buffer size if supporting GigE */
1903 if (mp->port_serial_control & MV643XX_ETH_SET_GMII_SPEED_TO_1000)
1904 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
1905 (mp->port_serial_control & 0xfff1ffff) | (0x5 << 17));
1907 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
1908 mp->port_serial_control);
1910 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num),
1911 mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num)) |
1912 MV643XX_ETH_SERIAL_PORT_ENABLE);
1914 /* Assign port SDMA configuration */
1915 mv_write(MV643XX_ETH_SDMA_CONFIG_REG(port_num),
1916 mp->port_sdma_config);
1918 /* Enable port Rx. */
1919 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num),
1920 mp->port_rx_queue_command);
1922 /* Disable port bandwidth limits by clearing MTU register */
1923 mv_write(MV643XX_ETH_MAXIMUM_TRANSMIT_UNIT(port_num), 0);
1927 * eth_port_uc_addr_set - This function Set the port Unicast address.
1930 * This function Set the port Ethernet MAC address.
1933 * unsigned int eth_port_num Port number.
1934 * char * p_addr Address to be set
1937 * Set MAC address low and high registers. also calls eth_port_uc_addr()
1938 * To set the unicast table with the proper information.
1944 static void eth_port_uc_addr_set(unsigned int eth_port_num,
1945 unsigned char *p_addr)
1950 mac_l = (p_addr[4] << 8) | (p_addr[5]);
1951 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
1954 mv_write(MV643XX_ETH_MAC_ADDR_LOW(eth_port_num), mac_l);
1955 mv_write(MV643XX_ETH_MAC_ADDR_HIGH(eth_port_num), mac_h);
1957 /* Accept frames of this address */
1958 eth_port_uc_addr(eth_port_num, p_addr[5], ACCEPT_MAC_ADDR);
1964 * eth_port_uc_addr_get - This function retrieves the port Unicast address
1965 * (MAC address) from the ethernet hw registers.
1968 * This function retrieves the port Ethernet MAC address.
1971 * unsigned int eth_port_num Port number.
1972 * char *MacAddr pointer where the MAC address is stored
1975 * Copy the MAC address to the location pointed to by MacAddr
1981 static void eth_port_uc_addr_get(struct net_device *dev, unsigned char *p_addr)
1983 struct mv643xx_private *mp = netdev_priv(dev);
1987 mac_h = mv_read(MV643XX_ETH_MAC_ADDR_HIGH(mp->port_num));
1988 mac_l = mv_read(MV643XX_ETH_MAC_ADDR_LOW(mp->port_num));
1990 p_addr[0] = (mac_h >> 24) & 0xff;
1991 p_addr[1] = (mac_h >> 16) & 0xff;
1992 p_addr[2] = (mac_h >> 8) & 0xff;
1993 p_addr[3] = mac_h & 0xff;
1994 p_addr[4] = (mac_l >> 8) & 0xff;
1995 p_addr[5] = mac_l & 0xff;
1999 * eth_port_uc_addr - This function Set the port unicast address table
2002 * This function locates the proper entry in the Unicast table for the
2003 * specified MAC nibble and sets its properties according to function
2007 * unsigned int eth_port_num Port number.
2008 * unsigned char uc_nibble Unicast MAC Address last nibble.
2009 * int option 0 = Add, 1 = remove address.
2012 * This function add/removes MAC addresses from the port unicast address
2016 * true is output succeeded.
2017 * false if option parameter is invalid.
2020 static int eth_port_uc_addr(unsigned int eth_port_num, unsigned char uc_nibble,
2023 unsigned int unicast_reg;
2024 unsigned int tbl_offset;
2025 unsigned int reg_offset;
2027 /* Locate the Unicast table entry */
2028 uc_nibble = (0xf & uc_nibble);
2029 tbl_offset = (uc_nibble / 4) * 4; /* Register offset from unicast table base */
2030 reg_offset = uc_nibble % 4; /* Entry offset within the above register */
2033 case REJECT_MAC_ADDR:
2034 /* Clear accepts frame bit at given unicast DA table entry */
2035 unicast_reg = mv_read((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2036 (eth_port_num) + tbl_offset));
2038 unicast_reg &= (0x0E << (8 * reg_offset));
2040 mv_write((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2041 (eth_port_num) + tbl_offset), unicast_reg);
2044 case ACCEPT_MAC_ADDR:
2045 /* Set accepts frame bit at unicast DA filter table entry */
2047 mv_read((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2048 (eth_port_num) + tbl_offset));
2050 unicast_reg |= (0x01 << (8 * reg_offset));
2052 mv_write((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2053 (eth_port_num) + tbl_offset), unicast_reg);
2065 * The entries in each table are indexed by a hash of a packet's MAC
2066 * address. One bit in each entry determines whether the packet is
2067 * accepted. There are 4 entries (each 8 bits wide) in each register
2068 * of the table. The bits in each entry are defined as follows:
2069 * 0 Accept=1, Drop=0
2070 * 3-1 Queue (ETH_Q0=0)
2073 static void eth_port_set_filter_table_entry(int table, unsigned char entry)
2075 unsigned int table_reg;
2076 unsigned int tbl_offset;
2077 unsigned int reg_offset;
2079 tbl_offset = (entry / 4) * 4; /* Register offset of DA table entry */
2080 reg_offset = entry % 4; /* Entry offset within the register */
2082 /* Set "accepts frame bit" at specified table entry */
2083 table_reg = mv_read(table + tbl_offset);
2084 table_reg |= 0x01 << (8 * reg_offset);
2085 mv_write(table + tbl_offset, table_reg);
2089 * eth_port_mc_addr - Multicast address settings.
2091 * The MV device supports multicast using two tables:
2092 * 1) Special Multicast Table for MAC addresses of the form
2093 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_FF).
2094 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
2095 * Table entries in the DA-Filter table.
2096 * 2) Other Multicast Table for multicast of another type. A CRC-8bit
2097 * is used as an index to the Other Multicast Table entries in the
2098 * DA-Filter table. This function calculates the CRC-8bit value.
2099 * In either case, eth_port_set_filter_table_entry() is then called
2100 * to set to set the actual table entry.
2102 static void eth_port_mc_addr(unsigned int eth_port_num, unsigned char *p_addr)
2106 unsigned char crc_result = 0;
2112 if ((p_addr[0] == 0x01) && (p_addr[1] == 0x00) &&
2113 (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) {
2114 table = MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2116 eth_port_set_filter_table_entry(table, p_addr[5]);
2120 /* Calculate CRC-8 out of the given address */
2121 mac_h = (p_addr[0] << 8) | (p_addr[1]);
2122 mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
2123 (p_addr[4] << 8) | (p_addr[5] << 0);
2125 for (i = 0; i < 32; i++)
2126 mac_array[i] = (mac_l >> i) & 0x1;
2127 for (i = 32; i < 48; i++)
2128 mac_array[i] = (mac_h >> (i - 32)) & 0x1;
2130 crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ mac_array[39] ^
2131 mac_array[35] ^ mac_array[34] ^ mac_array[31] ^ mac_array[30] ^
2132 mac_array[28] ^ mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
2133 mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ mac_array[12] ^
2134 mac_array[8] ^ mac_array[7] ^ mac_array[6] ^ mac_array[0];
2136 crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
2137 mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ mac_array[34] ^
2138 mac_array[32] ^ mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
2139 mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ mac_array[21] ^
2140 mac_array[20] ^ mac_array[18] ^ mac_array[17] ^ mac_array[16] ^
2141 mac_array[15] ^ mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
2142 mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ mac_array[0];
2144 crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ mac_array[43] ^
2145 mac_array[42] ^ mac_array[39] ^ mac_array[37] ^ mac_array[34] ^
2146 mac_array[33] ^ mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
2147 mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ mac_array[15] ^
2148 mac_array[13] ^ mac_array[12] ^ mac_array[10] ^ mac_array[8] ^
2149 mac_array[6] ^ mac_array[2] ^ mac_array[1] ^ mac_array[0];
2151 crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
2152 mac_array[40] ^ mac_array[38] ^ mac_array[35] ^ mac_array[34] ^
2153 mac_array[30] ^ mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
2154 mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
2155 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[7] ^
2156 mac_array[3] ^ mac_array[2] ^ mac_array[1];
2158 crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[41] ^
2159 mac_array[39] ^ mac_array[36] ^ mac_array[35] ^ mac_array[31] ^
2160 mac_array[30] ^ mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
2161 mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ mac_array[14] ^
2162 mac_array[12] ^ mac_array[10] ^ mac_array[8] ^ mac_array[4] ^
2163 mac_array[3] ^ mac_array[2];
2165 crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ mac_array[42] ^
2166 mac_array[40] ^ mac_array[37] ^ mac_array[36] ^ mac_array[32] ^
2167 mac_array[31] ^ mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
2168 mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ mac_array[15] ^
2169 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[5] ^
2170 mac_array[4] ^ mac_array[3];
2172 crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ mac_array[41] ^
2173 mac_array[38] ^ mac_array[37] ^ mac_array[33] ^ mac_array[32] ^
2174 mac_array[29] ^ mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
2175 mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ mac_array[14] ^
2176 mac_array[12] ^ mac_array[10] ^ mac_array[6] ^ mac_array[5] ^
2179 crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ mac_array[39] ^
2180 mac_array[38] ^ mac_array[34] ^ mac_array[33] ^ mac_array[30] ^
2181 mac_array[29] ^ mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
2182 mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ mac_array[13] ^
2183 mac_array[11] ^ mac_array[7] ^ mac_array[6] ^ mac_array[5];
2185 for (i = 0; i < 8; i++)
2186 crc_result = crc_result | (crc[i] << i);
2188 table = MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num);
2189 eth_port_set_filter_table_entry(table, crc_result);
2193 * Set the entire multicast list based on dev->mc_list.
2195 static void eth_port_set_multicast_list(struct net_device *dev)
2198 struct dev_mc_list *mc_list;
2201 struct mv643xx_private *mp = netdev_priv(dev);
2202 unsigned int eth_port_num = mp->port_num;
2204 /* If the device is in promiscuous mode or in all multicast mode,
2205 * we will fully populate both multicast tables with accept.
2206 * This is guaranteed to yield a match on all multicast addresses...
2208 if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) {
2209 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2210 /* Set all entries in DA filter special multicast
2212 * Set for ETH_Q0 for now
2214 * 0 Accept=1, Drop=0
2215 * 3-1 Queue ETH_Q0=0
2218 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
2220 /* Set all entries in DA filter other multicast
2222 * Set for ETH_Q0 for now
2224 * 0 Accept=1, Drop=0
2225 * 3-1 Queue ETH_Q0=0
2228 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
2233 /* We will clear out multicast tables every time we get the list.
2234 * Then add the entire new list...
2236 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2237 /* Clear DA filter special multicast table (Ex_dFSMT) */
2238 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2239 (eth_port_num) + table_index, 0);
2241 /* Clear DA filter other multicast table (Ex_dFOMT) */
2242 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE
2243 (eth_port_num) + table_index, 0);
2246 /* Get pointer to net_device multicast list and add each one... */
2247 for (i = 0, mc_list = dev->mc_list;
2248 (i < 256) && (mc_list != NULL) && (i < dev->mc_count);
2249 i++, mc_list = mc_list->next)
2250 if (mc_list->dmi_addrlen == 6)
2251 eth_port_mc_addr(eth_port_num, mc_list->dmi_addr);
2255 * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
2258 * Go through all the DA filter tables (Unicast, Special Multicast &
2259 * Other Multicast) and set each entry to 0.
2262 * unsigned int eth_port_num Ethernet Port number.
2265 * Multicast and Unicast packets are rejected.
2270 static void eth_port_init_mac_tables(unsigned int eth_port_num)
2274 /* Clear DA filter unicast table (Ex_dFUT) */
2275 for (table_index = 0; table_index <= 0xC; table_index += 4)
2276 mv_write((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2277 (eth_port_num) + table_index), 0);
2279 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2280 /* Clear DA filter special multicast table (Ex_dFSMT) */
2281 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2282 (eth_port_num) + table_index, 0);
2283 /* Clear DA filter other multicast table (Ex_dFOMT) */
2284 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE
2285 (eth_port_num) + table_index, 0);
2290 * eth_clear_mib_counters - Clear all MIB counters
2293 * This function clears all MIB counters of a specific ethernet port.
2294 * A read from the MIB counter will reset the counter.
2297 * unsigned int eth_port_num Ethernet Port number.
2300 * After reading all MIB counters, the counters resets.
2303 * MIB counter value.
2306 static void eth_clear_mib_counters(unsigned int eth_port_num)
2310 /* Perform dummy reads from MIB counters */
2311 for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
2313 mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(eth_port_num) + i);
2316 static inline u32 read_mib(struct mv643xx_private *mp, int offset)
2318 return mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(mp->port_num) + offset);
2321 static void eth_update_mib_counters(struct mv643xx_private *mp)
2323 struct mv643xx_mib_counters *p = &mp->mib_counters;
2326 p->good_octets_received +=
2327 read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
2328 p->good_octets_received +=
2329 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32;
2331 for (offset = ETH_MIB_BAD_OCTETS_RECEIVED;
2332 offset <= ETH_MIB_FRAMES_1024_TO_MAX_OCTETS;
2334 *(u32 *)((char *)p + offset) = read_mib(mp, offset);
2336 p->good_octets_sent += read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_LOW);
2337 p->good_octets_sent +=
2338 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_HIGH) << 32;
2340 for (offset = ETH_MIB_GOOD_FRAMES_SENT;
2341 offset <= ETH_MIB_LATE_COLLISION;
2343 *(u32 *)((char *)p + offset) = read_mib(mp, offset);
2347 * ethernet_phy_detect - Detect whether a phy is present
2350 * This function tests whether there is a PHY present on
2351 * the specified port.
2354 * unsigned int eth_port_num Ethernet Port number.
2361 * -ENODEV on failure
2364 static int ethernet_phy_detect(unsigned int port_num)
2366 unsigned int phy_reg_data0;
2369 eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
2370 auto_neg = phy_reg_data0 & 0x1000;
2371 phy_reg_data0 ^= 0x1000; /* invert auto_neg */
2372 eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
2374 eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
2375 if ((phy_reg_data0 & 0x1000) == auto_neg)
2376 return -ENODEV; /* change didn't take */
2378 phy_reg_data0 ^= 0x1000;
2379 eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
2384 * ethernet_phy_get - Get the ethernet port PHY address.
2387 * This routine returns the given ethernet port PHY address.
2390 * unsigned int eth_port_num Ethernet Port number.
2399 static int ethernet_phy_get(unsigned int eth_port_num)
2401 unsigned int reg_data;
2403 reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG);
2405 return ((reg_data >> (5 * eth_port_num)) & 0x1f);
2409 * ethernet_phy_set - Set the ethernet port PHY address.
2412 * This routine sets the given ethernet port PHY address.
2415 * unsigned int eth_port_num Ethernet Port number.
2416 * int phy_addr PHY address.
2425 static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr)
2428 int addr_shift = 5 * eth_port_num;
2430 reg_data = mv_read(MV643XX_ETH_PHY_ADDR_REG);
2431 reg_data &= ~(0x1f << addr_shift);
2432 reg_data |= (phy_addr & 0x1f) << addr_shift;
2433 mv_write(MV643XX_ETH_PHY_ADDR_REG, reg_data);
2437 * ethernet_phy_reset - Reset Ethernet port PHY.
2440 * This routine utilizes the SMI interface to reset the ethernet port PHY.
2443 * unsigned int eth_port_num Ethernet Port number.
2452 static void ethernet_phy_reset(unsigned int eth_port_num)
2454 unsigned int phy_reg_data;
2457 eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data);
2458 phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
2459 eth_port_write_smi_reg(eth_port_num, 0, phy_reg_data);
2463 * eth_port_reset - Reset Ethernet port
2466 * This routine resets the chip by aborting any SDMA engine activity and
2467 * clearing the MIB counters. The Receiver and the Transmit unit are in
2468 * idle state after this command is performed and the port is disabled.
2471 * unsigned int eth_port_num Ethernet Port number.
2474 * Channel activity is halted.
2480 static void eth_port_reset(unsigned int port_num)
2482 unsigned int reg_data;
2484 /* Stop Tx port activity. Check port Tx activity. */
2485 reg_data = mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num));
2487 if (reg_data & 0xFF) {
2488 /* Issue stop command for active channels only */
2489 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num),
2492 /* Wait for all Tx activity to terminate. */
2493 /* Check port cause register that all Tx queues are stopped */
2494 while (mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num))
2499 /* Stop Rx port activity. Check port Rx activity. */
2500 reg_data = mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num));
2502 if (reg_data & 0xFF) {
2503 /* Issue stop command for active channels only */
2504 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num),
2507 /* Wait for all Rx activity to terminate. */
2508 /* Check port cause register that all Rx queues are stopped */
2509 while (mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num))
2514 /* Clear all MIB counters */
2515 eth_clear_mib_counters(port_num);
2517 /* Reset the Enable bit in the Configuration Register */
2518 reg_data = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
2519 reg_data &= ~MV643XX_ETH_SERIAL_PORT_ENABLE;
2520 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num), reg_data);
2524 static int eth_port_autoneg_supported(unsigned int eth_port_num)
2526 unsigned int phy_reg_data0;
2528 eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data0);
2530 return phy_reg_data0 & 0x1000;
2533 static int eth_port_link_is_up(unsigned int eth_port_num)
2535 unsigned int phy_reg_data1;
2537 eth_port_read_smi_reg(eth_port_num, 1, &phy_reg_data1);
2539 if (eth_port_autoneg_supported(eth_port_num)) {
2540 if (phy_reg_data1 & 0x20) /* auto-neg complete */
2542 } else if (phy_reg_data1 & 0x4) /* link up */
2549 * eth_port_read_smi_reg - Read PHY registers
2552 * This routine utilize the SMI interface to interact with the PHY in
2553 * order to perform PHY register read.
2556 * unsigned int port_num Ethernet Port number.
2557 * unsigned int phy_reg PHY register address offset.
2558 * unsigned int *value Register value buffer.
2561 * Write the value of a specified PHY register into given buffer.
2564 * false if the PHY is busy or read data is not in valid state.
2568 static void eth_port_read_smi_reg(unsigned int port_num,
2569 unsigned int phy_reg, unsigned int *value)
2571 int phy_addr = ethernet_phy_get(port_num);
2572 unsigned long flags;
2575 /* the SMI register is a shared resource */
2576 spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);
2578 /* wait for the SMI register to become available */
2579 for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) {
2580 if (i == PHY_WAIT_ITERATIONS) {
2581 printk("mv643xx PHY busy timeout, port %d\n", port_num);
2584 udelay(PHY_WAIT_MICRO_SECONDS);
2587 mv_write(MV643XX_ETH_SMI_REG,
2588 (phy_addr << 16) | (phy_reg << 21) | ETH_SMI_OPCODE_READ);
2590 /* now wait for the data to be valid */
2591 for (i = 0; !(mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_READ_VALID); i++) {
2592 if (i == PHY_WAIT_ITERATIONS) {
2593 printk("mv643xx PHY read timeout, port %d\n", port_num);
2596 udelay(PHY_WAIT_MICRO_SECONDS);
2599 *value = mv_read(MV643XX_ETH_SMI_REG) & 0xffff;
2601 spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
2605 * eth_port_write_smi_reg - Write to PHY registers
2608 * This routine utilize the SMI interface to interact with the PHY in
2609 * order to perform writes to PHY registers.
2612 * unsigned int eth_port_num Ethernet Port number.
2613 * unsigned int phy_reg PHY register address offset.
2614 * unsigned int value Register value.
2617 * Write the given value to the specified PHY register.
2620 * false if the PHY is busy.
2624 static void eth_port_write_smi_reg(unsigned int eth_port_num,
2625 unsigned int phy_reg, unsigned int value)
2629 unsigned long flags;
2631 phy_addr = ethernet_phy_get(eth_port_num);
2633 /* the SMI register is a shared resource */
2634 spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);
2636 /* wait for the SMI register to become available */
2637 for (i = 0; mv_read(MV643XX_ETH_SMI_REG) & ETH_SMI_BUSY; i++) {
2638 if (i == PHY_WAIT_ITERATIONS) {
2639 printk("mv643xx PHY busy timeout, port %d\n",
2643 udelay(PHY_WAIT_MICRO_SECONDS);
2646 mv_write(MV643XX_ETH_SMI_REG, (phy_addr << 16) | (phy_reg << 21) |
2647 ETH_SMI_OPCODE_WRITE | (value & 0xffff));
2649 spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
2653 * eth_port_send - Send an Ethernet packet
2656 * This routine send a given packet described by p_pktinfo parameter. It
2657 * supports transmitting of a packet spaned over multiple buffers. The
2658 * routine updates 'curr' and 'first' indexes according to the packet
2659 * segment passed to the routine. In case the packet segment is first,
2660 * the 'first' index is update. In any case, the 'curr' index is updated.
2661 * If the routine get into Tx resource error it assigns 'curr' index as
2662 * 'first'. This way the function can abort Tx process of multiple
2663 * descriptors per packet.
2666 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2667 * struct pkt_info *p_pkt_info User packet buffer.
2670 * Tx ring 'curr' and 'first' indexes are updated.
2673 * ETH_QUEUE_FULL in case of Tx resource error.
2674 * ETH_ERROR in case the routine can not access Tx desc ring.
2675 * ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource.
2679 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
2681 * Modified to include the first descriptor pointer in case of SG
2683 static ETH_FUNC_RET_STATUS eth_port_send(struct mv643xx_private *mp,
2684 struct pkt_info *p_pkt_info)
2686 int tx_desc_curr, tx_desc_used, tx_first_desc, tx_next_desc;
2687 struct eth_tx_desc *current_descriptor;
2688 struct eth_tx_desc *first_descriptor;
2691 /* Do not process Tx ring in case of Tx ring resource error */
2692 if (mp->tx_resource_err)
2693 return ETH_QUEUE_FULL;
2696 * The hardware requires that each buffer that is <= 8 bytes
2697 * in length must be aligned on an 8 byte boundary.
2699 if (p_pkt_info->byte_cnt <= 8 && p_pkt_info->buf_ptr & 0x7) {
2701 "mv643xx_eth port %d: packet size <= 8 problem\n",
2707 BUG_ON(mp->tx_ring_skbs > mp->tx_ring_size);
2709 /* Get the Tx Desc ring indexes */
2710 tx_desc_curr = mp->tx_curr_desc_q;
2711 tx_desc_used = mp->tx_used_desc_q;
2713 current_descriptor = &mp->p_tx_desc_area[tx_desc_curr];
2715 tx_next_desc = (tx_desc_curr + 1) % mp->tx_ring_size;
2717 current_descriptor->buf_ptr = p_pkt_info->buf_ptr;
2718 current_descriptor->byte_cnt = p_pkt_info->byte_cnt;
2719 current_descriptor->l4i_chk = p_pkt_info->l4i_chk;
2720 mp->tx_skb[tx_desc_curr] = p_pkt_info->return_info;
2722 command = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC |
2723 ETH_BUFFER_OWNED_BY_DMA;
2724 if (command & ETH_TX_FIRST_DESC) {
2725 tx_first_desc = tx_desc_curr;
2726 mp->tx_first_desc_q = tx_first_desc;
2727 first_descriptor = current_descriptor;
2728 mp->tx_first_command = command;
2730 tx_first_desc = mp->tx_first_desc_q;
2731 first_descriptor = &mp->p_tx_desc_area[tx_first_desc];
2732 BUG_ON(first_descriptor == NULL);
2733 current_descriptor->cmd_sts = command;
2736 if (command & ETH_TX_LAST_DESC) {
2738 first_descriptor->cmd_sts = mp->tx_first_command;
2741 ETH_ENABLE_TX_QUEUE(mp->port_num);
2744 * Finish Tx packet. Update first desc in case of Tx resource
2746 tx_first_desc = tx_next_desc;
2747 mp->tx_first_desc_q = tx_first_desc;
2750 /* Check for ring index overlap in the Tx desc ring */
2751 if (tx_next_desc == tx_desc_used) {
2752 mp->tx_resource_err = 1;
2753 mp->tx_curr_desc_q = tx_first_desc;
2755 return ETH_QUEUE_LAST_RESOURCE;
2758 mp->tx_curr_desc_q = tx_next_desc;
2763 static ETH_FUNC_RET_STATUS eth_port_send(struct mv643xx_private *mp,
2764 struct pkt_info *p_pkt_info)
2768 struct eth_tx_desc *current_descriptor;
2769 unsigned int command_status;
2771 /* Do not process Tx ring in case of Tx ring resource error */
2772 if (mp->tx_resource_err)
2773 return ETH_QUEUE_FULL;
2776 BUG_ON(mp->tx_ring_skbs > mp->tx_ring_size);
2778 /* Get the Tx Desc ring indexes */
2779 tx_desc_curr = mp->tx_curr_desc_q;
2780 tx_desc_used = mp->tx_used_desc_q;
2781 current_descriptor = &mp->p_tx_desc_area[tx_desc_curr];
2783 command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC;
2784 current_descriptor->buf_ptr = p_pkt_info->buf_ptr;
2785 current_descriptor->byte_cnt = p_pkt_info->byte_cnt;
2786 mp->tx_skb[tx_desc_curr] = p_pkt_info->return_info;
2788 /* Set last desc with DMA ownership and interrupt enable. */
2790 current_descriptor->cmd_sts = command_status |
2791 ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT;
2794 ETH_ENABLE_TX_QUEUE(mp->port_num);
2796 /* Finish Tx packet. Update first desc in case of Tx resource error */
2797 tx_desc_curr = (tx_desc_curr + 1) % mp->tx_ring_size;
2799 /* Update the current descriptor */
2800 mp->tx_curr_desc_q = tx_desc_curr;
2802 /* Check for ring index overlap in the Tx desc ring */
2803 if (tx_desc_curr == tx_desc_used) {
2804 mp->tx_resource_err = 1;
2805 return ETH_QUEUE_LAST_RESOURCE;
2813 * eth_tx_return_desc - Free all used Tx descriptors
2816 * This routine returns the transmitted packet information to the caller.
2817 * It uses the 'first' index to support Tx desc return in case a transmit
2818 * of a packet spanned over multiple buffer still in process.
2819 * In case the Tx queue was in "resource error" condition, where there are
2820 * no available Tx resources, the function resets the resource error flag.
2823 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2824 * struct pkt_info *p_pkt_info User packet buffer.
2827 * Tx ring 'first' and 'used' indexes are updated.
2830 * ETH_ERROR in case the routine can not access Tx desc ring.
2831 * ETH_RETRY in case there is transmission in process.
2832 * ETH_END_OF_JOB if the routine has nothing to release.
2836 static ETH_FUNC_RET_STATUS eth_tx_return_desc(struct mv643xx_private *mp,
2837 struct pkt_info *p_pkt_info)
2840 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
2841 int tx_busy_desc = mp->tx_first_desc_q;
2843 int tx_busy_desc = mp->tx_curr_desc_q;
2845 struct eth_tx_desc *p_tx_desc_used;
2846 unsigned int command_status;
2848 /* Get the Tx Desc ring indexes */
2849 tx_desc_used = mp->tx_used_desc_q;
2851 p_tx_desc_used = &mp->p_tx_desc_area[tx_desc_used];
2854 if (p_tx_desc_used == NULL)
2857 /* Stop release. About to overlap the current available Tx descriptor */
2858 if (tx_desc_used == tx_busy_desc && !mp->tx_resource_err)
2859 return ETH_END_OF_JOB;
2861 command_status = p_tx_desc_used->cmd_sts;
2863 /* Still transmitting... */
2864 if (command_status & (ETH_BUFFER_OWNED_BY_DMA))
2867 /* Pass the packet information to the caller */
2868 p_pkt_info->cmd_sts = command_status;
2869 p_pkt_info->return_info = mp->tx_skb[tx_desc_used];
2870 p_pkt_info->buf_ptr = p_tx_desc_used->buf_ptr;
2871 p_pkt_info->byte_cnt = p_tx_desc_used->byte_cnt;
2872 mp->tx_skb[tx_desc_used] = NULL;
2874 /* Update the next descriptor to release. */
2875 mp->tx_used_desc_q = (tx_desc_used + 1) % mp->tx_ring_size;
2877 /* Any Tx return cancels the Tx resource error status */
2878 mp->tx_resource_err = 0;
2880 BUG_ON(mp->tx_ring_skbs == 0);
2887 * eth_port_receive - Get received information from Rx ring.
2890 * This routine returns the received data to the caller. There is no
2891 * data copying during routine operation. All information is returned
2892 * using pointer to packet information struct passed from the caller.
2893 * If the routine exhausts Rx ring resources then the resource error flag
2897 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2898 * struct pkt_info *p_pkt_info User packet buffer.
2901 * Rx ring current and used indexes are updated.
2904 * ETH_ERROR in case the routine can not access Rx desc ring.
2905 * ETH_QUEUE_FULL if Rx ring resources are exhausted.
2906 * ETH_END_OF_JOB if there is no received data.
2909 static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
2910 struct pkt_info *p_pkt_info)
2912 int rx_next_curr_desc, rx_curr_desc, rx_used_desc;
2913 volatile struct eth_rx_desc *p_rx_desc;
2914 unsigned int command_status;
2916 /* Do not process Rx ring in case of Rx ring resource error */
2917 if (mp->rx_resource_err)
2918 return ETH_QUEUE_FULL;
2920 /* Get the Rx Desc ring 'curr and 'used' indexes */
2921 rx_curr_desc = mp->rx_curr_desc_q;
2922 rx_used_desc = mp->rx_used_desc_q;
2924 p_rx_desc = &mp->p_rx_desc_area[rx_curr_desc];
2926 /* The following parameters are used to save readings from memory */
2927 command_status = p_rx_desc->cmd_sts;
2930 /* Nothing to receive... */
2931 if (command_status & (ETH_BUFFER_OWNED_BY_DMA))
2932 return ETH_END_OF_JOB;
2934 p_pkt_info->byte_cnt = (p_rx_desc->byte_cnt) - RX_BUF_OFFSET;
2935 p_pkt_info->cmd_sts = command_status;
2936 p_pkt_info->buf_ptr = (p_rx_desc->buf_ptr) + RX_BUF_OFFSET;
2937 p_pkt_info->return_info = mp->rx_skb[rx_curr_desc];
2938 p_pkt_info->l4i_chk = p_rx_desc->buf_size;
2940 /* Clean the return info field to indicate that the packet has been */
2941 /* moved to the upper layers */
2942 mp->rx_skb[rx_curr_desc] = NULL;
2944 /* Update current index in data structure */
2945 rx_next_curr_desc = (rx_curr_desc + 1) % mp->rx_ring_size;
2946 mp->rx_curr_desc_q = rx_next_curr_desc;
2948 /* Rx descriptors exhausted. Set the Rx ring resource error flag */
2949 if (rx_next_curr_desc == rx_used_desc)
2950 mp->rx_resource_err = 1;
2956 * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
2959 * This routine returns a Rx buffer back to the Rx ring. It retrieves the
2960 * next 'used' descriptor and attached the returned buffer to it.
2961 * In case the Rx ring was in "resource error" condition, where there are
2962 * no available Rx resources, the function resets the resource error flag.
2965 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2966 * struct pkt_info *p_pkt_info Information on returned buffer.
2969 * New available Rx resource in Rx descriptor ring.
2972 * ETH_ERROR in case the routine can not access Rx desc ring.
2975 static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
2976 struct pkt_info *p_pkt_info)
2978 int used_rx_desc; /* Where to return Rx resource */
2979 volatile struct eth_rx_desc *p_used_rx_desc;
2981 /* Get 'used' Rx descriptor */
2982 used_rx_desc = mp->rx_used_desc_q;
2983 p_used_rx_desc = &mp->p_rx_desc_area[used_rx_desc];
2985 p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
2986 p_used_rx_desc->buf_size = p_pkt_info->byte_cnt;
2987 mp->rx_skb[used_rx_desc] = p_pkt_info->return_info;
2989 /* Flush the write pipe */
2991 /* Return the descriptor to DMA ownership */
2993 p_used_rx_desc->cmd_sts =
2994 ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
2997 /* Move the used descriptor pointer to the next descriptor */
2998 mp->rx_used_desc_q = (used_rx_desc + 1) % mp->rx_ring_size;
3000 /* Any Rx return cancels the Rx resource error status */
3001 mp->rx_resource_err = 0;
3006 /************* Begin ethtool support *************************/
3008 struct mv643xx_stats {
3009 char stat_string[ETH_GSTRING_LEN];
3014 #define MV643XX_STAT(m) sizeof(((struct mv643xx_private *)0)->m), \
3015 offsetof(struct mv643xx_private, m)
3017 static const struct mv643xx_stats mv643xx_gstrings_stats[] = {
3018 { "rx_packets", MV643XX_STAT(stats.rx_packets) },
3019 { "tx_packets", MV643XX_STAT(stats.tx_packets) },
3020 { "rx_bytes", MV643XX_STAT(stats.rx_bytes) },
3021 { "tx_bytes", MV643XX_STAT(stats.tx_bytes) },
3022 { "rx_errors", MV643XX_STAT(stats.rx_errors) },
3023 { "tx_errors", MV643XX_STAT(stats.tx_errors) },
3024 { "rx_dropped", MV643XX_STAT(stats.rx_dropped) },
3025 { "tx_dropped", MV643XX_STAT(stats.tx_dropped) },
3026 { "good_octets_received", MV643XX_STAT(mib_counters.good_octets_received) },
3027 { "bad_octets_received", MV643XX_STAT(mib_counters.bad_octets_received) },
3028 { "internal_mac_transmit_err", MV643XX_STAT(mib_counters.internal_mac_transmit_err) },
3029 { "good_frames_received", MV643XX_STAT(mib_counters.good_frames_received) },
3030 { "bad_frames_received", MV643XX_STAT(mib_counters.bad_frames_received) },
3031 { "broadcast_frames_received", MV643XX_STAT(mib_counters.broadcast_frames_received) },
3032 { "multicast_frames_received", MV643XX_STAT(mib_counters.multicast_frames_received) },
3033 { "frames_64_octets", MV643XX_STAT(mib_counters.frames_64_octets) },
3034 { "frames_65_to_127_octets", MV643XX_STAT(mib_counters.frames_65_to_127_octets) },
3035 { "frames_128_to_255_octets", MV643XX_STAT(mib_counters.frames_128_to_255_octets) },
3036 { "frames_256_to_511_octets", MV643XX_STAT(mib_counters.frames_256_to_511_octets) },
3037 { "frames_512_to_1023_octets", MV643XX_STAT(mib_counters.frames_512_to_1023_octets) },
3038 { "frames_1024_to_max_octets", MV643XX_STAT(mib_counters.frames_1024_to_max_octets) },
3039 { "good_octets_sent", MV643XX_STAT(mib_counters.good_octets_sent) },
3040 { "good_frames_sent", MV643XX_STAT(mib_counters.good_frames_sent) },
3041 { "excessive_collision", MV643XX_STAT(mib_counters.excessive_collision) },
3042 { "multicast_frames_sent", MV643XX_STAT(mib_counters.multicast_frames_sent) },
3043 { "broadcast_frames_sent", MV643XX_STAT(mib_counters.broadcast_frames_sent) },
3044 { "unrec_mac_control_received", MV643XX_STAT(mib_counters.unrec_mac_control_received) },
3045 { "fc_sent", MV643XX_STAT(mib_counters.fc_sent) },
3046 { "good_fc_received", MV643XX_STAT(mib_counters.good_fc_received) },
3047 { "bad_fc_received", MV643XX_STAT(mib_counters.bad_fc_received) },
3048 { "undersize_received", MV643XX_STAT(mib_counters.undersize_received) },
3049 { "fragments_received", MV643XX_STAT(mib_counters.fragments_received) },
3050 { "oversize_received", MV643XX_STAT(mib_counters.oversize_received) },
3051 { "jabber_received", MV643XX_STAT(mib_counters.jabber_received) },
3052 { "mac_receive_error", MV643XX_STAT(mib_counters.mac_receive_error) },
3053 { "bad_crc_event", MV643XX_STAT(mib_counters.bad_crc_event) },
3054 { "collision", MV643XX_STAT(mib_counters.collision) },
3055 { "late_collision", MV643XX_STAT(mib_counters.late_collision) },
3058 #define MV643XX_STATS_LEN \
3059 sizeof(mv643xx_gstrings_stats) / sizeof(struct mv643xx_stats)
3062 mv643xx_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
3064 struct mv643xx_private *mp = netdev->priv;
3065 int port_num = mp->port_num;
3066 int autoneg = eth_port_autoneg_supported(port_num);
3069 int half_duplex = 0;
3070 int full_duplex = 0;
3076 u32 pcs = mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num));
3077 u32 psr = mv_read(MV643XX_ETH_PORT_STATUS_REG(port_num));
3079 mode_10_bit = psr & MV643XX_ETH_PORT_STATUS_MODE_10_BIT;
3082 ecmd->supported = SUPPORTED_10baseT_Half;
3084 ecmd->supported = (SUPPORTED_10baseT_Half |
3085 SUPPORTED_10baseT_Full |
3086 SUPPORTED_100baseT_Half |
3087 SUPPORTED_100baseT_Full |
3088 SUPPORTED_1000baseT_Full |
3089 (autoneg ? SUPPORTED_Autoneg : 0) |
3092 auto_duplex = !(pcs & MV643XX_ETH_DISABLE_AUTO_NEG_FOR_DUPLX);
3093 auto_speed = !(pcs & MV643XX_ETH_DISABLE_AUTO_NEG_SPEED_GMII);
3095 ecmd->advertising = ADVERTISED_TP;
3098 ecmd->advertising |= ADVERTISED_Autoneg;
3104 if (pcs & MV643XX_ETH_SET_FULL_DUPLEX_MODE)
3115 if (pcs & MV643XX_ETH_SET_GMII_SPEED_TO_1000)
3117 else if (pcs & MV643XX_ETH_SET_MII_SPEED_TO_100)
3123 if (speed_10 & half_duplex)
3124 ecmd->advertising |= ADVERTISED_10baseT_Half;
3125 if (speed_10 & full_duplex)
3126 ecmd->advertising |= ADVERTISED_10baseT_Full;
3127 if (speed_100 & half_duplex)
3128 ecmd->advertising |= ADVERTISED_100baseT_Half;
3129 if (speed_100 & full_duplex)
3130 ecmd->advertising |= ADVERTISED_100baseT_Full;
3132 ecmd->advertising |= ADVERTISED_1000baseT_Full;
3136 ecmd->port = PORT_TP;
3137 ecmd->phy_address = ethernet_phy_get(port_num);
3139 ecmd->transceiver = XCVR_EXTERNAL;
3141 if (netif_carrier_ok(netdev)) {
3143 ecmd->speed = SPEED_10;
3145 if (psr & MV643XX_ETH_PORT_STATUS_GMII_1000)
3146 ecmd->speed = SPEED_1000;
3147 else if (psr & MV643XX_ETH_PORT_STATUS_MII_100)
3148 ecmd->speed = SPEED_100;
3150 ecmd->speed = SPEED_10;
3153 if (psr & MV643XX_ETH_PORT_STATUS_FULL_DUPLEX)
3154 ecmd->duplex = DUPLEX_FULL;
3156 ecmd->duplex = DUPLEX_HALF;
3162 ecmd->autoneg = autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3167 mv643xx_get_drvinfo(struct net_device *netdev,
3168 struct ethtool_drvinfo *drvinfo)
3170 strncpy(drvinfo->driver, mv643xx_driver_name, 32);
3171 strncpy(drvinfo->version, mv643xx_driver_version, 32);
3172 strncpy(drvinfo->fw_version, "N/A", 32);
3173 strncpy(drvinfo->bus_info, "mv643xx", 32);
3174 drvinfo->n_stats = MV643XX_STATS_LEN;
3178 mv643xx_get_stats_count(struct net_device *netdev)
3180 return MV643XX_STATS_LEN;
3184 mv643xx_get_ethtool_stats(struct net_device *netdev,
3185 struct ethtool_stats *stats, uint64_t *data)
3187 struct mv643xx_private *mp = netdev->priv;
3190 eth_update_mib_counters(mp);
3192 for(i = 0; i < MV643XX_STATS_LEN; i++) {
3193 char *p = (char *)mp+mv643xx_gstrings_stats[i].stat_offset;
3194 data[i] = (mv643xx_gstrings_stats[i].sizeof_stat ==
3195 sizeof(uint64_t)) ? *(uint64_t *)p : *(uint32_t *)p;
3200 mv643xx_get_strings(struct net_device *netdev, uint32_t stringset, uint8_t *data)
3206 for (i=0; i < MV643XX_STATS_LEN; i++) {
3207 memcpy(data + i * ETH_GSTRING_LEN,
3208 mv643xx_gstrings_stats[i].stat_string,
3215 static struct ethtool_ops mv643xx_ethtool_ops = {
3216 .get_settings = mv643xx_get_settings,
3217 .get_drvinfo = mv643xx_get_drvinfo,
3218 .get_link = ethtool_op_get_link,
3219 .get_sg = ethtool_op_get_sg,
3220 .set_sg = ethtool_op_set_sg,
3221 .get_strings = mv643xx_get_strings,
3222 .get_stats_count = mv643xx_get_stats_count,
3223 .get_ethtool_stats = mv643xx_get_ethtool_stats,
3226 /************* End ethtool support *************************/