2 * Copyright (c) 2004 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/init.h>
36 #include <linux/errno.h>
38 #include <linux/mlx4/cmd.h>
44 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
46 struct mlx4_mpt_entry {
60 __be32 first_byte_offset;
61 } __attribute__((packed));
63 #define MLX4_MPT_FLAG_SW_OWNS (0xfUL << 28)
64 #define MLX4_MPT_FLAG_MIO (1 << 17)
65 #define MLX4_MPT_FLAG_BIND_ENABLE (1 << 15)
66 #define MLX4_MPT_FLAG_PHYSICAL (1 << 9)
67 #define MLX4_MPT_FLAG_REGION (1 << 8)
69 #define MLX4_MTT_FLAG_PRESENT 1
71 static u32 mlx4_buddy_alloc(struct mlx4_buddy *buddy, int order)
77 spin_lock(&buddy->lock);
79 for (o = order; o <= buddy->max_order; ++o) {
80 m = 1 << (buddy->max_order - o);
81 seg = find_first_bit(buddy->bits[o], m);
86 spin_unlock(&buddy->lock);
90 clear_bit(seg, buddy->bits[o]);
95 set_bit(seg ^ 1, buddy->bits[o]);
98 spin_unlock(&buddy->lock);
105 static void mlx4_buddy_free(struct mlx4_buddy *buddy, u32 seg, int order)
109 spin_lock(&buddy->lock);
111 while (test_bit(seg ^ 1, buddy->bits[order])) {
112 clear_bit(seg ^ 1, buddy->bits[order]);
117 set_bit(seg, buddy->bits[order]);
119 spin_unlock(&buddy->lock);
122 static int __devinit mlx4_buddy_init(struct mlx4_buddy *buddy, int max_order)
126 buddy->max_order = max_order;
127 spin_lock_init(&buddy->lock);
129 buddy->bits = kzalloc((buddy->max_order + 1) * sizeof (long *),
134 for (i = 0; i <= buddy->max_order; ++i) {
135 s = BITS_TO_LONGS(1 << (buddy->max_order - i));
136 buddy->bits[i] = kmalloc(s * sizeof (long), GFP_KERNEL);
139 bitmap_zero(buddy->bits[i], 1 << (buddy->max_order - i));
142 set_bit(0, buddy->bits[buddy->max_order]);
147 for (i = 0; i <= buddy->max_order; ++i)
148 kfree(buddy->bits[i]);
156 static void mlx4_buddy_cleanup(struct mlx4_buddy *buddy)
160 for (i = 0; i <= buddy->max_order; ++i)
161 kfree(buddy->bits[i]);
166 static u32 mlx4_alloc_mtt_range(struct mlx4_dev *dev, int order)
168 struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
171 seg = mlx4_buddy_alloc(&mr_table->mtt_buddy, order);
175 if (mlx4_table_get_range(dev, &mr_table->mtt_table, seg,
176 seg + (1 << order) - 1)) {
177 mlx4_buddy_free(&mr_table->mtt_buddy, seg, order);
184 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
185 struct mlx4_mtt *mtt)
191 mtt->page_shift = MLX4_ICM_PAGE_SHIFT;
194 mtt->page_shift = page_shift;
196 for (mtt->order = 0, i = MLX4_MTT_ENTRY_PER_SEG; i < npages; i <<= 1)
199 mtt->first_seg = mlx4_alloc_mtt_range(dev, mtt->order);
200 if (mtt->first_seg == -1)
205 EXPORT_SYMBOL_GPL(mlx4_mtt_init);
207 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt)
209 struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
214 mlx4_buddy_free(&mr_table->mtt_buddy, mtt->first_seg, mtt->order);
215 mlx4_table_put_range(dev, &mr_table->mtt_table, mtt->first_seg,
216 mtt->first_seg + (1 << mtt->order) - 1);
218 EXPORT_SYMBOL_GPL(mlx4_mtt_cleanup);
220 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt)
222 return (u64) mtt->first_seg * dev->caps.mtt_entry_sz;
224 EXPORT_SYMBOL_GPL(mlx4_mtt_addr);
226 static u32 hw_index_to_key(u32 ind)
228 return (ind >> 24) | (ind << 8);
231 static u32 key_to_hw_index(u32 key)
233 return (key << 24) | (key >> 8);
236 static int mlx4_SW2HW_MPT(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
239 return mlx4_cmd(dev, mailbox->dma, mpt_index, 0, MLX4_CMD_SW2HW_MPT,
240 MLX4_CMD_TIME_CLASS_B);
243 static int mlx4_HW2SW_MPT(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
246 return mlx4_cmd_box(dev, 0, mailbox ? mailbox->dma : 0, mpt_index,
247 !mailbox, MLX4_CMD_HW2SW_MPT, MLX4_CMD_TIME_CLASS_B);
250 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
251 int npages, int page_shift, struct mlx4_mr *mr)
253 struct mlx4_priv *priv = mlx4_priv(dev);
257 index = mlx4_bitmap_alloc(&priv->mr_table.mpt_bitmap);
266 mr->key = hw_index_to_key(index);
268 err = mlx4_mtt_init(dev, npages, page_shift, &mr->mtt);
270 mlx4_bitmap_free(&priv->mr_table.mpt_bitmap, index);
274 EXPORT_SYMBOL_GPL(mlx4_mr_alloc);
276 void mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr)
278 struct mlx4_priv *priv = mlx4_priv(dev);
282 err = mlx4_HW2SW_MPT(dev, NULL,
283 key_to_hw_index(mr->key) &
284 (dev->caps.num_mpts - 1));
286 mlx4_warn(dev, "HW2SW_MPT failed (%d)\n", err);
289 mlx4_mtt_cleanup(dev, &mr->mtt);
290 mlx4_bitmap_free(&priv->mr_table.mpt_bitmap, key_to_hw_index(mr->key));
292 EXPORT_SYMBOL_GPL(mlx4_mr_free);
294 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr)
296 struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
297 struct mlx4_cmd_mailbox *mailbox;
298 struct mlx4_mpt_entry *mpt_entry;
301 err = mlx4_table_get(dev, &mr_table->dmpt_table, key_to_hw_index(mr->key));
305 mailbox = mlx4_alloc_cmd_mailbox(dev);
306 if (IS_ERR(mailbox)) {
307 err = PTR_ERR(mailbox);
310 mpt_entry = mailbox->buf;
312 memset(mpt_entry, 0, sizeof *mpt_entry);
314 mpt_entry->flags = cpu_to_be32(MLX4_MPT_FLAG_SW_OWNS |
316 MLX4_MPT_FLAG_REGION |
319 mpt_entry->key = cpu_to_be32(key_to_hw_index(mr->key));
320 mpt_entry->pd = cpu_to_be32(mr->pd);
321 mpt_entry->start = cpu_to_be64(mr->iova);
322 mpt_entry->length = cpu_to_be64(mr->size);
323 mpt_entry->entity_size = cpu_to_be32(mr->mtt.page_shift);
324 if (mr->mtt.order < 0) {
325 mpt_entry->flags |= cpu_to_be32(MLX4_MPT_FLAG_PHYSICAL);
326 mpt_entry->mtt_seg = 0;
328 mpt_entry->mtt_seg = cpu_to_be64(mlx4_mtt_addr(dev, &mr->mtt));
330 err = mlx4_SW2HW_MPT(dev, mailbox,
331 key_to_hw_index(mr->key) & (dev->caps.num_mpts - 1));
333 mlx4_warn(dev, "SW2HW_MPT failed (%d)\n", err);
339 mlx4_free_cmd_mailbox(dev, mailbox);
344 mlx4_free_cmd_mailbox(dev, mailbox);
347 mlx4_table_put(dev, &mr_table->dmpt_table, key_to_hw_index(mr->key));
350 EXPORT_SYMBOL_GPL(mlx4_mr_enable);
352 static int mlx4_WRITE_MTT(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox,
355 return mlx4_cmd(dev, mailbox->dma, num_mtt, 0, MLX4_CMD_WRITE_MTT,
356 MLX4_CMD_TIME_CLASS_B);
359 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
360 int start_index, int npages, u64 *page_list)
362 struct mlx4_cmd_mailbox *mailbox;
370 mailbox = mlx4_alloc_cmd_mailbox(dev);
372 return PTR_ERR(mailbox);
374 mtt_entry = mailbox->buf;
377 mtt_entry[0] = cpu_to_be64(mlx4_mtt_addr(dev, mtt) + start_index * 8);
380 for (i = 0; i < npages && i < MLX4_MAILBOX_SIZE / 8 - 2; ++i)
381 mtt_entry[i + 2] = cpu_to_be64(page_list[i] |
382 MLX4_MTT_FLAG_PRESENT);
385 * If we have an odd number of entries to write, add
386 * one more dummy entry for firmware efficiency.
389 mtt_entry[i + 2] = 0;
391 err = mlx4_WRITE_MTT(dev, mailbox, (i + 1) & ~1);
401 mlx4_free_cmd_mailbox(dev, mailbox);
405 EXPORT_SYMBOL_GPL(mlx4_write_mtt);
407 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
408 struct mlx4_buf *buf)
414 page_list = kmalloc(buf->npages * sizeof *page_list, GFP_KERNEL);
418 for (i = 0; i < buf->npages; ++i)
420 page_list[i] = buf->u.direct.map + (i << buf->page_shift);
422 page_list[i] = buf->u.page_list[i].map;
424 err = mlx4_write_mtt(dev, mtt, 0, buf->npages, page_list);
429 EXPORT_SYMBOL_GPL(mlx4_buf_write_mtt);
431 int __devinit mlx4_init_mr_table(struct mlx4_dev *dev)
433 struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
436 err = mlx4_bitmap_init(&mr_table->mpt_bitmap, dev->caps.num_mpts,
437 ~0, dev->caps.reserved_mrws);
441 err = mlx4_buddy_init(&mr_table->mtt_buddy,
442 ilog2(dev->caps.num_mtt_segs));
446 if (dev->caps.reserved_mtts) {
447 if (mlx4_alloc_mtt_range(dev, ilog2(dev->caps.reserved_mtts)) == -1) {
448 mlx4_warn(dev, "MTT table of order %d is too small.\n",
449 mr_table->mtt_buddy.max_order);
451 goto err_reserve_mtts;
458 mlx4_buddy_cleanup(&mr_table->mtt_buddy);
461 mlx4_bitmap_cleanup(&mr_table->mpt_bitmap);
466 void mlx4_cleanup_mr_table(struct mlx4_dev *dev)
468 struct mlx4_mr_table *mr_table = &mlx4_priv(dev)->mr_table;
470 mlx4_buddy_cleanup(&mr_table->mtt_buddy);
471 mlx4_bitmap_cleanup(&mr_table->mpt_bitmap);