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   1 /*
   2  * Derived from arch/powerpc/kernel/iommu.c
   3  *
   4  * Copyright IBM Corporation, 2006-2007
   5  * Copyright (C) 2006  Jon Mason <jdmason@kudzu.us>
   6  *
   7  * Author: Jon Mason <jdmason@kudzu.us>
   8  * Author: Muli Ben-Yehuda <muli@il.ibm.com>
   9
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  23  */
  24
  25 #include <linux/kernel.h>
  26 #include <linux/init.h>
  27 #include <linux/types.h>
  28 #include <linux/slab.h>
  29 #include <linux/mm.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/string.h>
  32 #include <linux/dma-mapping.h>
  33 #include <linux/init.h>
  34 #include <linux/bitops.h>
  35 #include <linux/pci_ids.h>
  36 #include <linux/pci.h>
  37 #include <linux/delay.h>
  38 #include <asm/proto.h>
  39 #include <asm/calgary.h>
  40 #include <asm/tce.h>
  41 #include <asm/pci-direct.h>
  42 #include <asm/system.h>
  43 #include <asm/dma.h>
  44 #include <asm/rio.h>
  45
  46 #ifdef CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT
  47 int use_calgary __read_mostly = 1;
  48 #else
  49 int use_calgary __read_mostly = 0;
  50 #endif /* CONFIG_CALGARY_DEFAULT_ENABLED */
  51
  52 #define PCI_DEVICE_ID_IBM_CALGARY 0x02a1
  53 #define PCI_DEVICE_ID_IBM_CALIOC2 0x0308
  54
  55 /* we need these for register space address calculation */
  56 #define START_ADDRESS           0xfe000000
  57 #define CHASSIS_BASE            0
  58 #define ONE_BASED_CHASSIS_NUM   1
  59
  60 /* register offsets inside the host bridge space */
  61 #define CALGARY_CONFIG_REG      0x0108
  62 #define PHB_CSR_OFFSET          0x0110 /* Channel Status */
  63 #define PHB_PLSSR_OFFSET        0x0120
  64 #define PHB_CONFIG_RW_OFFSET    0x0160
  65 #define PHB_IOBASE_BAR_LOW      0x0170
  66 #define PHB_IOBASE_BAR_HIGH     0x0180
  67 #define PHB_MEM_1_LOW           0x0190
  68 #define PHB_MEM_1_HIGH          0x01A0
  69 #define PHB_IO_ADDR_SIZE        0x01B0
  70 #define PHB_MEM_1_SIZE          0x01C0
  71 #define PHB_MEM_ST_OFFSET       0x01D0
  72 #define PHB_AER_OFFSET          0x0200
  73 #define PHB_CONFIG_0_HIGH       0x0220
  74 #define PHB_CONFIG_0_LOW        0x0230
  75 #define PHB_CONFIG_0_END        0x0240
  76 #define PHB_MEM_2_LOW           0x02B0
  77 #define PHB_MEM_2_HIGH          0x02C0
  78 #define PHB_MEM_2_SIZE_HIGH     0x02D0
  79 #define PHB_MEM_2_SIZE_LOW      0x02E0
  80 #define PHB_DOSHOLE_OFFSET      0x08E0
  81
  82 /* CalIOC2 specific */
  83 #define PHB_SAVIOR_L2           0x0DB0
  84 #define PHB_PAGE_MIG_CTRL       0x0DA8
  85 #define PHB_PAGE_MIG_DEBUG      0x0DA0
  86 #define PHB_ROOT_COMPLEX_STATUS 0x0CB0
  87
  88 /* PHB_CONFIG_RW */
  89 #define PHB_TCE_ENABLE          0x20000000
  90 #define PHB_SLOT_DISABLE        0x1C000000
  91 #define PHB_DAC_DISABLE         0x01000000
  92 #define PHB_MEM2_ENABLE         0x00400000
  93 #define PHB_MCSR_ENABLE         0x00100000
  94 /* TAR (Table Address Register) */
  95 #define TAR_SW_BITS             0x0000ffffffff800fUL
  96 #define TAR_VALID               0x0000000000000008UL
  97 /* CSR (Channel/DMA Status Register) */
  98 #define CSR_AGENT_MASK          0xffe0ffff
  99 /* CCR (Calgary Configuration Register) */
 100 #define CCR_2SEC_TIMEOUT        0x000000000000000EUL
 101 /* PMCR/PMDR (Page Migration Control/Debug Registers */
 102 #define PMR_SOFTSTOP            0x80000000
 103 #define PMR_SOFTSTOPFAULT       0x40000000
 104 #define PMR_HARDSTOP            0x20000000
 105
 106 #define MAX_NUM_OF_PHBS         8 /* how many PHBs in total? */
 107 #define MAX_NUM_CHASSIS         8 /* max number of chassis */
 108 /* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */
 109 #define MAX_PHB_BUS_NUM         (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2)
 110 #define PHBS_PER_CALGARY        4
 111
 112 /* register offsets in Calgary's internal register space */
 113 static const unsigned long tar_offsets[] = {
 114         0x0580 /* TAR0 */,
 115         0x0588 /* TAR1 */,
 116         0x0590 /* TAR2 */,
 117         0x0598 /* TAR3 */
 118 };
 119
 120 static const unsigned long split_queue_offsets[] = {
 121         0x4870 /* SPLIT QUEUE 0 */,
 122         0x5870 /* SPLIT QUEUE 1 */,
 123         0x6870 /* SPLIT QUEUE 2 */,
 124         0x7870 /* SPLIT QUEUE 3 */
 125 };
 126
 127 static const unsigned long phb_offsets[] = {
 128         0x8000 /* PHB0 */,
 129         0x9000 /* PHB1 */,
 130         0xA000 /* PHB2 */,
 131         0xB000 /* PHB3 */
 132 };
 133
 134 /* PHB debug registers */
 135
 136 static const unsigned long phb_debug_offsets[] = {
 137         0x4000  /* PHB 0 DEBUG */,
 138         0x5000  /* PHB 1 DEBUG */,
 139         0x6000  /* PHB 2 DEBUG */,
 140         0x7000  /* PHB 3 DEBUG */
 141 };
 142
 143 /*
 144  * STUFF register for each debug PHB,
 145  * byte 1 = start bus number, byte 2 = end bus number
 146  */
 147
 148 #define PHB_DEBUG_STUFF_OFFSET  0x0020
 149
 150 #define EMERGENCY_PAGES 32 /* = 128KB */
 151
 152 unsigned int specified_table_size = TCE_TABLE_SIZE_UNSPECIFIED;
 153 static int translate_empty_slots __read_mostly = 0;
 154 static int calgary_detected __read_mostly = 0;
 155
 156 static struct rio_table_hdr     *rio_table_hdr __initdata;
 157 static struct scal_detail       *scal_devs[MAX_NUMNODES] __initdata;
 158 static struct rio_detail        *rio_devs[MAX_NUMNODES * 4] __initdata;
 159
 160 struct calgary_bus_info {
 161         void *tce_space;
 162         unsigned char translation_disabled;
 163         signed char phbid;
 164         void __iomem *bbar;
 165 };
 166
 167 static void calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
 168 static void calgary_tce_cache_blast(struct iommu_table *tbl);
 169 static void calgary_dump_error_regs(struct iommu_table *tbl);
 170 static void calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
 171 static void calioc2_tce_cache_blast(struct iommu_table *tbl);
 172 static void calioc2_dump_error_regs(struct iommu_table *tbl);
 173
 174 static struct cal_chipset_ops calgary_chip_ops = {
 175         .handle_quirks = calgary_handle_quirks,
 176         .tce_cache_blast = calgary_tce_cache_blast,
 177         .dump_error_regs = calgary_dump_error_regs
 178 };
 179
 180 static struct cal_chipset_ops calioc2_chip_ops = {
 181         .handle_quirks = calioc2_handle_quirks,
 182         .tce_cache_blast = calioc2_tce_cache_blast,
 183         .dump_error_regs = calioc2_dump_error_regs
 184 };
 185
 186 static struct calgary_bus_info bus_info[MAX_PHB_BUS_NUM] = { { NULL, 0, 0 }, };
 187
 188 /* enable this to stress test the chip's TCE cache */
 189 #ifdef CONFIG_IOMMU_DEBUG
 190 int debugging __read_mostly = 1;
 191
 192 static inline unsigned long verify_bit_range(unsigned long* bitmap,
 193         int expected, unsigned long start, unsigned long end)
 194 {
 195         unsigned long idx = start;
 196
 197         BUG_ON(start >= end);
 198
 199         while (idx < end) {
 200                 if (!!test_bit(idx, bitmap) != expected)
 201                         return idx;
 202                 ++idx;
 203         }
 204
 205         /* all bits have the expected value */
 206         return ~0UL;
 207 }
 208 #else /* debugging is disabled */
 209 int debugging __read_mostly = 0;
 210
 211 static inline unsigned long verify_bit_range(unsigned long* bitmap,
 212         int expected, unsigned long start, unsigned long end)
 213 {
 214         return ~0UL;
 215 }
 216
 217 #endif /* CONFIG_IOMMU_DEBUG */
 218
 219 static inline unsigned int num_dma_pages(unsigned long dma, unsigned int dmalen)
 220 {
 221         unsigned int npages;
 222
 223         npages = PAGE_ALIGN(dma + dmalen) - (dma & PAGE_MASK);
 224         npages >>= PAGE_SHIFT;
 225
 226         return npages;
 227 }
 228
 229 static inline int translate_phb(struct pci_dev* dev)
 230 {
 231         int disabled = bus_info[dev->bus->number].translation_disabled;
 232         return !disabled;
 233 }
 234
 235 static void iommu_range_reserve(struct iommu_table *tbl,
 236         unsigned long start_addr, unsigned int npages)
 237 {
 238         unsigned long index;
 239         unsigned long end;
 240         unsigned long badbit;
 241
 242         index = start_addr >> PAGE_SHIFT;
 243
 244         /* bail out if we're asked to reserve a region we don't cover */
 245         if (index >= tbl->it_size)
 246                 return;
 247
 248         end = index + npages;
 249         if (end > tbl->it_size) /* don't go off the table */
 250                 end = tbl->it_size;
 251
 252         badbit = verify_bit_range(tbl->it_map, 0, index, end);
 253         if (badbit != ~0UL) {
 254                 if (printk_ratelimit())
 255                         printk(KERN_ERR "Calgary: entry already allocated at "
 256                                "0x%lx tbl %p dma 0x%lx npages %u\n",
 257                                badbit, tbl, start_addr, npages);
 258         }
 259
 260         set_bit_string(tbl->it_map, index, npages);
 261 }
 262
 263 static unsigned long iommu_range_alloc(struct iommu_table *tbl,
 264         unsigned int npages)
 265 {
 266         unsigned long offset;
 267
 268         BUG_ON(npages == 0);
 269
 270         offset = find_next_zero_string(tbl->it_map, tbl->it_hint,
 271                                        tbl->it_size, npages);
 272         if (offset == ~0UL) {
 273                 tbl->chip_ops->tce_cache_blast(tbl);
 274                 offset = find_next_zero_string(tbl->it_map, 0,
 275                                                tbl->it_size, npages);
 276                 if (offset == ~0UL) {
 277                         printk(KERN_WARNING "Calgary: IOMMU full.\n");
 278                         if (panic_on_overflow)
 279                                 panic("Calgary: fix the allocator.\n");
 280                         else
 281                                 return bad_dma_address;
 282                 }
 283         }
 284
 285         set_bit_string(tbl->it_map, offset, npages);
 286         tbl->it_hint = offset + npages;
 287         BUG_ON(tbl->it_hint > tbl->it_size);
 288
 289         return offset;
 290 }
 291
 292 static dma_addr_t iommu_alloc(struct iommu_table *tbl, void *vaddr,
 293         unsigned int npages, int direction)
 294 {
 295         unsigned long entry, flags;
 296         dma_addr_t ret = bad_dma_address;
 297
 298         spin_lock_irqsave(&tbl->it_lock, flags);
 299
 300         entry = iommu_range_alloc(tbl, npages);
 301
 302         if (unlikely(entry == bad_dma_address))
 303                 goto error;
 304
 305         /* set the return dma address */
 306         ret = (entry << PAGE_SHIFT) | ((unsigned long)vaddr & ~PAGE_MASK);
 307
 308         /* put the TCEs in the HW table */
 309         tce_build(tbl, entry, npages, (unsigned long)vaddr & PAGE_MASK,
 310                   direction);
 311
 312         spin_unlock_irqrestore(&tbl->it_lock, flags);
 313
 314         return ret;
 315
 316 error:
 317         spin_unlock_irqrestore(&tbl->it_lock, flags);
 318         printk(KERN_WARNING "Calgary: failed to allocate %u pages in "
 319                "iommu %p\n", npages, tbl);
 320         return bad_dma_address;
 321 }
 322
 323 static void __iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
 324         unsigned int npages)
 325 {
 326         unsigned long entry;
 327         unsigned long badbit;
 328         unsigned long badend;
 329
 330         /* were we called with bad_dma_address? */
 331         badend = bad_dma_address + (EMERGENCY_PAGES * PAGE_SIZE);
 332         if (unlikely((dma_addr >= bad_dma_address) && (dma_addr < badend))) {
 333                 printk(KERN_ERR "Calgary: driver tried unmapping bad DMA "
 334                        "address 0x%Lx\n", dma_addr);
 335                 WARN_ON(1);
 336                 return;
 337         }
 338
 339         entry = dma_addr >> PAGE_SHIFT;
 340
 341         BUG_ON(entry + npages > tbl->it_size);
 342
 343         tce_free(tbl, entry, npages);
 344
 345         badbit = verify_bit_range(tbl->it_map, 1, entry, entry + npages);
 346         if (badbit != ~0UL) {
 347                 if (printk_ratelimit())
 348                         printk(KERN_ERR "Calgary: bit is off at 0x%lx "
 349                                "tbl %p dma 0x%Lx entry 0x%lx npages %u\n",
 350                                badbit, tbl, dma_addr, entry, npages);
 351         }
 352
 353         __clear_bit_string(tbl->it_map, entry, npages);
 354 }
 355
 356 static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
 357         unsigned int npages)
 358 {
 359         unsigned long flags;
 360
 361         spin_lock_irqsave(&tbl->it_lock, flags);
 362
 363         __iommu_free(tbl, dma_addr, npages);
 364
 365         spin_unlock_irqrestore(&tbl->it_lock, flags);
 366 }
 367
 368 static inline struct iommu_table *find_iommu_table(struct device *dev)
 369 {
 370         struct pci_dev *pdev;
 371         struct pci_bus *pbus;
 372         struct iommu_table *tbl;
 373
 374         pdev = to_pci_dev(dev);
 375
 376         /* is the device behind a bridge? */
 377         if (unlikely(pdev->bus->parent))
 378                 pbus = pdev->bus->parent;
 379         else
 380                 pbus = pdev->bus;
 381
 382         tbl = pbus->self->sysdata;
 383         BUG_ON(pdev->bus->parent && (tbl->it_busno != pdev->bus->parent->number));
 384
 385         return tbl;
 386 }
 387
 388 static void __calgary_unmap_sg(struct iommu_table *tbl,
 389         struct scatterlist *sglist, int nelems, int direction)
 390 {
 391         while (nelems--) {
 392                 unsigned int npages;
 393                 dma_addr_t dma = sglist->dma_address;
 394                 unsigned int dmalen = sglist->dma_length;
 395
 396                 if (dmalen == 0)
 397                         break;
 398
 399                 npages = num_dma_pages(dma, dmalen);
 400                 __iommu_free(tbl, dma, npages);
 401                 sglist++;
 402         }
 403 }
 404
 405 void calgary_unmap_sg(struct device *dev, struct scatterlist *sglist,
 406                       int nelems, int direction)
 407 {
 408         unsigned long flags;
 409         struct iommu_table *tbl = find_iommu_table(dev);
 410
 411         if (!translate_phb(to_pci_dev(dev)))
 412                 return;
 413
 414         spin_lock_irqsave(&tbl->it_lock, flags);
 415
 416         __calgary_unmap_sg(tbl, sglist, nelems, direction);
 417
 418         spin_unlock_irqrestore(&tbl->it_lock, flags);
 419 }
 420
 421 static int calgary_nontranslate_map_sg(struct device* dev,
 422         struct scatterlist *sg, int nelems, int direction)
 423 {
 424         int i;
 425
 426         for (i = 0; i < nelems; i++ ) {
 427                 struct scatterlist *s = &sg[i];
 428                 BUG_ON(!s->page);
 429                 s->dma_address = virt_to_bus(page_address(s->page) +s->offset);
 430                 s->dma_length = s->length;
 431         }
 432         return nelems;
 433 }
 434
 435 int calgary_map_sg(struct device *dev, struct scatterlist *sg,
 436         int nelems, int direction)
 437 {
 438         struct iommu_table *tbl = find_iommu_table(dev);
 439         unsigned long flags;
 440         unsigned long vaddr;
 441         unsigned int npages;
 442         unsigned long entry;
 443         int i;
 444
 445         if (!translate_phb(to_pci_dev(dev)))
 446                 return calgary_nontranslate_map_sg(dev, sg, nelems, direction);
 447
 448         spin_lock_irqsave(&tbl->it_lock, flags);
 449
 450         for (i = 0; i < nelems; i++ ) {
 451                 struct scatterlist *s = &sg[i];
 452                 BUG_ON(!s->page);
 453
 454                 vaddr = (unsigned long)page_address(s->page) + s->offset;
 455                 npages = num_dma_pages(vaddr, s->length);
 456
 457                 entry = iommu_range_alloc(tbl, npages);
 458                 if (entry == bad_dma_address) {
 459                         /* makes sure unmap knows to stop */
 460                         s->dma_length = 0;
 461                         goto error;
 462                 }
 463
 464                 s->dma_address = (entry << PAGE_SHIFT) | s->offset;
 465
 466                 /* insert into HW table */
 467                 tce_build(tbl, entry, npages, vaddr & PAGE_MASK,
 468                           direction);
 469
 470                 s->dma_length = s->length;
 471         }
 472
 473         spin_unlock_irqrestore(&tbl->it_lock, flags);
 474
 475         return nelems;
 476 error:
 477         __calgary_unmap_sg(tbl, sg, nelems, direction);
 478         for (i = 0; i < nelems; i++) {
 479                 sg[i].dma_address = bad_dma_address;
 480                 sg[i].dma_length = 0;
 481         }
 482         spin_unlock_irqrestore(&tbl->it_lock, flags);
 483         return 0;
 484 }
 485
 486 dma_addr_t calgary_map_single(struct device *dev, void *vaddr,
 487         size_t size, int direction)
 488 {
 489         dma_addr_t dma_handle = bad_dma_address;
 490         unsigned long uaddr;
 491         unsigned int npages;
 492         struct iommu_table *tbl = find_iommu_table(dev);
 493
 494         uaddr = (unsigned long)vaddr;
 495         npages = num_dma_pages(uaddr, size);
 496
 497         if (translate_phb(to_pci_dev(dev)))
 498                 dma_handle = iommu_alloc(tbl, vaddr, npages, direction);
 499         else
 500                 dma_handle = virt_to_bus(vaddr);
 501
 502         return dma_handle;
 503 }
 504
 505 void calgary_unmap_single(struct device *dev, dma_addr_t dma_handle,
 506         size_t size, int direction)
 507 {
 508         struct iommu_table *tbl = find_iommu_table(dev);
 509         unsigned int npages;
 510
 511         if (!translate_phb(to_pci_dev(dev)))
 512                 return;
 513
 514         npages = num_dma_pages(dma_handle, size);
 515         iommu_free(tbl, dma_handle, npages);
 516 }
 517
 518 void* calgary_alloc_coherent(struct device *dev, size_t size,
 519         dma_addr_t *dma_handle, gfp_t flag)
 520 {
 521         void *ret = NULL;
 522         dma_addr_t mapping;
 523         unsigned int npages, order;
 524         struct iommu_table *tbl = find_iommu_table(dev);
 525
 526         size = PAGE_ALIGN(size); /* size rounded up to full pages */
 527         npages = size >> PAGE_SHIFT;
 528         order = get_order(size);
 529
 530         /* alloc enough pages (and possibly more) */
 531         ret = (void *)__get_free_pages(flag, order);
 532         if (!ret)
 533                 goto error;
 534         memset(ret, 0, size);
 535
 536         if (translate_phb(to_pci_dev(dev))) {
 537                 /* set up tces to cover the allocated range */
 538                 mapping = iommu_alloc(tbl, ret, npages, DMA_BIDIRECTIONAL);
 539                 if (mapping == bad_dma_address)
 540                         goto free;
 541
 542                 *dma_handle = mapping;
 543         } else /* non translated slot */
 544                 *dma_handle = virt_to_bus(ret);
 545
 546         return ret;
 547
 548 free:
 549         free_pages((unsigned long)ret, get_order(size));
 550         ret = NULL;
 551 error:
 552         return ret;
 553 }
 554
 555 static const struct dma_mapping_ops calgary_dma_ops = {
 556         .alloc_coherent = calgary_alloc_coherent,
 557         .map_single = calgary_map_single,
 558         .unmap_single = calgary_unmap_single,
 559         .map_sg = calgary_map_sg,
 560         .unmap_sg = calgary_unmap_sg,
 561 };
 562
 563 static inline void __iomem * busno_to_bbar(unsigned char num)
 564 {
 565         return bus_info[num].bbar;
 566 }
 567
 568 static inline int busno_to_phbid(unsigned char num)
 569 {
 570         return bus_info[num].phbid;
 571 }
 572
 573 static inline unsigned long split_queue_offset(unsigned char num)
 574 {
 575         size_t idx = busno_to_phbid(num);
 576
 577         return split_queue_offsets[idx];
 578 }
 579
 580 static inline unsigned long tar_offset(unsigned char num)
 581 {
 582         size_t idx = busno_to_phbid(num);
 583
 584         return tar_offsets[idx];
 585 }
 586
 587 static inline unsigned long phb_offset(unsigned char num)
 588 {
 589         size_t idx = busno_to_phbid(num);
 590
 591         return phb_offsets[idx];
 592 }
 593
 594 static inline void __iomem* calgary_reg(void __iomem *bar, unsigned long offset)
 595 {
 596         unsigned long target = ((unsigned long)bar) | offset;
 597         return (void __iomem*)target;
 598 }
 599
 600 static inline int is_calioc2(unsigned short device)
 601 {
 602         return (device == PCI_DEVICE_ID_IBM_CALIOC2);
 603 }
 604
 605 static inline int is_calgary(unsigned short device)
 606 {
 607         return (device == PCI_DEVICE_ID_IBM_CALGARY);
 608 }
 609
 610 static inline int is_cal_pci_dev(unsigned short device)
 611 {
 612         return (is_calgary(device) || is_calioc2(device));
 613 }
 614
 615 static void calgary_tce_cache_blast(struct iommu_table *tbl)
 616 {
 617         u64 val;
 618         u32 aer;
 619         int i = 0;
 620         void __iomem *bbar = tbl->bbar;
 621         void __iomem *target;
 622
 623         /* disable arbitration on the bus */
 624         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
 625         aer = readl(target);
 626         writel(0, target);
 627
 628         /* read plssr to ensure it got there */
 629         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
 630         val = readl(target);
 631
 632         /* poll split queues until all DMA activity is done */
 633         target = calgary_reg(bbar, split_queue_offset(tbl->it_busno));
 634         do {
 635                 val = readq(target);
 636                 i++;
 637         } while ((val & 0xff) != 0xff && i < 100);
 638         if (i == 100)
 639                 printk(KERN_WARNING "Calgary: PCI bus not quiesced, "
 640                        "continuing anyway\n");
 641
 642         /* invalidate TCE cache */
 643         target = calgary_reg(bbar, tar_offset(tbl->it_busno));
 644         writeq(tbl->tar_val, target);
 645
 646         /* enable arbitration */
 647         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
 648         writel(aer, target);
 649         (void)readl(target); /* flush */
 650 }
 651
 652 static void calioc2_tce_cache_blast(struct iommu_table *tbl)
 653 {
 654         void __iomem *bbar = tbl->bbar;
 655         void __iomem *target;
 656         u64 val64;
 657         u32 val;
 658         int i = 0;
 659         int count = 1;
 660         unsigned char bus = tbl->it_busno;
 661
 662 begin:
 663         printk(KERN_DEBUG "Calgary: CalIOC2 bus 0x%x entering tce cache blast "
 664                "sequence - count %d\n", bus, count);
 665
 666         /* 1. using the Page Migration Control reg set SoftStop */
 667         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 668         val = be32_to_cpu(readl(target));
 669         printk(KERN_DEBUG "1a. read 0x%x [LE] from %p\n", val, target);
 670         val |= PMR_SOFTSTOP;
 671         printk(KERN_DEBUG "1b. writing 0x%x [LE] to %p\n", val, target);
 672         writel(cpu_to_be32(val), target);
 673
 674         /* 2. poll split queues until all DMA activity is done */
 675         printk(KERN_DEBUG "2a. starting to poll split queues\n");
 676         target = calgary_reg(bbar, split_queue_offset(bus));
 677         do {
 678                 val64 = readq(target);
 679                 i++;
 680         } while ((val64 & 0xff) != 0xff && i < 100);
 681         if (i == 100)
 682                 printk(KERN_WARNING "CalIOC2: PCI bus not quiesced, "
 683                        "continuing anyway\n");
 684
 685         /* 3. poll Page Migration DEBUG for SoftStopFault */
 686         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
 687         val = be32_to_cpu(readl(target));
 688         printk(KERN_DEBUG "3. read 0x%x [LE] from %p\n", val, target);
 689
 690         /* 4. if SoftStopFault - goto (1) */
 691         if (val & PMR_SOFTSTOPFAULT) {
 692                 if (++count < 100)
 693                         goto begin;
 694                 else {
 695                         printk(KERN_WARNING "CalIOC2: too many SoftStopFaults, "
 696                                "aborting TCE cache flush sequence!\n");
 697                         return; /* pray for the best */
 698                 }
 699         }
 700
 701         /* 5. Slam into HardStop by reading PHB_PAGE_MIG_CTRL */
 702         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 703         printk(KERN_DEBUG "5a. slamming into HardStop by reading %p\n", target);
 704         val = be32_to_cpu(readl(target));
 705         printk(KERN_DEBUG "5b. read 0x%x [LE] from %p\n", val, target);
 706         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
 707         val = be32_to_cpu(readl(target));
 708         printk(KERN_DEBUG "5c. read 0x%x [LE] from %p (debug)\n", val, target);
 709
 710         /* 6. invalidate TCE cache */
 711         printk(KERN_DEBUG "6. invalidating TCE cache\n");
 712         target = calgary_reg(bbar, tar_offset(bus));
 713         writeq(tbl->tar_val, target);
 714
 715         /* 7. Re-read PMCR */
 716         printk(KERN_DEBUG "7a. Re-reading PMCR\n");
 717         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 718         val = be32_to_cpu(readl(target));
 719         printk(KERN_DEBUG "7b. read 0x%x [LE] from %p\n", val, target);
 720
 721         /* 8. Remove HardStop */
 722         printk(KERN_DEBUG "8a. removing HardStop from PMCR\n");
 723         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 724         val = 0;
 725         printk(KERN_DEBUG "8b. writing 0x%x [LE] to %p\n", val, target);
 726         writel(cpu_to_be32(val), target);
 727         val = be32_to_cpu(readl(target));
 728         printk(KERN_DEBUG "8c. read 0x%x [LE] from %p\n", val, target);
 729 }
 730
 731 static void __init calgary_reserve_mem_region(struct pci_dev *dev, u64 start,
 732         u64 limit)
 733 {
 734         unsigned int numpages;
 735
 736         limit = limit | 0xfffff;
 737         limit++;
 738
 739         numpages = ((limit - start) >> PAGE_SHIFT);
 740         iommu_range_reserve(dev->sysdata, start, numpages);
 741 }
 742
 743 static void __init calgary_reserve_peripheral_mem_1(struct pci_dev *dev)
 744 {
 745         void __iomem *target;
 746         u64 low, high, sizelow;
 747         u64 start, limit;
 748         struct iommu_table *tbl = dev->sysdata;
 749         unsigned char busnum = dev->bus->number;
 750         void __iomem *bbar = tbl->bbar;
 751
 752         /* peripheral MEM_1 region */
 753         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_LOW);
 754         low = be32_to_cpu(readl(target));
 755         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_HIGH);
 756         high = be32_to_cpu(readl(target));
 757         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_SIZE);
 758         sizelow = be32_to_cpu(readl(target));
 759
 760         start = (high << 32) | low;
 761         limit = sizelow;
 762
 763         calgary_reserve_mem_region(dev, start, limit);
 764 }
 765
 766 static void __init calgary_reserve_peripheral_mem_2(struct pci_dev *dev)
 767 {
 768         void __iomem *target;
 769         u32 val32;
 770         u64 low, high, sizelow, sizehigh;
 771         u64 start, limit;
 772         struct iommu_table *tbl = dev->sysdata;
 773         unsigned char busnum = dev->bus->number;
 774         void __iomem *bbar = tbl->bbar;
 775
 776         /* is it enabled? */
 777         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
 778         val32 = be32_to_cpu(readl(target));
 779         if (!(val32 & PHB_MEM2_ENABLE))
 780                 return;
 781
 782         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_LOW);
 783         low = be32_to_cpu(readl(target));
 784         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_HIGH);
 785         high = be32_to_cpu(readl(target));
 786         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_LOW);
 787         sizelow = be32_to_cpu(readl(target));
 788         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_HIGH);
 789         sizehigh = be32_to_cpu(readl(target));
 790
 791         start = (high << 32) | low;
 792         limit = (sizehigh << 32) | sizelow;
 793
 794         calgary_reserve_mem_region(dev, start, limit);
 795 }
 796
 797 /*
 798  * some regions of the IO address space do not get translated, so we
 799  * must not give devices IO addresses in those regions. The regions
 800  * are the 640KB-1MB region and the two PCI peripheral memory holes.
 801  * Reserve all of them in the IOMMU bitmap to avoid giving them out
 802  * later.
 803  */
 804 static void __init calgary_reserve_regions(struct pci_dev *dev)
 805 {
 806         unsigned int npages;
 807         u64 start;
 808         struct iommu_table *tbl = dev->sysdata;
 809
 810         /* reserve EMERGENCY_PAGES from bad_dma_address and up */
 811         iommu_range_reserve(tbl, bad_dma_address, EMERGENCY_PAGES);
 812
 813         /* avoid the BIOS/VGA first 640KB-1MB region */
 814         /* for CalIOC2 - avoid the entire first 2MB */
 815         if (is_calgary(dev->device)) {
 816                 start = (640 * 1024);
 817                 npages = ((1024 - 640) * 1024) >> PAGE_SHIFT;
 818         } else { /* calioc2 */
 819                 start = 0;
 820                 npages = (2 * 1024 * 1024) >> PAGE_SHIFT;
 821         }
 822         iommu_range_reserve(tbl, start, npages);
 823
 824         /* reserve the two PCI peripheral memory regions in IO space */
 825         calgary_reserve_peripheral_mem_1(dev);
 826         calgary_reserve_peripheral_mem_2(dev);
 827 }
 828
 829 static int __init calgary_setup_tar(struct pci_dev *dev, void __iomem *bbar)
 830 {
 831         u64 val64;
 832         u64 table_phys;
 833         void __iomem *target;
 834         int ret;
 835         struct iommu_table *tbl;
 836
 837         /* build TCE tables for each PHB */
 838         ret = build_tce_table(dev, bbar);
 839         if (ret)
 840                 return ret;
 841
 842         tbl = dev->sysdata;
 843         tbl->it_base = (unsigned long)bus_info[dev->bus->number].tce_space;
 844         tce_free(tbl, 0, tbl->it_size);
 845
 846         if (is_calgary(dev->device))
 847                 tbl->chip_ops = &calgary_chip_ops;
 848         else if (is_calioc2(dev->device))
 849                 tbl->chip_ops = &calioc2_chip_ops;
 850         else
 851                 BUG();
 852
 853         calgary_reserve_regions(dev);
 854
 855         /* set TARs for each PHB */
 856         target = calgary_reg(bbar, tar_offset(dev->bus->number));
 857         val64 = be64_to_cpu(readq(target));
 858
 859         /* zero out all TAR bits under sw control */
 860         val64 &= ~TAR_SW_BITS;
 861         table_phys = (u64)__pa(tbl->it_base);
 862
 863         val64 |= table_phys;
 864
 865         BUG_ON(specified_table_size > TCE_TABLE_SIZE_8M);
 866         val64 |= (u64) specified_table_size;
 867
 868         tbl->tar_val = cpu_to_be64(val64);
 869
 870         writeq(tbl->tar_val, target);
 871         readq(target); /* flush */
 872
 873         return 0;
 874 }
 875
 876 static void __init calgary_free_bus(struct pci_dev *dev)
 877 {
 878         u64 val64;
 879         struct iommu_table *tbl = dev->sysdata;
 880         void __iomem *target;
 881         unsigned int bitmapsz;
 882
 883         target = calgary_reg(tbl->bbar, tar_offset(dev->bus->number));
 884         val64 = be64_to_cpu(readq(target));
 885         val64 &= ~TAR_SW_BITS;
 886         writeq(cpu_to_be64(val64), target);
 887         readq(target); /* flush */
 888
 889         bitmapsz = tbl->it_size / BITS_PER_BYTE;
 890         free_pages((unsigned long)tbl->it_map, get_order(bitmapsz));
 891         tbl->it_map = NULL;
 892
 893         kfree(tbl);
 894         dev->sysdata = NULL;
 895
 896         /* Can't free bootmem allocated memory after system is up :-( */
 897         bus_info[dev->bus->number].tce_space = NULL;
 898 }
 899
 900 static void calgary_dump_error_regs(struct iommu_table *tbl)
 901 {
 902         void __iomem *bbar = tbl->bbar;
 903         void __iomem *target;
 904         u32 csr, plssr;
 905
 906         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
 907         csr = be32_to_cpu(readl(target));
 908
 909         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
 910         plssr = be32_to_cpu(readl(target));
 911
 912         /* If no error, the agent ID in the CSR is not valid */
 913         printk(KERN_EMERG "Calgary: DMA error on Calgary PHB 0x%x, "
 914                "0x%08x@CSR 0x%08x@PLSSR\n", tbl->it_busno, csr, plssr);
 915 }
 916
 917 static void calioc2_dump_error_regs(struct iommu_table *tbl)
 918 {
 919         void __iomem *bbar = tbl->bbar;
 920         u32 csr, csmr, plssr, mck, rcstat;
 921         void __iomem *target;
 922         unsigned long phboff = phb_offset(tbl->it_busno);
 923         unsigned long erroff;
 924         u32 errregs[7];
 925         int i;
 926
 927         /* dump CSR */
 928         target = calgary_reg(bbar, phboff | PHB_CSR_OFFSET);
 929         csr = be32_to_cpu(readl(target));
 930         /* dump PLSSR */
 931         target = calgary_reg(bbar, phboff | PHB_PLSSR_OFFSET);
 932         plssr = be32_to_cpu(readl(target));
 933         /* dump CSMR */
 934         target = calgary_reg(bbar, phboff | 0x290);
 935         csmr = be32_to_cpu(readl(target));
 936         /* dump mck */
 937         target = calgary_reg(bbar, phboff | 0x800);
 938         mck = be32_to_cpu(readl(target));
 939
 940         printk(KERN_EMERG "Calgary: DMA error on CalIOC2 PHB 0x%x\n",
 941                tbl->it_busno);
 942
 943         printk(KERN_EMERG "Calgary: 0x%08x@CSR 0x%08x@PLSSR 0x%08x@CSMR 0x%08x@MCK\n",
 944                csr, plssr, csmr, mck);
 945
 946         /* dump rest of error regs */
 947         printk(KERN_EMERG "Calgary: ");
 948         for (i = 0; i < ARRAY_SIZE(errregs); i++) {
 949                 erroff = (0x810 + (i * 0x10)); /* err regs are at 0x810 - 0x870 */
 950                 target = calgary_reg(bbar, phboff | erroff);
 951                 errregs[i] = be32_to_cpu(readl(target));
 952                 printk("0x%08x@0x%lx ", errregs[i], erroff);
 953         }
 954         printk("\n");
 955
 956         /* root complex status */
 957         target = calgary_reg(bbar, phboff | PHB_ROOT_COMPLEX_STATUS);
 958         rcstat = be32_to_cpu(readl(target));
 959         printk(KERN_EMERG "Calgary: 0x%08x@0x%x\n", rcstat,
 960                PHB_ROOT_COMPLEX_STATUS);
 961 }
 962
 963 static void calgary_watchdog(unsigned long data)
 964 {
 965         struct pci_dev *dev = (struct pci_dev *)data;
 966         struct iommu_table *tbl = dev->sysdata;
 967         void __iomem *bbar = tbl->bbar;
 968         u32 val32;
 969         void __iomem *target;
 970
 971         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
 972         val32 = be32_to_cpu(readl(target));
 973
 974         /* If no error, the agent ID in the CSR is not valid */
 975         if (val32 & CSR_AGENT_MASK) {
 976                 tbl->chip_ops->dump_error_regs(tbl);
 977
 978                 /* reset error */
 979                 writel(0, target);
 980
 981                 /* Disable bus that caused the error */
 982                 target = calgary_reg(bbar, phb_offset(tbl->it_busno) |
 983                                      PHB_CONFIG_RW_OFFSET);
 984                 val32 = be32_to_cpu(readl(target));
 985                 val32 |= PHB_SLOT_DISABLE;
 986                 writel(cpu_to_be32(val32), target);
 987                 readl(target); /* flush */
 988         } else {
 989                 /* Reset the timer */
 990                 mod_timer(&tbl->watchdog_timer, jiffies + 2 * HZ);
 991         }
 992 }
 993
 994 static void __init calgary_set_split_completion_timeout(void __iomem *bbar,
 995         unsigned char busnum, unsigned long timeout)
 996 {
 997         u64 val64;
 998         void __iomem *target;
 999         unsigned int phb_shift = ~0; /* silence gcc */
1000         u64 mask;
1001
1002         switch (busno_to_phbid(busnum)) {
1003         case 0: phb_shift = (63 - 19);
1004                 break;
1005         case 1: phb_shift = (63 - 23);
1006                 break;
1007         case 2: phb_shift = (63 - 27);
1008                 break;
1009         case 3: phb_shift = (63 - 35);
1010                 break;
1011         default:
1012                 BUG_ON(busno_to_phbid(busnum));
1013         }
1014
1015         target = calgary_reg(bbar, CALGARY_CONFIG_REG);
1016         val64 = be64_to_cpu(readq(target));
1017
1018         /* zero out this PHB's timer bits */
1019         mask = ~(0xFUL << phb_shift);
1020         val64 &= mask;
1021         val64 |= (timeout << phb_shift);
1022         writeq(cpu_to_be64(val64), target);
1023         readq(target); /* flush */
1024 }
1025
1026 static void calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
1027 {
1028         unsigned char busnum = dev->bus->number;
1029         void __iomem *bbar = tbl->bbar;
1030         void __iomem *target;
1031         u32 val;
1032
1033         /*
1034          * CalIOC2 designers recommend setting bit 8 in 0xnDB0 to 1
1035          */
1036         target = calgary_reg(bbar, phb_offset(busnum) | PHB_SAVIOR_L2);
1037         val = cpu_to_be32(readl(target));
1038         val |= 0x00800000;
1039         writel(cpu_to_be32(val), target);
1040 }
1041
1042 static void calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
1043 {
1044         unsigned char busnum = dev->bus->number;
1045
1046         /*
1047          * Give split completion a longer timeout on bus 1 for aic94xx
1048          * http://bugzilla.kernel.org/show_bug.cgi?id=7180
1049          */
1050         if (is_calgary(dev->device) && (busnum == 1))
1051                 calgary_set_split_completion_timeout(tbl->bbar, busnum,
1052                                                      CCR_2SEC_TIMEOUT);
1053 }
1054
1055 static void __init calgary_enable_translation(struct pci_dev *dev)
1056 {
1057         u32 val32;
1058         unsigned char busnum;
1059         void __iomem *target;
1060         void __iomem *bbar;
1061         struct iommu_table *tbl;
1062
1063         busnum = dev->bus->number;
1064         tbl = dev->sysdata;
1065         bbar = tbl->bbar;
1066
1067         /* enable TCE in PHB Config Register */
1068         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
1069         val32 = be32_to_cpu(readl(target));
1070         val32 |= PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE;
1071
1072         printk(KERN_INFO "Calgary: enabling translation on %s PHB %#x\n",
1073                (dev->device == PCI_DEVICE_ID_IBM_CALGARY) ?
1074                "Calgary" : "CalIOC2", busnum);
1075         printk(KERN_INFO "Calgary: errant DMAs will now be prevented on this "
1076                "bus.\n");
1077
1078         writel(cpu_to_be32(val32), target);
1079         readl(target); /* flush */
1080
1081         init_timer(&tbl->watchdog_timer);
1082         tbl->watchdog_timer.function = &calgary_watchdog;
1083         tbl->watchdog_timer.data = (unsigned long)dev;
1084         mod_timer(&tbl->watchdog_timer, jiffies);
1085 }
1086
1087 static void __init calgary_disable_translation(struct pci_dev *dev)
1088 {
1089         u32 val32;
1090         unsigned char busnum;
1091         void __iomem *target;
1092         void __iomem *bbar;
1093         struct iommu_table *tbl;
1094
1095         busnum = dev->bus->number;
1096         tbl = dev->sysdata;
1097         bbar = tbl->bbar;
1098
1099         /* disable TCE in PHB Config Register */
1100         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
1101         val32 = be32_to_cpu(readl(target));
1102         val32 &= ~(PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE);
1103
1104         printk(KERN_INFO "Calgary: disabling translation on PHB %#x!\n", busnum);
1105         writel(cpu_to_be32(val32), target);
1106         readl(target); /* flush */
1107
1108         del_timer_sync(&tbl->watchdog_timer);
1109 }
1110
1111 static void __init calgary_init_one_nontraslated(struct pci_dev *dev)
1112 {
1113         pci_dev_get(dev);
1114         dev->sysdata = NULL;
1115
1116         /* is the device behind a bridge? */
1117         if (dev->bus->parent)
1118                 dev->bus->parent->self = dev;
1119         else
1120                 dev->bus->self = dev;
1121 }
1122
1123 static int __init calgary_init_one(struct pci_dev *dev)
1124 {
1125         void __iomem *bbar;
1126         struct iommu_table *tbl;
1127         int ret;
1128
1129         BUG_ON(dev->bus->number >= MAX_PHB_BUS_NUM);
1130
1131         bbar = busno_to_bbar(dev->bus->number);
1132         ret = calgary_setup_tar(dev, bbar);
1133         if (ret)
1134                 goto done;
1135
1136         pci_dev_get(dev);
1137
1138         if (dev->bus->parent) {
1139                 if (dev->bus->parent->self)
1140                         printk(KERN_WARNING "Calgary: IEEEE, dev %p has "
1141                                "bus->parent->self!\n", dev);
1142                 dev->bus->parent->self = dev;
1143         } else
1144                 dev->bus->self = dev;
1145
1146         tbl = dev->sysdata;
1147         tbl->chip_ops->handle_quirks(tbl, dev);
1148
1149         calgary_enable_translation(dev);
1150
1151         return 0;
1152
1153 done:
1154         return ret;
1155 }
1156
1157 static int __init calgary_locate_bbars(void)
1158 {
1159         int ret;
1160         int rioidx, phb, bus;
1161         void __iomem *bbar;
1162         void __iomem *target;
1163         unsigned long offset;
1164         u8 start_bus, end_bus;
1165         u32 val;
1166
1167         ret = -ENODATA;
1168         for (rioidx = 0; rioidx < rio_table_hdr->num_rio_dev; rioidx++) {
1169                 struct rio_detail *rio = rio_devs[rioidx];
1170
1171                 if ((rio->type != COMPAT_CALGARY) && (rio->type != ALT_CALGARY))
1172                         continue;
1173
1174                 /* map entire 1MB of Calgary config space */
1175                 bbar = ioremap_nocache(rio->BBAR, 1024 * 1024);
1176                 if (!bbar)
1177                         goto error;
1178
1179                 for (phb = 0; phb < PHBS_PER_CALGARY; phb++) {
1180                         offset = phb_debug_offsets[phb] | PHB_DEBUG_STUFF_OFFSET;
1181                         target = calgary_reg(bbar, offset);
1182
1183                         val = be32_to_cpu(readl(target));
1184
1185                         start_bus = (u8)((val & 0x00FF0000) >> 16);
1186                         end_bus = (u8)((val & 0x0000FF00) >> 8);
1187
1188                         if (end_bus) {
1189                                 for (bus = start_bus; bus <= end_bus; bus++) {
1190                                         bus_info[bus].bbar = bbar;
1191                                         bus_info[bus].phbid = phb;
1192                                 }
1193                         } else {
1194                                 bus_info[start_bus].bbar = bbar;
1195                                 bus_info[start_bus].phbid = phb;
1196                         }
1197                 }
1198         }
1199
1200         return 0;
1201
1202 error:
1203         /* scan bus_info and iounmap any bbars we previously ioremap'd */
1204         for (bus = 0; bus < ARRAY_SIZE(bus_info); bus++)
1205                 if (bus_info[bus].bbar)
1206                         iounmap(bus_info[bus].bbar);
1207
1208         return ret;
1209 }
1210
1211 static int __init calgary_init(void)
1212 {
1213         int ret;
1214         struct pci_dev *dev = NULL;
1215         void* tce_space;
1216
1217         ret = calgary_locate_bbars();
1218         if (ret)
1219                 return ret;
1220
1221         do {
1222                 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1223                 if (!dev)
1224                         break;
1225                 if (!is_cal_pci_dev(dev->device))
1226                         continue;
1227                 if (!translate_phb(dev)) {
1228                         calgary_init_one_nontraslated(dev);
1229                         continue;
1230                 }
1231                 tce_space = bus_info[dev->bus->number].tce_space;
1232                 if (!tce_space && !translate_empty_slots) {
1233                         printk("Calg: %p failed tce_space check\n", dev);
1234                         continue;
1235                 }
1236                 ret = calgary_init_one(dev);
1237                 if (ret)
1238                         goto error;
1239         } while (1);
1240
1241         return ret;
1242
1243 error:
1244         do {
1245                 dev = pci_get_device_reverse(PCI_VENDOR_ID_IBM,
1246                                              PCI_ANY_ID, dev);
1247                 if (!dev)
1248                         break;
1249                 if (!is_cal_pci_dev(dev->device))
1250                         continue;
1251                 if (!translate_phb(dev)) {
1252                         pci_dev_put(dev);
1253                         continue;
1254                 }
1255                 if (!bus_info[dev->bus->number].tce_space && !translate_empty_slots)
1256                         continue;
1257
1258                 calgary_disable_translation(dev);
1259                 calgary_free_bus(dev);
1260                 pci_dev_put(dev); /* Undo calgary_init_one()'s pci_dev_get() */
1261         } while (1);
1262
1263         return ret;
1264 }
1265
1266 static inline int __init determine_tce_table_size(u64 ram)
1267 {
1268         int ret;
1269
1270         if (specified_table_size != TCE_TABLE_SIZE_UNSPECIFIED)
1271                 return specified_table_size;
1272
1273         /*
1274          * Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to
1275          * TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each
1276          * larger table size has twice as many entries, so shift the
1277          * max ram address by 13 to divide by 8K and then look at the
1278          * order of the result to choose between 0-7.
1279          */
1280         ret = get_order(ram >> 13);
1281         if (ret > TCE_TABLE_SIZE_8M)
1282                 ret = TCE_TABLE_SIZE_8M;
1283
1284         return ret;
1285 }
1286
1287 static int __init build_detail_arrays(void)
1288 {
1289         unsigned long ptr;
1290         int i, scal_detail_size, rio_detail_size;
1291
1292         if (rio_table_hdr->num_scal_dev > MAX_NUMNODES){
1293                 printk(KERN_WARNING
1294                         "Calgary: MAX_NUMNODES too low! Defined as %d, "
1295                         "but system has %d nodes.\n",
1296                         MAX_NUMNODES, rio_table_hdr->num_scal_dev);
1297                 return -ENODEV;
1298         }
1299
1300         switch (rio_table_hdr->version){
1301         case 2:
1302                 scal_detail_size = 11;
1303                 rio_detail_size = 13;
1304                 break;
1305         case 3:
1306                 scal_detail_size = 12;
1307                 rio_detail_size = 15;
1308                 break;
1309         default:
1310                 printk(KERN_WARNING
1311                        "Calgary: Invalid Rio Grande Table Version: %d\n",
1312                        rio_table_hdr->version);
1313                 return -EPROTO;
1314         }
1315
1316         ptr = ((unsigned long)rio_table_hdr) + 3;
1317         for (i = 0; i < rio_table_hdr->num_scal_dev;
1318                     i++, ptr += scal_detail_size)
1319                 scal_devs[i] = (struct scal_detail *)ptr;
1320
1321         for (i = 0; i < rio_table_hdr->num_rio_dev;
1322                     i++, ptr += rio_detail_size)
1323                 rio_devs[i] = (struct rio_detail *)ptr;
1324
1325         return 0;
1326 }
1327
1328 static int __init calgary_bus_has_devices(int bus, unsigned short pci_dev)
1329 {
1330         int dev;
1331         u32 val;
1332
1333         if (pci_dev == PCI_DEVICE_ID_IBM_CALIOC2) {
1334                 /*
1335                  * FIXME: properly scan for devices accross the
1336                  * PCI-to-PCI bridge on every CalIOC2 port.
1337                  */
1338                 return 1;
1339         }
1340
1341         for (dev = 1; dev < 8; dev++) {
1342                 val = read_pci_config(bus, dev, 0, 0);
1343                 if (val != 0xffffffff)
1344                         break;
1345         }
1346         return (val != 0xffffffff);
1347 }
1348
1349 void __init detect_calgary(void)
1350 {
1351         int bus;
1352         void *tbl;
1353         int calgary_found = 0;
1354         unsigned long ptr;
1355         unsigned int offset, prev_offset;
1356         int ret;
1357
1358         /*
1359          * if the user specified iommu=off or iommu=soft or we found
1360          * another HW IOMMU already, bail out.
1361          */
1362         if (swiotlb || no_iommu || iommu_detected)
1363                 return;
1364
1365         if (!use_calgary)
1366                 return;
1367
1368         if (!early_pci_allowed())
1369                 return;
1370
1371         printk(KERN_DEBUG "Calgary: detecting Calgary via BIOS EBDA area\n");
1372
1373         ptr = (unsigned long)phys_to_virt(get_bios_ebda());
1374
1375         rio_table_hdr = NULL;
1376         prev_offset = 0;
1377         offset = 0x180;
1378         /*
1379          * The next offset is stored in the 1st word.
1380          * Only parse up until the offset increases:
1381          */
1382         while (offset > prev_offset) {
1383                 /* The block id is stored in the 2nd word */
1384                 if (*((unsigned short *)(ptr + offset + 2)) == 0x4752){
1385                         /* set the pointer past the offset & block id */
1386                         rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4);
1387                         break;
1388                 }
1389                 prev_offset = offset;
1390                 offset = *((unsigned short *)(ptr + offset));
1391         }
1392         if (!rio_table_hdr) {
1393                 printk(KERN_DEBUG "Calgary: Unable to locate Rio Grande table "
1394                        "in EBDA - bailing!\n");
1395                 return;
1396         }
1397
1398         ret = build_detail_arrays();
1399         if (ret) {
1400                 printk(KERN_DEBUG "Calgary: build_detail_arrays ret %d\n", ret);
1401                 return;
1402         }
1403
1404         specified_table_size = determine_tce_table_size(end_pfn * PAGE_SIZE);
1405
1406         for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
1407                 struct calgary_bus_info *info = &bus_info[bus];
1408                 unsigned short pci_device;
1409                 u32 val;
1410
1411                 val = read_pci_config(bus, 0, 0, 0);
1412                 pci_device = (val & 0xFFFF0000) >> 16;
1413
1414                 if (!is_cal_pci_dev(pci_device))
1415                         continue;
1416
1417                 if (info->translation_disabled)
1418                         continue;
1419
1420                 if (calgary_bus_has_devices(bus, pci_device) ||
1421                     translate_empty_slots) {
1422                         tbl = alloc_tce_table();
1423                         if (!tbl)
1424                                 goto cleanup;
1425                         info->tce_space = tbl;
1426                         calgary_found = 1;
1427                         printk("Calg: allocated tce_table %p for bus 0x%x\n",
1428                                info->tce_space, bus);
1429                 }
1430         }
1431
1432         printk(KERN_DEBUG "Calgary: finished detection, Calgary %s\n",
1433                calgary_found ? "found" : "not found");
1434
1435         if (calgary_found) {
1436                 iommu_detected = 1;
1437                 calgary_detected = 1;
1438                 printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected.\n");
1439                 printk(KERN_INFO "PCI-DMA: Calgary TCE table spec is %d, "
1440                        "CONFIG_IOMMU_DEBUG is %s.\n", specified_table_size,
1441                        debugging ? "enabled" : "disabled");
1442         }
1443         return;
1444
1445 cleanup:
1446         for (--bus; bus >= 0; --bus) {
1447                 struct calgary_bus_info *info = &bus_info[bus];
1448
1449                 if (info->tce_space)
1450                         free_tce_table(info->tce_space);
1451         }
1452 }
1453
1454 int __init calgary_iommu_init(void)
1455 {
1456         int ret;
1457
1458         if (no_iommu || swiotlb)
1459                 return -ENODEV;
1460
1461         if (!calgary_detected)
1462                 return -ENODEV;
1463
1464         /* ok, we're trying to use Calgary - let's roll */
1465         printk(KERN_INFO "PCI-DMA: Using Calgary IOMMU\n");
1466
1467         ret = calgary_init();
1468         if (ret) {
1469                 printk(KERN_ERR "PCI-DMA: Calgary init failed %d, "
1470                        "falling back to no_iommu\n", ret);
1471                 if (end_pfn > MAX_DMA32_PFN)
1472                         printk(KERN_ERR "WARNING more than 4GB of memory, "
1473                                         "32bit PCI may malfunction.\n");
1474                 return ret;
1475         }
1476
1477         force_iommu = 1;
1478         bad_dma_address = 0x0;
1479         dma_ops = &calgary_dma_ops;
1480
1481         return 0;
1482 }
1483
1484 static int __init calgary_parse_options(char *p)
1485 {
1486         unsigned int bridge;
1487         size_t len;
1488         char* endp;
1489
1490         while (*p) {
1491                 if (!strncmp(p, "64k", 3))
1492                         specified_table_size = TCE_TABLE_SIZE_64K;
1493                 else if (!strncmp(p, "128k", 4))
1494                         specified_table_size = TCE_TABLE_SIZE_128K;
1495                 else if (!strncmp(p, "256k", 4))
1496                         specified_table_size = TCE_TABLE_SIZE_256K;
1497                 else if (!strncmp(p, "512k", 4))
1498                         specified_table_size = TCE_TABLE_SIZE_512K;
1499                 else if (!strncmp(p, "1M", 2))
1500                         specified_table_size = TCE_TABLE_SIZE_1M;
1501                 else if (!strncmp(p, "2M", 2))
1502                         specified_table_size = TCE_TABLE_SIZE_2M;
1503                 else if (!strncmp(p, "4M", 2))
1504                         specified_table_size = TCE_TABLE_SIZE_4M;
1505                 else if (!strncmp(p, "8M", 2))
1506                         specified_table_size = TCE_TABLE_SIZE_8M;
1507
1508                 len = strlen("translate_empty_slots");
1509                 if (!strncmp(p, "translate_empty_slots", len))
1510                         translate_empty_slots = 1;
1511
1512                 len = strlen("disable");
1513                 if (!strncmp(p, "disable", len)) {
1514                         p += len;
1515                         if (*p == '=')
1516                                 ++p;
1517                         if (*p == '\0')
1518                                 break;
1519                         bridge = simple_strtol(p, &endp, 0);
1520                         if (p == endp)
1521                                 break;
1522
1523                         if (bridge < MAX_PHB_BUS_NUM) {
1524                                 printk(KERN_INFO "Calgary: disabling "
1525                                        "translation for PHB %#x\n", bridge);
1526                                 bus_info[bridge].translation_disabled = 1;
1527                         }
1528                 }
1529
1530                 p = strpbrk(p, ",");
1531                 if (!p)
1532                         break;
1533
1534                 p++; /* skip ',' */
1535         }
1536         return 1;
1537 }
1538 __setup("calgary=", calgary_parse_options);