Merge master.kernel.org:/pub/scm/linux/kernel/git/chrisw/lsm-2.6
[linux-2.6] / arch / arm / mach-clps7500 / core.c
1 /*
2  *  linux/arch/arm/mach-clps7500/core.c
3  *
4  *  Copyright (C) 1998 Russell King
5  *  Copyright (C) 1999 Nexus Electronics Ltd
6  *
7  * Extra MM routines for CL7500 architecture
8  */
9 #include <linux/kernel.h>
10 #include <linux/types.h>
11 #include <linux/interrupt.h>
12 #include <linux/list.h>
13 #include <linux/sched.h>
14 #include <linux/init.h>
15 #include <linux/device.h>
16 #include <linux/serial_8250.h>
17
18 #include <asm/mach/arch.h>
19 #include <asm/mach/map.h>
20 #include <asm/mach/irq.h>
21 #include <asm/mach/time.h>
22
23 #include <asm/hardware.h>
24 #include <asm/hardware/iomd.h>
25 #include <asm/io.h>
26 #include <asm/irq.h>
27 #include <asm/mach-types.h>
28
29 unsigned int vram_size;
30
31 static void cl7500_ack_irq_a(unsigned int irq)
32 {
33         unsigned int val, mask;
34
35         mask = 1 << irq;
36         val = iomd_readb(IOMD_IRQMASKA);
37         iomd_writeb(val & ~mask, IOMD_IRQMASKA);
38         iomd_writeb(mask, IOMD_IRQCLRA);
39 }
40
41 static void cl7500_mask_irq_a(unsigned int irq)
42 {
43         unsigned int val, mask;
44
45         mask = 1 << irq;
46         val = iomd_readb(IOMD_IRQMASKA);
47         iomd_writeb(val & ~mask, IOMD_IRQMASKA);
48 }
49
50 static void cl7500_unmask_irq_a(unsigned int irq)
51 {
52         unsigned int val, mask;
53
54         mask = 1 << irq;
55         val = iomd_readb(IOMD_IRQMASKA);
56         iomd_writeb(val | mask, IOMD_IRQMASKA);
57 }
58
59 static struct irqchip clps7500_a_chip = {
60         .ack    = cl7500_ack_irq_a,
61         .mask   = cl7500_mask_irq_a,
62         .unmask = cl7500_unmask_irq_a,
63 };
64
65 static void cl7500_mask_irq_b(unsigned int irq)
66 {
67         unsigned int val, mask;
68
69         mask = 1 << (irq & 7);
70         val = iomd_readb(IOMD_IRQMASKB);
71         iomd_writeb(val & ~mask, IOMD_IRQMASKB);
72 }
73
74 static void cl7500_unmask_irq_b(unsigned int irq)
75 {
76         unsigned int val, mask;
77
78         mask = 1 << (irq & 7);
79         val = iomd_readb(IOMD_IRQMASKB);
80         iomd_writeb(val | mask, IOMD_IRQMASKB);
81 }
82
83 static struct irqchip clps7500_b_chip = {
84         .ack    = cl7500_mask_irq_b,
85         .mask   = cl7500_mask_irq_b,
86         .unmask = cl7500_unmask_irq_b,
87 };
88
89 static void cl7500_mask_irq_c(unsigned int irq)
90 {
91         unsigned int val, mask;
92
93         mask = 1 << (irq & 7);
94         val = iomd_readb(IOMD_IRQMASKC);
95         iomd_writeb(val & ~mask, IOMD_IRQMASKC);
96 }
97
98 static void cl7500_unmask_irq_c(unsigned int irq)
99 {
100         unsigned int val, mask;
101
102         mask = 1 << (irq & 7);
103         val = iomd_readb(IOMD_IRQMASKC);
104         iomd_writeb(val | mask, IOMD_IRQMASKC);
105 }
106
107 static struct irqchip clps7500_c_chip = {
108         .ack    = cl7500_mask_irq_c,
109         .mask   = cl7500_mask_irq_c,
110         .unmask = cl7500_unmask_irq_c,
111 };
112
113 static void cl7500_mask_irq_d(unsigned int irq)
114 {
115         unsigned int val, mask;
116
117         mask = 1 << (irq & 7);
118         val = iomd_readb(IOMD_IRQMASKD);
119         iomd_writeb(val & ~mask, IOMD_IRQMASKD);
120 }
121
122 static void cl7500_unmask_irq_d(unsigned int irq)
123 {
124         unsigned int val, mask;
125
126         mask = 1 << (irq & 7);
127         val = iomd_readb(IOMD_IRQMASKD);
128         iomd_writeb(val | mask, IOMD_IRQMASKD);
129 }
130
131 static struct irqchip clps7500_d_chip = {
132         .ack    = cl7500_mask_irq_d,
133         .mask   = cl7500_mask_irq_d,
134         .unmask = cl7500_unmask_irq_d,
135 };
136
137 static void cl7500_mask_irq_dma(unsigned int irq)
138 {
139         unsigned int val, mask;
140
141         mask = 1 << (irq & 7);
142         val = iomd_readb(IOMD_DMAMASK);
143         iomd_writeb(val & ~mask, IOMD_DMAMASK);
144 }
145
146 static void cl7500_unmask_irq_dma(unsigned int irq)
147 {
148         unsigned int val, mask;
149
150         mask = 1 << (irq & 7);
151         val = iomd_readb(IOMD_DMAMASK);
152         iomd_writeb(val | mask, IOMD_DMAMASK);
153 }
154
155 static struct irqchip clps7500_dma_chip = {
156         .ack    = cl7500_mask_irq_dma,
157         .mask   = cl7500_mask_irq_dma,
158         .unmask = cl7500_unmask_irq_dma,
159 };
160
161 static void cl7500_mask_irq_fiq(unsigned int irq)
162 {
163         unsigned int val, mask;
164
165         mask = 1 << (irq & 7);
166         val = iomd_readb(IOMD_FIQMASK);
167         iomd_writeb(val & ~mask, IOMD_FIQMASK);
168 }
169
170 static void cl7500_unmask_irq_fiq(unsigned int irq)
171 {
172         unsigned int val, mask;
173
174         mask = 1 << (irq & 7);
175         val = iomd_readb(IOMD_FIQMASK);
176         iomd_writeb(val | mask, IOMD_FIQMASK);
177 }
178
179 static struct irqchip clps7500_fiq_chip = {
180         .ack    = cl7500_mask_irq_fiq,
181         .mask   = cl7500_mask_irq_fiq,
182         .unmask = cl7500_unmask_irq_fiq,
183 };
184
185 static void cl7500_no_action(unsigned int irq)
186 {
187 }
188
189 static struct irqchip clps7500_no_chip = {
190         .ack    = cl7500_no_action,
191         .mask   = cl7500_no_action,
192         .unmask = cl7500_no_action,
193 };
194
195 static struct irqaction irq_isa = { no_action, 0, CPU_MASK_NONE, "isa", NULL, NULL };
196
197 static void __init clps7500_init_irq(void)
198 {
199         unsigned int irq, flags;
200
201         iomd_writeb(0, IOMD_IRQMASKA);
202         iomd_writeb(0, IOMD_IRQMASKB);
203         iomd_writeb(0, IOMD_FIQMASK);
204         iomd_writeb(0, IOMD_DMAMASK);
205
206         for (irq = 0; irq < NR_IRQS; irq++) {
207                 flags = IRQF_VALID;
208
209                 if (irq <= 6 || (irq >= 9 && irq <= 15) ||
210                     (irq >= 48 && irq <= 55))
211                         flags |= IRQF_PROBE;
212
213                 switch (irq) {
214                 case 0 ... 7:
215                         set_irq_chip(irq, &clps7500_a_chip);
216                         set_irq_handler(irq, do_level_IRQ);
217                         set_irq_flags(irq, flags);
218                         break;
219
220                 case 8 ... 15:
221                         set_irq_chip(irq, &clps7500_b_chip);
222                         set_irq_handler(irq, do_level_IRQ);
223                         set_irq_flags(irq, flags);
224                         break;
225
226                 case 16 ... 22:
227                         set_irq_chip(irq, &clps7500_dma_chip);
228                         set_irq_handler(irq, do_level_IRQ);
229                         set_irq_flags(irq, flags);
230                         break;
231
232                 case 24 ... 31:
233                         set_irq_chip(irq, &clps7500_c_chip);
234                         set_irq_handler(irq, do_level_IRQ);
235                         set_irq_flags(irq, flags);
236                         break;
237
238                 case 40 ... 47:
239                         set_irq_chip(irq, &clps7500_d_chip);
240                         set_irq_handler(irq, do_level_IRQ);
241                         set_irq_flags(irq, flags);
242                         break;
243
244                 case 48 ... 55:
245                         set_irq_chip(irq, &clps7500_no_chip);
246                         set_irq_handler(irq, do_level_IRQ);
247                         set_irq_flags(irq, flags);
248                         break;
249
250                 case 64 ... 72:
251                         set_irq_chip(irq, &clps7500_fiq_chip);
252                         set_irq_handler(irq, do_level_IRQ);
253                         set_irq_flags(irq, flags);
254                         break;
255                 }
256         }
257
258         setup_irq(IRQ_ISA, &irq_isa);
259 }
260
261 static struct map_desc cl7500_io_desc[] __initdata = {
262         { IO_BASE,      IO_START,       IO_SIZE,    MT_DEVICE },        /* IO space     */
263         { ISA_BASE,     ISA_START,      ISA_SIZE,   MT_DEVICE },        /* ISA space    */
264         { FLASH_BASE,   FLASH_START,    FLASH_SIZE, MT_DEVICE },        /* Flash        */
265         { LED_BASE,     LED_START,      LED_SIZE,   MT_DEVICE }         /* LED          */
266 };
267
268 static void __init clps7500_map_io(void)
269 {
270         iotable_init(cl7500_io_desc, ARRAY_SIZE(cl7500_io_desc));
271 }
272
273 extern void ioctime_init(void);
274 extern unsigned long ioc_timer_gettimeoffset(void);
275
276 static irqreturn_t
277 clps7500_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
278 {
279         write_seqlock(&xtime_lock);
280
281         timer_tick(regs);
282
283         /* Why not using do_leds interface?? */
284         {
285                 /* Twinkle the lights. */
286                 static int count, state = 0xff00;
287                 if (count-- == 0) {
288                         state ^= 0x100;
289                         count = 25;
290                         *((volatile unsigned int *)LED_ADDRESS) = state;
291                 }
292         }
293
294         write_sequnlock(&xtime_lock);
295
296         return IRQ_HANDLED;
297 }
298
299 static struct irqaction clps7500_timer_irq = {
300         .name           = "CLPS7500 Timer Tick",
301         .flags          = SA_INTERRUPT | SA_TIMER,
302         .handler        = clps7500_timer_interrupt,
303 };
304
305 /*
306  * Set up timer interrupt.
307  */
308 static void __init clps7500_timer_init(void)
309 {
310         ioctime_init();
311         setup_irq(IRQ_TIMER, &clps7500_timer_irq);
312 }
313
314 static struct sys_timer clps7500_timer = {
315         .init           = clps7500_timer_init,
316         .offset         = ioc_timer_gettimeoffset,
317 };
318
319 static struct plat_serial8250_port serial_platform_data[] = {
320         {
321                 .mapbase        = 0x03010fe0,
322                 .irq            = 10,
323                 .uartclk        = 1843200,
324                 .regshift       = 2,
325                 .iotype         = UPIO_MEM,
326                 .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SKIP_TEST,
327         },
328         {
329                 .mapbase        = 0x03010be0,
330                 .irq            = 0,
331                 .uartclk        = 1843200,
332                 .regshift       = 2,
333                 .iotype         = UPIO_MEM,
334                 .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SKIP_TEST,
335         },
336         {
337                 .iobase         = ISASLOT_IO + 0x2e8,
338                 .irq            = 41,
339                 .uartclk        = 1843200,
340                 .regshift       = 0,
341                 .iotype         = UPIO_PORT,
342                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
343         },
344         {
345                 .iobase         = ISASLOT_IO + 0x3e8,
346                 .irq            = 40,
347                 .uartclk        = 1843200,
348                 .regshift       = 0,
349                 .iotype         = UPIO_PORT,
350                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
351         },
352         { },
353 };
354
355 static struct platform_device serial_device = {
356         .name                   = "serial8250",
357         .id                     = PLAT8250_DEV_PLATFORM,
358         .dev                    = {
359                 .platform_data  = serial_platform_data,
360         },
361 };
362
363 static void __init clps7500_init(void)
364 {
365         platform_device_register(&serial_device);
366 }
367
368 MACHINE_START(CLPS7500, "CL-PS7500")
369         /* Maintainer: Philip Blundell */
370         .phys_ram       = 0x10000000,
371         .phys_io        = 0x03000000,
372         .io_pg_offst    = ((0xe0000000) >> 18) & 0xfffc,
373         .map_io         = clps7500_map_io,
374         .init_irq       = clps7500_init_irq,
375         .init_machine   = clps7500_init,
376         .timer          = &clps7500_timer,
377 MACHINE_END
378