git.oblomov.eu Git - linux-2.6/blob - drivers/char/agp/intel-agp.c

   1 /*
   2  * Intel AGPGART routines.
   3  */
   4
   5 #include <linux/module.h>
   6 #include <linux/pci.h>
   7 #include <linux/init.h>
   8 #include <linux/kernel.h>
   9 #include <linux/pagemap.h>
  10 #include <linux/agp_backend.h>
  11 #include "agp.h"
  12
  13 #define PCI_DEVICE_ID_INTEL_82946GZ_HB      0x2970
  14 #define PCI_DEVICE_ID_INTEL_82946GZ_IG      0x2972
  15 #define PCI_DEVICE_ID_INTEL_82965G_1_HB     0x2980
  16 #define PCI_DEVICE_ID_INTEL_82965G_1_IG     0x2982
  17 #define PCI_DEVICE_ID_INTEL_82965Q_HB       0x2990
  18 #define PCI_DEVICE_ID_INTEL_82965Q_IG       0x2992
  19 #define PCI_DEVICE_ID_INTEL_82965G_HB       0x29A0
  20 #define PCI_DEVICE_ID_INTEL_82965G_IG       0x29A2
  21 #define PCI_DEVICE_ID_INTEL_82965GM_HB      0x2A00
  22 #define PCI_DEVICE_ID_INTEL_82965GM_IG      0x2A02
  23 #define PCI_DEVICE_ID_INTEL_82965GME_HB     0x2A10
  24 #define PCI_DEVICE_ID_INTEL_82965GME_IG     0x2A12
  25 #define PCI_DEVICE_ID_INTEL_82945GME_HB     0x27AC
  26 #define PCI_DEVICE_ID_INTEL_82945GME_IG     0x27AE
  27 #define PCI_DEVICE_ID_INTEL_G33_HB          0x29C0
  28 #define PCI_DEVICE_ID_INTEL_G33_IG          0x29C2
  29 #define PCI_DEVICE_ID_INTEL_Q35_HB          0x29B0
  30 #define PCI_DEVICE_ID_INTEL_Q35_IG          0x29B2
  31 #define PCI_DEVICE_ID_INTEL_Q33_HB          0x29D0
  32 #define PCI_DEVICE_ID_INTEL_Q33_IG          0x29D2
  33
  34 #define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \
  35                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_1_HB || \
  36                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \
  37                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \
  38                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \
  39                  agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB)
  40
  41 #define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \
  42                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
  43                 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB)
  44
  45 extern int agp_memory_reserved;
  46
  47
  48 /* Intel 815 register */
  49 #define INTEL_815_APCONT        0x51
  50 #define INTEL_815_ATTBASE_MASK  ~0x1FFFFFFF
  51
  52 /* Intel i820 registers */
  53 #define INTEL_I820_RDCR         0x51
  54 #define INTEL_I820_ERRSTS       0xc8
  55
  56 /* Intel i840 registers */
  57 #define INTEL_I840_MCHCFG       0x50
  58 #define INTEL_I840_ERRSTS       0xc8
  59
  60 /* Intel i850 registers */
  61 #define INTEL_I850_MCHCFG       0x50
  62 #define INTEL_I850_ERRSTS       0xc8
  63
  64 /* intel 915G registers */
  65 #define I915_GMADDR     0x18
  66 #define I915_MMADDR     0x10
  67 #define I915_PTEADDR    0x1C
  68 #define I915_GMCH_GMS_STOLEN_48M        (0x6 << 4)
  69 #define I915_GMCH_GMS_STOLEN_64M        (0x7 << 4)
  70 #define G33_GMCH_GMS_STOLEN_128M       (0x8 << 4)
  71 #define G33_GMCH_GMS_STOLEN_256M       (0x9 << 4)
  72
  73 /* Intel 965G registers */
  74 #define I965_MSAC 0x62
  75
  76 /* Intel 7505 registers */
  77 #define INTEL_I7505_APSIZE      0x74
  78 #define INTEL_I7505_NCAPID      0x60
  79 #define INTEL_I7505_NISTAT      0x6c
  80 #define INTEL_I7505_ATTBASE     0x78
  81 #define INTEL_I7505_ERRSTS      0x42
  82 #define INTEL_I7505_AGPCTRL     0x70
  83 #define INTEL_I7505_MCHCFG      0x50
  84
  85 static const struct aper_size_info_fixed intel_i810_sizes[] =
  86 {
  87         {64, 16384, 4},
  88         /* The 32M mode still requires a 64k gatt */
  89         {32, 8192, 4}
  90 };
  91
  92 #define AGP_DCACHE_MEMORY       1
  93 #define AGP_PHYS_MEMORY         2
  94 #define INTEL_AGP_CACHED_MEMORY 3
  95
  96 static struct gatt_mask intel_i810_masks[] =
  97 {
  98         {.mask = I810_PTE_VALID, .type = 0},
  99         {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
 100         {.mask = I810_PTE_VALID, .type = 0},
 101         {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
 102          .type = INTEL_AGP_CACHED_MEMORY}
 103 };
 104
 105 static struct _intel_private {
 106         struct pci_dev *pcidev; /* device one */
 107         u8 __iomem *registers;
 108         u32 __iomem *gtt;               /* I915G */
 109         int num_dcache_entries;
 110         /* gtt_entries is the number of gtt entries that are already mapped
 111          * to stolen memory.  Stolen memory is larger than the memory mapped
 112          * through gtt_entries, as it includes some reserved space for the BIOS
 113          * popup and for the GTT.
 114          */
 115         int gtt_entries;                        /* i830+ */
 116 } intel_private;
 117
 118 static int intel_i810_fetch_size(void)
 119 {
 120         u32 smram_miscc;
 121         struct aper_size_info_fixed *values;
 122
 123         pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc);
 124         values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
 125
 126         if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
 127                 printk(KERN_WARNING PFX "i810 is disabled\n");
 128                 return 0;
 129         }
 130         if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
 131                 agp_bridge->previous_size =
 132                         agp_bridge->current_size = (void *) (values + 1);
 133                 agp_bridge->aperture_size_idx = 1;
 134                 return values[1].size;
 135         } else {
 136                 agp_bridge->previous_size =
 137                         agp_bridge->current_size = (void *) (values);
 138                 agp_bridge->aperture_size_idx = 0;
 139                 return values[0].size;
 140         }
 141
 142         return 0;
 143 }
 144
 145 static int intel_i810_configure(void)
 146 {
 147         struct aper_size_info_fixed *current_size;
 148         u32 temp;
 149         int i;
 150
 151         current_size = A_SIZE_FIX(agp_bridge->current_size);
 152
 153         if (!intel_private.registers) {
 154                 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
 155                 temp &= 0xfff80000;
 156
 157                 intel_private.registers = ioremap(temp, 128 * 4096);
 158                 if (!intel_private.registers) {
 159                         printk(KERN_ERR PFX "Unable to remap memory.\n");
 160                         return -ENOMEM;
 161                 }
 162         }
 163
 164         if ((readl(intel_private.registers+I810_DRAM_CTL)
 165                 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
 166                 /* This will need to be dynamically assigned */
 167                 printk(KERN_INFO PFX "detected 4MB dedicated video ram.\n");
 168                 intel_private.num_dcache_entries = 1024;
 169         }
 170         pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
 171         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 172         writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
 173         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
 174
 175         if (agp_bridge->driver->needs_scratch_page) {
 176                 for (i = 0; i < current_size->num_entries; i++) {
 177                         writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 178                         readl(intel_private.registers+I810_PTE_BASE+(i*4));     /* PCI posting. */
 179                 }
 180         }
 181         global_cache_flush();
 182         return 0;
 183 }
 184
 185 static void intel_i810_cleanup(void)
 186 {
 187         writel(0, intel_private.registers+I810_PGETBL_CTL);
 188         readl(intel_private.registers); /* PCI Posting. */
 189         iounmap(intel_private.registers);
 190 }
 191
 192 static void intel_i810_tlbflush(struct agp_memory *mem)
 193 {
 194         return;
 195 }
 196
 197 static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode)
 198 {
 199         return;
 200 }
 201
 202 /* Exists to support ARGB cursors */
 203 static void *i8xx_alloc_pages(void)
 204 {
 205         struct page * page;
 206
 207         page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
 208         if (page == NULL)
 209                 return NULL;
 210
 211         if (change_page_attr(page, 4, PAGE_KERNEL_NOCACHE) < 0) {
 212                 change_page_attr(page, 4, PAGE_KERNEL);
 213                 global_flush_tlb();
 214                 __free_pages(page, 2);
 215                 return NULL;
 216         }
 217         global_flush_tlb();
 218         get_page(page);
 219         atomic_inc(&agp_bridge->current_memory_agp);
 220         return page_address(page);
 221 }
 222
 223 static void i8xx_destroy_pages(void *addr)
 224 {
 225         struct page *page;
 226
 227         if (addr == NULL)
 228                 return;
 229
 230         page = virt_to_page(addr);
 231         change_page_attr(page, 4, PAGE_KERNEL);
 232         global_flush_tlb();
 233         put_page(page);
 234         __free_pages(page, 2);
 235         atomic_dec(&agp_bridge->current_memory_agp);
 236 }
 237
 238 static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge,
 239                                         int type)
 240 {
 241         if (type < AGP_USER_TYPES)
 242                 return type;
 243         else if (type == AGP_USER_CACHED_MEMORY)
 244                 return INTEL_AGP_CACHED_MEMORY;
 245         else
 246                 return 0;
 247 }
 248
 249 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
 250                                 int type)
 251 {
 252         int i, j, num_entries;
 253         void *temp;
 254         int ret = -EINVAL;
 255         int mask_type;
 256
 257         if (mem->page_count == 0)
 258                 goto out;
 259
 260         temp = agp_bridge->current_size;
 261         num_entries = A_SIZE_FIX(temp)->num_entries;
 262
 263         if ((pg_start + mem->page_count) > num_entries)
 264                 goto out_err;
 265
 266
 267         for (j = pg_start; j < (pg_start + mem->page_count); j++) {
 268                 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) {
 269                         ret = -EBUSY;
 270                         goto out_err;
 271                 }
 272         }
 273
 274         if (type != mem->type)
 275                 goto out_err;
 276
 277         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
 278
 279         switch (mask_type) {
 280         case AGP_DCACHE_MEMORY:
 281                 if (!mem->is_flushed)
 282                         global_cache_flush();
 283                 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
 284                         writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
 285                                intel_private.registers+I810_PTE_BASE+(i*4));
 286                 }
 287                 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
 288                 break;
 289         case AGP_PHYS_MEMORY:
 290         case AGP_NORMAL_MEMORY:
 291                 if (!mem->is_flushed)
 292                         global_cache_flush();
 293                 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 294                         writel(agp_bridge->driver->mask_memory(agp_bridge,
 295                                                                mem->memory[i],
 296                                                                mask_type),
 297                                intel_private.registers+I810_PTE_BASE+(j*4));
 298                 }
 299                 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
 300                 break;
 301         default:
 302                 goto out_err;
 303         }
 304
 305         agp_bridge->driver->tlb_flush(mem);
 306 out:
 307         ret = 0;
 308 out_err:
 309         mem->is_flushed = 1;
 310         return ret;
 311 }
 312
 313 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
 314                                 int type)
 315 {
 316         int i;
 317
 318         if (mem->page_count == 0)
 319                 return 0;
 320
 321         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
 322                 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 323         }
 324         readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
 325
 326         agp_bridge->driver->tlb_flush(mem);
 327         return 0;
 328 }
 329
 330 /*
 331  * The i810/i830 requires a physical address to program its mouse
 332  * pointer into hardware.
 333  * However the Xserver still writes to it through the agp aperture.
 334  */
 335 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
 336 {
 337         struct agp_memory *new;
 338         void *addr;
 339
 340         switch (pg_count) {
 341         case 1: addr = agp_bridge->driver->agp_alloc_page(agp_bridge);
 342                 global_flush_tlb();
 343                 break;
 344         case 4:
 345                 /* kludge to get 4 physical pages for ARGB cursor */
 346                 addr = i8xx_alloc_pages();
 347                 break;
 348         default:
 349                 return NULL;
 350         }
 351
 352         if (addr == NULL)
 353                 return NULL;
 354
 355         new = agp_create_memory(pg_count);
 356         if (new == NULL)
 357                 return NULL;
 358
 359         new->memory[0] = virt_to_gart(addr);
 360         if (pg_count == 4) {
 361                 /* kludge to get 4 physical pages for ARGB cursor */
 362                 new->memory[1] = new->memory[0] + PAGE_SIZE;
 363                 new->memory[2] = new->memory[1] + PAGE_SIZE;
 364                 new->memory[3] = new->memory[2] + PAGE_SIZE;
 365         }
 366         new->page_count = pg_count;
 367         new->num_scratch_pages = pg_count;
 368         new->type = AGP_PHYS_MEMORY;
 369         new->physical = new->memory[0];
 370         return new;
 371 }
 372
 373 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
 374 {
 375         struct agp_memory *new;
 376
 377         if (type == AGP_DCACHE_MEMORY) {
 378                 if (pg_count != intel_private.num_dcache_entries)
 379                         return NULL;
 380
 381                 new = agp_create_memory(1);
 382                 if (new == NULL)
 383                         return NULL;
 384
 385                 new->type = AGP_DCACHE_MEMORY;
 386                 new->page_count = pg_count;
 387                 new->num_scratch_pages = 0;
 388                 agp_free_page_array(new);
 389                 return new;
 390         }
 391         if (type == AGP_PHYS_MEMORY)
 392                 return alloc_agpphysmem_i8xx(pg_count, type);
 393         return NULL;
 394 }
 395
 396 static void intel_i810_free_by_type(struct agp_memory *curr)
 397 {
 398         agp_free_key(curr->key);
 399         if (curr->type == AGP_PHYS_MEMORY) {
 400                 if (curr->page_count == 4)
 401                         i8xx_destroy_pages(gart_to_virt(curr->memory[0]));
 402                 else {
 403                         agp_bridge->driver->agp_destroy_page(
 404                                  gart_to_virt(curr->memory[0]));
 405                         global_flush_tlb();
 406                 }
 407                 agp_free_page_array(curr);
 408         }
 409         kfree(curr);
 410 }
 411
 412 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
 413         unsigned long addr, int type)
 414 {
 415         /* Type checking must be done elsewhere */
 416         return addr | bridge->driver->masks[type].mask;
 417 }
 418
 419 static struct aper_size_info_fixed intel_i830_sizes[] =
 420 {
 421         {128, 32768, 5},
 422         /* The 64M mode still requires a 128k gatt */
 423         {64, 16384, 5},
 424         {256, 65536, 6},
 425         {512, 131072, 7},
 426 };
 427
 428 static void intel_i830_init_gtt_entries(void)
 429 {
 430         u16 gmch_ctrl;
 431         int gtt_entries;
 432         u8 rdct;
 433         int local = 0;
 434         static const int ddt[4] = { 0, 16, 32, 64 };
 435         int size; /* reserved space (in kb) at the top of stolen memory */
 436
 437         pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
 438
 439         if (IS_I965) {
 440                 u32 pgetbl_ctl;
 441                 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
 442
 443                 /* The 965 has a field telling us the size of the GTT,
 444                  * which may be larger than what is necessary to map the
 445                  * aperture.
 446                  */
 447                 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
 448                 case I965_PGETBL_SIZE_128KB:
 449                         size = 128;
 450                         break;
 451                 case I965_PGETBL_SIZE_256KB:
 452                         size = 256;
 453                         break;
 454                 case I965_PGETBL_SIZE_512KB:
 455                         size = 512;
 456                         break;
 457                 default:
 458                         printk(KERN_INFO PFX "Unknown page table size, "
 459                                "assuming 512KB\n");
 460                         size = 512;
 461                 }
 462                 size += 4; /* add in BIOS popup space */
 463         } else if (IS_G33) {
 464         /* G33's GTT size defined in gmch_ctrl */
 465                 switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) {
 466                 case G33_PGETBL_SIZE_1M:
 467                         size = 1024;
 468                         break;
 469                 case G33_PGETBL_SIZE_2M:
 470                         size = 2048;
 471                         break;
 472                 default:
 473                         printk(KERN_INFO PFX "Unknown page table size 0x%x, "
 474                                 "assuming 512KB\n",
 475                                 (gmch_ctrl & G33_PGETBL_SIZE_MASK));
 476                         size = 512;
 477                 }
 478                 size += 4;
 479         } else {
 480                 /* On previous hardware, the GTT size was just what was
 481                  * required to map the aperture.
 482                  */
 483                 size = agp_bridge->driver->fetch_size() + 4;
 484         }
 485
 486         if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
 487             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
 488                 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
 489                 case I830_GMCH_GMS_STOLEN_512:
 490                         gtt_entries = KB(512) - KB(size);
 491                         break;
 492                 case I830_GMCH_GMS_STOLEN_1024:
 493                         gtt_entries = MB(1) - KB(size);
 494                         break;
 495                 case I830_GMCH_GMS_STOLEN_8192:
 496                         gtt_entries = MB(8) - KB(size);
 497                         break;
 498                 case I830_GMCH_GMS_LOCAL:
 499                         rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
 500                         gtt_entries = (I830_RDRAM_ND(rdct) + 1) *
 501                                         MB(ddt[I830_RDRAM_DDT(rdct)]);
 502                         local = 1;
 503                         break;
 504                 default:
 505                         gtt_entries = 0;
 506                         break;
 507                 }
 508         } else {
 509                 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
 510                 case I855_GMCH_GMS_STOLEN_1M:
 511                         gtt_entries = MB(1) - KB(size);
 512                         break;
 513                 case I855_GMCH_GMS_STOLEN_4M:
 514                         gtt_entries = MB(4) - KB(size);
 515                         break;
 516                 case I855_GMCH_GMS_STOLEN_8M:
 517                         gtt_entries = MB(8) - KB(size);
 518                         break;
 519                 case I855_GMCH_GMS_STOLEN_16M:
 520                         gtt_entries = MB(16) - KB(size);
 521                         break;
 522                 case I855_GMCH_GMS_STOLEN_32M:
 523                         gtt_entries = MB(32) - KB(size);
 524                         break;
 525                 case I915_GMCH_GMS_STOLEN_48M:
 526                         /* Check it's really I915G */
 527                         if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB ||
 528                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB ||
 529                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB ||
 530                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB ||
 531                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB ||
 532                             IS_I965 || IS_G33)
 533                                 gtt_entries = MB(48) - KB(size);
 534                         else
 535                                 gtt_entries = 0;
 536                         break;
 537                 case I915_GMCH_GMS_STOLEN_64M:
 538                         /* Check it's really I915G */
 539                         if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB ||
 540                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB ||
 541                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB ||
 542                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB ||
 543                             agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB ||
 544                             IS_I965 || IS_G33)
 545                                 gtt_entries = MB(64) - KB(size);
 546                         else
 547                                 gtt_entries = 0;
 548                         break;
 549                 case G33_GMCH_GMS_STOLEN_128M:
 550                         if (IS_G33)
 551                                 gtt_entries = MB(128) - KB(size);
 552                         else
 553                                 gtt_entries = 0;
 554                         break;
 555                 case G33_GMCH_GMS_STOLEN_256M:
 556                         if (IS_G33)
 557                                 gtt_entries = MB(256) - KB(size);
 558                         else
 559                                 gtt_entries = 0;
 560                         break;
 561                 default:
 562                         gtt_entries = 0;
 563                         break;
 564                 }
 565         }
 566         if (gtt_entries > 0)
 567                 printk(KERN_INFO PFX "Detected %dK %s memory.\n",
 568                        gtt_entries / KB(1), local ? "local" : "stolen");
 569         else
 570                 printk(KERN_INFO PFX
 571                        "No pre-allocated video memory detected.\n");
 572         gtt_entries /= KB(4);
 573
 574         intel_private.gtt_entries = gtt_entries;
 575 }
 576
 577 /* The intel i830 automatically initializes the agp aperture during POST.
 578  * Use the memory already set aside for in the GTT.
 579  */
 580 static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
 581 {
 582         int page_order;
 583         struct aper_size_info_fixed *size;
 584         int num_entries;
 585         u32 temp;
 586
 587         size = agp_bridge->current_size;
 588         page_order = size->page_order;
 589         num_entries = size->num_entries;
 590         agp_bridge->gatt_table_real = NULL;
 591
 592         pci_read_config_dword(intel_private.pcidev,I810_MMADDR,&temp);
 593         temp &= 0xfff80000;
 594
 595         intel_private.registers = ioremap(temp,128 * 4096);
 596         if (!intel_private.registers)
 597                 return -ENOMEM;
 598
 599         temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
 600         global_cache_flush();   /* FIXME: ?? */
 601
 602         /* we have to call this as early as possible after the MMIO base address is known */
 603         intel_i830_init_gtt_entries();
 604
 605         agp_bridge->gatt_table = NULL;
 606
 607         agp_bridge->gatt_bus_addr = temp;
 608
 609         return 0;
 610 }
 611
 612 /* Return the gatt table to a sane state. Use the top of stolen
 613  * memory for the GTT.
 614  */
 615 static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge)
 616 {
 617         return 0;
 618 }
 619
 620 static int intel_i830_fetch_size(void)
 621 {
 622         u16 gmch_ctrl;
 623         struct aper_size_info_fixed *values;
 624
 625         values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
 626
 627         if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB &&
 628             agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) {
 629                 /* 855GM/852GM/865G has 128MB aperture size */
 630                 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
 631                 agp_bridge->aperture_size_idx = 0;
 632                 return values[0].size;
 633         }
 634
 635         pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
 636
 637         if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
 638                 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
 639                 agp_bridge->aperture_size_idx = 0;
 640                 return values[0].size;
 641         } else {
 642                 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1);
 643                 agp_bridge->aperture_size_idx = 1;
 644                 return values[1].size;
 645         }
 646
 647         return 0;
 648 }
 649
 650 static int intel_i830_configure(void)
 651 {
 652         struct aper_size_info_fixed *current_size;
 653         u32 temp;
 654         u16 gmch_ctrl;
 655         int i;
 656
 657         current_size = A_SIZE_FIX(agp_bridge->current_size);
 658
 659         pci_read_config_dword(intel_private.pcidev,I810_GMADDR,&temp);
 660         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 661
 662         pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
 663         gmch_ctrl |= I830_GMCH_ENABLED;
 664         pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl);
 665
 666         writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
 667         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
 668
 669         if (agp_bridge->driver->needs_scratch_page) {
 670                 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
 671                         writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 672                         readl(intel_private.registers+I810_PTE_BASE+(i*4));     /* PCI Posting. */
 673                 }
 674         }
 675
 676         global_cache_flush();
 677         return 0;
 678 }
 679
 680 static void intel_i830_cleanup(void)
 681 {
 682         iounmap(intel_private.registers);
 683 }
 684
 685 static int intel_i830_insert_entries(struct agp_memory *mem,off_t pg_start, int type)
 686 {
 687         int i,j,num_entries;
 688         void *temp;
 689         int ret = -EINVAL;
 690         int mask_type;
 691
 692         if (mem->page_count == 0)
 693                 goto out;
 694
 695         temp = agp_bridge->current_size;
 696         num_entries = A_SIZE_FIX(temp)->num_entries;
 697
 698         if (pg_start < intel_private.gtt_entries) {
 699                 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_private.gtt_entries == 0x%.8x\n",
 700                                 pg_start,intel_private.gtt_entries);
 701
 702                 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n");
 703                 goto out_err;
 704         }
 705
 706         if ((pg_start + mem->page_count) > num_entries)
 707                 goto out_err;
 708
 709         /* The i830 can't check the GTT for entries since its read only,
 710          * depend on the caller to make the correct offset decisions.
 711          */
 712
 713         if (type != mem->type)
 714                 goto out_err;
 715
 716         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
 717
 718         if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
 719             mask_type != INTEL_AGP_CACHED_MEMORY)
 720                 goto out_err;
 721
 722         if (!mem->is_flushed)
 723                 global_cache_flush();
 724
 725         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 726                 writel(agp_bridge->driver->mask_memory(agp_bridge,
 727                                                        mem->memory[i], mask_type),
 728                        intel_private.registers+I810_PTE_BASE+(j*4));
 729         }
 730         readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
 731         agp_bridge->driver->tlb_flush(mem);
 732
 733 out:
 734         ret = 0;
 735 out_err:
 736         mem->is_flushed = 1;
 737         return ret;
 738 }
 739
 740 static int intel_i830_remove_entries(struct agp_memory *mem,off_t pg_start,
 741                                 int type)
 742 {
 743         int i;
 744
 745         if (mem->page_count == 0)
 746                 return 0;
 747
 748         if (pg_start < intel_private.gtt_entries) {
 749                 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n");
 750                 return -EINVAL;
 751         }
 752
 753         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
 754                 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
 755         }
 756         readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
 757
 758         agp_bridge->driver->tlb_flush(mem);
 759         return 0;
 760 }
 761
 762 static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count,int type)
 763 {
 764         if (type == AGP_PHYS_MEMORY)
 765                 return alloc_agpphysmem_i8xx(pg_count, type);
 766         /* always return NULL for other allocation types for now */
 767         return NULL;
 768 }
 769
 770 static int intel_i915_configure(void)
 771 {
 772         struct aper_size_info_fixed *current_size;
 773         u32 temp;
 774         u16 gmch_ctrl;
 775         int i;
 776
 777         current_size = A_SIZE_FIX(agp_bridge->current_size);
 778
 779         pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp);
 780
 781         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 782
 783         pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
 784         gmch_ctrl |= I830_GMCH_ENABLED;
 785         pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl);
 786
 787         writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
 788         readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
 789
 790         if (agp_bridge->driver->needs_scratch_page) {
 791                 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
 792                         writel(agp_bridge->scratch_page, intel_private.gtt+i);
 793                         readl(intel_private.gtt+i);     /* PCI Posting. */
 794                 }
 795         }
 796
 797         global_cache_flush();
 798         return 0;
 799 }
 800
 801 static void intel_i915_cleanup(void)
 802 {
 803         iounmap(intel_private.gtt);
 804         iounmap(intel_private.registers);
 805 }
 806
 807 static int intel_i915_insert_entries(struct agp_memory *mem,off_t pg_start,
 808                                 int type)
 809 {
 810         int i,j,num_entries;
 811         void *temp;
 812         int ret = -EINVAL;
 813         int mask_type;
 814
 815         if (mem->page_count == 0)
 816                 goto out;
 817
 818         temp = agp_bridge->current_size;
 819         num_entries = A_SIZE_FIX(temp)->num_entries;
 820
 821         if (pg_start < intel_private.gtt_entries) {
 822                 printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_private.gtt_entries == 0x%.8x\n",
 823                                 pg_start,intel_private.gtt_entries);
 824
 825                 printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n");
 826                 goto out_err;
 827         }
 828
 829         if ((pg_start + mem->page_count) > num_entries)
 830                 goto out_err;
 831
 832         /* The i915 can't check the GTT for entries since its read only,
 833          * depend on the caller to make the correct offset decisions.
 834          */
 835
 836         if (type != mem->type)
 837                 goto out_err;
 838
 839         mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
 840
 841         if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
 842             mask_type != INTEL_AGP_CACHED_MEMORY)
 843                 goto out_err;
 844
 845         if (!mem->is_flushed)
 846                 global_cache_flush();
 847
 848         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 849                 writel(agp_bridge->driver->mask_memory(agp_bridge,
 850                         mem->memory[i], mask_type), intel_private.gtt+j);
 851         }
 852
 853         readl(intel_private.gtt+j-1);
 854         agp_bridge->driver->tlb_flush(mem);
 855
 856  out:
 857         ret = 0;
 858  out_err:
 859         mem->is_flushed = 1;
 860         return ret;
 861 }
 862
 863 static int intel_i915_remove_entries(struct agp_memory *mem,off_t pg_start,
 864                                 int type)
 865 {
 866         int i;
 867
 868         if (mem->page_count == 0)
 869                 return 0;
 870
 871         if (pg_start < intel_private.gtt_entries) {
 872                 printk (KERN_INFO PFX "Trying to disable local/stolen memory\n");
 873                 return -EINVAL;
 874         }
 875
 876         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
 877                 writel(agp_bridge->scratch_page, intel_private.gtt+i);
 878         }
 879         readl(intel_private.gtt+i-1);
 880
 881         agp_bridge->driver->tlb_flush(mem);
 882         return 0;
 883 }
 884
 885 /* Return the aperture size by just checking the resource length.  The effect
 886  * described in the spec of the MSAC registers is just changing of the
 887  * resource size.
 888  */
 889 static int intel_i9xx_fetch_size(void)
 890 {
 891         int num_sizes = ARRAY_SIZE(intel_i830_sizes);
 892         int aper_size; /* size in megabytes */
 893         int i;
 894
 895         aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1);
 896
 897         for (i = 0; i < num_sizes; i++) {
 898                 if (aper_size == intel_i830_sizes[i].size) {
 899                         agp_bridge->current_size = intel_i830_sizes + i;
 900                         agp_bridge->previous_size = agp_bridge->current_size;
 901                         return aper_size;
 902                 }
 903         }
 904
 905         return 0;
 906 }
 907
 908 /* The intel i915 automatically initializes the agp aperture during POST.
 909  * Use the memory already set aside for in the GTT.
 910  */
 911 static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
 912 {
 913         int page_order;
 914         struct aper_size_info_fixed *size;
 915         int num_entries;
 916         u32 temp, temp2;
 917
 918         size = agp_bridge->current_size;
 919         page_order = size->page_order;
 920         num_entries = size->num_entries;
 921         agp_bridge->gatt_table_real = NULL;
 922
 923         pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
 924         pci_read_config_dword(intel_private.pcidev, I915_PTEADDR,&temp2);
 925
 926         intel_private.gtt = ioremap(temp2, 256 * 1024);
 927         if (!intel_private.gtt)
 928                 return -ENOMEM;
 929
 930         temp &= 0xfff80000;
 931
 932         intel_private.registers = ioremap(temp,128 * 4096);
 933         if (!intel_private.registers)
 934                 return -ENOMEM;
 935
 936         temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
 937         global_cache_flush();   /* FIXME: ? */
 938
 939         /* we have to call this as early as possible after the MMIO base address is known */
 940         intel_i830_init_gtt_entries();
 941
 942         agp_bridge->gatt_table = NULL;
 943
 944         agp_bridge->gatt_bus_addr = temp;
 945
 946         return 0;
 947 }
 948
 949 /*
 950  * The i965 supports 36-bit physical addresses, but to keep
 951  * the format of the GTT the same, the bits that don't fit
 952  * in a 32-bit word are shifted down to bits 4..7.
 953  *
 954  * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
 955  * is always zero on 32-bit architectures, so no need to make
 956  * this conditional.
 957  */
 958 static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
 959         unsigned long addr, int type)
 960 {
 961         /* Shift high bits down */
 962         addr |= (addr >> 28) & 0xf0;
 963
 964         /* Type checking must be done elsewhere */
 965         return addr | bridge->driver->masks[type].mask;
 966 }
 967
 968 /* The intel i965 automatically initializes the agp aperture during POST.
 969  * Use the memory already set aside for in the GTT.
 970  */
 971 static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
 972 {
 973        int page_order;
 974        struct aper_size_info_fixed *size;
 975        int num_entries;
 976        u32 temp;
 977
 978        size = agp_bridge->current_size;
 979        page_order = size->page_order;
 980        num_entries = size->num_entries;
 981        agp_bridge->gatt_table_real = NULL;
 982
 983        pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
 984
 985        temp &= 0xfff00000;
 986        intel_private.gtt = ioremap((temp + (512 * 1024)) , 512 * 1024);
 987
 988        if (!intel_private.gtt)
 989                return -ENOMEM;
 990
 991
 992        intel_private.registers = ioremap(temp,128 * 4096);
 993        if (!intel_private.registers)
 994                return -ENOMEM;
 995
 996        temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
 997        global_cache_flush();   /* FIXME: ? */
 998
 999        /* we have to call this as early as possible after the MMIO base address is known */
1000        intel_i830_init_gtt_entries();
1001
1002        agp_bridge->gatt_table = NULL;
1003
1004        agp_bridge->gatt_bus_addr = temp;
1005
1006        return 0;
1007 }
1008
1009
1010 static int intel_fetch_size(void)
1011 {
1012         int i;
1013         u16 temp;
1014         struct aper_size_info_16 *values;
1015
1016         pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);
1017         values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
1018
1019         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1020                 if (temp == values[i].size_value) {
1021                         agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
1022                         agp_bridge->aperture_size_idx = i;
1023                         return values[i].size;
1024                 }
1025         }
1026
1027         return 0;
1028 }
1029
1030 static int __intel_8xx_fetch_size(u8 temp)
1031 {
1032         int i;
1033         struct aper_size_info_8 *values;
1034
1035         values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
1036
1037         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1038                 if (temp == values[i].size_value) {
1039                         agp_bridge->previous_size =
1040                                 agp_bridge->current_size = (void *) (values + i);
1041                         agp_bridge->aperture_size_idx = i;
1042                         return values[i].size;
1043                 }
1044         }
1045         return 0;
1046 }
1047
1048 static int intel_8xx_fetch_size(void)
1049 {
1050         u8 temp;
1051
1052         pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1053         return __intel_8xx_fetch_size(temp);
1054 }
1055
1056 static int intel_815_fetch_size(void)
1057 {
1058         u8 temp;
1059
1060         /* Intel 815 chipsets have a _weird_ APSIZE register with only
1061          * one non-reserved bit, so mask the others out ... */
1062         pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1063         temp &= (1 << 3);
1064
1065         return __intel_8xx_fetch_size(temp);
1066 }
1067
1068 static void intel_tlbflush(struct agp_memory *mem)
1069 {
1070         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);
1071         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1072 }
1073
1074
1075 static void intel_8xx_tlbflush(struct agp_memory *mem)
1076 {
1077         u32 temp;
1078         pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1079         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7));
1080         pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1081         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7));
1082 }
1083
1084
1085 static void intel_cleanup(void)
1086 {
1087         u16 temp;
1088         struct aper_size_info_16 *previous_size;
1089
1090         previous_size = A_SIZE_16(agp_bridge->previous_size);
1091         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1092         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1093         pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1094 }
1095
1096
1097 static void intel_8xx_cleanup(void)
1098 {
1099         u16 temp;
1100         struct aper_size_info_8 *previous_size;
1101
1102         previous_size = A_SIZE_8(agp_bridge->previous_size);
1103         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1104         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1105         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1106 }
1107
1108
1109 static int intel_configure(void)
1110 {
1111         u32 temp;
1112         u16 temp2;
1113         struct aper_size_info_16 *current_size;
1114
1115         current_size = A_SIZE_16(agp_bridge->current_size);
1116
1117         /* aperture size */
1118         pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1119
1120         /* address to map to */
1121         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1122         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1123
1124         /* attbase - aperture base */
1125         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1126
1127         /* agpctrl */
1128         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1129
1130         /* paccfg/nbxcfg */
1131         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1132         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG,
1133                         (temp2 & ~(1 << 10)) | (1 << 9));
1134         /* clear any possible error conditions */
1135         pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7);
1136         return 0;
1137 }
1138
1139 static int intel_815_configure(void)
1140 {
1141         u32 temp, addr;
1142         u8 temp2;
1143         struct aper_size_info_8 *current_size;
1144
1145         /* attbase - aperture base */
1146         /* the Intel 815 chipset spec. says that bits 29-31 in the
1147         * ATTBASE register are reserved -> try not to write them */
1148         if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) {
1149                 printk (KERN_EMERG PFX "gatt bus addr too high");
1150                 return -EINVAL;
1151         }
1152
1153         current_size = A_SIZE_8(agp_bridge->current_size);
1154
1155         /* aperture size */
1156         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1157                         current_size->size_value);
1158
1159         /* address to map to */
1160         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1161         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1162
1163         pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);
1164         addr &= INTEL_815_ATTBASE_MASK;
1165         addr |= agp_bridge->gatt_bus_addr;
1166         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr);
1167
1168         /* agpctrl */
1169         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1170
1171         /* apcont */
1172         pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2);
1173         pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1));
1174
1175         /* clear any possible error conditions */
1176         /* Oddness : this chipset seems to have no ERRSTS register ! */
1177         return 0;
1178 }
1179
1180 static void intel_820_tlbflush(struct agp_memory *mem)
1181 {
1182         return;
1183 }
1184
1185 static void intel_820_cleanup(void)
1186 {
1187         u8 temp;
1188         struct aper_size_info_8 *previous_size;
1189
1190         previous_size = A_SIZE_8(agp_bridge->previous_size);
1191         pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp);
1192         pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR,
1193                         temp & ~(1 << 1));
1194         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1195                         previous_size->size_value);
1196 }
1197
1198
1199 static int intel_820_configure(void)
1200 {
1201         u32 temp;
1202         u8 temp2;
1203         struct aper_size_info_8 *current_size;
1204
1205         current_size = A_SIZE_8(agp_bridge->current_size);
1206
1207         /* aperture size */
1208         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1209
1210         /* address to map to */
1211         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1212         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1213
1214         /* attbase - aperture base */
1215         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1216
1217         /* agpctrl */
1218         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1219
1220         /* global enable aperture access */
1221         /* This flag is not accessed through MCHCFG register as in */
1222         /* i850 chipset. */
1223         pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2);
1224         pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1));
1225         /* clear any possible AGP-related error conditions */
1226         pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c);
1227         return 0;
1228 }
1229
1230 static int intel_840_configure(void)
1231 {
1232         u32 temp;
1233         u16 temp2;
1234         struct aper_size_info_8 *current_size;
1235
1236         current_size = A_SIZE_8(agp_bridge->current_size);
1237
1238         /* aperture size */
1239         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1240
1241         /* address to map to */
1242         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1243         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1244
1245         /* attbase - aperture base */
1246         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1247
1248         /* agpctrl */
1249         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1250
1251         /* mcgcfg */
1252         pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2);
1253         pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9));
1254         /* clear any possible error conditions */
1255         pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000);
1256         return 0;
1257 }
1258
1259 static int intel_845_configure(void)
1260 {
1261         u32 temp;
1262         u8 temp2;
1263         struct aper_size_info_8 *current_size;
1264
1265         current_size = A_SIZE_8(agp_bridge->current_size);
1266
1267         /* aperture size */
1268         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1269
1270         if (agp_bridge->apbase_config != 0) {
1271                 pci_write_config_dword(agp_bridge->dev, AGP_APBASE,
1272                                        agp_bridge->apbase_config);
1273         } else {
1274                 /* address to map to */
1275                 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1276                 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1277                 agp_bridge->apbase_config = temp;
1278         }
1279
1280         /* attbase - aperture base */
1281         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1282
1283         /* agpctrl */
1284         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1285
1286         /* agpm */
1287         pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2);
1288         pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));
1289         /* clear any possible error conditions */
1290         pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);
1291         return 0;
1292 }
1293
1294 static int intel_850_configure(void)
1295 {
1296         u32 temp;
1297         u16 temp2;
1298         struct aper_size_info_8 *current_size;
1299
1300         current_size = A_SIZE_8(agp_bridge->current_size);
1301
1302         /* aperture size */
1303         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1304
1305         /* address to map to */
1306         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1307         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1308
1309         /* attbase - aperture base */
1310         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1311
1312         /* agpctrl */
1313         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1314
1315         /* mcgcfg */
1316         pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2);
1317         pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9));
1318         /* clear any possible AGP-related error conditions */
1319         pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c);
1320         return 0;
1321 }
1322
1323 static int intel_860_configure(void)
1324 {
1325         u32 temp;
1326         u16 temp2;
1327         struct aper_size_info_8 *current_size;
1328
1329         current_size = A_SIZE_8(agp_bridge->current_size);
1330
1331         /* aperture size */
1332         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1333
1334         /* address to map to */
1335         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1336         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1337
1338         /* attbase - aperture base */
1339         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1340
1341         /* agpctrl */
1342         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1343
1344         /* mcgcfg */
1345         pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2);
1346         pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9));
1347         /* clear any possible AGP-related error conditions */
1348         pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700);
1349         return 0;
1350 }
1351
1352 static int intel_830mp_configure(void)
1353 {
1354         u32 temp;
1355         u16 temp2;
1356         struct aper_size_info_8 *current_size;
1357
1358         current_size = A_SIZE_8(agp_bridge->current_size);
1359
1360         /* aperture size */
1361         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1362
1363         /* address to map to */
1364         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1365         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1366
1367         /* attbase - aperture base */
1368         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1369
1370         /* agpctrl */
1371         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1372
1373         /* gmch */
1374         pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1375         pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9));
1376         /* clear any possible AGP-related error conditions */
1377         pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c);
1378         return 0;
1379 }
1380
1381 static int intel_7505_configure(void)
1382 {
1383         u32 temp;
1384         u16 temp2;
1385         struct aper_size_info_8 *current_size;
1386
1387         current_size = A_SIZE_8(agp_bridge->current_size);
1388
1389         /* aperture size */
1390         pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1391
1392         /* address to map to */
1393         pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1394         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1395
1396         /* attbase - aperture base */
1397         pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1398
1399         /* agpctrl */
1400         pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1401
1402         /* mchcfg */
1403         pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2);
1404         pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9));
1405
1406         return 0;
1407 }
1408
1409 /* Setup function */
1410 static const struct gatt_mask intel_generic_masks[] =
1411 {
1412         {.mask = 0x00000017, .type = 0}
1413 };
1414
1415 static const struct aper_size_info_8 intel_815_sizes[2] =
1416 {
1417         {64, 16384, 4, 0},
1418         {32, 8192, 3, 8},
1419 };
1420
1421 static const struct aper_size_info_8 intel_8xx_sizes[7] =
1422 {
1423         {256, 65536, 6, 0},
1424         {128, 32768, 5, 32},
1425         {64, 16384, 4, 48},
1426         {32, 8192, 3, 56},
1427         {16, 4096, 2, 60},
1428         {8, 2048, 1, 62},
1429         {4, 1024, 0, 63}
1430 };
1431
1432 static const struct aper_size_info_16 intel_generic_sizes[7] =
1433 {
1434         {256, 65536, 6, 0},
1435         {128, 32768, 5, 32},
1436         {64, 16384, 4, 48},
1437         {32, 8192, 3, 56},
1438         {16, 4096, 2, 60},
1439         {8, 2048, 1, 62},
1440         {4, 1024, 0, 63}
1441 };
1442
1443 static const struct aper_size_info_8 intel_830mp_sizes[4] =
1444 {
1445         {256, 65536, 6, 0},
1446         {128, 32768, 5, 32},
1447         {64, 16384, 4, 48},
1448         {32, 8192, 3, 56}
1449 };
1450
1451 static const struct agp_bridge_driver intel_generic_driver = {
1452         .owner                  = THIS_MODULE,
1453         .aperture_sizes         = intel_generic_sizes,
1454         .size_type              = U16_APER_SIZE,
1455         .num_aperture_sizes     = 7,
1456         .configure              = intel_configure,
1457         .fetch_size             = intel_fetch_size,
1458         .cleanup                = intel_cleanup,
1459         .tlb_flush              = intel_tlbflush,
1460         .mask_memory            = agp_generic_mask_memory,
1461         .masks                  = intel_generic_masks,
1462         .agp_enable             = agp_generic_enable,
1463         .cache_flush            = global_cache_flush,
1464         .create_gatt_table      = agp_generic_create_gatt_table,
1465         .free_gatt_table        = agp_generic_free_gatt_table,
1466         .insert_memory          = agp_generic_insert_memory,
1467         .remove_memory          = agp_generic_remove_memory,
1468         .alloc_by_type          = agp_generic_alloc_by_type,
1469         .free_by_type           = agp_generic_free_by_type,
1470         .agp_alloc_page         = agp_generic_alloc_page,
1471         .agp_destroy_page       = agp_generic_destroy_page,
1472         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1473 };
1474
1475 static const struct agp_bridge_driver intel_810_driver = {
1476         .owner                  = THIS_MODULE,
1477         .aperture_sizes         = intel_i810_sizes,
1478         .size_type              = FIXED_APER_SIZE,
1479         .num_aperture_sizes     = 2,
1480         .needs_scratch_page     = TRUE,
1481         .configure              = intel_i810_configure,
1482         .fetch_size             = intel_i810_fetch_size,
1483         .cleanup                = intel_i810_cleanup,
1484         .tlb_flush              = intel_i810_tlbflush,
1485         .mask_memory            = intel_i810_mask_memory,
1486         .masks                  = intel_i810_masks,
1487         .agp_enable             = intel_i810_agp_enable,
1488         .cache_flush            = global_cache_flush,
1489         .create_gatt_table      = agp_generic_create_gatt_table,
1490         .free_gatt_table        = agp_generic_free_gatt_table,
1491         .insert_memory          = intel_i810_insert_entries,
1492         .remove_memory          = intel_i810_remove_entries,
1493         .alloc_by_type          = intel_i810_alloc_by_type,
1494         .free_by_type           = intel_i810_free_by_type,
1495         .agp_alloc_page         = agp_generic_alloc_page,
1496         .agp_destroy_page       = agp_generic_destroy_page,
1497         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1498 };
1499
1500 static const struct agp_bridge_driver intel_815_driver = {
1501         .owner                  = THIS_MODULE,
1502         .aperture_sizes         = intel_815_sizes,
1503         .size_type              = U8_APER_SIZE,
1504         .num_aperture_sizes     = 2,
1505         .configure              = intel_815_configure,
1506         .fetch_size             = intel_815_fetch_size,
1507         .cleanup                = intel_8xx_cleanup,
1508         .tlb_flush              = intel_8xx_tlbflush,
1509         .mask_memory            = agp_generic_mask_memory,
1510         .masks                  = intel_generic_masks,
1511         .agp_enable             = agp_generic_enable,
1512         .cache_flush            = global_cache_flush,
1513         .create_gatt_table      = agp_generic_create_gatt_table,
1514         .free_gatt_table        = agp_generic_free_gatt_table,
1515         .insert_memory          = agp_generic_insert_memory,
1516         .remove_memory          = agp_generic_remove_memory,
1517         .alloc_by_type          = agp_generic_alloc_by_type,
1518         .free_by_type           = agp_generic_free_by_type,
1519         .agp_alloc_page         = agp_generic_alloc_page,
1520         .agp_destroy_page       = agp_generic_destroy_page,
1521         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1522 };
1523
1524 static const struct agp_bridge_driver intel_830_driver = {
1525         .owner                  = THIS_MODULE,
1526         .aperture_sizes         = intel_i830_sizes,
1527         .size_type              = FIXED_APER_SIZE,
1528         .num_aperture_sizes     = 4,
1529         .needs_scratch_page     = TRUE,
1530         .configure              = intel_i830_configure,
1531         .fetch_size             = intel_i830_fetch_size,
1532         .cleanup                = intel_i830_cleanup,
1533         .tlb_flush              = intel_i810_tlbflush,
1534         .mask_memory            = intel_i810_mask_memory,
1535         .masks                  = intel_i810_masks,
1536         .agp_enable             = intel_i810_agp_enable,
1537         .cache_flush            = global_cache_flush,
1538         .create_gatt_table      = intel_i830_create_gatt_table,
1539         .free_gatt_table        = intel_i830_free_gatt_table,
1540         .insert_memory          = intel_i830_insert_entries,
1541         .remove_memory          = intel_i830_remove_entries,
1542         .alloc_by_type          = intel_i830_alloc_by_type,
1543         .free_by_type           = intel_i810_free_by_type,
1544         .agp_alloc_page         = agp_generic_alloc_page,
1545         .agp_destroy_page       = agp_generic_destroy_page,
1546         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1547 };
1548
1549 static const struct agp_bridge_driver intel_820_driver = {
1550         .owner                  = THIS_MODULE,
1551         .aperture_sizes         = intel_8xx_sizes,
1552         .size_type              = U8_APER_SIZE,
1553         .num_aperture_sizes     = 7,
1554         .configure              = intel_820_configure,
1555         .fetch_size             = intel_8xx_fetch_size,
1556         .cleanup                = intel_820_cleanup,
1557         .tlb_flush              = intel_820_tlbflush,
1558         .mask_memory            = agp_generic_mask_memory,
1559         .masks                  = intel_generic_masks,
1560         .agp_enable             = agp_generic_enable,
1561         .cache_flush            = global_cache_flush,
1562         .create_gatt_table      = agp_generic_create_gatt_table,
1563         .free_gatt_table        = agp_generic_free_gatt_table,
1564         .insert_memory          = agp_generic_insert_memory,
1565         .remove_memory          = agp_generic_remove_memory,
1566         .alloc_by_type          = agp_generic_alloc_by_type,
1567         .free_by_type           = agp_generic_free_by_type,
1568         .agp_alloc_page         = agp_generic_alloc_page,
1569         .agp_destroy_page       = agp_generic_destroy_page,
1570         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1571 };
1572
1573 static const struct agp_bridge_driver intel_830mp_driver = {
1574         .owner                  = THIS_MODULE,
1575         .aperture_sizes         = intel_830mp_sizes,
1576         .size_type              = U8_APER_SIZE,
1577         .num_aperture_sizes     = 4,
1578         .configure              = intel_830mp_configure,
1579         .fetch_size             = intel_8xx_fetch_size,
1580         .cleanup                = intel_8xx_cleanup,
1581         .tlb_flush              = intel_8xx_tlbflush,
1582         .mask_memory            = agp_generic_mask_memory,
1583         .masks                  = intel_generic_masks,
1584         .agp_enable             = agp_generic_enable,
1585         .cache_flush            = global_cache_flush,
1586         .create_gatt_table      = agp_generic_create_gatt_table,
1587         .free_gatt_table        = agp_generic_free_gatt_table,
1588         .insert_memory          = agp_generic_insert_memory,
1589         .remove_memory          = agp_generic_remove_memory,
1590         .alloc_by_type          = agp_generic_alloc_by_type,
1591         .free_by_type           = agp_generic_free_by_type,
1592         .agp_alloc_page         = agp_generic_alloc_page,
1593         .agp_destroy_page       = agp_generic_destroy_page,
1594         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1595 };
1596
1597 static const struct agp_bridge_driver intel_840_driver = {
1598         .owner                  = THIS_MODULE,
1599         .aperture_sizes         = intel_8xx_sizes,
1600         .size_type              = U8_APER_SIZE,
1601         .num_aperture_sizes     = 7,
1602         .configure              = intel_840_configure,
1603         .fetch_size             = intel_8xx_fetch_size,
1604         .cleanup                = intel_8xx_cleanup,
1605         .tlb_flush              = intel_8xx_tlbflush,
1606         .mask_memory            = agp_generic_mask_memory,
1607         .masks                  = intel_generic_masks,
1608         .agp_enable             = agp_generic_enable,
1609         .cache_flush            = global_cache_flush,
1610         .create_gatt_table      = agp_generic_create_gatt_table,
1611         .free_gatt_table        = agp_generic_free_gatt_table,
1612         .insert_memory          = agp_generic_insert_memory,
1613         .remove_memory          = agp_generic_remove_memory,
1614         .alloc_by_type          = agp_generic_alloc_by_type,
1615         .free_by_type           = agp_generic_free_by_type,
1616         .agp_alloc_page         = agp_generic_alloc_page,
1617         .agp_destroy_page       = agp_generic_destroy_page,
1618         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1619 };
1620
1621 static const struct agp_bridge_driver intel_845_driver = {
1622         .owner                  = THIS_MODULE,
1623         .aperture_sizes         = intel_8xx_sizes,
1624         .size_type              = U8_APER_SIZE,
1625         .num_aperture_sizes     = 7,
1626         .configure              = intel_845_configure,
1627         .fetch_size             = intel_8xx_fetch_size,
1628         .cleanup                = intel_8xx_cleanup,
1629         .tlb_flush              = intel_8xx_tlbflush,
1630         .mask_memory            = agp_generic_mask_memory,
1631         .masks                  = intel_generic_masks,
1632         .agp_enable             = agp_generic_enable,
1633         .cache_flush            = global_cache_flush,
1634         .create_gatt_table      = agp_generic_create_gatt_table,
1635         .free_gatt_table        = agp_generic_free_gatt_table,
1636         .insert_memory          = agp_generic_insert_memory,
1637         .remove_memory          = agp_generic_remove_memory,
1638         .alloc_by_type          = agp_generic_alloc_by_type,
1639         .free_by_type           = agp_generic_free_by_type,
1640         .agp_alloc_page         = agp_generic_alloc_page,
1641         .agp_destroy_page       = agp_generic_destroy_page,
1642         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1643 };
1644
1645 static const struct agp_bridge_driver intel_850_driver = {
1646         .owner                  = THIS_MODULE,
1647         .aperture_sizes         = intel_8xx_sizes,
1648         .size_type              = U8_APER_SIZE,
1649         .num_aperture_sizes     = 7,
1650         .configure              = intel_850_configure,
1651         .fetch_size             = intel_8xx_fetch_size,
1652         .cleanup                = intel_8xx_cleanup,
1653         .tlb_flush              = intel_8xx_tlbflush,
1654         .mask_memory            = agp_generic_mask_memory,
1655         .masks                  = intel_generic_masks,
1656         .agp_enable             = agp_generic_enable,
1657         .cache_flush            = global_cache_flush,
1658         .create_gatt_table      = agp_generic_create_gatt_table,
1659         .free_gatt_table        = agp_generic_free_gatt_table,
1660         .insert_memory          = agp_generic_insert_memory,
1661         .remove_memory          = agp_generic_remove_memory,
1662         .alloc_by_type          = agp_generic_alloc_by_type,
1663         .free_by_type           = agp_generic_free_by_type,
1664         .agp_alloc_page         = agp_generic_alloc_page,
1665         .agp_destroy_page       = agp_generic_destroy_page,
1666         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1667 };
1668
1669 static const struct agp_bridge_driver intel_860_driver = {
1670         .owner                  = THIS_MODULE,
1671         .aperture_sizes         = intel_8xx_sizes,
1672         .size_type              = U8_APER_SIZE,
1673         .num_aperture_sizes     = 7,
1674         .configure              = intel_860_configure,
1675         .fetch_size             = intel_8xx_fetch_size,
1676         .cleanup                = intel_8xx_cleanup,
1677         .tlb_flush              = intel_8xx_tlbflush,
1678         .mask_memory            = agp_generic_mask_memory,
1679         .masks                  = intel_generic_masks,
1680         .agp_enable             = agp_generic_enable,
1681         .cache_flush            = global_cache_flush,
1682         .create_gatt_table      = agp_generic_create_gatt_table,
1683         .free_gatt_table        = agp_generic_free_gatt_table,
1684         .insert_memory          = agp_generic_insert_memory,
1685         .remove_memory          = agp_generic_remove_memory,
1686         .alloc_by_type          = agp_generic_alloc_by_type,
1687         .free_by_type           = agp_generic_free_by_type,
1688         .agp_alloc_page         = agp_generic_alloc_page,
1689         .agp_destroy_page       = agp_generic_destroy_page,
1690         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1691 };
1692
1693 static const struct agp_bridge_driver intel_915_driver = {
1694         .owner                  = THIS_MODULE,
1695         .aperture_sizes         = intel_i830_sizes,
1696         .size_type              = FIXED_APER_SIZE,
1697         .num_aperture_sizes     = 4,
1698         .needs_scratch_page     = TRUE,
1699         .configure              = intel_i915_configure,
1700         .fetch_size             = intel_i9xx_fetch_size,
1701         .cleanup                = intel_i915_cleanup,
1702         .tlb_flush              = intel_i810_tlbflush,
1703         .mask_memory            = intel_i810_mask_memory,
1704         .masks                  = intel_i810_masks,
1705         .agp_enable             = intel_i810_agp_enable,
1706         .cache_flush            = global_cache_flush,
1707         .create_gatt_table      = intel_i915_create_gatt_table,
1708         .free_gatt_table        = intel_i830_free_gatt_table,
1709         .insert_memory          = intel_i915_insert_entries,
1710         .remove_memory          = intel_i915_remove_entries,
1711         .alloc_by_type          = intel_i830_alloc_by_type,
1712         .free_by_type           = intel_i810_free_by_type,
1713         .agp_alloc_page         = agp_generic_alloc_page,
1714         .agp_destroy_page       = agp_generic_destroy_page,
1715         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1716 };
1717
1718 static const struct agp_bridge_driver intel_i965_driver = {
1719        .owner                  = THIS_MODULE,
1720        .aperture_sizes         = intel_i830_sizes,
1721        .size_type              = FIXED_APER_SIZE,
1722        .num_aperture_sizes     = 4,
1723        .needs_scratch_page     = TRUE,
1724        .configure              = intel_i915_configure,
1725        .fetch_size             = intel_i9xx_fetch_size,
1726        .cleanup                = intel_i915_cleanup,
1727        .tlb_flush              = intel_i810_tlbflush,
1728        .mask_memory            = intel_i965_mask_memory,
1729        .masks                  = intel_i810_masks,
1730        .agp_enable             = intel_i810_agp_enable,
1731        .cache_flush            = global_cache_flush,
1732        .create_gatt_table      = intel_i965_create_gatt_table,
1733        .free_gatt_table        = intel_i830_free_gatt_table,
1734        .insert_memory          = intel_i915_insert_entries,
1735        .remove_memory          = intel_i915_remove_entries,
1736        .alloc_by_type          = intel_i830_alloc_by_type,
1737        .free_by_type           = intel_i810_free_by_type,
1738        .agp_alloc_page         = agp_generic_alloc_page,
1739        .agp_destroy_page       = agp_generic_destroy_page,
1740        .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1741 };
1742
1743 static const struct agp_bridge_driver intel_7505_driver = {
1744         .owner                  = THIS_MODULE,
1745         .aperture_sizes         = intel_8xx_sizes,
1746         .size_type              = U8_APER_SIZE,
1747         .num_aperture_sizes     = 7,
1748         .configure              = intel_7505_configure,
1749         .fetch_size             = intel_8xx_fetch_size,
1750         .cleanup                = intel_8xx_cleanup,
1751         .tlb_flush              = intel_8xx_tlbflush,
1752         .mask_memory            = agp_generic_mask_memory,
1753         .masks                  = intel_generic_masks,
1754         .agp_enable             = agp_generic_enable,
1755         .cache_flush            = global_cache_flush,
1756         .create_gatt_table      = agp_generic_create_gatt_table,
1757         .free_gatt_table        = agp_generic_free_gatt_table,
1758         .insert_memory          = agp_generic_insert_memory,
1759         .remove_memory          = agp_generic_remove_memory,
1760         .alloc_by_type          = agp_generic_alloc_by_type,
1761         .free_by_type           = agp_generic_free_by_type,
1762         .agp_alloc_page         = agp_generic_alloc_page,
1763         .agp_destroy_page       = agp_generic_destroy_page,
1764         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
1765 };
1766
1767 static const struct agp_bridge_driver intel_g33_driver = {
1768         .owner                  = THIS_MODULE,
1769         .aperture_sizes         = intel_i830_sizes,
1770         .size_type              = FIXED_APER_SIZE,
1771         .num_aperture_sizes     = 4,
1772         .needs_scratch_page     = TRUE,
1773         .configure              = intel_i915_configure,
1774         .fetch_size             = intel_i9xx_fetch_size,
1775         .cleanup                = intel_i915_cleanup,
1776         .tlb_flush              = intel_i810_tlbflush,
1777         .mask_memory            = intel_i965_mask_memory,
1778         .masks                  = intel_i810_masks,
1779         .agp_enable             = intel_i810_agp_enable,
1780         .cache_flush            = global_cache_flush,
1781         .create_gatt_table      = intel_i915_create_gatt_table,
1782         .free_gatt_table        = intel_i830_free_gatt_table,
1783         .insert_memory          = intel_i915_insert_entries,
1784         .remove_memory          = intel_i915_remove_entries,
1785         .alloc_by_type          = intel_i830_alloc_by_type,
1786         .free_by_type           = intel_i810_free_by_type,
1787         .agp_alloc_page         = agp_generic_alloc_page,
1788         .agp_destroy_page       = agp_generic_destroy_page,
1789         .agp_type_to_mask_type  = intel_i830_type_to_mask_type,
1790 };
1791
1792 static int find_gmch(u16 device)
1793 {
1794         struct pci_dev *gmch_device;
1795
1796         gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
1797         if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
1798                 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
1799                                 device, gmch_device);
1800         }
1801
1802         if (!gmch_device)
1803                 return 0;
1804
1805         intel_private.pcidev = gmch_device;
1806         return 1;
1807 }
1808
1809 /* Table to describe Intel GMCH and AGP/PCIE GART drivers.  At least one of
1810  * driver and gmch_driver must be non-null, and find_gmch will determine
1811  * which one should be used if a gmch_chip_id is present.
1812  */
1813 static const struct intel_driver_description {
1814         unsigned int chip_id;
1815         unsigned int gmch_chip_id;
1816         unsigned int multi_gmch_chip; /* if we have more gfx chip type on this HB. */
1817         char *name;
1818         const struct agp_bridge_driver *driver;
1819         const struct agp_bridge_driver *gmch_driver;
1820 } intel_agp_chipsets[] = {
1821         { PCI_DEVICE_ID_INTEL_82443LX_0, 0, 0, "440LX", &intel_generic_driver, NULL },
1822         { PCI_DEVICE_ID_INTEL_82443BX_0, 0, 0, "440BX", &intel_generic_driver, NULL },
1823         { PCI_DEVICE_ID_INTEL_82443GX_0, 0, 0, "440GX", &intel_generic_driver, NULL },
1824         { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, 0, "i810",
1825                 NULL, &intel_810_driver },
1826         { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, 0, "i810",
1827                 NULL, &intel_810_driver },
1828         { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, 0, "i810",
1829                 NULL, &intel_810_driver },
1830         { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, 0, "i815",
1831                 &intel_815_driver, &intel_810_driver },
1832         { PCI_DEVICE_ID_INTEL_82820_HB, 0, 0, "i820", &intel_820_driver, NULL },
1833         { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, 0, "i820", &intel_820_driver, NULL },
1834         { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, 0, "830M",
1835                 &intel_830mp_driver, &intel_830_driver },
1836         { PCI_DEVICE_ID_INTEL_82840_HB, 0, 0, "i840", &intel_840_driver, NULL },
1837         { PCI_DEVICE_ID_INTEL_82845_HB, 0, 0, "845G", &intel_845_driver, NULL },
1838         { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, 0, "830M",
1839                 &intel_845_driver, &intel_830_driver },
1840         { PCI_DEVICE_ID_INTEL_82850_HB, 0, 0, "i850", &intel_850_driver, NULL },
1841         { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, 0, "855PM", &intel_845_driver, NULL },
1842         { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, 0, "855GM",
1843                 &intel_845_driver, &intel_830_driver },
1844         { PCI_DEVICE_ID_INTEL_82860_HB, 0, 0, "i860", &intel_860_driver, NULL },
1845         { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, 0, "865",
1846                 &intel_845_driver, &intel_830_driver },
1847         { PCI_DEVICE_ID_INTEL_82875_HB, 0, 0, "i875", &intel_845_driver, NULL },
1848         { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, 0, "915G",
1849                 NULL, &intel_915_driver },
1850         { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, 0, "915GM",
1851                 NULL, &intel_915_driver },
1852         { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, 0, "945G",
1853                 NULL, &intel_915_driver },
1854         { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, 0, "945GM",
1855                 NULL, &intel_915_driver },
1856         { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, 0, "945GME",
1857                 NULL, &intel_915_driver },
1858         { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, 0, "946GZ",
1859                 NULL, &intel_i965_driver },
1860         { PCI_DEVICE_ID_INTEL_82965G_1_HB, PCI_DEVICE_ID_INTEL_82965G_1_IG, 0, "965G",
1861                 NULL, &intel_i965_driver },
1862         { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, 0, "965Q",
1863                 NULL, &intel_i965_driver },
1864         { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, 0, "965G",
1865                 NULL, &intel_i965_driver },
1866         { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, 0, "965GM",
1867                 NULL, &intel_i965_driver },
1868         { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, 0, "965GME/GLE",
1869                 NULL, &intel_i965_driver },
1870         { PCI_DEVICE_ID_INTEL_7505_0, 0, 0, "E7505", &intel_7505_driver, NULL },
1871         { PCI_DEVICE_ID_INTEL_7205_0, 0, 0, "E7205", &intel_7505_driver, NULL },
1872         { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, 0, "G33",
1873                 NULL, &intel_g33_driver },
1874         { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, 0, "Q35",
1875                 NULL, &intel_g33_driver },
1876         { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33",
1877                 NULL, &intel_g33_driver },
1878         { 0, 0, 0, NULL, NULL, NULL }
1879 };
1880
1881 static int __devinit agp_intel_probe(struct pci_dev *pdev,
1882                                      const struct pci_device_id *ent)
1883 {
1884         struct agp_bridge_data *bridge;
1885         u8 cap_ptr = 0;
1886         struct resource *r;
1887         int i;
1888
1889         cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
1890
1891         bridge = agp_alloc_bridge();
1892         if (!bridge)
1893                 return -ENOMEM;
1894
1895         for (i = 0; intel_agp_chipsets[i].name != NULL; i++) {
1896                 /* In case that multiple models of gfx chip may
1897                    stand on same host bridge type, this can be
1898                    sure we detect the right IGD. */
1899                 if (pdev->device == intel_agp_chipsets[i].chip_id) {
1900                         if ((intel_agp_chipsets[i].gmch_chip_id != 0) &&
1901                                 find_gmch(intel_agp_chipsets[i].gmch_chip_id)) {
1902                                 bridge->driver =
1903                                         intel_agp_chipsets[i].gmch_driver;
1904                                 break;
1905                         } else if (intel_agp_chipsets[i].multi_gmch_chip) {
1906                                 continue;
1907                         } else {
1908                                 bridge->driver = intel_agp_chipsets[i].driver;
1909                                 break;
1910                         }
1911                 }
1912         }
1913
1914         if (intel_agp_chipsets[i].name == NULL) {
1915                 if (cap_ptr)
1916                         printk(KERN_WARNING PFX "Unsupported Intel chipset"
1917                                "(device id: %04x)\n", pdev->device);
1918                 agp_put_bridge(bridge);
1919                 return -ENODEV;
1920         }
1921
1922         if (bridge->driver == NULL) {
1923                 /* bridge has no AGP and no IGD detected */
1924                 if (cap_ptr)
1925                         printk(KERN_WARNING PFX "Failed to find bridge device "
1926                                 "(chip_id: %04x)\n",
1927                                 intel_agp_chipsets[i].gmch_chip_id);
1928                 agp_put_bridge(bridge);
1929                 return -ENODEV;
1930         }
1931
1932         bridge->dev = pdev;
1933         bridge->capndx = cap_ptr;
1934         bridge->dev_private_data = &intel_private;
1935
1936         printk(KERN_INFO PFX "Detected an Intel %s Chipset.\n",
1937                 intel_agp_chipsets[i].name);
1938
1939         /*
1940         * The following fixes the case where the BIOS has "forgotten" to
1941         * provide an address range for the GART.
1942         * 20030610 - hamish@zot.org
1943         */
1944         r = &pdev->resource[0];
1945         if (!r->start && r->end) {
1946                 if (pci_assign_resource(pdev, 0)) {
1947                         printk(KERN_ERR PFX "could not assign resource 0\n");
1948                         agp_put_bridge(bridge);
1949                         return -ENODEV;
1950                 }
1951         }
1952
1953         /*
1954         * If the device has not been properly setup, the following will catch
1955         * the problem and should stop the system from crashing.
1956         * 20030610 - hamish@zot.org
1957         */
1958         if (pci_enable_device(pdev)) {
1959                 printk(KERN_ERR PFX "Unable to Enable PCI device\n");
1960                 agp_put_bridge(bridge);
1961                 return -ENODEV;
1962         }
1963
1964         /* Fill in the mode register */
1965         if (cap_ptr) {
1966                 pci_read_config_dword(pdev,
1967                                 bridge->capndx+PCI_AGP_STATUS,
1968                                 &bridge->mode);
1969         }
1970
1971         pci_set_drvdata(pdev, bridge);
1972         return agp_add_bridge(bridge);
1973 }
1974
1975 static void __devexit agp_intel_remove(struct pci_dev *pdev)
1976 {
1977         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
1978
1979         agp_remove_bridge(bridge);
1980
1981         if (intel_private.pcidev)
1982                 pci_dev_put(intel_private.pcidev);
1983
1984         agp_put_bridge(bridge);
1985 }
1986
1987 #ifdef CONFIG_PM
1988 static int agp_intel_resume(struct pci_dev *pdev)
1989 {
1990         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
1991
1992         pci_restore_state(pdev);
1993
1994         /* We should restore our graphics device's config space,
1995          * as host bridge (00:00) resumes before graphics device (02:00),
1996          * then our access to its pci space can work right.
1997          */
1998         if (intel_private.pcidev)
1999                 pci_restore_state(intel_private.pcidev);
2000
2001         if (bridge->driver == &intel_generic_driver)
2002                 intel_configure();
2003         else if (bridge->driver == &intel_850_driver)
2004                 intel_850_configure();
2005         else if (bridge->driver == &intel_845_driver)
2006                 intel_845_configure();
2007         else if (bridge->driver == &intel_830mp_driver)
2008                 intel_830mp_configure();
2009         else if (bridge->driver == &intel_915_driver)
2010                 intel_i915_configure();
2011         else if (bridge->driver == &intel_830_driver)
2012                 intel_i830_configure();
2013         else if (bridge->driver == &intel_810_driver)
2014                 intel_i810_configure();
2015         else if (bridge->driver == &intel_i965_driver)
2016                 intel_i915_configure();
2017
2018         return 0;
2019 }
2020 #endif
2021
2022 static struct pci_device_id agp_intel_pci_table[] = {
2023 #define ID(x)                                           \
2024         {                                               \
2025         .class          = (PCI_CLASS_BRIDGE_HOST << 8), \
2026         .class_mask     = ~0,                           \
2027         .vendor         = PCI_VENDOR_ID_INTEL,          \
2028         .device         = x,                            \
2029         .subvendor      = PCI_ANY_ID,                   \
2030         .subdevice      = PCI_ANY_ID,                   \
2031         }
2032         ID(PCI_DEVICE_ID_INTEL_82443LX_0),
2033         ID(PCI_DEVICE_ID_INTEL_82443BX_0),
2034         ID(PCI_DEVICE_ID_INTEL_82443GX_0),
2035         ID(PCI_DEVICE_ID_INTEL_82810_MC1),
2036         ID(PCI_DEVICE_ID_INTEL_82810_MC3),
2037         ID(PCI_DEVICE_ID_INTEL_82810E_MC),
2038         ID(PCI_DEVICE_ID_INTEL_82815_MC),
2039         ID(PCI_DEVICE_ID_INTEL_82820_HB),
2040         ID(PCI_DEVICE_ID_INTEL_82820_UP_HB),
2041         ID(PCI_DEVICE_ID_INTEL_82830_HB),
2042         ID(PCI_DEVICE_ID_INTEL_82840_HB),
2043         ID(PCI_DEVICE_ID_INTEL_82845_HB),
2044         ID(PCI_DEVICE_ID_INTEL_82845G_HB),
2045         ID(PCI_DEVICE_ID_INTEL_82850_HB),
2046         ID(PCI_DEVICE_ID_INTEL_82855PM_HB),
2047         ID(PCI_DEVICE_ID_INTEL_82855GM_HB),
2048         ID(PCI_DEVICE_ID_INTEL_82860_HB),
2049         ID(PCI_DEVICE_ID_INTEL_82865_HB),
2050         ID(PCI_DEVICE_ID_INTEL_82875_HB),
2051         ID(PCI_DEVICE_ID_INTEL_7505_0),
2052         ID(PCI_DEVICE_ID_INTEL_7205_0),
2053         ID(PCI_DEVICE_ID_INTEL_82915G_HB),
2054         ID(PCI_DEVICE_ID_INTEL_82915GM_HB),
2055         ID(PCI_DEVICE_ID_INTEL_82945G_HB),
2056         ID(PCI_DEVICE_ID_INTEL_82945GM_HB),
2057         ID(PCI_DEVICE_ID_INTEL_82945GME_HB),
2058         ID(PCI_DEVICE_ID_INTEL_82946GZ_HB),
2059         ID(PCI_DEVICE_ID_INTEL_82965G_1_HB),
2060         ID(PCI_DEVICE_ID_INTEL_82965Q_HB),
2061         ID(PCI_DEVICE_ID_INTEL_82965G_HB),
2062         ID(PCI_DEVICE_ID_INTEL_82965GM_HB),
2063         ID(PCI_DEVICE_ID_INTEL_82965GME_HB),
2064         ID(PCI_DEVICE_ID_INTEL_G33_HB),
2065         ID(PCI_DEVICE_ID_INTEL_Q35_HB),
2066         ID(PCI_DEVICE_ID_INTEL_Q33_HB),
2067         { }
2068 };
2069
2070 MODULE_DEVICE_TABLE(pci, agp_intel_pci_table);
2071
2072 static struct pci_driver agp_intel_pci_driver = {
2073         .name           = "agpgart-intel",
2074         .id_table       = agp_intel_pci_table,
2075         .probe          = agp_intel_probe,
2076         .remove         = __devexit_p(agp_intel_remove),
2077 #ifdef CONFIG_PM
2078         .resume         = agp_intel_resume,
2079 #endif
2080 };
2081
2082 static int __init agp_intel_init(void)
2083 {
2084         if (agp_off)
2085                 return -EINVAL;
2086         return pci_register_driver(&agp_intel_pci_driver);
2087 }
2088
2089 static void __exit agp_intel_cleanup(void)
2090 {
2091         pci_unregister_driver(&agp_intel_pci_driver);
2092 }
2093
2094 module_init(agp_intel_init);
2095 module_exit(agp_intel_cleanup);
2096
2097 MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>");
2098 MODULE_LICENSE("GPL and additional rights");