git.oblomov.eu Git - linux-2.6/blob - drivers/infiniband/hw/mthca/mthca_qp.c

   1 /*
   2  * Copyright (c) 2004 Topspin Communications.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  *
  32  * $Id: mthca_qp.c 1355 2004-12-17 15:23:43Z roland $
  33  */
  34
  35 #include <linux/init.h>
  36
  37 #include <ib_verbs.h>
  38 #include <ib_cache.h>
  39 #include <ib_pack.h>
  40
  41 #include "mthca_dev.h"
  42 #include "mthca_cmd.h"
  43 #include "mthca_memfree.h"
  44
  45 enum {
  46         MTHCA_MAX_DIRECT_QP_SIZE = 4 * PAGE_SIZE,
  47         MTHCA_ACK_REQ_FREQ       = 10,
  48         MTHCA_FLIGHT_LIMIT       = 9,
  49         MTHCA_UD_HEADER_SIZE     = 72 /* largest UD header possible */
  50 };
  51
  52 enum {
  53         MTHCA_QP_STATE_RST  = 0,
  54         MTHCA_QP_STATE_INIT = 1,
  55         MTHCA_QP_STATE_RTR  = 2,
  56         MTHCA_QP_STATE_RTS  = 3,
  57         MTHCA_QP_STATE_SQE  = 4,
  58         MTHCA_QP_STATE_SQD  = 5,
  59         MTHCA_QP_STATE_ERR  = 6,
  60         MTHCA_QP_STATE_DRAINING = 7
  61 };
  62
  63 enum {
  64         MTHCA_QP_ST_RC  = 0x0,
  65         MTHCA_QP_ST_UC  = 0x1,
  66         MTHCA_QP_ST_RD  = 0x2,
  67         MTHCA_QP_ST_UD  = 0x3,
  68         MTHCA_QP_ST_MLX = 0x7
  69 };
  70
  71 enum {
  72         MTHCA_QP_PM_MIGRATED = 0x3,
  73         MTHCA_QP_PM_ARMED    = 0x0,
  74         MTHCA_QP_PM_REARM    = 0x1
  75 };
  76
  77 enum {
  78         /* qp_context flags */
  79         MTHCA_QP_BIT_DE  = 1 <<  8,
  80         /* params1 */
  81         MTHCA_QP_BIT_SRE = 1 << 15,
  82         MTHCA_QP_BIT_SWE = 1 << 14,
  83         MTHCA_QP_BIT_SAE = 1 << 13,
  84         MTHCA_QP_BIT_SIC = 1 <<  4,
  85         MTHCA_QP_BIT_SSC = 1 <<  3,
  86         /* params2 */
  87         MTHCA_QP_BIT_RRE = 1 << 15,
  88         MTHCA_QP_BIT_RWE = 1 << 14,
  89         MTHCA_QP_BIT_RAE = 1 << 13,
  90         MTHCA_QP_BIT_RIC = 1 <<  4,
  91         MTHCA_QP_BIT_RSC = 1 <<  3
  92 };
  93
  94 struct mthca_qp_path {
  95         u32 port_pkey;
  96         u8  rnr_retry;
  97         u8  g_mylmc;
  98         u16 rlid;
  99         u8  ackto;
 100         u8  mgid_index;
 101         u8  static_rate;
 102         u8  hop_limit;
 103         u32 sl_tclass_flowlabel;
 104         u8  rgid[16];
 105 } __attribute__((packed));
 106
 107 struct mthca_qp_context {
 108         u32 flags;
 109         u32 tavor_sched_queue;  /* Reserved on Arbel */
 110         u8  mtu_msgmax;
 111         u8  rq_size_stride;     /* Reserved on Tavor */
 112         u8  sq_size_stride;     /* Reserved on Tavor */
 113         u8  rlkey_arbel_sched_queue;    /* Reserved on Tavor */
 114         u32 usr_page;
 115         u32 local_qpn;
 116         u32 remote_qpn;
 117         u32 reserved1[2];
 118         struct mthca_qp_path pri_path;
 119         struct mthca_qp_path alt_path;
 120         u32 rdd;
 121         u32 pd;
 122         u32 wqe_base;
 123         u32 wqe_lkey;
 124         u32 params1;
 125         u32 reserved2;
 126         u32 next_send_psn;
 127         u32 cqn_snd;
 128         u32 snd_wqe_base_l;     /* Next send WQE on Tavor */
 129         u32 snd_db_index;       /* (debugging only entries) */
 130         u32 last_acked_psn;
 131         u32 ssn;
 132         u32 params2;
 133         u32 rnr_nextrecvpsn;
 134         u32 ra_buff_indx;
 135         u32 cqn_rcv;
 136         u32 rcv_wqe_base_l;     /* Next recv WQE on Tavor */
 137         u32 rcv_db_index;       /* (debugging only entries) */
 138         u32 qkey;
 139         u32 srqn;
 140         u32 rmsn;
 141         u16 rq_wqe_counter;     /* reserved on Tavor */
 142         u16 sq_wqe_counter;     /* reserved on Tavor */
 143         u32 reserved3[18];
 144 } __attribute__((packed));
 145
 146 struct mthca_qp_param {
 147         u32 opt_param_mask;
 148         u32 reserved1;
 149         struct mthca_qp_context context;
 150         u32 reserved2[62];
 151 } __attribute__((packed));
 152
 153 enum {
 154         MTHCA_QP_OPTPAR_ALT_ADDR_PATH     = 1 << 0,
 155         MTHCA_QP_OPTPAR_RRE               = 1 << 1,
 156         MTHCA_QP_OPTPAR_RAE               = 1 << 2,
 157         MTHCA_QP_OPTPAR_RWE               = 1 << 3,
 158         MTHCA_QP_OPTPAR_PKEY_INDEX        = 1 << 4,
 159         MTHCA_QP_OPTPAR_Q_KEY             = 1 << 5,
 160         MTHCA_QP_OPTPAR_RNR_TIMEOUT       = 1 << 6,
 161         MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
 162         MTHCA_QP_OPTPAR_SRA_MAX           = 1 << 8,
 163         MTHCA_QP_OPTPAR_RRA_MAX           = 1 << 9,
 164         MTHCA_QP_OPTPAR_PM_STATE          = 1 << 10,
 165         MTHCA_QP_OPTPAR_PORT_NUM          = 1 << 11,
 166         MTHCA_QP_OPTPAR_RETRY_COUNT       = 1 << 12,
 167         MTHCA_QP_OPTPAR_ALT_RNR_RETRY     = 1 << 13,
 168         MTHCA_QP_OPTPAR_ACK_TIMEOUT       = 1 << 14,
 169         MTHCA_QP_OPTPAR_RNR_RETRY         = 1 << 15,
 170         MTHCA_QP_OPTPAR_SCHED_QUEUE       = 1 << 16
 171 };
 172
 173 enum {
 174         MTHCA_NEXT_DBD       = 1 << 7,
 175         MTHCA_NEXT_FENCE     = 1 << 6,
 176         MTHCA_NEXT_CQ_UPDATE = 1 << 3,
 177         MTHCA_NEXT_EVENT_GEN = 1 << 2,
 178         MTHCA_NEXT_SOLICIT   = 1 << 1,
 179
 180         MTHCA_MLX_VL15       = 1 << 17,
 181         MTHCA_MLX_SLR        = 1 << 16
 182 };
 183
 184 enum {
 185         MTHCA_INVAL_LKEY = 0x100
 186 };
 187
 188 struct mthca_next_seg {
 189         u32 nda_op;             /* [31:6] next WQE [4:0] next opcode */
 190         u32 ee_nds;             /* [31:8] next EE  [7] DBD [6] F [5:0] next WQE size */
 191         u32 flags;              /* [3] CQ [2] Event [1] Solicit */
 192         u32 imm;                /* immediate data */
 193 };
 194
 195 struct mthca_tavor_ud_seg {
 196         u32 reserved1;
 197         u32 lkey;
 198         u64 av_addr;
 199         u32 reserved2[4];
 200         u32 dqpn;
 201         u32 qkey;
 202         u32 reserved3[2];
 203 };
 204
 205 struct mthca_arbel_ud_seg {
 206         u32 av[8];
 207         u32 dqpn;
 208         u32 qkey;
 209         u32 reserved[2];
 210 };
 211
 212 struct mthca_bind_seg {
 213         u32 flags;              /* [31] Atomic [30] rem write [29] rem read */
 214         u32 reserved;
 215         u32 new_rkey;
 216         u32 lkey;
 217         u64 addr;
 218         u64 length;
 219 };
 220
 221 struct mthca_raddr_seg {
 222         u64 raddr;
 223         u32 rkey;
 224         u32 reserved;
 225 };
 226
 227 struct mthca_atomic_seg {
 228         u64 swap_add;
 229         u64 compare;
 230 };
 231
 232 struct mthca_data_seg {
 233         u32 byte_count;
 234         u32 lkey;
 235         u64 addr;
 236 };
 237
 238 struct mthca_mlx_seg {
 239         u32 nda_op;
 240         u32 nds;
 241         u32 flags;              /* [17] VL15 [16] SLR [14:12] static rate
 242                                    [11:8] SL [3] C [2] E */
 243         u16 rlid;
 244         u16 vcrc;
 245 };
 246
 247 static const u8 mthca_opcode[] = {
 248         [IB_WR_SEND]                 = MTHCA_OPCODE_SEND,
 249         [IB_WR_SEND_WITH_IMM]        = MTHCA_OPCODE_SEND_IMM,
 250         [IB_WR_RDMA_WRITE]           = MTHCA_OPCODE_RDMA_WRITE,
 251         [IB_WR_RDMA_WRITE_WITH_IMM]  = MTHCA_OPCODE_RDMA_WRITE_IMM,
 252         [IB_WR_RDMA_READ]            = MTHCA_OPCODE_RDMA_READ,
 253         [IB_WR_ATOMIC_CMP_AND_SWP]   = MTHCA_OPCODE_ATOMIC_CS,
 254         [IB_WR_ATOMIC_FETCH_AND_ADD] = MTHCA_OPCODE_ATOMIC_FA,
 255 };
 256
 257 static int is_sqp(struct mthca_dev *dev, struct mthca_qp *qp)
 258 {
 259         return qp->qpn >= dev->qp_table.sqp_start &&
 260                 qp->qpn <= dev->qp_table.sqp_start + 3;
 261 }
 262
 263 static int is_qp0(struct mthca_dev *dev, struct mthca_qp *qp)
 264 {
 265         return qp->qpn >= dev->qp_table.sqp_start &&
 266                 qp->qpn <= dev->qp_table.sqp_start + 1;
 267 }
 268
 269 static void *get_recv_wqe(struct mthca_qp *qp, int n)
 270 {
 271         if (qp->is_direct)
 272                 return qp->queue.direct.buf + (n << qp->rq.wqe_shift);
 273         else
 274                 return qp->queue.page_list[(n << qp->rq.wqe_shift) >> PAGE_SHIFT].buf +
 275                         ((n << qp->rq.wqe_shift) & (PAGE_SIZE - 1));
 276 }
 277
 278 static void *get_send_wqe(struct mthca_qp *qp, int n)
 279 {
 280         if (qp->is_direct)
 281                 return qp->queue.direct.buf + qp->send_wqe_offset +
 282                         (n << qp->sq.wqe_shift);
 283         else
 284                 return qp->queue.page_list[(qp->send_wqe_offset +
 285                                             (n << qp->sq.wqe_shift)) >>
 286                                            PAGE_SHIFT].buf +
 287                         ((qp->send_wqe_offset + (n << qp->sq.wqe_shift)) &
 288                          (PAGE_SIZE - 1));
 289 }
 290
 291 void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
 292                     enum ib_event_type event_type)
 293 {
 294         struct mthca_qp *qp;
 295         struct ib_event event;
 296
 297         spin_lock(&dev->qp_table.lock);
 298         qp = mthca_array_get(&dev->qp_table.qp, qpn & (dev->limits.num_qps - 1));
 299         if (qp)
 300                 atomic_inc(&qp->refcount);
 301         spin_unlock(&dev->qp_table.lock);
 302
 303         if (!qp) {
 304                 mthca_warn(dev, "Async event for bogus QP %08x\n", qpn);
 305                 return;
 306         }
 307
 308         event.device      = &dev->ib_dev;
 309         event.event       = event_type;
 310         event.element.qp  = &qp->ibqp;
 311         if (qp->ibqp.event_handler)
 312                 qp->ibqp.event_handler(&event, qp->ibqp.qp_context);
 313
 314         if (atomic_dec_and_test(&qp->refcount))
 315                 wake_up(&qp->wait);
 316 }
 317
 318 static int to_mthca_state(enum ib_qp_state ib_state)
 319 {
 320         switch (ib_state) {
 321         case IB_QPS_RESET: return MTHCA_QP_STATE_RST;
 322         case IB_QPS_INIT:  return MTHCA_QP_STATE_INIT;
 323         case IB_QPS_RTR:   return MTHCA_QP_STATE_RTR;
 324         case IB_QPS_RTS:   return MTHCA_QP_STATE_RTS;
 325         case IB_QPS_SQD:   return MTHCA_QP_STATE_SQD;
 326         case IB_QPS_SQE:   return MTHCA_QP_STATE_SQE;
 327         case IB_QPS_ERR:   return MTHCA_QP_STATE_ERR;
 328         default:                return -1;
 329         }
 330 }
 331
 332 enum { RC, UC, UD, RD, RDEE, MLX, NUM_TRANS };
 333
 334 static int to_mthca_st(int transport)
 335 {
 336         switch (transport) {
 337         case RC:  return MTHCA_QP_ST_RC;
 338         case UC:  return MTHCA_QP_ST_UC;
 339         case UD:  return MTHCA_QP_ST_UD;
 340         case RD:  return MTHCA_QP_ST_RD;
 341         case MLX: return MTHCA_QP_ST_MLX;
 342         default:  return -1;
 343         }
 344 }
 345
 346 static const struct {
 347         int trans;
 348         u32 req_param[NUM_TRANS];
 349         u32 opt_param[NUM_TRANS];
 350 } state_table[IB_QPS_ERR + 1][IB_QPS_ERR + 1] = {
 351         [IB_QPS_RESET] = {
 352                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 353                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 354                 [IB_QPS_INIT]  = {
 355                         .trans = MTHCA_TRANS_RST2INIT,
 356                         .req_param = {
 357                                 [UD]  = (IB_QP_PKEY_INDEX |
 358                                          IB_QP_PORT       |
 359                                          IB_QP_QKEY),
 360                                 [RC]  = (IB_QP_PKEY_INDEX |
 361                                          IB_QP_PORT       |
 362                                          IB_QP_ACCESS_FLAGS),
 363                                 [MLX] = (IB_QP_PKEY_INDEX |
 364                                          IB_QP_QKEY),
 365                         },
 366                         /* bug-for-bug compatibility with VAPI: */
 367                         .opt_param = {
 368                                 [MLX] = IB_QP_PORT
 369                         }
 370                 },
 371         },
 372         [IB_QPS_INIT]  = {
 373                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 374                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 375                 [IB_QPS_INIT]  = {
 376                         .trans = MTHCA_TRANS_INIT2INIT,
 377                         .opt_param = {
 378                                 [UD]  = (IB_QP_PKEY_INDEX |
 379                                          IB_QP_PORT       |
 380                                          IB_QP_QKEY),
 381                                 [RC]  = (IB_QP_PKEY_INDEX |
 382                                          IB_QP_PORT       |
 383                                          IB_QP_ACCESS_FLAGS),
 384                                 [MLX] = (IB_QP_PKEY_INDEX |
 385                                          IB_QP_QKEY),
 386                         }
 387                 },
 388                 [IB_QPS_RTR]   = {
 389                         .trans = MTHCA_TRANS_INIT2RTR,
 390                         .req_param = {
 391                                 [RC]  = (IB_QP_AV                  |
 392                                          IB_QP_PATH_MTU            |
 393                                          IB_QP_DEST_QPN            |
 394                                          IB_QP_RQ_PSN              |
 395                                          IB_QP_MAX_DEST_RD_ATOMIC  |
 396                                          IB_QP_MIN_RNR_TIMER),
 397                         },
 398                         .opt_param = {
 399                                 [UD]  = (IB_QP_PKEY_INDEX |
 400                                          IB_QP_QKEY),
 401                                 [RC]  = (IB_QP_ALT_PATH     |
 402                                          IB_QP_ACCESS_FLAGS |
 403                                          IB_QP_PKEY_INDEX),
 404                                 [MLX] = (IB_QP_PKEY_INDEX |
 405                                          IB_QP_QKEY),
 406                         }
 407                 }
 408         },
 409         [IB_QPS_RTR]   = {
 410                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 411                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 412                 [IB_QPS_RTS]   = {
 413                         .trans = MTHCA_TRANS_RTR2RTS,
 414                         .req_param = {
 415                                 [UD]  = IB_QP_SQ_PSN,
 416                                 [RC]  = (IB_QP_TIMEOUT           |
 417                                          IB_QP_RETRY_CNT         |
 418                                          IB_QP_RNR_RETRY         |
 419                                          IB_QP_SQ_PSN            |
 420                                          IB_QP_MAX_QP_RD_ATOMIC),
 421                                 [MLX] = IB_QP_SQ_PSN,
 422                         },
 423                         .opt_param = {
 424                                 [UD]  = (IB_QP_CUR_STATE             |
 425                                          IB_QP_QKEY),
 426                                 [RC]  = (IB_QP_CUR_STATE             |
 427                                          IB_QP_ALT_PATH              |
 428                                          IB_QP_ACCESS_FLAGS          |
 429                                          IB_QP_PKEY_INDEX            |
 430                                          IB_QP_MIN_RNR_TIMER         |
 431                                          IB_QP_PATH_MIG_STATE),
 432                                 [MLX] = (IB_QP_CUR_STATE             |
 433                                          IB_QP_QKEY),
 434                         }
 435                 }
 436         },
 437         [IB_QPS_RTS]   = {
 438                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 439                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 440                 [IB_QPS_RTS]   = {
 441                         .trans = MTHCA_TRANS_RTS2RTS,
 442                         .opt_param = {
 443                                 [UD]  = (IB_QP_CUR_STATE             |
 444                                          IB_QP_QKEY),
 445                                 [RC]  = (IB_QP_ACCESS_FLAGS          |
 446                                          IB_QP_ALT_PATH              |
 447                                          IB_QP_PATH_MIG_STATE        |
 448                                          IB_QP_MIN_RNR_TIMER),
 449                                 [MLX] = (IB_QP_CUR_STATE             |
 450                                          IB_QP_QKEY),
 451                         }
 452                 },
 453                 [IB_QPS_SQD]   = {
 454                         .trans = MTHCA_TRANS_RTS2SQD,
 455                 },
 456         },
 457         [IB_QPS_SQD]   = {
 458                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 459                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 460                 [IB_QPS_RTS]   = {
 461                         .trans = MTHCA_TRANS_SQD2RTS,
 462                         .opt_param = {
 463                                 [UD]  = (IB_QP_CUR_STATE             |
 464                                          IB_QP_QKEY),
 465                                 [RC]  = (IB_QP_CUR_STATE             |
 466                                          IB_QP_ALT_PATH              |
 467                                          IB_QP_ACCESS_FLAGS          |
 468                                          IB_QP_MIN_RNR_TIMER         |
 469                                          IB_QP_PATH_MIG_STATE),
 470                                 [MLX] = (IB_QP_CUR_STATE             |
 471                                          IB_QP_QKEY),
 472                         }
 473                 },
 474                 [IB_QPS_SQD]   = {
 475                         .trans = MTHCA_TRANS_SQD2SQD,
 476                         .opt_param = {
 477                                 [UD]  = (IB_QP_PKEY_INDEX            |
 478                                          IB_QP_QKEY),
 479                                 [RC]  = (IB_QP_AV                    |
 480                                          IB_QP_TIMEOUT               |
 481                                          IB_QP_RETRY_CNT             |
 482                                          IB_QP_RNR_RETRY             |
 483                                          IB_QP_MAX_QP_RD_ATOMIC      |
 484                                          IB_QP_MAX_DEST_RD_ATOMIC    |
 485                                          IB_QP_CUR_STATE             |
 486                                          IB_QP_ALT_PATH              |
 487                                          IB_QP_ACCESS_FLAGS          |
 488                                          IB_QP_PKEY_INDEX            |
 489                                          IB_QP_MIN_RNR_TIMER         |
 490                                          IB_QP_PATH_MIG_STATE),
 491                                 [MLX] = (IB_QP_PKEY_INDEX            |
 492                                          IB_QP_QKEY),
 493                         }
 494                 }
 495         },
 496         [IB_QPS_SQE]   = {
 497                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 498                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 499                 [IB_QPS_RTS]   = {
 500                         .trans = MTHCA_TRANS_SQERR2RTS,
 501                         .opt_param = {
 502                                 [UD]  = (IB_QP_CUR_STATE             |
 503                                          IB_QP_QKEY),
 504                                 [RC]  = (IB_QP_CUR_STATE             |
 505                                          IB_QP_MIN_RNR_TIMER),
 506                                 [MLX] = (IB_QP_CUR_STATE             |
 507                                          IB_QP_QKEY),
 508                         }
 509                 }
 510         },
 511         [IB_QPS_ERR] = {
 512                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 513                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR }
 514         }
 515 };
 516
 517 static void store_attrs(struct mthca_sqp *sqp, struct ib_qp_attr *attr,
 518                         int attr_mask)
 519 {
 520         if (attr_mask & IB_QP_PKEY_INDEX)
 521                 sqp->pkey_index = attr->pkey_index;
 522         if (attr_mask & IB_QP_QKEY)
 523                 sqp->qkey = attr->qkey;
 524         if (attr_mask & IB_QP_SQ_PSN)
 525                 sqp->send_psn = attr->sq_psn;
 526 }
 527
 528 static void init_port(struct mthca_dev *dev, int port)
 529 {
 530         int err;
 531         u8 status;
 532         struct mthca_init_ib_param param;
 533
 534         memset(&param, 0, sizeof param);
 535
 536         param.enable_1x = 1;
 537         param.enable_4x = 1;
 538         param.vl_cap    = dev->limits.vl_cap;
 539         param.mtu_cap   = dev->limits.mtu_cap;
 540         param.gid_cap   = dev->limits.gid_table_len;
 541         param.pkey_cap  = dev->limits.pkey_table_len;
 542
 543         err = mthca_INIT_IB(dev, &param, port, &status);
 544         if (err)
 545                 mthca_warn(dev, "INIT_IB failed, return code %d.\n", err);
 546         if (status)
 547                 mthca_warn(dev, "INIT_IB returned status %02x.\n", status);
 548 }
 549
 550 int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask)
 551 {
 552         struct mthca_dev *dev = to_mdev(ibqp->device);
 553         struct mthca_qp *qp = to_mqp(ibqp);
 554         enum ib_qp_state cur_state, new_state;
 555         void *mailbox = NULL;
 556         struct mthca_qp_param *qp_param;
 557         struct mthca_qp_context *qp_context;
 558         u32 req_param, opt_param;
 559         u8 status;
 560         int err;
 561
 562         if (attr_mask & IB_QP_CUR_STATE) {
 563                 if (attr->cur_qp_state != IB_QPS_RTR &&
 564                     attr->cur_qp_state != IB_QPS_RTS &&
 565                     attr->cur_qp_state != IB_QPS_SQD &&
 566                     attr->cur_qp_state != IB_QPS_SQE)
 567                         return -EINVAL;
 568                 else
 569                         cur_state = attr->cur_qp_state;
 570         } else {
 571                 spin_lock_irq(&qp->sq.lock);
 572                 spin_lock(&qp->rq.lock);
 573                 cur_state = qp->state;
 574                 spin_unlock(&qp->rq.lock);
 575                 spin_unlock_irq(&qp->sq.lock);
 576         }
 577
 578         if (attr_mask & IB_QP_STATE) {
 579                if (attr->qp_state < 0 || attr->qp_state > IB_QPS_ERR)
 580                         return -EINVAL;
 581                 new_state = attr->qp_state;
 582         } else
 583                 new_state = cur_state;
 584
 585         if (state_table[cur_state][new_state].trans == MTHCA_TRANS_INVALID) {
 586                 mthca_dbg(dev, "Illegal QP transition "
 587                           "%d->%d\n", cur_state, new_state);
 588                 return -EINVAL;
 589         }
 590
 591         req_param = state_table[cur_state][new_state].req_param[qp->transport];
 592         opt_param = state_table[cur_state][new_state].opt_param[qp->transport];
 593
 594         if ((req_param & attr_mask) != req_param) {
 595                 mthca_dbg(dev, "QP transition "
 596                           "%d->%d missing req attr 0x%08x\n",
 597                           cur_state, new_state,
 598                           req_param & ~attr_mask);
 599                 return -EINVAL;
 600         }
 601
 602         if (attr_mask & ~(req_param | opt_param | IB_QP_STATE)) {
 603                 mthca_dbg(dev, "QP transition (transport %d) "
 604                           "%d->%d has extra attr 0x%08x\n",
 605                           qp->transport,
 606                           cur_state, new_state,
 607                           attr_mask & ~(req_param | opt_param |
 608                                                  IB_QP_STATE));
 609                 return -EINVAL;
 610         }
 611
 612         mailbox = kmalloc(sizeof (*qp_param) + MTHCA_CMD_MAILBOX_EXTRA, GFP_KERNEL);
 613         if (!mailbox)
 614                 return -ENOMEM;
 615         qp_param = MAILBOX_ALIGN(mailbox);
 616         qp_context = &qp_param->context;
 617         memset(qp_param, 0, sizeof *qp_param);
 618
 619         qp_context->flags      = cpu_to_be32((to_mthca_state(new_state) << 28) |
 620                                              (to_mthca_st(qp->transport) << 16));
 621         qp_context->flags     |= cpu_to_be32(MTHCA_QP_BIT_DE);
 622         if (!(attr_mask & IB_QP_PATH_MIG_STATE))
 623                 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
 624         else {
 625                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PM_STATE);
 626                 switch (attr->path_mig_state) {
 627                 case IB_MIG_MIGRATED:
 628                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
 629                         break;
 630                 case IB_MIG_REARM:
 631                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_REARM << 11);
 632                         break;
 633                 case IB_MIG_ARMED:
 634                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_ARMED << 11);
 635                         break;
 636                 }
 637         }
 638
 639         /* leave tavor_sched_queue as 0 */
 640
 641         if (qp->transport == MLX || qp->transport == UD)
 642                 qp_context->mtu_msgmax = (IB_MTU_2048 << 5) | 11;
 643         else if (attr_mask & IB_QP_PATH_MTU)
 644                 qp_context->mtu_msgmax = (attr->path_mtu << 5) | 31;
 645
 646         if (mthca_is_memfree(dev)) {
 647                 qp_context->rq_size_stride =
 648                         ((ffs(qp->rq.max) - 1) << 3) | (qp->rq.wqe_shift - 4);
 649                 qp_context->sq_size_stride =
 650                         ((ffs(qp->sq.max) - 1) << 3) | (qp->sq.wqe_shift - 4);
 651         }
 652
 653         /* leave arbel_sched_queue as 0 */
 654
 655         qp_context->usr_page   = cpu_to_be32(dev->driver_uar.index);
 656         qp_context->local_qpn  = cpu_to_be32(qp->qpn);
 657         if (attr_mask & IB_QP_DEST_QPN) {
 658                 qp_context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
 659         }
 660
 661         if (qp->transport == MLX)
 662                 qp_context->pri_path.port_pkey |=
 663                         cpu_to_be32(to_msqp(qp)->port << 24);
 664         else {
 665                 if (attr_mask & IB_QP_PORT) {
 666                         qp_context->pri_path.port_pkey |=
 667                                 cpu_to_be32(attr->port_num << 24);
 668                         qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PORT_NUM);
 669                 }
 670         }
 671
 672         if (attr_mask & IB_QP_PKEY_INDEX) {
 673                 qp_context->pri_path.port_pkey |=
 674                         cpu_to_be32(attr->pkey_index);
 675                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PKEY_INDEX);
 676         }
 677
 678         if (attr_mask & IB_QP_RNR_RETRY) {
 679                 qp_context->pri_path.rnr_retry = attr->rnr_retry << 5;
 680                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_RETRY);
 681         }
 682
 683         if (attr_mask & IB_QP_AV) {
 684                 qp_context->pri_path.g_mylmc     = attr->ah_attr.src_path_bits & 0x7f;
 685                 qp_context->pri_path.rlid        = cpu_to_be16(attr->ah_attr.dlid);
 686                 qp_context->pri_path.static_rate = (!!attr->ah_attr.static_rate) << 3;
 687                 if (attr->ah_attr.ah_flags & IB_AH_GRH) {
 688                         qp_context->pri_path.g_mylmc |= 1 << 7;
 689                         qp_context->pri_path.mgid_index = attr->ah_attr.grh.sgid_index;
 690                         qp_context->pri_path.hop_limit = attr->ah_attr.grh.hop_limit;
 691                         qp_context->pri_path.sl_tclass_flowlabel =
 692                                 cpu_to_be32((attr->ah_attr.sl << 28)                |
 693                                             (attr->ah_attr.grh.traffic_class << 20) |
 694                                             (attr->ah_attr.grh.flow_label));
 695                         memcpy(qp_context->pri_path.rgid,
 696                                attr->ah_attr.grh.dgid.raw, 16);
 697                 } else {
 698                         qp_context->pri_path.sl_tclass_flowlabel =
 699                                 cpu_to_be32(attr->ah_attr.sl << 28);
 700                 }
 701                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH);
 702         }
 703
 704         if (attr_mask & IB_QP_TIMEOUT) {
 705                 qp_context->pri_path.ackto = attr->timeout;
 706                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ACK_TIMEOUT);
 707         }
 708
 709         /* XXX alt_path */
 710
 711         /* leave rdd as 0 */
 712         qp_context->pd         = cpu_to_be32(to_mpd(ibqp->pd)->pd_num);
 713         /* leave wqe_base as 0 (we always create an MR based at 0 for WQs) */
 714         qp_context->wqe_lkey   = cpu_to_be32(qp->mr.ibmr.lkey);
 715         qp_context->params1    = cpu_to_be32((MTHCA_ACK_REQ_FREQ << 28) |
 716                                              (MTHCA_FLIGHT_LIMIT << 24) |
 717                                              MTHCA_QP_BIT_SRE           |
 718                                              MTHCA_QP_BIT_SWE           |
 719                                              MTHCA_QP_BIT_SAE);
 720         if (qp->sq_policy == IB_SIGNAL_ALL_WR)
 721                 qp_context->params1 |= cpu_to_be32(MTHCA_QP_BIT_SSC);
 722         if (attr_mask & IB_QP_RETRY_CNT) {
 723                 qp_context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
 724                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RETRY_COUNT);
 725         }
 726
 727         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
 728                 qp_context->params1 |= cpu_to_be32(min(attr->max_dest_rd_atomic ?
 729                                                        ffs(attr->max_dest_rd_atomic) - 1 : 0,
 730                                                        7) << 21);
 731                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_SRA_MAX);
 732         }
 733
 734         if (attr_mask & IB_QP_SQ_PSN)
 735                 qp_context->next_send_psn = cpu_to_be32(attr->sq_psn);
 736         qp_context->cqn_snd = cpu_to_be32(to_mcq(ibqp->send_cq)->cqn);
 737
 738         if (mthca_is_memfree(dev)) {
 739                 qp_context->snd_wqe_base_l = cpu_to_be32(qp->send_wqe_offset);
 740                 qp_context->snd_db_index   = cpu_to_be32(qp->sq.db_index);
 741         }
 742
 743         if (attr_mask & IB_QP_ACCESS_FLAGS) {
 744                 /*
 745                  * Only enable RDMA/atomics if we have responder
 746                  * resources set to a non-zero value.
 747                  */
 748                 if (qp->resp_depth) {
 749                         qp_context->params2 |=
 750                                 cpu_to_be32(attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE ?
 751                                             MTHCA_QP_BIT_RWE : 0);
 752                         qp_context->params2 |=
 753                                 cpu_to_be32(attr->qp_access_flags & IB_ACCESS_REMOTE_READ ?
 754                                             MTHCA_QP_BIT_RRE : 0);
 755                         qp_context->params2 |=
 756                                 cpu_to_be32(attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC ?
 757                                             MTHCA_QP_BIT_RAE : 0);
 758                 }
 759
 760                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
 761                                                         MTHCA_QP_OPTPAR_RRE |
 762                                                         MTHCA_QP_OPTPAR_RAE);
 763
 764                 qp->atomic_rd_en = attr->qp_access_flags;
 765         }
 766
 767         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
 768                 u8 rra_max;
 769
 770                 if (qp->resp_depth && !attr->max_rd_atomic) {
 771                         /*
 772                          * Lowering our responder resources to zero.
 773                          * Turn off RDMA/atomics as responder.
 774                          * (RWE/RRE/RAE in params2 already zero)
 775                          */
 776                         qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
 777                                                                 MTHCA_QP_OPTPAR_RRE |
 778                                                                 MTHCA_QP_OPTPAR_RAE);
 779                 }
 780
 781                 if (!qp->resp_depth && attr->max_rd_atomic) {
 782                         /*
 783                          * Increasing our responder resources from
 784                          * zero.  Turn on RDMA/atomics as appropriate.
 785                          */
 786                         qp_context->params2 |=
 787                                 cpu_to_be32(qp->atomic_rd_en & IB_ACCESS_REMOTE_WRITE ?
 788                                             MTHCA_QP_BIT_RWE : 0);
 789                         qp_context->params2 |=
 790                                 cpu_to_be32(qp->atomic_rd_en & IB_ACCESS_REMOTE_READ ?
 791                                             MTHCA_QP_BIT_RRE : 0);
 792                         qp_context->params2 |=
 793                                 cpu_to_be32(qp->atomic_rd_en & IB_ACCESS_REMOTE_ATOMIC ?
 794                                             MTHCA_QP_BIT_RAE : 0);
 795
 796                         qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
 797                                                                 MTHCA_QP_OPTPAR_RRE |
 798                                                                 MTHCA_QP_OPTPAR_RAE);
 799                 }
 800
 801                 for (rra_max = 0;
 802                      1 << rra_max < attr->max_rd_atomic &&
 803                              rra_max < dev->qp_table.rdb_shift;
 804                      ++rra_max)
 805                         ; /* nothing */
 806
 807                 qp_context->params2      |= cpu_to_be32(rra_max << 21);
 808                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RRA_MAX);
 809
 810                 qp->resp_depth = attr->max_rd_atomic;
 811         }
 812
 813         qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RSC);
 814
 815         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
 816                 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
 817                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_TIMEOUT);
 818         }
 819         if (attr_mask & IB_QP_RQ_PSN)
 820                 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
 821
 822         qp_context->ra_buff_indx =
 823                 cpu_to_be32(dev->qp_table.rdb_base +
 824                             ((qp->qpn & (dev->limits.num_qps - 1)) * MTHCA_RDB_ENTRY_SIZE <<
 825                              dev->qp_table.rdb_shift));
 826
 827         qp_context->cqn_rcv = cpu_to_be32(to_mcq(ibqp->recv_cq)->cqn);
 828
 829         if (mthca_is_memfree(dev))
 830                 qp_context->rcv_db_index   = cpu_to_be32(qp->rq.db_index);
 831
 832         if (attr_mask & IB_QP_QKEY) {
 833                 qp_context->qkey = cpu_to_be32(attr->qkey);
 834                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_Q_KEY);
 835         }
 836
 837         err = mthca_MODIFY_QP(dev, state_table[cur_state][new_state].trans,
 838                               qp->qpn, 0, qp_param, 0, &status);
 839         if (status) {
 840                 mthca_warn(dev, "modify QP %d returned status %02x.\n",
 841                            state_table[cur_state][new_state].trans, status);
 842                 err = -EINVAL;
 843         }
 844
 845         if (!err)
 846                 qp->state = new_state;
 847
 848         kfree(mailbox);
 849
 850         if (is_sqp(dev, qp))
 851                 store_attrs(to_msqp(qp), attr, attr_mask);
 852
 853         /*
 854          * If we are moving QP0 to RTR, bring the IB link up; if we
 855          * are moving QP0 to RESET or ERROR, bring the link back down.
 856          */
 857         if (is_qp0(dev, qp)) {
 858                 if (cur_state != IB_QPS_RTR &&
 859                     new_state == IB_QPS_RTR)
 860                         init_port(dev, to_msqp(qp)->port);
 861
 862                 if (cur_state != IB_QPS_RESET &&
 863                     cur_state != IB_QPS_ERR &&
 864                     (new_state == IB_QPS_RESET ||
 865                      new_state == IB_QPS_ERR))
 866                         mthca_CLOSE_IB(dev, to_msqp(qp)->port, &status);
 867         }
 868
 869         return err;
 870 }
 871
 872 /*
 873  * Allocate and register buffer for WQEs.  qp->rq.max, sq.max,
 874  * rq.max_gs and sq.max_gs must all be assigned.
 875  * mthca_alloc_wqe_buf will calculate rq.wqe_shift and
 876  * sq.wqe_shift (as well as send_wqe_offset, is_direct, and
 877  * queue)
 878  */
 879 static int mthca_alloc_wqe_buf(struct mthca_dev *dev,
 880                                struct mthca_pd *pd,
 881                                struct mthca_qp *qp)
 882 {
 883         int size;
 884         int i;
 885         int npages, shift;
 886         dma_addr_t t;
 887         u64 *dma_list = NULL;
 888         int err = -ENOMEM;
 889
 890         size = sizeof (struct mthca_next_seg) +
 891                 qp->rq.max_gs * sizeof (struct mthca_data_seg);
 892
 893         for (qp->rq.wqe_shift = 6; 1 << qp->rq.wqe_shift < size;
 894              qp->rq.wqe_shift++)
 895                 ; /* nothing */
 896
 897         size = sizeof (struct mthca_next_seg) +
 898                 qp->sq.max_gs * sizeof (struct mthca_data_seg);
 899         switch (qp->transport) {
 900         case MLX:
 901                 size += 2 * sizeof (struct mthca_data_seg);
 902                 break;
 903         case UD:
 904                 if (mthca_is_memfree(dev))
 905                         size += sizeof (struct mthca_arbel_ud_seg);
 906                 else
 907                         size += sizeof (struct mthca_tavor_ud_seg);
 908                 break;
 909         default:
 910                 /* bind seg is as big as atomic + raddr segs */
 911                 size += sizeof (struct mthca_bind_seg);
 912         }
 913
 914         for (qp->sq.wqe_shift = 6; 1 << qp->sq.wqe_shift < size;
 915              qp->sq.wqe_shift++)
 916                 ; /* nothing */
 917
 918         qp->send_wqe_offset = ALIGN(qp->rq.max << qp->rq.wqe_shift,
 919                                     1 << qp->sq.wqe_shift);
 920         size = PAGE_ALIGN(qp->send_wqe_offset +
 921                           (qp->sq.max << qp->sq.wqe_shift));
 922
 923         qp->wrid = kmalloc((qp->rq.max + qp->sq.max) * sizeof (u64),
 924                            GFP_KERNEL);
 925         if (!qp->wrid)
 926                 goto err_out;
 927
 928         if (size <= MTHCA_MAX_DIRECT_QP_SIZE) {
 929                 qp->is_direct = 1;
 930                 npages = 1;
 931                 shift = get_order(size) + PAGE_SHIFT;
 932
 933                 if (0)
 934                         mthca_dbg(dev, "Creating direct QP of size %d (shift %d)\n",
 935                                   size, shift);
 936
 937                 qp->queue.direct.buf = pci_alloc_consistent(dev->pdev, size, &t);
 938                 if (!qp->queue.direct.buf)
 939                         goto err_out;
 940
 941                 pci_unmap_addr_set(&qp->queue.direct, mapping, t);
 942
 943                 memset(qp->queue.direct.buf, 0, size);
 944
 945                 while (t & ((1 << shift) - 1)) {
 946                         --shift;
 947                         npages *= 2;
 948                 }
 949
 950                 dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL);
 951                 if (!dma_list)
 952                         goto err_out_free;
 953
 954                 for (i = 0; i < npages; ++i)
 955                         dma_list[i] = t + i * (1 << shift);
 956         } else {
 957                 qp->is_direct = 0;
 958                 npages = size / PAGE_SIZE;
 959                 shift = PAGE_SHIFT;
 960
 961                 if (0)
 962                         mthca_dbg(dev, "Creating indirect QP with %d pages\n", npages);
 963
 964                 dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL);
 965                 if (!dma_list)
 966                         goto err_out;
 967
 968                 qp->queue.page_list = kmalloc(npages *
 969                                               sizeof *qp->queue.page_list,
 970                                               GFP_KERNEL);
 971                 if (!qp->queue.page_list)
 972                         goto err_out;
 973
 974                 for (i = 0; i < npages; ++i) {
 975                         qp->queue.page_list[i].buf =
 976                                 pci_alloc_consistent(dev->pdev, PAGE_SIZE, &t);
 977                         if (!qp->queue.page_list[i].buf)
 978                                 goto err_out_free;
 979
 980                         memset(qp->queue.page_list[i].buf, 0, PAGE_SIZE);
 981
 982                         pci_unmap_addr_set(&qp->queue.page_list[i], mapping, t);
 983                         dma_list[i] = t;
 984                 }
 985         }
 986
 987         err = mthca_mr_alloc_phys(dev, pd->pd_num, dma_list, shift,
 988                                   npages, 0, size,
 989                                   MTHCA_MPT_FLAG_LOCAL_READ,
 990                                   &qp->mr);
 991         if (err)
 992                 goto err_out_free;
 993
 994         kfree(dma_list);
 995         return 0;
 996
 997  err_out_free:
 998         if (qp->is_direct) {
 999                 pci_free_consistent(dev->pdev, size,
1000                                     qp->queue.direct.buf,
1001                                     pci_unmap_addr(&qp->queue.direct, mapping));
1002         } else
1003                 for (i = 0; i < npages; ++i) {
1004                         if (qp->queue.page_list[i].buf)
1005                                 pci_free_consistent(dev->pdev, PAGE_SIZE,
1006                                                     qp->queue.page_list[i].buf,
1007                                                     pci_unmap_addr(&qp->queue.page_list[i],
1008                                                                    mapping));
1009
1010                 }
1011
1012  err_out:
1013         kfree(qp->wrid);
1014         kfree(dma_list);
1015         return err;
1016 }
1017
1018 static int mthca_alloc_memfree(struct mthca_dev *dev,
1019                                struct mthca_qp *qp)
1020 {
1021         int ret = 0;
1022
1023         if (mthca_is_memfree(dev)) {
1024                 ret = mthca_table_get(dev, dev->qp_table.qp_table, qp->qpn);
1025                 if (ret)
1026                         return ret;
1027
1028                 ret = mthca_table_get(dev, dev->qp_table.eqp_table, qp->qpn);
1029                 if (ret)
1030                         goto err_qpc;
1031
1032                 qp->rq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_RQ,
1033                                                  qp->qpn, &qp->rq.db);
1034                 if (qp->rq.db_index < 0) {
1035                         ret = -ENOMEM;
1036                         goto err_eqpc;
1037                 }
1038
1039                 qp->sq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_SQ,
1040                                                  qp->qpn, &qp->sq.db);
1041                 if (qp->sq.db_index < 0) {
1042                         ret = -ENOMEM;
1043                         goto err_rq_db;
1044                 }
1045         }
1046
1047         return 0;
1048
1049 err_rq_db:
1050         mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1051
1052 err_eqpc:
1053         mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1054
1055 err_qpc:
1056         mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1057
1058         return ret;
1059 }
1060
1061 static void mthca_free_memfree(struct mthca_dev *dev,
1062                                struct mthca_qp *qp)
1063 {
1064         if (mthca_is_memfree(dev)) {
1065                 mthca_free_db(dev, MTHCA_DB_TYPE_SQ, qp->sq.db_index);
1066                 mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1067                 mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1068                 mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1069         }
1070 }
1071
1072 static void mthca_wq_init(struct mthca_wq* wq)
1073 {
1074         spin_lock_init(&wq->lock);
1075         wq->next_ind  = 0;
1076         wq->last_comp = wq->max - 1;
1077         wq->head      = 0;
1078         wq->tail      = 0;
1079         wq->last      = NULL;
1080 }
1081
1082 static int mthca_alloc_qp_common(struct mthca_dev *dev,
1083                                  struct mthca_pd *pd,
1084                                  struct mthca_cq *send_cq,
1085                                  struct mthca_cq *recv_cq,
1086                                  enum ib_sig_type send_policy,
1087                                  struct mthca_qp *qp)
1088 {
1089         int ret;
1090         int i;
1091
1092         atomic_set(&qp->refcount, 1);
1093         qp->state        = IB_QPS_RESET;
1094         qp->atomic_rd_en = 0;
1095         qp->resp_depth   = 0;
1096         qp->sq_policy    = send_policy;
1097         mthca_wq_init(&qp->sq);
1098         mthca_wq_init(&qp->rq);
1099
1100         ret = mthca_alloc_memfree(dev, qp);
1101         if (ret)
1102                 return ret;
1103
1104         ret = mthca_alloc_wqe_buf(dev, pd, qp);
1105         if (ret) {
1106                 mthca_free_memfree(dev, qp);
1107                 return ret;
1108         }
1109
1110         if (mthca_is_memfree(dev)) {
1111                 struct mthca_next_seg *next;
1112                 struct mthca_data_seg *scatter;
1113                 int size = (sizeof (struct mthca_next_seg) +
1114                             qp->rq.max_gs * sizeof (struct mthca_data_seg)) / 16;
1115
1116                 for (i = 0; i < qp->rq.max; ++i) {
1117                         next = get_recv_wqe(qp, i);
1118                         next->nda_op = cpu_to_be32(((i + 1) & (qp->rq.max - 1)) <<
1119                                                    qp->rq.wqe_shift);
1120                         next->ee_nds = cpu_to_be32(size);
1121
1122                         for (scatter = (void *) (next + 1);
1123                              (void *) scatter < (void *) next + (1 << qp->rq.wqe_shift);
1124                              ++scatter)
1125                                 scatter->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
1126                 }
1127
1128                 for (i = 0; i < qp->sq.max; ++i) {
1129                         next = get_send_wqe(qp, i);
1130                         next->nda_op = cpu_to_be32((((i + 1) & (qp->sq.max - 1)) <<
1131                                                     qp->sq.wqe_shift) +
1132                                                    qp->send_wqe_offset);
1133                 }
1134         }
1135
1136         return 0;
1137 }
1138
1139 static void mthca_align_qp_size(struct mthca_dev *dev, struct mthca_qp *qp)
1140 {
1141         int i;
1142
1143         if (!mthca_is_memfree(dev))
1144                 return;
1145
1146         for (i = 0; 1 << i < qp->rq.max; ++i)
1147                 ; /* nothing */
1148
1149         qp->rq.max = 1 << i;
1150
1151         for (i = 0; 1 << i < qp->sq.max; ++i)
1152                 ; /* nothing */
1153
1154         qp->sq.max = 1 << i;
1155 }
1156
1157 int mthca_alloc_qp(struct mthca_dev *dev,
1158                    struct mthca_pd *pd,
1159                    struct mthca_cq *send_cq,
1160                    struct mthca_cq *recv_cq,
1161                    enum ib_qp_type type,
1162                    enum ib_sig_type send_policy,
1163                    struct mthca_qp *qp)
1164 {
1165         int err;
1166
1167         mthca_align_qp_size(dev, qp);
1168
1169         switch (type) {
1170         case IB_QPT_RC: qp->transport = RC; break;
1171         case IB_QPT_UC: qp->transport = UC; break;
1172         case IB_QPT_UD: qp->transport = UD; break;
1173         default: return -EINVAL;
1174         }
1175
1176         qp->qpn = mthca_alloc(&dev->qp_table.alloc);
1177         if (qp->qpn == -1)
1178                 return -ENOMEM;
1179
1180         err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1181                                     send_policy, qp);
1182         if (err) {
1183                 mthca_free(&dev->qp_table.alloc, qp->qpn);
1184                 return err;
1185         }
1186
1187         spin_lock_irq(&dev->qp_table.lock);
1188         mthca_array_set(&dev->qp_table.qp,
1189                         qp->qpn & (dev->limits.num_qps - 1), qp);
1190         spin_unlock_irq(&dev->qp_table.lock);
1191
1192         return 0;
1193 }
1194
1195 int mthca_alloc_sqp(struct mthca_dev *dev,
1196                     struct mthca_pd *pd,
1197                     struct mthca_cq *send_cq,
1198                     struct mthca_cq *recv_cq,
1199                     enum ib_sig_type send_policy,
1200                     int qpn,
1201                     int port,
1202                     struct mthca_sqp *sqp)
1203 {
1204         int err = 0;
1205         u32 mqpn = qpn * 2 + dev->qp_table.sqp_start + port - 1;
1206
1207         mthca_align_qp_size(dev, &sqp->qp);
1208
1209         sqp->header_buf_size = sqp->qp.sq.max * MTHCA_UD_HEADER_SIZE;
1210         sqp->header_buf = dma_alloc_coherent(&dev->pdev->dev, sqp->header_buf_size,
1211                                              &sqp->header_dma, GFP_KERNEL);
1212         if (!sqp->header_buf)
1213                 return -ENOMEM;
1214
1215         spin_lock_irq(&dev->qp_table.lock);
1216         if (mthca_array_get(&dev->qp_table.qp, mqpn))
1217                 err = -EBUSY;
1218         else
1219                 mthca_array_set(&dev->qp_table.qp, mqpn, sqp);
1220         spin_unlock_irq(&dev->qp_table.lock);
1221
1222         if (err)
1223                 goto err_out;
1224
1225         sqp->port = port;
1226         sqp->qp.qpn       = mqpn;
1227         sqp->qp.transport = MLX;
1228
1229         err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1230                                     send_policy, &sqp->qp);
1231         if (err)
1232                 goto err_out_free;
1233
1234         atomic_inc(&pd->sqp_count);
1235
1236         return 0;
1237
1238  err_out_free:
1239         /*
1240          * Lock CQs here, so that CQ polling code can do QP lookup
1241          * without taking a lock.
1242          */
1243         spin_lock_irq(&send_cq->lock);
1244         if (send_cq != recv_cq)
1245                 spin_lock(&recv_cq->lock);
1246
1247         spin_lock(&dev->qp_table.lock);
1248         mthca_array_clear(&dev->qp_table.qp, mqpn);
1249         spin_unlock(&dev->qp_table.lock);
1250
1251         if (send_cq != recv_cq)
1252                 spin_unlock(&recv_cq->lock);
1253         spin_unlock_irq(&send_cq->lock);
1254
1255  err_out:
1256         dma_free_coherent(&dev->pdev->dev, sqp->header_buf_size,
1257                           sqp->header_buf, sqp->header_dma);
1258
1259         return err;
1260 }
1261
1262 void mthca_free_qp(struct mthca_dev *dev,
1263                    struct mthca_qp *qp)
1264 {
1265         u8 status;
1266         int size;
1267         int i;
1268         struct mthca_cq *send_cq;
1269         struct mthca_cq *recv_cq;
1270
1271         send_cq = to_mcq(qp->ibqp.send_cq);
1272         recv_cq = to_mcq(qp->ibqp.recv_cq);
1273
1274         /*
1275          * Lock CQs here, so that CQ polling code can do QP lookup
1276          * without taking a lock.
1277          */
1278         spin_lock_irq(&send_cq->lock);
1279         if (send_cq != recv_cq)
1280                 spin_lock(&recv_cq->lock);
1281
1282         spin_lock(&dev->qp_table.lock);
1283         mthca_array_clear(&dev->qp_table.qp,
1284                           qp->qpn & (dev->limits.num_qps - 1));
1285         spin_unlock(&dev->qp_table.lock);
1286
1287         if (send_cq != recv_cq)
1288                 spin_unlock(&recv_cq->lock);
1289         spin_unlock_irq(&send_cq->lock);
1290
1291         atomic_dec(&qp->refcount);
1292         wait_event(qp->wait, !atomic_read(&qp->refcount));
1293
1294         if (qp->state != IB_QPS_RESET)
1295                 mthca_MODIFY_QP(dev, MTHCA_TRANS_ANY2RST, qp->qpn, 0, NULL, 0, &status);
1296
1297         mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq)->cqn, qp->qpn);
1298         if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
1299                 mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq)->cqn, qp->qpn);
1300
1301         mthca_free_mr(dev, &qp->mr);
1302
1303         size = PAGE_ALIGN(qp->send_wqe_offset +
1304                           (qp->sq.max << qp->sq.wqe_shift));
1305
1306         if (qp->is_direct) {
1307                 pci_free_consistent(dev->pdev, size,
1308                                     qp->queue.direct.buf,
1309                                     pci_unmap_addr(&qp->queue.direct, mapping));
1310         } else {
1311                 for (i = 0; i < size / PAGE_SIZE; ++i) {
1312                         pci_free_consistent(dev->pdev, PAGE_SIZE,
1313                                             qp->queue.page_list[i].buf,
1314                                             pci_unmap_addr(&qp->queue.page_list[i],
1315                                                            mapping));
1316                 }
1317         }
1318
1319         kfree(qp->wrid);
1320
1321         mthca_free_memfree(dev, qp);
1322
1323         if (is_sqp(dev, qp)) {
1324                 atomic_dec(&(to_mpd(qp->ibqp.pd)->sqp_count));
1325                 dma_free_coherent(&dev->pdev->dev,
1326                                   to_msqp(qp)->header_buf_size,
1327                                   to_msqp(qp)->header_buf,
1328                                   to_msqp(qp)->header_dma);
1329         } else
1330                 mthca_free(&dev->qp_table.alloc, qp->qpn);
1331 }
1332
1333 /* Create UD header for an MLX send and build a data segment for it */
1334 static int build_mlx_header(struct mthca_dev *dev, struct mthca_sqp *sqp,
1335                             int ind, struct ib_send_wr *wr,
1336                             struct mthca_mlx_seg *mlx,
1337                             struct mthca_data_seg *data)
1338 {
1339         int header_size;
1340         int err;
1341
1342         ib_ud_header_init(256, /* assume a MAD */
1343                           sqp->ud_header.grh_present,
1344                           &sqp->ud_header);
1345
1346         err = mthca_read_ah(dev, to_mah(wr->wr.ud.ah), &sqp->ud_header);
1347         if (err)
1348                 return err;
1349         mlx->flags &= ~cpu_to_be32(MTHCA_NEXT_SOLICIT | 1);
1350         mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MTHCA_MLX_VL15 : 0) |
1351                                   (sqp->ud_header.lrh.destination_lid == 0xffff ?
1352                                    MTHCA_MLX_SLR : 0) |
1353                                   (sqp->ud_header.lrh.service_level << 8));
1354         mlx->rlid = sqp->ud_header.lrh.destination_lid;
1355         mlx->vcrc = 0;
1356
1357         switch (wr->opcode) {
1358         case IB_WR_SEND:
1359                 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
1360                 sqp->ud_header.immediate_present = 0;
1361                 break;
1362         case IB_WR_SEND_WITH_IMM:
1363                 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1364                 sqp->ud_header.immediate_present = 1;
1365                 sqp->ud_header.immediate_data = wr->imm_data;
1366                 break;
1367         default:
1368                 return -EINVAL;
1369         }
1370
1371         sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 : 0;
1372         if (sqp->ud_header.lrh.destination_lid == 0xffff)
1373                 sqp->ud_header.lrh.source_lid = 0xffff;
1374         sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1375         if (!sqp->qp.ibqp.qp_num)
1376                 ib_get_cached_pkey(&dev->ib_dev, sqp->port,
1377                                    sqp->pkey_index,
1378                                    &sqp->ud_header.bth.pkey);
1379         else
1380                 ib_get_cached_pkey(&dev->ib_dev, sqp->port,
1381                                    wr->wr.ud.pkey_index,
1382                                    &sqp->ud_header.bth.pkey);
1383         cpu_to_be16s(&sqp->ud_header.bth.pkey);
1384         sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1385         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1386         sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1387                                                sqp->qkey : wr->wr.ud.remote_qkey);
1388         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1389
1390         header_size = ib_ud_header_pack(&sqp->ud_header,
1391                                         sqp->header_buf +
1392                                         ind * MTHCA_UD_HEADER_SIZE);
1393
1394         data->byte_count = cpu_to_be32(header_size);
1395         data->lkey       = cpu_to_be32(to_mpd(sqp->qp.ibqp.pd)->ntmr.ibmr.lkey);
1396         data->addr       = cpu_to_be64(sqp->header_dma +
1397                                        ind * MTHCA_UD_HEADER_SIZE);
1398
1399         return 0;
1400 }
1401
1402 static inline int mthca_wq_overflow(struct mthca_wq *wq, int nreq,
1403                                     struct ib_cq *ib_cq)
1404 {
1405         unsigned cur;
1406         struct mthca_cq *cq;
1407
1408         cur = wq->head - wq->tail;
1409         if (likely(cur + nreq < wq->max))
1410                 return 0;
1411
1412         cq = to_mcq(ib_cq);
1413         spin_lock(&cq->lock);
1414         cur = wq->head - wq->tail;
1415         spin_unlock(&cq->lock);
1416
1417         return cur + nreq >= wq->max;
1418 }
1419
1420 int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1421                           struct ib_send_wr **bad_wr)
1422 {
1423         struct mthca_dev *dev = to_mdev(ibqp->device);
1424         struct mthca_qp *qp = to_mqp(ibqp);
1425         void *wqe;
1426         void *prev_wqe;
1427         unsigned long flags;
1428         int err = 0;
1429         int nreq;
1430         int i;
1431         int size;
1432         int size0 = 0;
1433         u32 f0 = 0;
1434         int ind;
1435         u8 op0 = 0;
1436
1437         spin_lock_irqsave(&qp->sq.lock, flags);
1438
1439         /* XXX check that state is OK to post send */
1440
1441         ind = qp->sq.next_ind;
1442
1443         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1444                 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1445                         mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1446                                         " %d max, %d nreq)\n", qp->qpn,
1447                                         qp->sq.head, qp->sq.tail,
1448                                         qp->sq.max, nreq);
1449                         err = -ENOMEM;
1450                         *bad_wr = wr;
1451                         goto out;
1452                 }
1453
1454                 wqe = get_send_wqe(qp, ind);
1455                 prev_wqe = qp->sq.last;
1456                 qp->sq.last = wqe;
1457
1458                 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1459                 ((struct mthca_next_seg *) wqe)->ee_nds = 0;
1460                 ((struct mthca_next_seg *) wqe)->flags =
1461                         ((wr->send_flags & IB_SEND_SIGNALED) ?
1462                          cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1463                         ((wr->send_flags & IB_SEND_SOLICITED) ?
1464                          cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0)   |
1465                         cpu_to_be32(1);
1466                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1467                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1468                         ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1469
1470                 wqe += sizeof (struct mthca_next_seg);
1471                 size = sizeof (struct mthca_next_seg) / 16;
1472
1473                 switch (qp->transport) {
1474                 case RC:
1475                         switch (wr->opcode) {
1476                         case IB_WR_ATOMIC_CMP_AND_SWP:
1477                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1478                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1479                                         cpu_to_be64(wr->wr.atomic.remote_addr);
1480                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1481                                         cpu_to_be32(wr->wr.atomic.rkey);
1482                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1483
1484                                 wqe += sizeof (struct mthca_raddr_seg);
1485
1486                                 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1487                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1488                                                 cpu_to_be64(wr->wr.atomic.swap);
1489                                         ((struct mthca_atomic_seg *) wqe)->compare =
1490                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1491                                 } else {
1492                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1493                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1494                                         ((struct mthca_atomic_seg *) wqe)->compare = 0;
1495                                 }
1496
1497                                 wqe += sizeof (struct mthca_atomic_seg);
1498                                 size += sizeof (struct mthca_raddr_seg) / 16 +
1499                                         sizeof (struct mthca_atomic_seg);
1500                                 break;
1501
1502                         case IB_WR_RDMA_WRITE:
1503                         case IB_WR_RDMA_WRITE_WITH_IMM:
1504                         case IB_WR_RDMA_READ:
1505                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1506                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1507                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1508                                         cpu_to_be32(wr->wr.rdma.rkey);
1509                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1510                                 wqe += sizeof (struct mthca_raddr_seg);
1511                                 size += sizeof (struct mthca_raddr_seg) / 16;
1512                                 break;
1513
1514                         default:
1515                                 /* No extra segments required for sends */
1516                                 break;
1517                         }
1518
1519                         break;
1520
1521                 case UD:
1522                         ((struct mthca_tavor_ud_seg *) wqe)->lkey =
1523                                 cpu_to_be32(to_mah(wr->wr.ud.ah)->key);
1524                         ((struct mthca_tavor_ud_seg *) wqe)->av_addr =
1525                                 cpu_to_be64(to_mah(wr->wr.ud.ah)->avdma);
1526                         ((struct mthca_tavor_ud_seg *) wqe)->dqpn =
1527                                 cpu_to_be32(wr->wr.ud.remote_qpn);
1528                         ((struct mthca_tavor_ud_seg *) wqe)->qkey =
1529                                 cpu_to_be32(wr->wr.ud.remote_qkey);
1530
1531                         wqe += sizeof (struct mthca_tavor_ud_seg);
1532                         size += sizeof (struct mthca_tavor_ud_seg) / 16;
1533                         break;
1534
1535                 case MLX:
1536                         err = build_mlx_header(dev, to_msqp(qp), ind, wr,
1537                                                wqe - sizeof (struct mthca_next_seg),
1538                                                wqe);
1539                         if (err) {
1540                                 *bad_wr = wr;
1541                                 goto out;
1542                         }
1543                         wqe += sizeof (struct mthca_data_seg);
1544                         size += sizeof (struct mthca_data_seg) / 16;
1545                         break;
1546                 }
1547
1548                 if (wr->num_sge > qp->sq.max_gs) {
1549                         mthca_err(dev, "too many gathers\n");
1550                         err = -EINVAL;
1551                         *bad_wr = wr;
1552                         goto out;
1553                 }
1554
1555                 for (i = 0; i < wr->num_sge; ++i) {
1556                         ((struct mthca_data_seg *) wqe)->byte_count =
1557                                 cpu_to_be32(wr->sg_list[i].length);
1558                         ((struct mthca_data_seg *) wqe)->lkey =
1559                                 cpu_to_be32(wr->sg_list[i].lkey);
1560                         ((struct mthca_data_seg *) wqe)->addr =
1561                                 cpu_to_be64(wr->sg_list[i].addr);
1562                         wqe += sizeof (struct mthca_data_seg);
1563                         size += sizeof (struct mthca_data_seg) / 16;
1564                 }
1565
1566                 /* Add one more inline data segment for ICRC */
1567                 if (qp->transport == MLX) {
1568                         ((struct mthca_data_seg *) wqe)->byte_count =
1569                                 cpu_to_be32((1 << 31) | 4);
1570                         ((u32 *) wqe)[1] = 0;
1571                         wqe += sizeof (struct mthca_data_seg);
1572                         size += sizeof (struct mthca_data_seg) / 16;
1573                 }
1574
1575                 qp->wrid[ind + qp->rq.max] = wr->wr_id;
1576
1577                 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
1578                         mthca_err(dev, "opcode invalid\n");
1579                         err = -EINVAL;
1580                         *bad_wr = wr;
1581                         goto out;
1582                 }
1583
1584                 if (prev_wqe) {
1585                         ((struct mthca_next_seg *) prev_wqe)->nda_op =
1586                                 cpu_to_be32(((ind << qp->sq.wqe_shift) +
1587                                              qp->send_wqe_offset) |
1588                                             mthca_opcode[wr->opcode]);
1589                         wmb();
1590                         ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1591                                 cpu_to_be32((size0 ? 0 : MTHCA_NEXT_DBD) | size);
1592                 }
1593
1594                 if (!size0) {
1595                         size0 = size;
1596                         op0   = mthca_opcode[wr->opcode];
1597                 }
1598
1599                 ++ind;
1600                 if (unlikely(ind >= qp->sq.max))
1601                         ind -= qp->sq.max;
1602         }
1603
1604 out:
1605         if (likely(nreq)) {
1606                 u32 doorbell[2];
1607
1608                 doorbell[0] = cpu_to_be32(((qp->sq.next_ind << qp->sq.wqe_shift) +
1609                                            qp->send_wqe_offset) | f0 | op0);
1610                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1611
1612                 wmb();
1613
1614                 mthca_write64(doorbell,
1615                               dev->kar + MTHCA_SEND_DOORBELL,
1616                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1617         }
1618
1619         qp->sq.next_ind = ind;
1620         qp->sq.head    += nreq;
1621
1622         spin_unlock_irqrestore(&qp->sq.lock, flags);
1623         return err;
1624 }
1625
1626 int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1627                              struct ib_recv_wr **bad_wr)
1628 {
1629         struct mthca_dev *dev = to_mdev(ibqp->device);
1630         struct mthca_qp *qp = to_mqp(ibqp);
1631         unsigned long flags;
1632         int err = 0;
1633         int nreq;
1634         int i;
1635         int size;
1636         int size0 = 0;
1637         int ind;
1638         void *wqe;
1639         void *prev_wqe;
1640
1641         spin_lock_irqsave(&qp->rq.lock, flags);
1642
1643         /* XXX check that state is OK to post receive */
1644
1645         ind = qp->rq.next_ind;
1646
1647         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1648                 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
1649                         mthca_err(dev, "RQ %06x full (%u head, %u tail,"
1650                                         " %d max, %d nreq)\n", qp->qpn,
1651                                         qp->rq.head, qp->rq.tail,
1652                                         qp->rq.max, nreq);
1653                         err = -ENOMEM;
1654                         *bad_wr = wr;
1655                         goto out;
1656                 }
1657
1658                 wqe = get_recv_wqe(qp, ind);
1659                 prev_wqe = qp->rq.last;
1660                 qp->rq.last = wqe;
1661
1662                 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1663                 ((struct mthca_next_seg *) wqe)->ee_nds =
1664                         cpu_to_be32(MTHCA_NEXT_DBD);
1665                 ((struct mthca_next_seg *) wqe)->flags = 0;
1666
1667                 wqe += sizeof (struct mthca_next_seg);
1668                 size = sizeof (struct mthca_next_seg) / 16;
1669
1670                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1671                         err = -EINVAL;
1672                         *bad_wr = wr;
1673                         goto out;
1674                 }
1675
1676                 for (i = 0; i < wr->num_sge; ++i) {
1677                         ((struct mthca_data_seg *) wqe)->byte_count =
1678                                 cpu_to_be32(wr->sg_list[i].length);
1679                         ((struct mthca_data_seg *) wqe)->lkey =
1680                                 cpu_to_be32(wr->sg_list[i].lkey);
1681                         ((struct mthca_data_seg *) wqe)->addr =
1682                                 cpu_to_be64(wr->sg_list[i].addr);
1683                         wqe += sizeof (struct mthca_data_seg);
1684                         size += sizeof (struct mthca_data_seg) / 16;
1685                 }
1686
1687                 qp->wrid[ind] = wr->wr_id;
1688
1689                 if (likely(prev_wqe)) {
1690                         ((struct mthca_next_seg *) prev_wqe)->nda_op =
1691                                 cpu_to_be32((ind << qp->rq.wqe_shift) | 1);
1692                         wmb();
1693                         ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1694                                 cpu_to_be32(MTHCA_NEXT_DBD | size);
1695                 }
1696
1697                 if (!size0)
1698                         size0 = size;
1699
1700                 ++ind;
1701                 if (unlikely(ind >= qp->rq.max))
1702                         ind -= qp->rq.max;
1703         }
1704
1705 out:
1706         if (likely(nreq)) {
1707                 u32 doorbell[2];
1708
1709                 doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0);
1710                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | nreq);
1711
1712                 wmb();
1713
1714                 mthca_write64(doorbell,
1715                               dev->kar + MTHCA_RECEIVE_DOORBELL,
1716                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1717         }
1718
1719         qp->rq.next_ind = ind;
1720         qp->rq.head    += nreq;
1721
1722         spin_unlock_irqrestore(&qp->rq.lock, flags);
1723         return err;
1724 }
1725
1726 int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1727                           struct ib_send_wr **bad_wr)
1728 {
1729         struct mthca_dev *dev = to_mdev(ibqp->device);
1730         struct mthca_qp *qp = to_mqp(ibqp);
1731         void *wqe;
1732         void *prev_wqe;
1733         unsigned long flags;
1734         int err = 0;
1735         int nreq;
1736         int i;
1737         int size;
1738         int size0 = 0;
1739         u32 f0 = 0;
1740         int ind;
1741         u8 op0 = 0;
1742
1743         spin_lock_irqsave(&qp->sq.lock, flags);
1744
1745         /* XXX check that state is OK to post send */
1746
1747         ind = qp->sq.head & (qp->sq.max - 1);
1748
1749         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1750                 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1751                         mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1752                                         " %d max, %d nreq)\n", qp->qpn,
1753                                         qp->sq.head, qp->sq.tail,
1754                                         qp->sq.max, nreq);
1755                         err = -ENOMEM;
1756                         *bad_wr = wr;
1757                         goto out;
1758                 }
1759
1760                 wqe = get_send_wqe(qp, ind);
1761                 prev_wqe = qp->sq.last;
1762                 qp->sq.last = wqe;
1763
1764                 ((struct mthca_next_seg *) wqe)->flags =
1765                         ((wr->send_flags & IB_SEND_SIGNALED) ?
1766                          cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1767                         ((wr->send_flags & IB_SEND_SOLICITED) ?
1768                          cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0)   |
1769                         cpu_to_be32(1);
1770                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1771                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1772                         ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1773
1774                 wqe += sizeof (struct mthca_next_seg);
1775                 size = sizeof (struct mthca_next_seg) / 16;
1776
1777                 switch (qp->transport) {
1778                 case RC:
1779                         switch (wr->opcode) {
1780                         case IB_WR_ATOMIC_CMP_AND_SWP:
1781                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1782                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1783                                         cpu_to_be64(wr->wr.atomic.remote_addr);
1784                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1785                                         cpu_to_be32(wr->wr.atomic.rkey);
1786                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1787
1788                                 wqe += sizeof (struct mthca_raddr_seg);
1789
1790                                 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1791                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1792                                                 cpu_to_be64(wr->wr.atomic.swap);
1793                                         ((struct mthca_atomic_seg *) wqe)->compare =
1794                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1795                                 } else {
1796                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1797                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1798                                         ((struct mthca_atomic_seg *) wqe)->compare = 0;
1799                                 }
1800
1801                                 wqe += sizeof (struct mthca_atomic_seg);
1802                                 size += sizeof (struct mthca_raddr_seg) / 16 +
1803                                         sizeof (struct mthca_atomic_seg);
1804                                 break;
1805
1806                         case IB_WR_RDMA_WRITE:
1807                         case IB_WR_RDMA_WRITE_WITH_IMM:
1808                         case IB_WR_RDMA_READ:
1809                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1810                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1811                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1812                                         cpu_to_be32(wr->wr.rdma.rkey);
1813                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1814                                 wqe += sizeof (struct mthca_raddr_seg);
1815                                 size += sizeof (struct mthca_raddr_seg) / 16;
1816                                 break;
1817
1818                         default:
1819                                 /* No extra segments required for sends */
1820                                 break;
1821                         }
1822
1823                         break;
1824
1825                 case UD:
1826                         memcpy(((struct mthca_arbel_ud_seg *) wqe)->av,
1827                                to_mah(wr->wr.ud.ah)->av, MTHCA_AV_SIZE);
1828                         ((struct mthca_arbel_ud_seg *) wqe)->dqpn =
1829                                 cpu_to_be32(wr->wr.ud.remote_qpn);
1830                         ((struct mthca_arbel_ud_seg *) wqe)->qkey =
1831                                 cpu_to_be32(wr->wr.ud.remote_qkey);
1832
1833                         wqe += sizeof (struct mthca_arbel_ud_seg);
1834                         size += sizeof (struct mthca_arbel_ud_seg) / 16;
1835                         break;
1836
1837                 case MLX:
1838                         err = build_mlx_header(dev, to_msqp(qp), ind, wr,
1839                                                wqe - sizeof (struct mthca_next_seg),
1840                                                wqe);
1841                         if (err) {
1842                                 *bad_wr = wr;
1843                                 goto out;
1844                         }
1845                         wqe += sizeof (struct mthca_data_seg);
1846                         size += sizeof (struct mthca_data_seg) / 16;
1847                         break;
1848                 }
1849
1850                 if (wr->num_sge > qp->sq.max_gs) {
1851                         mthca_err(dev, "too many gathers\n");
1852                         err = -EINVAL;
1853                         *bad_wr = wr;
1854                         goto out;
1855                 }
1856
1857                 for (i = 0; i < wr->num_sge; ++i) {
1858                         ((struct mthca_data_seg *) wqe)->byte_count =
1859                                 cpu_to_be32(wr->sg_list[i].length);
1860                         ((struct mthca_data_seg *) wqe)->lkey =
1861                                 cpu_to_be32(wr->sg_list[i].lkey);
1862                         ((struct mthca_data_seg *) wqe)->addr =
1863                                 cpu_to_be64(wr->sg_list[i].addr);
1864                         wqe += sizeof (struct mthca_data_seg);
1865                         size += sizeof (struct mthca_data_seg) / 16;
1866                 }
1867
1868                 /* Add one more inline data segment for ICRC */
1869                 if (qp->transport == MLX) {
1870                         ((struct mthca_data_seg *) wqe)->byte_count =
1871                                 cpu_to_be32((1 << 31) | 4);
1872                         ((u32 *) wqe)[1] = 0;
1873                         wqe += sizeof (struct mthca_data_seg);
1874                         size += sizeof (struct mthca_data_seg) / 16;
1875                 }
1876
1877                 qp->wrid[ind + qp->rq.max] = wr->wr_id;
1878
1879                 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
1880                         mthca_err(dev, "opcode invalid\n");
1881                         err = -EINVAL;
1882                         *bad_wr = wr;
1883                         goto out;
1884                 }
1885
1886                 if (likely(prev_wqe)) {
1887                         ((struct mthca_next_seg *) prev_wqe)->nda_op =
1888                                 cpu_to_be32(((ind << qp->sq.wqe_shift) +
1889                                              qp->send_wqe_offset) |
1890                                             mthca_opcode[wr->opcode]);
1891                         wmb();
1892                         ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1893                                 cpu_to_be32(MTHCA_NEXT_DBD | size);
1894                 }
1895
1896                 if (!size0) {
1897                         size0 = size;
1898                         op0   = mthca_opcode[wr->opcode];
1899                 }
1900
1901                 ++ind;
1902                 if (unlikely(ind >= qp->sq.max))
1903                         ind -= qp->sq.max;
1904         }
1905
1906 out:
1907         if (likely(nreq)) {
1908                 u32 doorbell[2];
1909
1910                 doorbell[0] = cpu_to_be32((nreq << 24)                  |
1911                                           ((qp->sq.head & 0xffff) << 8) |
1912                                           f0 | op0);
1913                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1914
1915                 qp->sq.head += nreq;
1916
1917                 /*
1918                  * Make sure that descriptors are written before
1919                  * doorbell record.
1920                  */
1921                 wmb();
1922                 *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
1923
1924                 /*
1925                  * Make sure doorbell record is written before we
1926                  * write MMIO send doorbell.
1927                  */
1928                 wmb();
1929                 mthca_write64(doorbell,
1930                               dev->kar + MTHCA_SEND_DOORBELL,
1931                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1932         }
1933
1934         spin_unlock_irqrestore(&qp->sq.lock, flags);
1935         return err;
1936 }
1937
1938 int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1939                              struct ib_recv_wr **bad_wr)
1940 {
1941         struct mthca_dev *dev = to_mdev(ibqp->device);
1942         struct mthca_qp *qp = to_mqp(ibqp);
1943         unsigned long flags;
1944         int err = 0;
1945         int nreq;
1946         int ind;
1947         int i;
1948         void *wqe;
1949
1950         spin_lock_irqsave(&qp->rq.lock, flags);
1951
1952         /* XXX check that state is OK to post receive */
1953
1954         ind = qp->rq.head & (qp->rq.max - 1);
1955
1956         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1957                 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
1958                         mthca_err(dev, "RQ %06x full (%u head, %u tail,"
1959                                         " %d max, %d nreq)\n", qp->qpn,
1960                                         qp->rq.head, qp->rq.tail,
1961                                         qp->rq.max, nreq);
1962                         err = -ENOMEM;
1963                         *bad_wr = wr;
1964                         goto out;
1965                 }
1966
1967                 wqe = get_recv_wqe(qp, ind);
1968
1969                 ((struct mthca_next_seg *) wqe)->flags = 0;
1970
1971                 wqe += sizeof (struct mthca_next_seg);
1972
1973                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1974                         err = -EINVAL;
1975                         *bad_wr = wr;
1976                         goto out;
1977                 }
1978
1979                 for (i = 0; i < wr->num_sge; ++i) {
1980                         ((struct mthca_data_seg *) wqe)->byte_count =
1981                                 cpu_to_be32(wr->sg_list[i].length);
1982                         ((struct mthca_data_seg *) wqe)->lkey =
1983                                 cpu_to_be32(wr->sg_list[i].lkey);
1984                         ((struct mthca_data_seg *) wqe)->addr =
1985                                 cpu_to_be64(wr->sg_list[i].addr);
1986                         wqe += sizeof (struct mthca_data_seg);
1987                 }
1988
1989                 if (i < qp->rq.max_gs) {
1990                         ((struct mthca_data_seg *) wqe)->byte_count = 0;
1991                         ((struct mthca_data_seg *) wqe)->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
1992                         ((struct mthca_data_seg *) wqe)->addr = 0;
1993                 }
1994
1995                 qp->wrid[ind] = wr->wr_id;
1996
1997                 ++ind;
1998                 if (unlikely(ind >= qp->rq.max))
1999                         ind -= qp->rq.max;
2000         }
2001 out:
2002         if (likely(nreq)) {
2003                 qp->rq.head += nreq;
2004
2005                 /*
2006                  * Make sure that descriptors are written before
2007                  * doorbell record.
2008                  */
2009                 wmb();
2010                 *qp->rq.db = cpu_to_be32(qp->rq.head & 0xffff);
2011         }
2012
2013         spin_unlock_irqrestore(&qp->rq.lock, flags);
2014         return err;
2015 }
2016
2017 int mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
2018                        int index, int *dbd, u32 *new_wqe)
2019 {
2020         struct mthca_next_seg *next;
2021
2022         if (is_send)
2023                 next = get_send_wqe(qp, index);
2024         else
2025                 next = get_recv_wqe(qp, index);
2026
2027         if (mthca_is_memfree(dev))
2028                 *dbd = 1;
2029         else
2030                 *dbd = !!(next->ee_nds & cpu_to_be32(MTHCA_NEXT_DBD));
2031         if (next->ee_nds & cpu_to_be32(0x3f))
2032                 *new_wqe = (next->nda_op & cpu_to_be32(~0x3f)) |
2033                         (next->ee_nds & cpu_to_be32(0x3f));
2034         else
2035                 *new_wqe = 0;
2036
2037         return 0;
2038 }
2039
2040 int __devinit mthca_init_qp_table(struct mthca_dev *dev)
2041 {
2042         int err;
2043         u8 status;
2044         int i;
2045
2046         spin_lock_init(&dev->qp_table.lock);
2047
2048         /*
2049          * We reserve 2 extra QPs per port for the special QPs.  The
2050          * special QP for port 1 has to be even, so round up.
2051          */
2052         dev->qp_table.sqp_start = (dev->limits.reserved_qps + 1) & ~1UL;
2053         err = mthca_alloc_init(&dev->qp_table.alloc,
2054                                dev->limits.num_qps,
2055                                (1 << 24) - 1,
2056                                dev->qp_table.sqp_start +
2057                                MTHCA_MAX_PORTS * 2);
2058         if (err)
2059                 return err;
2060
2061         err = mthca_array_init(&dev->qp_table.qp,
2062                                dev->limits.num_qps);
2063         if (err) {
2064                 mthca_alloc_cleanup(&dev->qp_table.alloc);
2065                 return err;
2066         }
2067
2068         for (i = 0; i < 2; ++i) {
2069                 err = mthca_CONF_SPECIAL_QP(dev, i ? IB_QPT_GSI : IB_QPT_SMI,
2070                                             dev->qp_table.sqp_start + i * 2,
2071                                             &status);
2072                 if (err)
2073                         goto err_out;
2074                 if (status) {
2075                         mthca_warn(dev, "CONF_SPECIAL_QP returned "
2076                                    "status %02x, aborting.\n",
2077                                    status);
2078                         err = -EINVAL;
2079                         goto err_out;
2080                 }
2081         }
2082         return 0;
2083
2084  err_out:
2085         for (i = 0; i < 2; ++i)
2086                 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2087
2088         mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2089         mthca_alloc_cleanup(&dev->qp_table.alloc);
2090
2091         return err;
2092 }
2093
2094 void __devexit mthca_cleanup_qp_table(struct mthca_dev *dev)
2095 {
2096         int i;
2097         u8 status;
2098
2099         for (i = 0; i < 2; ++i)
2100                 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2101
2102         mthca_alloc_cleanup(&dev->qp_table.alloc);
2103 }