git.oblomov.eu Git - linux-2.6/blob - drivers/net/typhoon.c

   1 /* typhoon.c: A Linux Ethernet device driver for 3Com 3CR990 family of NICs */
   2 /*
   3         Written 2002-2004 by David Dillow <dave@thedillows.org>
   4         Based on code written 1998-2000 by Donald Becker <becker@scyld.com> and
   5         Linux 2.2.x driver by David P. McLean <davidpmclean@yahoo.com>.
   6
   7         This software may be used and distributed according to the terms of
   8         the GNU General Public License (GPL), incorporated herein by reference.
   9         Drivers based on or derived from this code fall under the GPL and must
  10         retain the authorship, copyright and license notice.  This file is not
  11         a complete program and may only be used when the entire operating
  12         system is licensed under the GPL.
  13
  14         This software is available on a public web site. It may enable
  15         cryptographic capabilities of the 3Com hardware, and may be
  16         exported from the United States under License Exception "TSU"
  17         pursuant to 15 C.F.R. Section 740.13(e).
  18
  19         This work was funded by the National Library of Medicine under
  20         the Department of Energy project number 0274DD06D1 and NLM project
  21         number Y1-LM-2015-01.
  22
  23         This driver is designed for the 3Com 3CR990 Family of cards with the
  24         3XP Processor. It has been tested on x86 and sparc64.
  25
  26         KNOWN ISSUES:
  27         *) The current firmware always strips the VLAN tag off, even if
  28                 we tell it not to. You should filter VLANs at the switch
  29                 as a workaround (good practice in any event) until we can
  30                 get this fixed.
  31         *) Cannot DMA Rx packets to a 2 byte aligned address. Also firmware
  32                 issue. Hopefully 3Com will fix it.
  33         *) Waiting for a command response takes 8ms due to non-preemptable
  34                 polling. Only significant for getting stats and creating
  35                 SAs, but an ugly wart never the less.
  36
  37         TODO:
  38         *) Doesn't do IPSEC offloading. Yet. Keep yer pants on, it's coming.
  39         *) Add more support for ethtool (especially for NIC stats)
  40         *) Allow disabling of RX checksum offloading
  41         *) Fix MAC changing to work while the interface is up
  42                 (Need to put commands on the TX ring, which changes
  43                 the locking)
  44         *) Add in FCS to {rx,tx}_bytes, since the hardware doesn't. See
  45                 http://oss.sgi.com/cgi-bin/mesg.cgi?a=netdev&i=20031215152211.7003fe8e.rddunlap%40osdl.org
  46 */
  47
  48 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
  49  * Setting to > 1518 effectively disables this feature.
  50  */
  51 static int rx_copybreak = 200;
  52
  53 /* Should we use MMIO or Port IO?
  54  * 0: Port IO
  55  * 1: MMIO
  56  * 2: Try MMIO, fallback to Port IO
  57  */
  58 static unsigned int use_mmio = 2;
  59
  60 /* end user-configurable values */
  61
  62 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
  63  */
  64 static const int multicast_filter_limit = 32;
  65
  66 /* Operational parameters that are set at compile time. */
  67
  68 /* Keep the ring sizes a power of two for compile efficiency.
  69  * The compiler will convert <unsigned>'%'<2^N> into a bit mask.
  70  * Making the Tx ring too large decreases the effectiveness of channel
  71  * bonding and packet priority.
  72  * There are no ill effects from too-large receive rings.
  73  *
  74  * We don't currently use the Hi Tx ring so, don't make it very big.
  75  *
  76  * Beware that if we start using the Hi Tx ring, we will need to change
  77  * typhoon_num_free_tx() and typhoon_tx_complete() to account for that.
  78  */
  79 #define TXHI_ENTRIES            2
  80 #define TXLO_ENTRIES            128
  81 #define RX_ENTRIES              32
  82 #define COMMAND_ENTRIES         16
  83 #define RESPONSE_ENTRIES        32
  84
  85 #define COMMAND_RING_SIZE       (COMMAND_ENTRIES * sizeof(struct cmd_desc))
  86 #define RESPONSE_RING_SIZE      (RESPONSE_ENTRIES * sizeof(struct resp_desc))
  87
  88 /* The 3XP will preload and remove 64 entries from the free buffer
  89  * list, and we need one entry to keep the ring from wrapping, so
  90  * to keep this a power of two, we use 128 entries.
  91  */
  92 #define RXFREE_ENTRIES          128
  93 #define RXENT_ENTRIES           (RXFREE_ENTRIES - 1)
  94
  95 /* Operational parameters that usually are not changed. */
  96
  97 /* Time in jiffies before concluding the transmitter is hung. */
  98 #define TX_TIMEOUT  (2*HZ)
  99
 100 #define PKT_BUF_SZ              1536
 101
 102 #define DRV_MODULE_NAME         "typhoon"
 103 #define DRV_MODULE_VERSION      "1.5.8"
 104 #define DRV_MODULE_RELDATE      "06/11/09"
 105 #define PFX                     DRV_MODULE_NAME ": "
 106 #define ERR_PFX                 KERN_ERR PFX
 107
 108 #include <linux/module.h>
 109 #include <linux/kernel.h>
 110 #include <linux/string.h>
 111 #include <linux/timer.h>
 112 #include <linux/errno.h>
 113 #include <linux/ioport.h>
 114 #include <linux/slab.h>
 115 #include <linux/interrupt.h>
 116 #include <linux/pci.h>
 117 #include <linux/netdevice.h>
 118 #include <linux/etherdevice.h>
 119 #include <linux/skbuff.h>
 120 #include <linux/mm.h>
 121 #include <linux/init.h>
 122 #include <linux/delay.h>
 123 #include <linux/ethtool.h>
 124 #include <linux/if_vlan.h>
 125 #include <linux/crc32.h>
 126 #include <linux/bitops.h>
 127 #include <asm/processor.h>
 128 #include <asm/io.h>
 129 #include <asm/uaccess.h>
 130 #include <linux/in6.h>
 131 #include <linux/version.h>
 132 #include <linux/dma-mapping.h>
 133
 134 #include "typhoon.h"
 135 #include "typhoon-firmware.h"
 136
 137 static const char version[] __devinitdata =
 138     "typhoon.c: version " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 139
 140 MODULE_AUTHOR("David Dillow <dave@thedillows.org>");
 141 MODULE_VERSION(DRV_MODULE_VERSION);
 142 MODULE_LICENSE("GPL");
 143 MODULE_DESCRIPTION("3Com Typhoon Family (3C990, 3CR990, and variants)");
 144 MODULE_PARM_DESC(rx_copybreak, "Packets smaller than this are copied and "
 145                                "the buffer given back to the NIC. Default "
 146                                "is 200.");
 147 MODULE_PARM_DESC(use_mmio, "Use MMIO (1) or PIO(0) to access the NIC. "
 148                            "Default is to try MMIO and fallback to PIO.");
 149 module_param(rx_copybreak, int, 0);
 150 module_param(use_mmio, int, 0);
 151
 152 #if defined(NETIF_F_TSO) && MAX_SKB_FRAGS > 32
 153 #warning Typhoon only supports 32 entries in its SG list for TSO, disabling TSO
 154 #undef NETIF_F_TSO
 155 #endif
 156
 157 #if TXLO_ENTRIES <= (2 * MAX_SKB_FRAGS)
 158 #error TX ring too small!
 159 #endif
 160
 161 struct typhoon_card_info {
 162         char *name;
 163         int capabilities;
 164 };
 165
 166 #define TYPHOON_CRYPTO_NONE             0x00
 167 #define TYPHOON_CRYPTO_DES              0x01
 168 #define TYPHOON_CRYPTO_3DES             0x02
 169 #define TYPHOON_CRYPTO_VARIABLE         0x04
 170 #define TYPHOON_FIBER                   0x08
 171 #define TYPHOON_WAKEUP_NEEDS_RESET      0x10
 172
 173 enum typhoon_cards {
 174         TYPHOON_TX = 0, TYPHOON_TX95, TYPHOON_TX97, TYPHOON_SVR,
 175         TYPHOON_SVR95, TYPHOON_SVR97, TYPHOON_TXM, TYPHOON_BSVR,
 176         TYPHOON_FX95, TYPHOON_FX97, TYPHOON_FX95SVR, TYPHOON_FX97SVR,
 177         TYPHOON_FXM,
 178 };
 179
 180 /* directly indexed by enum typhoon_cards, above */
 181 static const struct typhoon_card_info typhoon_card_info[] __devinitdata = {
 182         { "3Com Typhoon (3C990-TX)",
 183                 TYPHOON_CRYPTO_NONE},
 184         { "3Com Typhoon (3CR990-TX-95)",
 185                 TYPHOON_CRYPTO_DES},
 186         { "3Com Typhoon (3CR990-TX-97)",
 187                 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES},
 188         { "3Com Typhoon (3C990SVR)",
 189                 TYPHOON_CRYPTO_NONE},
 190         { "3Com Typhoon (3CR990SVR95)",
 191                 TYPHOON_CRYPTO_DES},
 192         { "3Com Typhoon (3CR990SVR97)",
 193                 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES},
 194         { "3Com Typhoon2 (3C990B-TX-M)",
 195                 TYPHOON_CRYPTO_VARIABLE},
 196         { "3Com Typhoon2 (3C990BSVR)",
 197                 TYPHOON_CRYPTO_VARIABLE},
 198         { "3Com Typhoon (3CR990-FX-95)",
 199                 TYPHOON_CRYPTO_DES | TYPHOON_FIBER},
 200         { "3Com Typhoon (3CR990-FX-97)",
 201                 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES | TYPHOON_FIBER},
 202         { "3Com Typhoon (3CR990-FX-95 Server)",
 203                 TYPHOON_CRYPTO_DES | TYPHOON_FIBER},
 204         { "3Com Typhoon (3CR990-FX-97 Server)",
 205                 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES | TYPHOON_FIBER},
 206         { "3Com Typhoon2 (3C990B-FX-97)",
 207                 TYPHOON_CRYPTO_VARIABLE | TYPHOON_FIBER},
 208 };
 209
 210 /* Notes on the new subsystem numbering scheme:
 211  * bits 0-1 indicate crypto capabilities: (0) variable, (1) DES, or (2) 3DES
 212  * bit 4 indicates if this card has secured firmware (we don't support it)
 213  * bit 8 indicates if this is a (0) copper or (1) fiber card
 214  * bits 12-16 indicate card type: (0) client and (1) server
 215  */
 216 static struct pci_device_id typhoon_pci_tbl[] = {
 217         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990,
 218           PCI_ANY_ID, PCI_ANY_ID, 0, 0,TYPHOON_TX },
 219         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_TX_95,
 220           PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_TX95 },
 221         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_TX_97,
 222           PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_TX97 },
 223         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
 224           PCI_ANY_ID, 0x1000, 0, 0, TYPHOON_TXM },
 225         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
 226           PCI_ANY_ID, 0x1102, 0, 0, TYPHOON_FXM },
 227         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
 228           PCI_ANY_ID, 0x2000, 0, 0, TYPHOON_BSVR },
 229         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
 230           PCI_ANY_ID, 0x1101, 0, 0, TYPHOON_FX95 },
 231         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
 232           PCI_ANY_ID, 0x1102, 0, 0, TYPHOON_FX97 },
 233         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
 234           PCI_ANY_ID, 0x2101, 0, 0, TYPHOON_FX95SVR },
 235         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
 236           PCI_ANY_ID, 0x2102, 0, 0, TYPHOON_FX97SVR },
 237         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR95,
 238           PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR95 },
 239         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR97,
 240           PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR97 },
 241         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR,
 242           PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR },
 243         { 0, }
 244 };
 245 MODULE_DEVICE_TABLE(pci, typhoon_pci_tbl);
 246
 247 /* Define the shared memory area
 248  * Align everything the 3XP will normally be using.
 249  * We'll need to move/align txHi if we start using that ring.
 250  */
 251 #define __3xp_aligned   ____cacheline_aligned
 252 struct typhoon_shared {
 253         struct typhoon_interface        iface;
 254         struct typhoon_indexes          indexes                 __3xp_aligned;
 255         struct tx_desc                  txLo[TXLO_ENTRIES]      __3xp_aligned;
 256         struct rx_desc                  rxLo[RX_ENTRIES]        __3xp_aligned;
 257         struct rx_desc                  rxHi[RX_ENTRIES]        __3xp_aligned;
 258         struct cmd_desc                 cmd[COMMAND_ENTRIES]    __3xp_aligned;
 259         struct resp_desc                resp[RESPONSE_ENTRIES]  __3xp_aligned;
 260         struct rx_free                  rxBuff[RXFREE_ENTRIES]  __3xp_aligned;
 261         u32                             zeroWord;
 262         struct tx_desc                  txHi[TXHI_ENTRIES];
 263 } __attribute__ ((packed));
 264
 265 struct rxbuff_ent {
 266         struct sk_buff *skb;
 267         dma_addr_t      dma_addr;
 268 };
 269
 270 struct typhoon {
 271         /* Tx cache line section */
 272         struct transmit_ring    txLoRing        ____cacheline_aligned;
 273         struct pci_dev *        tx_pdev;
 274         void __iomem            *tx_ioaddr;
 275         u32                     txlo_dma_addr;
 276
 277         /* Irq/Rx cache line section */
 278         void __iomem            *ioaddr         ____cacheline_aligned;
 279         struct typhoon_indexes *indexes;
 280         u8                      awaiting_resp;
 281         u8                      duplex;
 282         u8                      speed;
 283         u8                      card_state;
 284         struct basic_ring       rxLoRing;
 285         struct pci_dev *        pdev;
 286         struct net_device *     dev;
 287         struct napi_struct      napi;
 288         spinlock_t              state_lock;
 289         struct vlan_group *     vlgrp;
 290         struct basic_ring       rxHiRing;
 291         struct basic_ring       rxBuffRing;
 292         struct rxbuff_ent       rxbuffers[RXENT_ENTRIES];
 293
 294         /* general section */
 295         spinlock_t              command_lock    ____cacheline_aligned;
 296         struct basic_ring       cmdRing;
 297         struct basic_ring       respRing;
 298         struct net_device_stats stats;
 299         struct net_device_stats stats_saved;
 300         const char *            name;
 301         struct typhoon_shared * shared;
 302         dma_addr_t              shared_dma;
 303         __le16                  xcvr_select;
 304         __le16                  wol_events;
 305         __le32                  offload;
 306
 307         /* unused stuff (future use) */
 308         int                     capabilities;
 309         struct transmit_ring    txHiRing;
 310 };
 311
 312 enum completion_wait_values {
 313         NoWait = 0, WaitNoSleep, WaitSleep,
 314 };
 315
 316 /* These are the values for the typhoon.card_state variable.
 317  * These determine where the statistics will come from in get_stats().
 318  * The sleep image does not support the statistics we need.
 319  */
 320 enum state_values {
 321         Sleeping = 0, Running,
 322 };
 323
 324 /* PCI writes are not guaranteed to be posted in order, but outstanding writes
 325  * cannot pass a read, so this forces current writes to post.
 326  */
 327 #define typhoon_post_pci_writes(x) \
 328         do { if(likely(use_mmio)) ioread32(x+TYPHOON_REG_HEARTBEAT); } while(0)
 329
 330 /* We'll wait up to six seconds for a reset, and half a second normally.
 331  */
 332 #define TYPHOON_UDELAY                  50
 333 #define TYPHOON_RESET_TIMEOUT_SLEEP     (6 * HZ)
 334 #define TYPHOON_RESET_TIMEOUT_NOSLEEP   ((6 * 1000000) / TYPHOON_UDELAY)
 335 #define TYPHOON_WAIT_TIMEOUT            ((1000000 / 2) / TYPHOON_UDELAY)
 336
 337 #define typhoon_synchronize_irq(x) synchronize_irq(x)
 338
 339 #if defined(NETIF_F_TSO)
 340 #define skb_tso_size(x)         (skb_shinfo(x)->gso_size)
 341 #define TSO_NUM_DESCRIPTORS     2
 342 #define TSO_OFFLOAD_ON          TYPHOON_OFFLOAD_TCP_SEGMENT
 343 #else
 344 #define NETIF_F_TSO             0
 345 #define skb_tso_size(x)         0
 346 #define TSO_NUM_DESCRIPTORS     0
 347 #define TSO_OFFLOAD_ON          0
 348 #endif
 349
 350 static inline void
 351 typhoon_inc_index(u32 *index, const int count, const int num_entries)
 352 {
 353         /* Increment a ring index -- we can use this for all rings execept
 354          * the Rx rings, as they use different size descriptors
 355          * otherwise, everything is the same size as a cmd_desc
 356          */
 357         *index += count * sizeof(struct cmd_desc);
 358         *index %= num_entries * sizeof(struct cmd_desc);
 359 }
 360
 361 static inline void
 362 typhoon_inc_cmd_index(u32 *index, const int count)
 363 {
 364         typhoon_inc_index(index, count, COMMAND_ENTRIES);
 365 }
 366
 367 static inline void
 368 typhoon_inc_resp_index(u32 *index, const int count)
 369 {
 370         typhoon_inc_index(index, count, RESPONSE_ENTRIES);
 371 }
 372
 373 static inline void
 374 typhoon_inc_rxfree_index(u32 *index, const int count)
 375 {
 376         typhoon_inc_index(index, count, RXFREE_ENTRIES);
 377 }
 378
 379 static inline void
 380 typhoon_inc_tx_index(u32 *index, const int count)
 381 {
 382         /* if we start using the Hi Tx ring, this needs updateing */
 383         typhoon_inc_index(index, count, TXLO_ENTRIES);
 384 }
 385
 386 static inline void
 387 typhoon_inc_rx_index(u32 *index, const int count)
 388 {
 389         /* sizeof(struct rx_desc) != sizeof(struct cmd_desc) */
 390         *index += count * sizeof(struct rx_desc);
 391         *index %= RX_ENTRIES * sizeof(struct rx_desc);
 392 }
 393
 394 static int
 395 typhoon_reset(void __iomem *ioaddr, int wait_type)
 396 {
 397         int i, err = 0;
 398         int timeout;
 399
 400         if(wait_type == WaitNoSleep)
 401                 timeout = TYPHOON_RESET_TIMEOUT_NOSLEEP;
 402         else
 403                 timeout = TYPHOON_RESET_TIMEOUT_SLEEP;
 404
 405         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
 406         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
 407
 408         iowrite32(TYPHOON_RESET_ALL, ioaddr + TYPHOON_REG_SOFT_RESET);
 409         typhoon_post_pci_writes(ioaddr);
 410         udelay(1);
 411         iowrite32(TYPHOON_RESET_NONE, ioaddr + TYPHOON_REG_SOFT_RESET);
 412
 413         if(wait_type != NoWait) {
 414                 for(i = 0; i < timeout; i++) {
 415                         if(ioread32(ioaddr + TYPHOON_REG_STATUS) ==
 416                            TYPHOON_STATUS_WAITING_FOR_HOST)
 417                                 goto out;
 418
 419                         if(wait_type == WaitSleep)
 420                                 schedule_timeout_uninterruptible(1);
 421                         else
 422                                 udelay(TYPHOON_UDELAY);
 423                 }
 424
 425                 err = -ETIMEDOUT;
 426         }
 427
 428 out:
 429         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
 430         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
 431
 432         /* The 3XP seems to need a little extra time to complete the load
 433          * of the sleep image before we can reliably boot it. Failure to
 434          * do this occasionally results in a hung adapter after boot in
 435          * typhoon_init_one() while trying to read the MAC address or
 436          * putting the card to sleep. 3Com's driver waits 5ms, but
 437          * that seems to be overkill. However, if we can sleep, we might
 438          * as well give it that much time. Otherwise, we'll give it 500us,
 439          * which should be enough (I've see it work well at 100us, but still
 440          * saw occasional problems.)
 441          */
 442         if(wait_type == WaitSleep)
 443                 msleep(5);
 444         else
 445                 udelay(500);
 446         return err;
 447 }
 448
 449 static int
 450 typhoon_wait_status(void __iomem *ioaddr, u32 wait_value)
 451 {
 452         int i, err = 0;
 453
 454         for(i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
 455                 if(ioread32(ioaddr + TYPHOON_REG_STATUS) == wait_value)
 456                         goto out;
 457                 udelay(TYPHOON_UDELAY);
 458         }
 459
 460         err = -ETIMEDOUT;
 461
 462 out:
 463         return err;
 464 }
 465
 466 static inline void
 467 typhoon_media_status(struct net_device *dev, struct resp_desc *resp)
 468 {
 469         if(resp->parm1 & TYPHOON_MEDIA_STAT_NO_LINK)
 470                 netif_carrier_off(dev);
 471         else
 472                 netif_carrier_on(dev);
 473 }
 474
 475 static inline void
 476 typhoon_hello(struct typhoon *tp)
 477 {
 478         struct basic_ring *ring = &tp->cmdRing;
 479         struct cmd_desc *cmd;
 480
 481         /* We only get a hello request if we've not sent anything to the
 482          * card in a long while. If the lock is held, then we're in the
 483          * process of issuing a command, so we don't need to respond.
 484          */
 485         if(spin_trylock(&tp->command_lock)) {
 486                 cmd = (struct cmd_desc *)(ring->ringBase + ring->lastWrite);
 487                 typhoon_inc_cmd_index(&ring->lastWrite, 1);
 488
 489                 INIT_COMMAND_NO_RESPONSE(cmd, TYPHOON_CMD_HELLO_RESP);
 490                 smp_wmb();
 491                 iowrite32(ring->lastWrite, tp->ioaddr + TYPHOON_REG_CMD_READY);
 492                 spin_unlock(&tp->command_lock);
 493         }
 494 }
 495
 496 static int
 497 typhoon_process_response(struct typhoon *tp, int resp_size,
 498                                 struct resp_desc *resp_save)
 499 {
 500         struct typhoon_indexes *indexes = tp->indexes;
 501         struct resp_desc *resp;
 502         u8 *base = tp->respRing.ringBase;
 503         int count, len, wrap_len;
 504         u32 cleared;
 505         u32 ready;
 506
 507         cleared = le32_to_cpu(indexes->respCleared);
 508         ready = le32_to_cpu(indexes->respReady);
 509         while(cleared != ready) {
 510                 resp = (struct resp_desc *)(base + cleared);
 511                 count = resp->numDesc + 1;
 512                 if(resp_save && resp->seqNo) {
 513                         if(count > resp_size) {
 514                                 resp_save->flags = TYPHOON_RESP_ERROR;
 515                                 goto cleanup;
 516                         }
 517
 518                         wrap_len = 0;
 519                         len = count * sizeof(*resp);
 520                         if(unlikely(cleared + len > RESPONSE_RING_SIZE)) {
 521                                 wrap_len = cleared + len - RESPONSE_RING_SIZE;
 522                                 len = RESPONSE_RING_SIZE - cleared;
 523                         }
 524
 525                         memcpy(resp_save, resp, len);
 526                         if(unlikely(wrap_len)) {
 527                                 resp_save += len / sizeof(*resp);
 528                                 memcpy(resp_save, base, wrap_len);
 529                         }
 530
 531                         resp_save = NULL;
 532                 } else if(resp->cmd == TYPHOON_CMD_READ_MEDIA_STATUS) {
 533                         typhoon_media_status(tp->dev, resp);
 534                 } else if(resp->cmd == TYPHOON_CMD_HELLO_RESP) {
 535                         typhoon_hello(tp);
 536                 } else {
 537                         printk(KERN_ERR "%s: dumping unexpected response "
 538                                "0x%04x:%d:0x%02x:0x%04x:%08x:%08x\n",
 539                                tp->name, le16_to_cpu(resp->cmd),
 540                                resp->numDesc, resp->flags,
 541                                le16_to_cpu(resp->parm1),
 542                                le32_to_cpu(resp->parm2),
 543                                le32_to_cpu(resp->parm3));
 544                 }
 545
 546 cleanup:
 547                 typhoon_inc_resp_index(&cleared, count);
 548         }
 549
 550         indexes->respCleared = cpu_to_le32(cleared);
 551         wmb();
 552         return (resp_save == NULL);
 553 }
 554
 555 static inline int
 556 typhoon_num_free(int lastWrite, int lastRead, int ringSize)
 557 {
 558         /* this works for all descriptors but rx_desc, as they are a
 559          * different size than the cmd_desc -- everyone else is the same
 560          */
 561         lastWrite /= sizeof(struct cmd_desc);
 562         lastRead /= sizeof(struct cmd_desc);
 563         return (ringSize + lastRead - lastWrite - 1) % ringSize;
 564 }
 565
 566 static inline int
 567 typhoon_num_free_cmd(struct typhoon *tp)
 568 {
 569         int lastWrite = tp->cmdRing.lastWrite;
 570         int cmdCleared = le32_to_cpu(tp->indexes->cmdCleared);
 571
 572         return typhoon_num_free(lastWrite, cmdCleared, COMMAND_ENTRIES);
 573 }
 574
 575 static inline int
 576 typhoon_num_free_resp(struct typhoon *tp)
 577 {
 578         int respReady = le32_to_cpu(tp->indexes->respReady);
 579         int respCleared = le32_to_cpu(tp->indexes->respCleared);
 580
 581         return typhoon_num_free(respReady, respCleared, RESPONSE_ENTRIES);
 582 }
 583
 584 static inline int
 585 typhoon_num_free_tx(struct transmit_ring *ring)
 586 {
 587         /* if we start using the Hi Tx ring, this needs updating */
 588         return typhoon_num_free(ring->lastWrite, ring->lastRead, TXLO_ENTRIES);
 589 }
 590
 591 static int
 592 typhoon_issue_command(struct typhoon *tp, int num_cmd, struct cmd_desc *cmd,
 593                       int num_resp, struct resp_desc *resp)
 594 {
 595         struct typhoon_indexes *indexes = tp->indexes;
 596         struct basic_ring *ring = &tp->cmdRing;
 597         struct resp_desc local_resp;
 598         int i, err = 0;
 599         int got_resp;
 600         int freeCmd, freeResp;
 601         int len, wrap_len;
 602
 603         spin_lock(&tp->command_lock);
 604
 605         freeCmd = typhoon_num_free_cmd(tp);
 606         freeResp = typhoon_num_free_resp(tp);
 607
 608         if(freeCmd < num_cmd || freeResp < num_resp) {
 609                 printk("%s: no descs for cmd, had (needed) %d (%d) cmd, "
 610                         "%d (%d) resp\n", tp->name, freeCmd, num_cmd,
 611                         freeResp, num_resp);
 612                 err = -ENOMEM;
 613                 goto out;
 614         }
 615
 616         if(cmd->flags & TYPHOON_CMD_RESPOND) {
 617                 /* If we're expecting a response, but the caller hasn't given
 618                  * us a place to put it, we'll provide one.
 619                  */
 620                 tp->awaiting_resp = 1;
 621                 if(resp == NULL) {
 622                         resp = &local_resp;
 623                         num_resp = 1;
 624                 }
 625         }
 626
 627         wrap_len = 0;
 628         len = num_cmd * sizeof(*cmd);
 629         if(unlikely(ring->lastWrite + len > COMMAND_RING_SIZE)) {
 630                 wrap_len = ring->lastWrite + len - COMMAND_RING_SIZE;
 631                 len = COMMAND_RING_SIZE - ring->lastWrite;
 632         }
 633
 634         memcpy(ring->ringBase + ring->lastWrite, cmd, len);
 635         if(unlikely(wrap_len)) {
 636                 struct cmd_desc *wrap_ptr = cmd;
 637                 wrap_ptr += len / sizeof(*cmd);
 638                 memcpy(ring->ringBase, wrap_ptr, wrap_len);
 639         }
 640
 641         typhoon_inc_cmd_index(&ring->lastWrite, num_cmd);
 642
 643         /* "I feel a presence... another warrior is on the mesa."
 644          */
 645         wmb();
 646         iowrite32(ring->lastWrite, tp->ioaddr + TYPHOON_REG_CMD_READY);
 647         typhoon_post_pci_writes(tp->ioaddr);
 648
 649         if((cmd->flags & TYPHOON_CMD_RESPOND) == 0)
 650                 goto out;
 651
 652         /* Ugh. We'll be here about 8ms, spinning our thumbs, unable to
 653          * preempt or do anything other than take interrupts. So, don't
 654          * wait for a response unless you have to.
 655          *
 656          * I've thought about trying to sleep here, but we're called
 657          * from many contexts that don't allow that. Also, given the way
 658          * 3Com has implemented irq coalescing, we would likely timeout --
 659          * this has been observed in real life!
 660          *
 661          * The big killer is we have to wait to get stats from the card,
 662          * though we could go to a periodic refresh of those if we don't
 663          * mind them getting somewhat stale. The rest of the waiting
 664          * commands occur during open/close/suspend/resume, so they aren't
 665          * time critical. Creating SAs in the future will also have to
 666          * wait here.
 667          */
 668         got_resp = 0;
 669         for(i = 0; i < TYPHOON_WAIT_TIMEOUT && !got_resp; i++) {
 670                 if(indexes->respCleared != indexes->respReady)
 671                         got_resp = typhoon_process_response(tp, num_resp,
 672                                                                 resp);
 673                 udelay(TYPHOON_UDELAY);
 674         }
 675
 676         if(!got_resp) {
 677                 err = -ETIMEDOUT;
 678                 goto out;
 679         }
 680
 681         /* Collect the error response even if we don't care about the
 682          * rest of the response
 683          */
 684         if(resp->flags & TYPHOON_RESP_ERROR)
 685                 err = -EIO;
 686
 687 out:
 688         if(tp->awaiting_resp) {
 689                 tp->awaiting_resp = 0;
 690                 smp_wmb();
 691
 692                 /* Ugh. If a response was added to the ring between
 693                  * the call to typhoon_process_response() and the clearing
 694                  * of tp->awaiting_resp, we could have missed the interrupt
 695                  * and it could hang in the ring an indeterminate amount of
 696                  * time. So, check for it, and interrupt ourselves if this
 697                  * is the case.
 698                  */
 699                 if(indexes->respCleared != indexes->respReady)
 700                         iowrite32(1, tp->ioaddr + TYPHOON_REG_SELF_INTERRUPT);
 701         }
 702
 703         spin_unlock(&tp->command_lock);
 704         return err;
 705 }
 706
 707 static void
 708 typhoon_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
 709 {
 710         struct typhoon *tp = netdev_priv(dev);
 711         struct cmd_desc xp_cmd;
 712         int err;
 713
 714         spin_lock_bh(&tp->state_lock);
 715         if(!tp->vlgrp != !grp) {
 716                 /* We've either been turned on for the first time, or we've
 717                  * been turned off. Update the 3XP.
 718                  */
 719                 if(grp)
 720                         tp->offload |= TYPHOON_OFFLOAD_VLAN;
 721                 else
 722                         tp->offload &= ~TYPHOON_OFFLOAD_VLAN;
 723
 724                 /* If the interface is up, the runtime is running -- and we
 725                  * must be up for the vlan core to call us.
 726                  *
 727                  * Do the command outside of the spin lock, as it is slow.
 728                  */
 729                 INIT_COMMAND_WITH_RESPONSE(&xp_cmd,
 730                                         TYPHOON_CMD_SET_OFFLOAD_TASKS);
 731                 xp_cmd.parm2 = tp->offload;
 732                 xp_cmd.parm3 = tp->offload;
 733                 spin_unlock_bh(&tp->state_lock);
 734                 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
 735                 if(err < 0)
 736                         printk("%s: vlan offload error %d\n", tp->name, -err);
 737                 spin_lock_bh(&tp->state_lock);
 738         }
 739
 740         /* now make the change visible */
 741         tp->vlgrp = grp;
 742         spin_unlock_bh(&tp->state_lock);
 743 }
 744
 745 static inline void
 746 typhoon_tso_fill(struct sk_buff *skb, struct transmit_ring *txRing,
 747                         u32 ring_dma)
 748 {
 749         struct tcpopt_desc *tcpd;
 750         u32 tcpd_offset = ring_dma;
 751
 752         tcpd = (struct tcpopt_desc *) (txRing->ringBase + txRing->lastWrite);
 753         tcpd_offset += txRing->lastWrite;
 754         tcpd_offset += offsetof(struct tcpopt_desc, bytesTx);
 755         typhoon_inc_tx_index(&txRing->lastWrite, 1);
 756
 757         tcpd->flags = TYPHOON_OPT_DESC | TYPHOON_OPT_TCP_SEG;
 758         tcpd->numDesc = 1;
 759         tcpd->mss_flags = cpu_to_le16(skb_tso_size(skb));
 760         tcpd->mss_flags |= TYPHOON_TSO_FIRST | TYPHOON_TSO_LAST;
 761         tcpd->respAddrLo = cpu_to_le32(tcpd_offset);
 762         tcpd->bytesTx = cpu_to_le32(skb->len);
 763         tcpd->status = 0;
 764 }
 765
 766 static int
 767 typhoon_start_tx(struct sk_buff *skb, struct net_device *dev)
 768 {
 769         struct typhoon *tp = netdev_priv(dev);
 770         struct transmit_ring *txRing;
 771         struct tx_desc *txd, *first_txd;
 772         dma_addr_t skb_dma;
 773         int numDesc;
 774
 775         /* we have two rings to choose from, but we only use txLo for now
 776          * If we start using the Hi ring as well, we'll need to update
 777          * typhoon_stop_runtime(), typhoon_interrupt(), typhoon_num_free_tx(),
 778          * and TXHI_ENTRIES to match, as well as update the TSO code below
 779          * to get the right DMA address
 780          */
 781         txRing = &tp->txLoRing;
 782
 783         /* We need one descriptor for each fragment of the sk_buff, plus the
 784          * one for the ->data area of it.
 785          *
 786          * The docs say a maximum of 16 fragment descriptors per TCP option
 787          * descriptor, then make a new packet descriptor and option descriptor
 788          * for the next 16 fragments. The engineers say just an option
 789          * descriptor is needed. I've tested up to 26 fragments with a single
 790          * packet descriptor/option descriptor combo, so I use that for now.
 791          *
 792          * If problems develop with TSO, check this first.
 793          */
 794         numDesc = skb_shinfo(skb)->nr_frags + 1;
 795         if (skb_is_gso(skb))
 796                 numDesc++;
 797
 798         /* When checking for free space in the ring, we need to also
 799          * account for the initial Tx descriptor, and we always must leave
 800          * at least one descriptor unused in the ring so that it doesn't
 801          * wrap and look empty.
 802          *
 803          * The only time we should loop here is when we hit the race
 804          * between marking the queue awake and updating the cleared index.
 805          * Just loop and it will appear. This comes from the acenic driver.
 806          */
 807         while(unlikely(typhoon_num_free_tx(txRing) < (numDesc + 2)))
 808                 smp_rmb();
 809
 810         first_txd = (struct tx_desc *) (txRing->ringBase + txRing->lastWrite);
 811         typhoon_inc_tx_index(&txRing->lastWrite, 1);
 812
 813         first_txd->flags = TYPHOON_TX_DESC | TYPHOON_DESC_VALID;
 814         first_txd->numDesc = 0;
 815         first_txd->len = 0;
 816         first_txd->addr = (u64)((unsigned long) skb) & 0xffffffff;
 817         first_txd->addrHi = (u64)((unsigned long) skb) >> 32;
 818         first_txd->processFlags = 0;
 819
 820         if(skb->ip_summed == CHECKSUM_PARTIAL) {
 821                 /* The 3XP will figure out if this is UDP/TCP */
 822                 first_txd->processFlags |= TYPHOON_TX_PF_TCP_CHKSUM;
 823                 first_txd->processFlags |= TYPHOON_TX_PF_UDP_CHKSUM;
 824                 first_txd->processFlags |= TYPHOON_TX_PF_IP_CHKSUM;
 825         }
 826
 827         if(vlan_tx_tag_present(skb)) {
 828                 first_txd->processFlags |=
 829                     TYPHOON_TX_PF_INSERT_VLAN | TYPHOON_TX_PF_VLAN_PRIORITY;
 830                 first_txd->processFlags |=
 831                     cpu_to_le32(ntohs(vlan_tx_tag_get(skb)) <<
 832                                 TYPHOON_TX_PF_VLAN_TAG_SHIFT);
 833         }
 834
 835         if (skb_is_gso(skb)) {
 836                 first_txd->processFlags |= TYPHOON_TX_PF_TCP_SEGMENT;
 837                 first_txd->numDesc++;
 838
 839                 typhoon_tso_fill(skb, txRing, tp->txlo_dma_addr);
 840         }
 841
 842         txd = (struct tx_desc *) (txRing->ringBase + txRing->lastWrite);
 843         typhoon_inc_tx_index(&txRing->lastWrite, 1);
 844
 845         /* No need to worry about padding packet -- the firmware pads
 846          * it with zeros to ETH_ZLEN for us.
 847          */
 848         if(skb_shinfo(skb)->nr_frags == 0) {
 849                 skb_dma = pci_map_single(tp->tx_pdev, skb->data, skb->len,
 850                                        PCI_DMA_TODEVICE);
 851                 txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
 852                 txd->len = cpu_to_le16(skb->len);
 853                 txd->addr = cpu_to_le32(skb_dma);
 854                 txd->addrHi = 0;
 855                 first_txd->numDesc++;
 856         } else {
 857                 int i, len;
 858
 859                 len = skb_headlen(skb);
 860                 skb_dma = pci_map_single(tp->tx_pdev, skb->data, len,
 861                                          PCI_DMA_TODEVICE);
 862                 txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
 863                 txd->len = cpu_to_le16(len);
 864                 txd->addr = cpu_to_le32(skb_dma);
 865                 txd->addrHi = 0;
 866                 first_txd->numDesc++;
 867
 868                 for(i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
 869                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
 870                         void *frag_addr;
 871
 872                         txd = (struct tx_desc *) (txRing->ringBase +
 873                                                 txRing->lastWrite);
 874                         typhoon_inc_tx_index(&txRing->lastWrite, 1);
 875
 876                         len = frag->size;
 877                         frag_addr = (void *) page_address(frag->page) +
 878                                                 frag->page_offset;
 879                         skb_dma = pci_map_single(tp->tx_pdev, frag_addr, len,
 880                                          PCI_DMA_TODEVICE);
 881                         txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
 882                         txd->len = cpu_to_le16(len);
 883                         txd->addr = cpu_to_le32(skb_dma);
 884                         txd->addrHi = 0;
 885                         first_txd->numDesc++;
 886                 }
 887         }
 888
 889         /* Kick the 3XP
 890          */
 891         wmb();
 892         iowrite32(txRing->lastWrite, tp->tx_ioaddr + txRing->writeRegister);
 893
 894         dev->trans_start = jiffies;
 895
 896         /* If we don't have room to put the worst case packet on the
 897          * queue, then we must stop the queue. We need 2 extra
 898          * descriptors -- one to prevent ring wrap, and one for the
 899          * Tx header.
 900          */
 901         numDesc = MAX_SKB_FRAGS + TSO_NUM_DESCRIPTORS + 1;
 902
 903         if(typhoon_num_free_tx(txRing) < (numDesc + 2)) {
 904                 netif_stop_queue(dev);
 905
 906                 /* A Tx complete IRQ could have gotten inbetween, making
 907                  * the ring free again. Only need to recheck here, since
 908                  * Tx is serialized.
 909                  */
 910                 if(typhoon_num_free_tx(txRing) >= (numDesc + 2))
 911                         netif_wake_queue(dev);
 912         }
 913
 914         return 0;
 915 }
 916
 917 static void
 918 typhoon_set_rx_mode(struct net_device *dev)
 919 {
 920         struct typhoon *tp = netdev_priv(dev);
 921         struct cmd_desc xp_cmd;
 922         u32 mc_filter[2];
 923         __le16 filter;
 924
 925         filter = TYPHOON_RX_FILTER_DIRECTED | TYPHOON_RX_FILTER_BROADCAST;
 926         if(dev->flags & IFF_PROMISC) {
 927                 filter |= TYPHOON_RX_FILTER_PROMISCOUS;
 928         } else if((dev->mc_count > multicast_filter_limit) ||
 929                   (dev->flags & IFF_ALLMULTI)) {
 930                 /* Too many to match, or accept all multicasts. */
 931                 filter |= TYPHOON_RX_FILTER_ALL_MCAST;
 932         } else if(dev->mc_count) {
 933                 struct dev_mc_list *mclist;
 934                 int i;
 935
 936                 memset(mc_filter, 0, sizeof(mc_filter));
 937                 for(i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
 938                     i++, mclist = mclist->next) {
 939                         int bit = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3f;
 940                         mc_filter[bit >> 5] |= 1 << (bit & 0x1f);
 941                 }
 942
 943                 INIT_COMMAND_NO_RESPONSE(&xp_cmd,
 944                                          TYPHOON_CMD_SET_MULTICAST_HASH);
 945                 xp_cmd.parm1 = TYPHOON_MCAST_HASH_SET;
 946                 xp_cmd.parm2 = cpu_to_le32(mc_filter[0]);
 947                 xp_cmd.parm3 = cpu_to_le32(mc_filter[1]);
 948                 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
 949
 950                 filter |= TYPHOON_RX_FILTER_MCAST_HASH;
 951         }
 952
 953         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_RX_FILTER);
 954         xp_cmd.parm1 = filter;
 955         typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
 956 }
 957
 958 static int
 959 typhoon_do_get_stats(struct typhoon *tp)
 960 {
 961         struct net_device_stats *stats = &tp->stats;
 962         struct net_device_stats *saved = &tp->stats_saved;
 963         struct cmd_desc xp_cmd;
 964         struct resp_desc xp_resp[7];
 965         struct stats_resp *s = (struct stats_resp *) xp_resp;
 966         int err;
 967
 968         INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_STATS);
 969         err = typhoon_issue_command(tp, 1, &xp_cmd, 7, xp_resp);
 970         if(err < 0)
 971                 return err;
 972
 973         /* 3Com's Linux driver uses txMultipleCollisions as it's
 974          * collisions value, but there is some other collision info as well...
 975          *
 976          * The extra status reported would be a good candidate for
 977          * ethtool_ops->get_{strings,stats}()
 978          */
 979         stats->tx_packets = le32_to_cpu(s->txPackets);
 980         stats->tx_bytes = le32_to_cpu(s->txBytes);
 981         stats->tx_errors = le32_to_cpu(s->txCarrierLost);
 982         stats->tx_carrier_errors = le32_to_cpu(s->txCarrierLost);
 983         stats->collisions = le32_to_cpu(s->txMultipleCollisions);
 984         stats->rx_packets = le32_to_cpu(s->rxPacketsGood);
 985         stats->rx_bytes = le32_to_cpu(s->rxBytesGood);
 986         stats->rx_fifo_errors = le32_to_cpu(s->rxFifoOverruns);
 987         stats->rx_errors = le32_to_cpu(s->rxFifoOverruns) +
 988                         le32_to_cpu(s->BadSSD) + le32_to_cpu(s->rxCrcErrors);
 989         stats->rx_crc_errors = le32_to_cpu(s->rxCrcErrors);
 990         stats->rx_length_errors = le32_to_cpu(s->rxOversized);
 991         tp->speed = (s->linkStatus & TYPHOON_LINK_100MBPS) ?
 992                         SPEED_100 : SPEED_10;
 993         tp->duplex = (s->linkStatus & TYPHOON_LINK_FULL_DUPLEX) ?
 994                         DUPLEX_FULL : DUPLEX_HALF;
 995
 996         /* add in the saved statistics
 997          */
 998         stats->tx_packets += saved->tx_packets;
 999         stats->tx_bytes += saved->tx_bytes;
1000         stats->tx_errors += saved->tx_errors;
1001         stats->collisions += saved->collisions;
1002         stats->rx_packets += saved->rx_packets;
1003         stats->rx_bytes += saved->rx_bytes;
1004         stats->rx_fifo_errors += saved->rx_fifo_errors;
1005         stats->rx_errors += saved->rx_errors;
1006         stats->rx_crc_errors += saved->rx_crc_errors;
1007         stats->rx_length_errors += saved->rx_length_errors;
1008
1009         return 0;
1010 }
1011
1012 static struct net_device_stats *
1013 typhoon_get_stats(struct net_device *dev)
1014 {
1015         struct typhoon *tp = netdev_priv(dev);
1016         struct net_device_stats *stats = &tp->stats;
1017         struct net_device_stats *saved = &tp->stats_saved;
1018
1019         smp_rmb();
1020         if(tp->card_state == Sleeping)
1021                 return saved;
1022
1023         if(typhoon_do_get_stats(tp) < 0) {
1024                 printk(KERN_ERR "%s: error getting stats\n", dev->name);
1025                 return saved;
1026         }
1027
1028         return stats;
1029 }
1030
1031 static int
1032 typhoon_set_mac_address(struct net_device *dev, void *addr)
1033 {
1034         struct sockaddr *saddr = (struct sockaddr *) addr;
1035
1036         if(netif_running(dev))
1037                 return -EBUSY;
1038
1039         memcpy(dev->dev_addr, saddr->sa_data, dev->addr_len);
1040         return 0;
1041 }
1042
1043 static void
1044 typhoon_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1045 {
1046         struct typhoon *tp = netdev_priv(dev);
1047         struct pci_dev *pci_dev = tp->pdev;
1048         struct cmd_desc xp_cmd;
1049         struct resp_desc xp_resp[3];
1050
1051         smp_rmb();
1052         if(tp->card_state == Sleeping) {
1053                 strcpy(info->fw_version, "Sleep image");
1054         } else {
1055                 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_VERSIONS);
1056                 if(typhoon_issue_command(tp, 1, &xp_cmd, 3, xp_resp) < 0) {
1057                         strcpy(info->fw_version, "Unknown runtime");
1058                 } else {
1059                         u32 sleep_ver = xp_resp[0].parm2;
1060                         snprintf(info->fw_version, 32, "%02x.%03x.%03x",
1061                                  sleep_ver >> 24, (sleep_ver >> 12) & 0xfff,
1062                                  sleep_ver & 0xfff);
1063                 }
1064         }
1065
1066         strcpy(info->driver, DRV_MODULE_NAME);
1067         strcpy(info->version, DRV_MODULE_VERSION);
1068         strcpy(info->bus_info, pci_name(pci_dev));
1069 }
1070
1071 static int
1072 typhoon_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1073 {
1074         struct typhoon *tp = netdev_priv(dev);
1075
1076         cmd->supported = SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
1077                                 SUPPORTED_Autoneg;
1078
1079         switch (tp->xcvr_select) {
1080         case TYPHOON_XCVR_10HALF:
1081                 cmd->advertising = ADVERTISED_10baseT_Half;
1082                 break;
1083         case TYPHOON_XCVR_10FULL:
1084                 cmd->advertising = ADVERTISED_10baseT_Full;
1085                 break;
1086         case TYPHOON_XCVR_100HALF:
1087                 cmd->advertising = ADVERTISED_100baseT_Half;
1088                 break;
1089         case TYPHOON_XCVR_100FULL:
1090                 cmd->advertising = ADVERTISED_100baseT_Full;
1091                 break;
1092         case TYPHOON_XCVR_AUTONEG:
1093                 cmd->advertising = ADVERTISED_10baseT_Half |
1094                                             ADVERTISED_10baseT_Full |
1095                                             ADVERTISED_100baseT_Half |
1096                                             ADVERTISED_100baseT_Full |
1097                                             ADVERTISED_Autoneg;
1098                 break;
1099         }
1100
1101         if(tp->capabilities & TYPHOON_FIBER) {
1102                 cmd->supported |= SUPPORTED_FIBRE;
1103                 cmd->advertising |= ADVERTISED_FIBRE;
1104                 cmd->port = PORT_FIBRE;
1105         } else {
1106                 cmd->supported |= SUPPORTED_10baseT_Half |
1107                                         SUPPORTED_10baseT_Full |
1108                                         SUPPORTED_TP;
1109                 cmd->advertising |= ADVERTISED_TP;
1110                 cmd->port = PORT_TP;
1111         }
1112
1113         /* need to get stats to make these link speed/duplex valid */
1114         typhoon_do_get_stats(tp);
1115         cmd->speed = tp->speed;
1116         cmd->duplex = tp->duplex;
1117         cmd->phy_address = 0;
1118         cmd->transceiver = XCVR_INTERNAL;
1119         if(tp->xcvr_select == TYPHOON_XCVR_AUTONEG)
1120                 cmd->autoneg = AUTONEG_ENABLE;
1121         else
1122                 cmd->autoneg = AUTONEG_DISABLE;
1123         cmd->maxtxpkt = 1;
1124         cmd->maxrxpkt = 1;
1125
1126         return 0;
1127 }
1128
1129 static int
1130 typhoon_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1131 {
1132         struct typhoon *tp = netdev_priv(dev);
1133         struct cmd_desc xp_cmd;
1134         __le16 xcvr;
1135         int err;
1136
1137         err = -EINVAL;
1138         if(cmd->autoneg == AUTONEG_ENABLE) {
1139                 xcvr = TYPHOON_XCVR_AUTONEG;
1140         } else {
1141                 if(cmd->duplex == DUPLEX_HALF) {
1142                         if(cmd->speed == SPEED_10)
1143                                 xcvr = TYPHOON_XCVR_10HALF;
1144                         else if(cmd->speed == SPEED_100)
1145                                 xcvr = TYPHOON_XCVR_100HALF;
1146                         else
1147                                 goto out;
1148                 } else if(cmd->duplex == DUPLEX_FULL) {
1149                         if(cmd->speed == SPEED_10)
1150                                 xcvr = TYPHOON_XCVR_10FULL;
1151                         else if(cmd->speed == SPEED_100)
1152                                 xcvr = TYPHOON_XCVR_100FULL;
1153                         else
1154                                 goto out;
1155                 } else
1156                         goto out;
1157         }
1158
1159         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_XCVR_SELECT);
1160         xp_cmd.parm1 = cpu_to_le16(xcvr);
1161         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1162         if(err < 0)
1163                 goto out;
1164
1165         tp->xcvr_select = xcvr;
1166         if(cmd->autoneg == AUTONEG_ENABLE) {
1167                 tp->speed = 0xff;       /* invalid */
1168                 tp->duplex = 0xff;      /* invalid */
1169         } else {
1170                 tp->speed = cmd->speed;
1171                 tp->duplex = cmd->duplex;
1172         }
1173
1174 out:
1175         return err;
1176 }
1177
1178 static void
1179 typhoon_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1180 {
1181         struct typhoon *tp = netdev_priv(dev);
1182
1183         wol->supported = WAKE_PHY | WAKE_MAGIC;
1184         wol->wolopts = 0;
1185         if(tp->wol_events & TYPHOON_WAKE_LINK_EVENT)
1186                 wol->wolopts |= WAKE_PHY;
1187         if(tp->wol_events & TYPHOON_WAKE_MAGIC_PKT)
1188                 wol->wolopts |= WAKE_MAGIC;
1189         memset(&wol->sopass, 0, sizeof(wol->sopass));
1190 }
1191
1192 static int
1193 typhoon_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1194 {
1195         struct typhoon *tp = netdev_priv(dev);
1196
1197         if(wol->wolopts & ~(WAKE_PHY | WAKE_MAGIC))
1198                 return -EINVAL;
1199
1200         tp->wol_events = 0;
1201         if(wol->wolopts & WAKE_PHY)
1202                 tp->wol_events |= TYPHOON_WAKE_LINK_EVENT;
1203         if(wol->wolopts & WAKE_MAGIC)
1204                 tp->wol_events |= TYPHOON_WAKE_MAGIC_PKT;
1205
1206         return 0;
1207 }
1208
1209 static u32
1210 typhoon_get_rx_csum(struct net_device *dev)
1211 {
1212         /* For now, we don't allow turning off RX checksums.
1213          */
1214         return 1;
1215 }
1216
1217 static void
1218 typhoon_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
1219 {
1220         ering->rx_max_pending = RXENT_ENTRIES;
1221         ering->rx_mini_max_pending = 0;
1222         ering->rx_jumbo_max_pending = 0;
1223         ering->tx_max_pending = TXLO_ENTRIES - 1;
1224
1225         ering->rx_pending = RXENT_ENTRIES;
1226         ering->rx_mini_pending = 0;
1227         ering->rx_jumbo_pending = 0;
1228         ering->tx_pending = TXLO_ENTRIES - 1;
1229 }
1230
1231 static const struct ethtool_ops typhoon_ethtool_ops = {
1232         .get_settings           = typhoon_get_settings,
1233         .set_settings           = typhoon_set_settings,
1234         .get_drvinfo            = typhoon_get_drvinfo,
1235         .get_wol                = typhoon_get_wol,
1236         .set_wol                = typhoon_set_wol,
1237         .get_link               = ethtool_op_get_link,
1238         .get_rx_csum            = typhoon_get_rx_csum,
1239         .set_tx_csum            = ethtool_op_set_tx_csum,
1240         .set_sg                 = ethtool_op_set_sg,
1241         .set_tso                = ethtool_op_set_tso,
1242         .get_ringparam          = typhoon_get_ringparam,
1243 };
1244
1245 static int
1246 typhoon_wait_interrupt(void __iomem *ioaddr)
1247 {
1248         int i, err = 0;
1249
1250         for(i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
1251                 if(ioread32(ioaddr + TYPHOON_REG_INTR_STATUS) &
1252                    TYPHOON_INTR_BOOTCMD)
1253                         goto out;
1254                 udelay(TYPHOON_UDELAY);
1255         }
1256
1257         err = -ETIMEDOUT;
1258
1259 out:
1260         iowrite32(TYPHOON_INTR_BOOTCMD, ioaddr + TYPHOON_REG_INTR_STATUS);
1261         return err;
1262 }
1263
1264 #define shared_offset(x)        offsetof(struct typhoon_shared, x)
1265
1266 static void
1267 typhoon_init_interface(struct typhoon *tp)
1268 {
1269         struct typhoon_interface *iface = &tp->shared->iface;
1270         dma_addr_t shared_dma;
1271
1272         memset(tp->shared, 0, sizeof(struct typhoon_shared));
1273
1274         /* The *Hi members of iface are all init'd to zero by the memset().
1275          */
1276         shared_dma = tp->shared_dma + shared_offset(indexes);
1277         iface->ringIndex = cpu_to_le32(shared_dma);
1278
1279         shared_dma = tp->shared_dma + shared_offset(txLo);
1280         iface->txLoAddr = cpu_to_le32(shared_dma);
1281         iface->txLoSize = cpu_to_le32(TXLO_ENTRIES * sizeof(struct tx_desc));
1282
1283         shared_dma = tp->shared_dma + shared_offset(txHi);
1284         iface->txHiAddr = cpu_to_le32(shared_dma);
1285         iface->txHiSize = cpu_to_le32(TXHI_ENTRIES * sizeof(struct tx_desc));
1286
1287         shared_dma = tp->shared_dma + shared_offset(rxBuff);
1288         iface->rxBuffAddr = cpu_to_le32(shared_dma);
1289         iface->rxBuffSize = cpu_to_le32(RXFREE_ENTRIES *
1290                                         sizeof(struct rx_free));
1291
1292         shared_dma = tp->shared_dma + shared_offset(rxLo);
1293         iface->rxLoAddr = cpu_to_le32(shared_dma);
1294         iface->rxLoSize = cpu_to_le32(RX_ENTRIES * sizeof(struct rx_desc));
1295
1296         shared_dma = tp->shared_dma + shared_offset(rxHi);
1297         iface->rxHiAddr = cpu_to_le32(shared_dma);
1298         iface->rxHiSize = cpu_to_le32(RX_ENTRIES * sizeof(struct rx_desc));
1299
1300         shared_dma = tp->shared_dma + shared_offset(cmd);
1301         iface->cmdAddr = cpu_to_le32(shared_dma);
1302         iface->cmdSize = cpu_to_le32(COMMAND_RING_SIZE);
1303
1304         shared_dma = tp->shared_dma + shared_offset(resp);
1305         iface->respAddr = cpu_to_le32(shared_dma);
1306         iface->respSize = cpu_to_le32(RESPONSE_RING_SIZE);
1307
1308         shared_dma = tp->shared_dma + shared_offset(zeroWord);
1309         iface->zeroAddr = cpu_to_le32(shared_dma);
1310
1311         tp->indexes = &tp->shared->indexes;
1312         tp->txLoRing.ringBase = (u8 *) tp->shared->txLo;
1313         tp->txHiRing.ringBase = (u8 *) tp->shared->txHi;
1314         tp->rxLoRing.ringBase = (u8 *) tp->shared->rxLo;
1315         tp->rxHiRing.ringBase = (u8 *) tp->shared->rxHi;
1316         tp->rxBuffRing.ringBase = (u8 *) tp->shared->rxBuff;
1317         tp->cmdRing.ringBase = (u8 *) tp->shared->cmd;
1318         tp->respRing.ringBase = (u8 *) tp->shared->resp;
1319
1320         tp->txLoRing.writeRegister = TYPHOON_REG_TX_LO_READY;
1321         tp->txHiRing.writeRegister = TYPHOON_REG_TX_HI_READY;
1322
1323         tp->txlo_dma_addr = iface->txLoAddr;
1324         tp->card_state = Sleeping;
1325         smp_wmb();
1326
1327         tp->offload = TYPHOON_OFFLOAD_IP_CHKSUM | TYPHOON_OFFLOAD_TCP_CHKSUM;
1328         tp->offload |= TYPHOON_OFFLOAD_UDP_CHKSUM | TSO_OFFLOAD_ON;
1329
1330         spin_lock_init(&tp->command_lock);
1331         spin_lock_init(&tp->state_lock);
1332 }
1333
1334 static void
1335 typhoon_init_rings(struct typhoon *tp)
1336 {
1337         memset(tp->indexes, 0, sizeof(struct typhoon_indexes));
1338
1339         tp->txLoRing.lastWrite = 0;
1340         tp->txHiRing.lastWrite = 0;
1341         tp->rxLoRing.lastWrite = 0;
1342         tp->rxHiRing.lastWrite = 0;
1343         tp->rxBuffRing.lastWrite = 0;
1344         tp->cmdRing.lastWrite = 0;
1345         tp->cmdRing.lastWrite = 0;
1346
1347         tp->txLoRing.lastRead = 0;
1348         tp->txHiRing.lastRead = 0;
1349 }
1350
1351 static int
1352 typhoon_download_firmware(struct typhoon *tp)
1353 {
1354         void __iomem *ioaddr = tp->ioaddr;
1355         struct pci_dev *pdev = tp->pdev;
1356         struct typhoon_file_header *fHdr;
1357         struct typhoon_section_header *sHdr;
1358         u8 *image_data;
1359         void *dpage;
1360         dma_addr_t dpage_dma;
1361         unsigned int csum;
1362         u32 irqEnabled;
1363         u32 irqMasked;
1364         u32 numSections;
1365         u32 section_len;
1366         u32 len;
1367         u32 load_addr;
1368         u32 hmac;
1369         int i;
1370         int err;
1371
1372         err = -EINVAL;
1373         fHdr = (struct typhoon_file_header *) typhoon_firmware_image;
1374         image_data = (u8 *) fHdr;
1375
1376         if(memcmp(fHdr->tag, "TYPHOON", 8)) {
1377                 printk(KERN_ERR "%s: Invalid firmware image!\n", tp->name);
1378                 goto err_out;
1379         }
1380
1381         /* Cannot just map the firmware image using pci_map_single() as
1382          * the firmware is part of the kernel/module image, so we allocate
1383          * some consistent memory to copy the sections into, as it is simpler,
1384          * and short-lived. If we ever split out and require a userland
1385          * firmware loader, then we can revisit this.
1386          */
1387         err = -ENOMEM;
1388         dpage = pci_alloc_consistent(pdev, PAGE_SIZE, &dpage_dma);
1389         if(!dpage) {
1390                 printk(KERN_ERR "%s: no DMA mem for firmware\n", tp->name);
1391                 goto err_out;
1392         }
1393
1394         irqEnabled = ioread32(ioaddr + TYPHOON_REG_INTR_ENABLE);
1395         iowrite32(irqEnabled | TYPHOON_INTR_BOOTCMD,
1396                ioaddr + TYPHOON_REG_INTR_ENABLE);
1397         irqMasked = ioread32(ioaddr + TYPHOON_REG_INTR_MASK);
1398         iowrite32(irqMasked | TYPHOON_INTR_BOOTCMD,
1399                ioaddr + TYPHOON_REG_INTR_MASK);
1400
1401         err = -ETIMEDOUT;
1402         if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
1403                 printk(KERN_ERR "%s: card ready timeout\n", tp->name);
1404                 goto err_out_irq;
1405         }
1406
1407         numSections = le32_to_cpu(fHdr->numSections);
1408         load_addr = le32_to_cpu(fHdr->startAddr);
1409
1410         iowrite32(TYPHOON_INTR_BOOTCMD, ioaddr + TYPHOON_REG_INTR_STATUS);
1411         iowrite32(load_addr, ioaddr + TYPHOON_REG_DOWNLOAD_BOOT_ADDR);
1412         hmac = le32_to_cpu(fHdr->hmacDigest[0]);
1413         iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_0);
1414         hmac = le32_to_cpu(fHdr->hmacDigest[1]);
1415         iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_1);
1416         hmac = le32_to_cpu(fHdr->hmacDigest[2]);
1417         iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_2);
1418         hmac = le32_to_cpu(fHdr->hmacDigest[3]);
1419         iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_3);
1420         hmac = le32_to_cpu(fHdr->hmacDigest[4]);
1421         iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_4);
1422         typhoon_post_pci_writes(ioaddr);
1423         iowrite32(TYPHOON_BOOTCMD_RUNTIME_IMAGE, ioaddr + TYPHOON_REG_COMMAND);
1424
1425         image_data += sizeof(struct typhoon_file_header);
1426
1427         /* The ioread32() in typhoon_wait_interrupt() will force the
1428          * last write to the command register to post, so
1429          * we don't need a typhoon_post_pci_writes() after it.
1430          */
1431         for(i = 0; i < numSections; i++) {
1432                 sHdr = (struct typhoon_section_header *) image_data;
1433                 image_data += sizeof(struct typhoon_section_header);
1434                 load_addr = le32_to_cpu(sHdr->startAddr);
1435                 section_len = le32_to_cpu(sHdr->len);
1436
1437                 while(section_len) {
1438                         len = min_t(u32, section_len, PAGE_SIZE);
1439
1440                         if(typhoon_wait_interrupt(ioaddr) < 0 ||
1441                            ioread32(ioaddr + TYPHOON_REG_STATUS) !=
1442                            TYPHOON_STATUS_WAITING_FOR_SEGMENT) {
1443                                 printk(KERN_ERR "%s: segment ready timeout\n",
1444                                        tp->name);
1445                                 goto err_out_irq;
1446                         }
1447
1448                         /* Do an pseudo IPv4 checksum on the data -- first
1449                          * need to convert each u16 to cpu order before
1450                          * summing. Fortunately, due to the properties of
1451                          * the checksum, we can do this once, at the end.
1452                          */
1453                         csum = csum_partial_copy_nocheck(image_data, dpage,
1454                                                          len, 0);
1455                         csum = csum_fold(csum);
1456                         csum = le16_to_cpu(csum);
1457
1458                         iowrite32(len, ioaddr + TYPHOON_REG_BOOT_LENGTH);
1459                         iowrite32(csum, ioaddr + TYPHOON_REG_BOOT_CHECKSUM);
1460                         iowrite32(load_addr,
1461                                         ioaddr + TYPHOON_REG_BOOT_DEST_ADDR);
1462                         iowrite32(0, ioaddr + TYPHOON_REG_BOOT_DATA_HI);
1463                         iowrite32(dpage_dma, ioaddr + TYPHOON_REG_BOOT_DATA_LO);
1464                         typhoon_post_pci_writes(ioaddr);
1465                         iowrite32(TYPHOON_BOOTCMD_SEG_AVAILABLE,
1466                                ioaddr + TYPHOON_REG_COMMAND);
1467
1468                         image_data += len;
1469                         load_addr += len;
1470                         section_len -= len;
1471                 }
1472         }
1473
1474         if(typhoon_wait_interrupt(ioaddr) < 0 ||
1475            ioread32(ioaddr + TYPHOON_REG_STATUS) !=
1476            TYPHOON_STATUS_WAITING_FOR_SEGMENT) {
1477                 printk(KERN_ERR "%s: final segment ready timeout\n", tp->name);
1478                 goto err_out_irq;
1479         }
1480
1481         iowrite32(TYPHOON_BOOTCMD_DNLD_COMPLETE, ioaddr + TYPHOON_REG_COMMAND);
1482
1483         if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_BOOT) < 0) {
1484                 printk(KERN_ERR "%s: boot ready timeout, status 0x%0x\n",
1485                        tp->name, ioread32(ioaddr + TYPHOON_REG_STATUS));
1486                 goto err_out_irq;
1487         }
1488
1489         err = 0;
1490
1491 err_out_irq:
1492         iowrite32(irqMasked, ioaddr + TYPHOON_REG_INTR_MASK);
1493         iowrite32(irqEnabled, ioaddr + TYPHOON_REG_INTR_ENABLE);
1494
1495         pci_free_consistent(pdev, PAGE_SIZE, dpage, dpage_dma);
1496
1497 err_out:
1498         return err;
1499 }
1500
1501 static int
1502 typhoon_boot_3XP(struct typhoon *tp, u32 initial_status)
1503 {
1504         void __iomem *ioaddr = tp->ioaddr;
1505
1506         if(typhoon_wait_status(ioaddr, initial_status) < 0) {
1507                 printk(KERN_ERR "%s: boot ready timeout\n", tp->name);
1508                 goto out_timeout;
1509         }
1510
1511         iowrite32(0, ioaddr + TYPHOON_REG_BOOT_RECORD_ADDR_HI);
1512         iowrite32(tp->shared_dma, ioaddr + TYPHOON_REG_BOOT_RECORD_ADDR_LO);
1513         typhoon_post_pci_writes(ioaddr);
1514         iowrite32(TYPHOON_BOOTCMD_REG_BOOT_RECORD,
1515                                 ioaddr + TYPHOON_REG_COMMAND);
1516
1517         if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_RUNNING) < 0) {
1518                 printk(KERN_ERR "%s: boot finish timeout (status 0x%x)\n",
1519                        tp->name, ioread32(ioaddr + TYPHOON_REG_STATUS));
1520                 goto out_timeout;
1521         }
1522
1523         /* Clear the Transmit and Command ready registers
1524          */
1525         iowrite32(0, ioaddr + TYPHOON_REG_TX_HI_READY);
1526         iowrite32(0, ioaddr + TYPHOON_REG_CMD_READY);
1527         iowrite32(0, ioaddr + TYPHOON_REG_TX_LO_READY);
1528         typhoon_post_pci_writes(ioaddr);
1529         iowrite32(TYPHOON_BOOTCMD_BOOT, ioaddr + TYPHOON_REG_COMMAND);
1530
1531         return 0;
1532
1533 out_timeout:
1534         return -ETIMEDOUT;
1535 }
1536
1537 static u32
1538 typhoon_clean_tx(struct typhoon *tp, struct transmit_ring *txRing,
1539                         volatile __le32 * index)
1540 {
1541         u32 lastRead = txRing->lastRead;
1542         struct tx_desc *tx;
1543         dma_addr_t skb_dma;
1544         int dma_len;
1545         int type;
1546
1547         while(lastRead != le32_to_cpu(*index)) {
1548                 tx = (struct tx_desc *) (txRing->ringBase + lastRead);
1549                 type = tx->flags & TYPHOON_TYPE_MASK;
1550
1551                 if(type == TYPHOON_TX_DESC) {
1552                         /* This tx_desc describes a packet.
1553                          */
1554                         unsigned long ptr = tx->addr | ((u64)tx->addrHi << 32);
1555                         struct sk_buff *skb = (struct sk_buff *) ptr;
1556                         dev_kfree_skb_irq(skb);
1557                 } else if(type == TYPHOON_FRAG_DESC) {
1558                         /* This tx_desc describes a memory mapping. Free it.
1559                          */
1560                         skb_dma = (dma_addr_t) le32_to_cpu(tx->addr);
1561                         dma_len = le16_to_cpu(tx->len);
1562                         pci_unmap_single(tp->pdev, skb_dma, dma_len,
1563                                        PCI_DMA_TODEVICE);
1564                 }
1565
1566                 tx->flags = 0;
1567                 typhoon_inc_tx_index(&lastRead, 1);
1568         }
1569
1570         return lastRead;
1571 }
1572
1573 static void
1574 typhoon_tx_complete(struct typhoon *tp, struct transmit_ring *txRing,
1575                         volatile __le32 * index)
1576 {
1577         u32 lastRead;
1578         int numDesc = MAX_SKB_FRAGS + 1;
1579
1580         /* This will need changing if we start to use the Hi Tx ring. */
1581         lastRead = typhoon_clean_tx(tp, txRing, index);
1582         if(netif_queue_stopped(tp->dev) && typhoon_num_free(txRing->lastWrite,
1583                                 lastRead, TXLO_ENTRIES) > (numDesc + 2))
1584                 netif_wake_queue(tp->dev);
1585
1586         txRing->lastRead = lastRead;
1587         smp_wmb();
1588 }
1589
1590 static void
1591 typhoon_recycle_rx_skb(struct typhoon *tp, u32 idx)
1592 {
1593         struct typhoon_indexes *indexes = tp->indexes;
1594         struct rxbuff_ent *rxb = &tp->rxbuffers[idx];
1595         struct basic_ring *ring = &tp->rxBuffRing;
1596         struct rx_free *r;
1597
1598         if((ring->lastWrite + sizeof(*r)) % (RXFREE_ENTRIES * sizeof(*r)) ==
1599                                 indexes->rxBuffCleared) {
1600                 /* no room in ring, just drop the skb
1601                  */
1602                 dev_kfree_skb_any(rxb->skb);
1603                 rxb->skb = NULL;
1604                 return;
1605         }
1606
1607         r = (struct rx_free *) (ring->ringBase + ring->lastWrite);
1608         typhoon_inc_rxfree_index(&ring->lastWrite, 1);
1609         r->virtAddr = idx;
1610         r->physAddr = cpu_to_le32(rxb->dma_addr);
1611
1612         /* Tell the card about it */
1613         wmb();
1614         indexes->rxBuffReady = cpu_to_le32(ring->lastWrite);
1615 }
1616
1617 static int
1618 typhoon_alloc_rx_skb(struct typhoon *tp, u32 idx)
1619 {
1620         struct typhoon_indexes *indexes = tp->indexes;
1621         struct rxbuff_ent *rxb = &tp->rxbuffers[idx];
1622         struct basic_ring *ring = &tp->rxBuffRing;
1623         struct rx_free *r;
1624         struct sk_buff *skb;
1625         dma_addr_t dma_addr;
1626
1627         rxb->skb = NULL;
1628
1629         if((ring->lastWrite + sizeof(*r)) % (RXFREE_ENTRIES * sizeof(*r)) ==
1630                                 indexes->rxBuffCleared)
1631                 return -ENOMEM;
1632
1633         skb = dev_alloc_skb(PKT_BUF_SZ);
1634         if(!skb)
1635                 return -ENOMEM;
1636
1637 #if 0
1638         /* Please, 3com, fix the firmware to allow DMA to a unaligned
1639          * address! Pretty please?
1640          */
1641         skb_reserve(skb, 2);
1642 #endif
1643
1644         skb->dev = tp->dev;
1645         dma_addr = pci_map_single(tp->pdev, skb->data,
1646                                   PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
1647
1648         /* Since no card does 64 bit DAC, the high bits will never
1649          * change from zero.
1650          */
1651         r = (struct rx_free *) (ring->ringBase + ring->lastWrite);
1652         typhoon_inc_rxfree_index(&ring->lastWrite, 1);
1653         r->virtAddr = idx;
1654         r->physAddr = cpu_to_le32(dma_addr);
1655         rxb->skb = skb;
1656         rxb->dma_addr = dma_addr;
1657
1658         /* Tell the card about it */
1659         wmb();
1660         indexes->rxBuffReady = cpu_to_le32(ring->lastWrite);
1661         return 0;
1662 }
1663
1664 static int
1665 typhoon_rx(struct typhoon *tp, struct basic_ring *rxRing, volatile __le32 * ready,
1666            volatile __le32 * cleared, int budget)
1667 {
1668         struct rx_desc *rx;
1669         struct sk_buff *skb, *new_skb;
1670         struct rxbuff_ent *rxb;
1671         dma_addr_t dma_addr;
1672         u32 local_ready;
1673         u32 rxaddr;
1674         int pkt_len;
1675         u32 idx;
1676         __le32 csum_bits;
1677         int received;
1678
1679         received = 0;
1680         local_ready = le32_to_cpu(*ready);
1681         rxaddr = le32_to_cpu(*cleared);
1682         while(rxaddr != local_ready && budget > 0) {
1683                 rx = (struct rx_desc *) (rxRing->ringBase + rxaddr);
1684                 idx = rx->addr;
1685                 rxb = &tp->rxbuffers[idx];
1686                 skb = rxb->skb;
1687                 dma_addr = rxb->dma_addr;
1688
1689                 typhoon_inc_rx_index(&rxaddr, 1);
1690
1691                 if(rx->flags & TYPHOON_RX_ERROR) {
1692                         typhoon_recycle_rx_skb(tp, idx);
1693                         continue;
1694                 }
1695
1696                 pkt_len = le16_to_cpu(rx->frameLen);
1697
1698                 if(pkt_len < rx_copybreak &&
1699                    (new_skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1700                         skb_reserve(new_skb, 2);
1701                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr,
1702                                                     PKT_BUF_SZ,
1703                                                     PCI_DMA_FROMDEVICE);
1704                         skb_copy_to_linear_data(new_skb, skb->data, pkt_len);
1705                         pci_dma_sync_single_for_device(tp->pdev, dma_addr,
1706                                                        PKT_BUF_SZ,
1707                                                        PCI_DMA_FROMDEVICE);
1708                         skb_put(new_skb, pkt_len);
1709                         typhoon_recycle_rx_skb(tp, idx);
1710                 } else {
1711                         new_skb = skb;
1712                         skb_put(new_skb, pkt_len);
1713                         pci_unmap_single(tp->pdev, dma_addr, PKT_BUF_SZ,
1714                                        PCI_DMA_FROMDEVICE);
1715                         typhoon_alloc_rx_skb(tp, idx);
1716                 }
1717                 new_skb->protocol = eth_type_trans(new_skb, tp->dev);
1718                 csum_bits = rx->rxStatus & (TYPHOON_RX_IP_CHK_GOOD |
1719                         TYPHOON_RX_UDP_CHK_GOOD | TYPHOON_RX_TCP_CHK_GOOD);
1720                 if(csum_bits ==
1721                    (TYPHOON_RX_IP_CHK_GOOD | TYPHOON_RX_TCP_CHK_GOOD)
1722                    || csum_bits ==
1723                    (TYPHOON_RX_IP_CHK_GOOD | TYPHOON_RX_UDP_CHK_GOOD)) {
1724                         new_skb->ip_summed = CHECKSUM_UNNECESSARY;
1725                 } else
1726                         new_skb->ip_summed = CHECKSUM_NONE;
1727
1728                 spin_lock(&tp->state_lock);
1729                 if(tp->vlgrp != NULL && rx->rxStatus & TYPHOON_RX_VLAN)
1730                         vlan_hwaccel_receive_skb(new_skb, tp->vlgrp,
1731                                                  ntohl(rx->vlanTag) & 0xffff);
1732                 else
1733                         netif_receive_skb(new_skb);
1734                 spin_unlock(&tp->state_lock);
1735
1736                 tp->dev->last_rx = jiffies;
1737                 received++;
1738                 budget--;
1739         }
1740         *cleared = cpu_to_le32(rxaddr);
1741
1742         return received;
1743 }
1744
1745 static void
1746 typhoon_fill_free_ring(struct typhoon *tp)
1747 {
1748         u32 i;
1749
1750         for(i = 0; i < RXENT_ENTRIES; i++) {
1751                 struct rxbuff_ent *rxb = &tp->rxbuffers[i];
1752                 if(rxb->skb)
1753                         continue;
1754                 if(typhoon_alloc_rx_skb(tp, i) < 0)
1755                         break;
1756         }
1757 }
1758
1759 static int
1760 typhoon_poll(struct napi_struct *napi, int budget)
1761 {
1762         struct typhoon *tp = container_of(napi, struct typhoon, napi);
1763         struct net_device *dev = tp->dev;
1764         struct typhoon_indexes *indexes = tp->indexes;
1765         int work_done;
1766
1767         rmb();
1768         if(!tp->awaiting_resp && indexes->respReady != indexes->respCleared)
1769                         typhoon_process_response(tp, 0, NULL);
1770
1771         if(le32_to_cpu(indexes->txLoCleared) != tp->txLoRing.lastRead)
1772                 typhoon_tx_complete(tp, &tp->txLoRing, &indexes->txLoCleared);
1773
1774         work_done = 0;
1775
1776         if(indexes->rxHiCleared != indexes->rxHiReady) {
1777                 work_done += typhoon_rx(tp, &tp->rxHiRing, &indexes->rxHiReady,
1778                                         &indexes->rxHiCleared, budget);
1779         }
1780
1781         if(indexes->rxLoCleared != indexes->rxLoReady) {
1782                 work_done += typhoon_rx(tp, &tp->rxLoRing, &indexes->rxLoReady,
1783                                         &indexes->rxLoCleared, budget - work_done);
1784         }
1785
1786         if(le32_to_cpu(indexes->rxBuffCleared) == tp->rxBuffRing.lastWrite) {
1787                 /* rxBuff ring is empty, try to fill it. */
1788                 typhoon_fill_free_ring(tp);
1789         }
1790
1791         if (work_done < budget) {
1792                 netif_rx_complete(dev, napi);
1793                 iowrite32(TYPHOON_INTR_NONE,
1794                                 tp->ioaddr + TYPHOON_REG_INTR_MASK);
1795                 typhoon_post_pci_writes(tp->ioaddr);
1796         }
1797
1798         return work_done;
1799 }
1800
1801 static irqreturn_t
1802 typhoon_interrupt(int irq, void *dev_instance)
1803 {
1804         struct net_device *dev = dev_instance;
1805         struct typhoon *tp = dev->priv;
1806         void __iomem *ioaddr = tp->ioaddr;
1807         u32 intr_status;
1808
1809         intr_status = ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
1810         if(!(intr_status & TYPHOON_INTR_HOST_INT))
1811                 return IRQ_NONE;
1812
1813         iowrite32(intr_status, ioaddr + TYPHOON_REG_INTR_STATUS);
1814
1815         if (netif_rx_schedule_prep(dev, &tp->napi)) {
1816                 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
1817                 typhoon_post_pci_writes(ioaddr);
1818                 __netif_rx_schedule(dev, &tp->napi);
1819         } else {
1820                 printk(KERN_ERR "%s: Error, poll already scheduled\n",
1821                        dev->name);
1822         }
1823         return IRQ_HANDLED;
1824 }
1825
1826 static void
1827 typhoon_free_rx_rings(struct typhoon *tp)
1828 {
1829         u32 i;
1830
1831         for(i = 0; i < RXENT_ENTRIES; i++) {
1832                 struct rxbuff_ent *rxb = &tp->rxbuffers[i];
1833                 if(rxb->skb) {
1834                         pci_unmap_single(tp->pdev, rxb->dma_addr, PKT_BUF_SZ,
1835                                        PCI_DMA_FROMDEVICE);
1836                         dev_kfree_skb(rxb->skb);
1837                         rxb->skb = NULL;
1838                 }
1839         }
1840 }
1841
1842 static int
1843 typhoon_sleep(struct typhoon *tp, pci_power_t state, __le16 events)
1844 {
1845         struct pci_dev *pdev = tp->pdev;
1846         void __iomem *ioaddr = tp->ioaddr;
1847         struct cmd_desc xp_cmd;
1848         int err;
1849
1850         INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_ENABLE_WAKE_EVENTS);
1851         xp_cmd.parm1 = events;
1852         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1853         if(err < 0) {
1854                 printk(KERN_ERR "%s: typhoon_sleep(): wake events cmd err %d\n",
1855                                 tp->name, err);
1856                 return err;
1857         }
1858
1859         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_GOTO_SLEEP);
1860         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1861         if(err < 0) {
1862                 printk(KERN_ERR "%s: typhoon_sleep(): sleep cmd err %d\n",
1863                                 tp->name, err);
1864                 return err;
1865         }
1866
1867         if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_SLEEPING) < 0)
1868                 return -ETIMEDOUT;
1869
1870         /* Since we cannot monitor the status of the link while sleeping,
1871          * tell the world it went away.
1872          */
1873         netif_carrier_off(tp->dev);
1874
1875         pci_enable_wake(tp->pdev, state, 1);
1876         pci_disable_device(pdev);
1877         return pci_set_power_state(pdev, state);
1878 }
1879
1880 static int
1881 typhoon_wakeup(struct typhoon *tp, int wait_type)
1882 {
1883         struct pci_dev *pdev = tp->pdev;
1884         void __iomem *ioaddr = tp->ioaddr;
1885
1886         pci_set_power_state(pdev, PCI_D0);
1887         pci_restore_state(pdev);
1888
1889         /* Post 2.x.x versions of the Sleep Image require a reset before
1890          * we can download the Runtime Image. But let's not make users of
1891          * the old firmware pay for the reset.
1892          */
1893         iowrite32(TYPHOON_BOOTCMD_WAKEUP, ioaddr + TYPHOON_REG_COMMAND);
1894         if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_HOST) < 0 ||
1895                         (tp->capabilities & TYPHOON_WAKEUP_NEEDS_RESET))
1896                 return typhoon_reset(ioaddr, wait_type);
1897
1898         return 0;
1899 }
1900
1901 static int
1902 typhoon_start_runtime(struct typhoon *tp)
1903 {
1904         struct net_device *dev = tp->dev;
1905         void __iomem *ioaddr = tp->ioaddr;
1906         struct cmd_desc xp_cmd;
1907         int err;
1908
1909         typhoon_init_rings(tp);
1910         typhoon_fill_free_ring(tp);
1911
1912         err = typhoon_download_firmware(tp);
1913         if(err < 0) {
1914                 printk("%s: cannot load runtime on 3XP\n", tp->name);
1915                 goto error_out;
1916         }
1917
1918         if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_BOOT) < 0) {
1919                 printk("%s: cannot boot 3XP\n", tp->name);
1920                 err = -EIO;
1921                 goto error_out;
1922         }
1923
1924         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAX_PKT_SIZE);
1925         xp_cmd.parm1 = cpu_to_le16(PKT_BUF_SZ);
1926         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1927         if(err < 0)
1928                 goto error_out;
1929
1930         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAC_ADDRESS);
1931         xp_cmd.parm1 = cpu_to_le16(ntohs(*(__be16 *)&dev->dev_addr[0]));
1932         xp_cmd.parm2 = cpu_to_le32(ntohl(*(__be32 *)&dev->dev_addr[2]));
1933         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1934         if(err < 0)
1935                 goto error_out;
1936
1937         /* Disable IRQ coalescing -- we can reenable it when 3Com gives
1938          * us some more information on how to control it.
1939          */
1940         INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_IRQ_COALESCE_CTRL);
1941         xp_cmd.parm1 = 0;
1942         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1943         if(err < 0)
1944                 goto error_out;
1945
1946         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_XCVR_SELECT);
1947         xp_cmd.parm1 = tp->xcvr_select;
1948         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1949         if(err < 0)
1950                 goto error_out;
1951
1952         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_VLAN_TYPE_WRITE);
1953         xp_cmd.parm1 = __constant_cpu_to_le16(ETH_P_8021Q);
1954         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1955         if(err < 0)
1956                 goto error_out;
1957
1958         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_OFFLOAD_TASKS);
1959         spin_lock_bh(&tp->state_lock);
1960         xp_cmd.parm2 = tp->offload;
1961         xp_cmd.parm3 = tp->offload;
1962         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1963         spin_unlock_bh(&tp->state_lock);
1964         if(err < 0)
1965                 goto error_out;
1966
1967         typhoon_set_rx_mode(dev);
1968
1969         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_TX_ENABLE);
1970         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1971         if(err < 0)
1972                 goto error_out;
1973
1974         INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_RX_ENABLE);
1975         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1976         if(err < 0)
1977                 goto error_out;
1978
1979         tp->card_state = Running;
1980         smp_wmb();
1981
1982         iowrite32(TYPHOON_INTR_ENABLE_ALL, ioaddr + TYPHOON_REG_INTR_ENABLE);
1983         iowrite32(TYPHOON_INTR_NONE, ioaddr + TYPHOON_REG_INTR_MASK);
1984         typhoon_post_pci_writes(ioaddr);
1985
1986         return 0;
1987
1988 error_out:
1989         typhoon_reset(ioaddr, WaitNoSleep);
1990         typhoon_free_rx_rings(tp);
1991         typhoon_init_rings(tp);
1992         return err;
1993 }
1994
1995 static int
1996 typhoon_stop_runtime(struct typhoon *tp, int wait_type)
1997 {
1998         struct typhoon_indexes *indexes = tp->indexes;
1999         struct transmit_ring *txLo = &tp->txLoRing;
2000         void __iomem *ioaddr = tp->ioaddr;
2001         struct cmd_desc xp_cmd;
2002         int i;
2003
2004         /* Disable interrupts early, since we can't schedule a poll
2005          * when called with !netif_running(). This will be posted
2006          * when we force the posting of the command.
2007          */
2008         iowrite32(TYPHOON_INTR_NONE, ioaddr + TYPHOON_REG_INTR_ENABLE);
2009
2010         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_RX_DISABLE);
2011         typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
2012
2013         /* Wait 1/2 sec for any outstanding transmits to occur
2014          * We'll cleanup after the reset if this times out.
2015          */
2016         for(i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
2017                 if(indexes->txLoCleared == cpu_to_le32(txLo->lastWrite))
2018                         break;
2019                 udelay(TYPHOON_UDELAY);
2020         }
2021
2022         if(i == TYPHOON_WAIT_TIMEOUT)
2023                 printk(KERN_ERR
2024                        "%s: halt timed out waiting for Tx to complete\n",
2025                        tp->name);
2026
2027         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_TX_DISABLE);
2028         typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
2029
2030         /* save the statistics so when we bring the interface up again,
2031          * the values reported to userspace are correct.
2032          */
2033         tp->card_state = Sleeping;
2034         smp_wmb();
2035         typhoon_do_get_stats(tp);
2036         memcpy(&tp->stats_saved, &tp->stats, sizeof(struct net_device_stats));
2037
2038         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_HALT);
2039         typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
2040
2041         if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_HALTED) < 0)
2042                 printk(KERN_ERR "%s: timed out waiting for 3XP to halt\n",
2043                        tp->name);
2044
2045         if(typhoon_reset(ioaddr, wait_type) < 0) {
2046                 printk(KERN_ERR "%s: unable to reset 3XP\n", tp->name);
2047                 return -ETIMEDOUT;
2048         }
2049
2050         /* cleanup any outstanding Tx packets */
2051         if(indexes->txLoCleared != cpu_to_le32(txLo->lastWrite)) {
2052                 indexes->txLoCleared = cpu_to_le32(txLo->lastWrite);
2053                 typhoon_clean_tx(tp, &tp->txLoRing, &indexes->txLoCleared);
2054         }
2055
2056         return 0;
2057 }
2058
2059 static void
2060 typhoon_tx_timeout(struct net_device *dev)
2061 {
2062         struct typhoon *tp = netdev_priv(dev);
2063
2064         if(typhoon_reset(tp->ioaddr, WaitNoSleep) < 0) {
2065                 printk(KERN_WARNING "%s: could not reset in tx timeout\n",
2066                                         dev->name);
2067                 goto truely_dead;
2068         }
2069
2070         /* If we ever start using the Hi ring, it will need cleaning too */
2071         typhoon_clean_tx(tp, &tp->txLoRing, &tp->indexes->txLoCleared);
2072         typhoon_free_rx_rings(tp);
2073
2074         if(typhoon_start_runtime(tp) < 0) {
2075                 printk(KERN_ERR "%s: could not start runtime in tx timeout\n",
2076                                         dev->name);
2077                 goto truely_dead;
2078         }
2079
2080         netif_wake_queue(dev);
2081         return;
2082
2083 truely_dead:
2084         /* Reset the hardware, and turn off carrier to avoid more timeouts */
2085         typhoon_reset(tp->ioaddr, NoWait);
2086         netif_carrier_off(dev);
2087 }
2088
2089 static int
2090 typhoon_open(struct net_device *dev)
2091 {
2092         struct typhoon *tp = netdev_priv(dev);
2093         int err;
2094
2095         err = typhoon_wakeup(tp, WaitSleep);
2096         if(err < 0) {
2097                 printk(KERN_ERR "%s: unable to wakeup device\n", dev->name);
2098                 goto out_sleep;
2099         }
2100
2101         err = request_irq(dev->irq, &typhoon_interrupt, IRQF_SHARED,
2102                                 dev->name, dev);
2103         if(err < 0)
2104                 goto out_sleep;
2105
2106         napi_enable(&tp->napi);
2107
2108         err = typhoon_start_runtime(tp);
2109         if(err < 0) {
2110                 napi_disable(&tp->napi);
2111                 goto out_irq;
2112         }
2113
2114         netif_start_queue(dev);
2115         return 0;
2116
2117 out_irq:
2118         free_irq(dev->irq, dev);
2119
2120 out_sleep:
2121         if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
2122                 printk(KERN_ERR "%s: unable to reboot into sleep img\n",
2123                                 dev->name);
2124                 typhoon_reset(tp->ioaddr, NoWait);
2125                 goto out;
2126         }
2127
2128         if(typhoon_sleep(tp, PCI_D3hot, 0) < 0)
2129                 printk(KERN_ERR "%s: unable to go back to sleep\n", dev->name);
2130
2131 out:
2132         return err;
2133 }
2134
2135 static int
2136 typhoon_close(struct net_device *dev)
2137 {
2138         struct typhoon *tp = netdev_priv(dev);
2139
2140         netif_stop_queue(dev);
2141         napi_disable(&tp->napi);
2142
2143         if(typhoon_stop_runtime(tp, WaitSleep) < 0)
2144                 printk(KERN_ERR "%s: unable to stop runtime\n", dev->name);
2145
2146         /* Make sure there is no irq handler running on a different CPU. */
2147         typhoon_synchronize_irq(dev->irq);
2148         free_irq(dev->irq, dev);
2149
2150         typhoon_free_rx_rings(tp);
2151         typhoon_init_rings(tp);
2152
2153         if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0)
2154                 printk(KERN_ERR "%s: unable to boot sleep image\n", dev->name);
2155
2156         if(typhoon_sleep(tp, PCI_D3hot, 0) < 0)
2157                 printk(KERN_ERR "%s: unable to put card to sleep\n", dev->name);
2158
2159         return 0;
2160 }
2161
2162 #ifdef CONFIG_PM
2163 static int
2164 typhoon_resume(struct pci_dev *pdev)
2165 {
2166         struct net_device *dev = pci_get_drvdata(pdev);
2167         struct typhoon *tp = netdev_priv(dev);
2168
2169         /* If we're down, resume when we are upped.
2170          */
2171         if(!netif_running(dev))
2172                 return 0;
2173
2174         if(typhoon_wakeup(tp, WaitNoSleep) < 0) {
2175                 printk(KERN_ERR "%s: critical: could not wake up in resume\n",
2176                                 dev->name);
2177                 goto reset;
2178         }
2179
2180         if(typhoon_start_runtime(tp) < 0) {
2181                 printk(KERN_ERR "%s: critical: could not start runtime in "
2182                                 "resume\n", dev->name);
2183                 goto reset;
2184         }
2185
2186         netif_device_attach(dev);
2187         netif_start_queue(dev);
2188         return 0;
2189
2190 reset:
2191         typhoon_reset(tp->ioaddr, NoWait);
2192         return -EBUSY;
2193 }
2194
2195 static int
2196 typhoon_suspend(struct pci_dev *pdev, pm_message_t state)
2197 {
2198         struct net_device *dev = pci_get_drvdata(pdev);
2199         struct typhoon *tp = netdev_priv(dev);
2200         struct cmd_desc xp_cmd;
2201
2202         /* If we're down, we're already suspended.
2203          */
2204         if(!netif_running(dev))
2205                 return 0;
2206
2207         spin_lock_bh(&tp->state_lock);
2208         if(tp->vlgrp && tp->wol_events & TYPHOON_WAKE_MAGIC_PKT) {
2209                 spin_unlock_bh(&tp->state_lock);
2210                 printk(KERN_ERR "%s: cannot do WAKE_MAGIC with VLANS\n",
2211                                 dev->name);
2212                 return -EBUSY;
2213         }
2214         spin_unlock_bh(&tp->state_lock);
2215
2216         netif_device_detach(dev);
2217
2218         if(typhoon_stop_runtime(tp, WaitNoSleep) < 0) {
2219                 printk(KERN_ERR "%s: unable to stop runtime\n", dev->name);
2220                 goto need_resume;
2221         }
2222
2223         typhoon_free_rx_rings(tp);
2224         typhoon_init_rings(tp);
2225
2226         if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
2227                 printk(KERN_ERR "%s: unable to boot sleep image\n", dev->name);
2228                 goto need_resume;
2229         }
2230
2231         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAC_ADDRESS);
2232         xp_cmd.parm1 = cpu_to_le16(ntohs(*(__be16 *)&dev->dev_addr[0]));
2233         xp_cmd.parm2 = cpu_to_le32(ntohl(*(__be32 *)&dev->dev_addr[2]));
2234         if(typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL) < 0) {
2235                 printk(KERN_ERR "%s: unable to set mac address in suspend\n",
2236                                 dev->name);
2237                 goto need_resume;
2238         }
2239
2240         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_RX_FILTER);
2241         xp_cmd.parm1 = TYPHOON_RX_FILTER_DIRECTED | TYPHOON_RX_FILTER_BROADCAST;
2242         if(typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL) < 0) {
2243                 printk(KERN_ERR "%s: unable to set rx filter in suspend\n",
2244                                 dev->name);
2245                 goto need_resume;
2246         }
2247
2248         if(typhoon_sleep(tp, pci_choose_state(pdev, state), tp->wol_events) < 0) {
2249                 printk(KERN_ERR "%s: unable to put card to sleep\n", dev->name);
2250                 goto need_resume;
2251         }
2252
2253         return 0;
2254
2255 need_resume:
2256         typhoon_resume(pdev);
2257         return -EBUSY;
2258 }
2259 #endif
2260
2261 static int __devinit
2262 typhoon_test_mmio(struct pci_dev *pdev)
2263 {
2264         void __iomem *ioaddr = pci_iomap(pdev, 1, 128);
2265         int mode = 0;
2266         u32 val;
2267
2268         if(!ioaddr)
2269                 goto out;
2270
2271         if(ioread32(ioaddr + TYPHOON_REG_STATUS) !=
2272                                 TYPHOON_STATUS_WAITING_FOR_HOST)
2273                 goto out_unmap;
2274
2275         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
2276         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
2277         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_ENABLE);
2278
2279         /* Ok, see if we can change our interrupt status register by
2280          * sending ourselves an interrupt. If so, then MMIO works.
2281          * The 50usec delay is arbitrary -- it could probably be smaller.
2282          */
2283         val = ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2284         if((val & TYPHOON_INTR_SELF) == 0) {
2285                 iowrite32(1, ioaddr + TYPHOON_REG_SELF_INTERRUPT);
2286                 ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2287                 udelay(50);
2288                 val = ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2289                 if(val & TYPHOON_INTR_SELF)
2290                         mode = 1;
2291         }
2292
2293         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
2294         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
2295         iowrite32(TYPHOON_INTR_NONE, ioaddr + TYPHOON_REG_INTR_ENABLE);
2296         ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2297
2298 out_unmap:
2299         pci_iounmap(pdev, ioaddr);
2300
2301 out:
2302         if(!mode)
2303                 printk(KERN_INFO PFX "falling back to port IO\n");
2304         return mode;
2305 }
2306
2307 static int __devinit
2308 typhoon_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2309 {
2310         static int did_version = 0;
2311         struct net_device *dev;
2312         struct typhoon *tp;
2313         int card_id = (int) ent->driver_data;
2314         void __iomem *ioaddr;
2315         void *shared;
2316         dma_addr_t shared_dma;
2317         struct cmd_desc xp_cmd;
2318         struct resp_desc xp_resp[3];
2319         int err = 0;
2320         DECLARE_MAC_BUF(mac);
2321
2322         if(!did_version++)
2323                 printk(KERN_INFO "%s", version);
2324
2325         dev = alloc_etherdev(sizeof(*tp));
2326         if(dev == NULL) {
2327                 printk(ERR_PFX "%s: unable to alloc new net device\n",
2328                        pci_name(pdev));
2329                 err = -ENOMEM;
2330                 goto error_out;
2331         }
2332         SET_NETDEV_DEV(dev, &pdev->dev);
2333
2334         err = pci_enable_device(pdev);
2335         if(err < 0) {
2336                 printk(ERR_PFX "%s: unable to enable device\n",
2337                        pci_name(pdev));
2338                 goto error_out_dev;
2339         }
2340
2341         err = pci_set_mwi(pdev);
2342         if(err < 0) {
2343                 printk(ERR_PFX "%s: unable to set MWI\n", pci_name(pdev));
2344                 goto error_out_disable;
2345         }
2346
2347         err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2348         if(err < 0) {
2349                 printk(ERR_PFX "%s: No usable DMA configuration\n",
2350                        pci_name(pdev));
2351                 goto error_out_mwi;
2352         }
2353
2354         /* sanity checks on IO and MMIO BARs
2355          */
2356         if(!(pci_resource_flags(pdev, 0) & IORESOURCE_IO)) {
2357                 printk(ERR_PFX
2358                        "%s: region #1 not a PCI IO resource, aborting\n",
2359                        pci_name(pdev));
2360                 err = -ENODEV;
2361                 goto error_out_mwi;
2362         }
2363         if(pci_resource_len(pdev, 0) < 128) {
2364                 printk(ERR_PFX "%s: Invalid PCI IO region size, aborting\n",
2365                        pci_name(pdev));
2366                 err = -ENODEV;
2367                 goto error_out_mwi;
2368         }
2369         if(!(pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
2370                 printk(ERR_PFX
2371                        "%s: region #1 not a PCI MMIO resource, aborting\n",
2372                        pci_name(pdev));
2373                 err = -ENODEV;
2374                 goto error_out_mwi;
2375         }
2376         if(pci_resource_len(pdev, 1) < 128) {
2377                 printk(ERR_PFX "%s: Invalid PCI MMIO region size, aborting\n",
2378                        pci_name(pdev));
2379                 err = -ENODEV;
2380                 goto error_out_mwi;
2381         }
2382
2383         err = pci_request_regions(pdev, "typhoon");
2384         if(err < 0) {
2385                 printk(ERR_PFX "%s: could not request regions\n",
2386                        pci_name(pdev));
2387                 goto error_out_mwi;
2388         }
2389
2390         /* map our registers
2391          */
2392         if(use_mmio != 0 && use_mmio != 1)
2393                 use_mmio = typhoon_test_mmio(pdev);
2394
2395         ioaddr = pci_iomap(pdev, use_mmio, 128);
2396         if (!ioaddr) {
2397                 printk(ERR_PFX "%s: cannot remap registers, aborting\n",
2398                        pci_name(pdev));
2399                 err = -EIO;
2400                 goto error_out_regions;
2401         }
2402
2403         /* allocate pci dma space for rx and tx descriptor rings
2404          */
2405         shared = pci_alloc_consistent(pdev, sizeof(struct typhoon_shared),
2406                                       &shared_dma);
2407         if(!shared) {
2408                 printk(ERR_PFX "%s: could not allocate DMA memory\n",
2409                        pci_name(pdev));
2410                 err = -ENOMEM;
2411                 goto error_out_remap;
2412         }
2413
2414         dev->irq = pdev->irq;
2415         tp = netdev_priv(dev);
2416         tp->shared = (struct typhoon_shared *) shared;
2417         tp->shared_dma = shared_dma;
2418         tp->pdev = pdev;
2419         tp->tx_pdev = pdev;
2420         tp->ioaddr = ioaddr;
2421         tp->tx_ioaddr = ioaddr;
2422         tp->dev = dev;
2423
2424         /* Init sequence:
2425          * 1) Reset the adapter to clear any bad juju
2426          * 2) Reload the sleep image
2427          * 3) Boot the sleep image
2428          * 4) Get the hardware address.
2429          * 5) Put the card to sleep.
2430          */
2431         if (typhoon_reset(ioaddr, WaitSleep) < 0) {
2432                 printk(ERR_PFX "%s: could not reset 3XP\n", pci_name(pdev));
2433                 err = -EIO;
2434                 goto error_out_dma;
2435         }
2436
2437         /* Now that we've reset the 3XP and are sure it's not going to
2438          * write all over memory, enable bus mastering, and save our
2439          * state for resuming after a suspend.
2440          */
2441         pci_set_master(pdev);
2442         pci_save_state(pdev);
2443
2444         /* dev->name is not valid until we register, but we need to
2445          * use some common routines to initialize the card. So that those
2446          * routines print the right name, we keep our oun pointer to the name
2447          */
2448         tp->name = pci_name(pdev);
2449
2450         typhoon_init_interface(tp);
2451         typhoon_init_rings(tp);
2452
2453         if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
2454                 printk(ERR_PFX "%s: cannot boot 3XP sleep image\n",
2455                        pci_name(pdev));
2456                 err = -EIO;
2457                 goto error_out_reset;
2458         }
2459
2460         INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_MAC_ADDRESS);
2461         if(typhoon_issue_command(tp, 1, &xp_cmd, 1, xp_resp) < 0) {
2462                 printk(ERR_PFX "%s: cannot read MAC address\n",
2463                        pci_name(pdev));
2464                 err = -EIO;
2465                 goto error_out_reset;
2466         }
2467
2468         *(__be16 *)&dev->dev_addr[0] = htons(le16_to_cpu(xp_resp[0].parm1));
2469         *(__be32 *)&dev->dev_addr[2] = htonl(le32_to_cpu(xp_resp[0].parm2));
2470
2471         if(!is_valid_ether_addr(dev->dev_addr)) {
2472                 printk(ERR_PFX "%s: Could not obtain valid ethernet address, "
2473                        "aborting\n", pci_name(pdev));
2474                 goto error_out_reset;
2475         }
2476
2477         /* Read the Sleep Image version last, so the response is valid
2478          * later when we print out the version reported.
2479          */
2480         INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_VERSIONS);
2481         if(typhoon_issue_command(tp, 1, &xp_cmd, 3, xp_resp) < 0) {
2482                 printk(ERR_PFX "%s: Could not get Sleep Image version\n",
2483                         pci_name(pdev));
2484                 goto error_out_reset;
2485         }
2486
2487         tp->capabilities = typhoon_card_info[card_id].capabilities;
2488         tp->xcvr_select = TYPHOON_XCVR_AUTONEG;
2489
2490         /* Typhoon 1.0 Sleep Images return one response descriptor to the
2491          * READ_VERSIONS command. Those versions are OK after waking up
2492          * from sleep without needing a reset. Typhoon 1.1+ Sleep Images
2493          * seem to need a little extra help to get started. Since we don't
2494          * know how to nudge it along, just kick it.
2495          */
2496         if(xp_resp[0].numDesc != 0)
2497                 tp->capabilities |= TYPHOON_WAKEUP_NEEDS_RESET;
2498
2499         if(typhoon_sleep(tp, PCI_D3hot, 0) < 0) {
2500                 printk(ERR_PFX "%s: cannot put adapter to sleep\n",
2501                        pci_name(pdev));
2502                 err = -EIO;
2503                 goto error_out_reset;
2504         }
2505
2506         /* The chip-specific entries in the device structure. */
2507         dev->open               = typhoon_open;
2508         dev->hard_start_xmit    = typhoon_start_tx;
2509         dev->stop               = typhoon_close;
2510         dev->set_multicast_list = typhoon_set_rx_mode;
2511         dev->tx_timeout         = typhoon_tx_timeout;
2512         netif_napi_add(dev, &tp->napi, typhoon_poll, 16);
2513         dev->watchdog_timeo     = TX_TIMEOUT;
2514         dev->get_stats          = typhoon_get_stats;
2515         dev->set_mac_address    = typhoon_set_mac_address;
2516         dev->vlan_rx_register   = typhoon_vlan_rx_register;
2517
2518         SET_ETHTOOL_OPS(dev, &typhoon_ethtool_ops);
2519
2520         /* We can handle scatter gather, up to 16 entries, and
2521          * we can do IP checksumming (only version 4, doh...)
2522          */
2523         dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
2524         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2525         dev->features |= NETIF_F_TSO;
2526
2527         if(register_netdev(dev) < 0)
2528                 goto error_out_reset;
2529
2530         /* fixup our local name */
2531         tp->name = dev->name;
2532
2533         pci_set_drvdata(pdev, dev);
2534
2535         printk(KERN_INFO "%s: %s at %s 0x%llx, %s\n",
2536                dev->name, typhoon_card_info[card_id].name,
2537                use_mmio ? "MMIO" : "IO",
2538                (unsigned long long)pci_resource_start(pdev, use_mmio),
2539                print_mac(mac, dev->dev_addr));
2540
2541         /* xp_resp still contains the response to the READ_VERSIONS command.
2542          * For debugging, let the user know what version he has.
2543          */
2544         if(xp_resp[0].numDesc == 0) {
2545                 /* This is the Typhoon 1.0 type Sleep Image, last 16 bits
2546                  * of version is Month/Day of build.
2547                  */
2548                 u16 monthday = le32_to_cpu(xp_resp[0].parm2) & 0xffff;
2549                 printk(KERN_INFO "%s: Typhoon 1.0 Sleep Image built "
2550                         "%02u/%02u/2000\n", dev->name, monthday >> 8,
2551                         monthday & 0xff);
2552         } else if(xp_resp[0].numDesc == 2) {
2553                 /* This is the Typhoon 1.1+ type Sleep Image
2554                  */
2555                 u32 sleep_ver = le32_to_cpu(xp_resp[0].parm2);
2556                 u8 *ver_string = (u8 *) &xp_resp[1];
2557                 ver_string[25] = 0;
2558                 printk(KERN_INFO "%s: Typhoon 1.1+ Sleep Image version "
2559                         "%02x.%03x.%03x %s\n", dev->name, sleep_ver >> 24,
2560                         (sleep_ver >> 12) & 0xfff, sleep_ver & 0xfff,
2561                         ver_string);
2562         } else {
2563                 printk(KERN_WARNING "%s: Unknown Sleep Image version "
2564                         "(%u:%04x)\n", dev->name, xp_resp[0].numDesc,
2565                         le32_to_cpu(xp_resp[0].parm2));
2566         }
2567
2568         return 0;
2569
2570 error_out_reset:
2571         typhoon_reset(ioaddr, NoWait);
2572
2573 error_out_dma:
2574         pci_free_consistent(pdev, sizeof(struct typhoon_shared),
2575                             shared, shared_dma);
2576 error_out_remap:
2577         pci_iounmap(pdev, ioaddr);
2578 error_out_regions:
2579         pci_release_regions(pdev);
2580 error_out_mwi:
2581         pci_clear_mwi(pdev);
2582 error_out_disable:
2583         pci_disable_device(pdev);
2584 error_out_dev:
2585         free_netdev(dev);
2586 error_out:
2587         return err;
2588 }
2589
2590 static void __devexit
2591 typhoon_remove_one(struct pci_dev *pdev)
2592 {
2593         struct net_device *dev = pci_get_drvdata(pdev);
2594         struct typhoon *tp = netdev_priv(dev);
2595
2596         unregister_netdev(dev);
2597         pci_set_power_state(pdev, PCI_D0);
2598         pci_restore_state(pdev);
2599         typhoon_reset(tp->ioaddr, NoWait);
2600         pci_iounmap(pdev, tp->ioaddr);
2601         pci_free_consistent(pdev, sizeof(struct typhoon_shared),
2602                             tp->shared, tp->shared_dma);
2603         pci_release_regions(pdev);
2604         pci_clear_mwi(pdev);
2605         pci_disable_device(pdev);
2606         pci_set_drvdata(pdev, NULL);
2607         free_netdev(dev);
2608 }
2609
2610 static struct pci_driver typhoon_driver = {
2611         .name           = DRV_MODULE_NAME,
2612         .id_table       = typhoon_pci_tbl,
2613         .probe          = typhoon_init_one,
2614         .remove         = __devexit_p(typhoon_remove_one),
2615 #ifdef CONFIG_PM
2616         .suspend        = typhoon_suspend,
2617         .resume         = typhoon_resume,
2618 #endif
2619 };
2620
2621 static int __init
2622 typhoon_init(void)
2623 {
2624         return pci_register_driver(&typhoon_driver);
2625 }
2626
2627 static void __exit
2628 typhoon_cleanup(void)
2629 {
2630         pci_unregister_driver(&typhoon_driver);
2631 }
2632
2633 module_init(typhoon_init);
2634 module_exit(typhoon_cleanup);