Merge git://oss.sgi.com:8090/oss/git/xfs-2.6
[linux-2.6] / arch / ppc / syslib / pci_auto.c
1 /*
2  * PCI autoconfiguration library
3  *
4  * Author: Matt Porter <mporter@mvista.com>
5  *
6  * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
7  * the terms of the GNU General Public License version 2.  This program
8  * is licensed "as is" without any warranty of any kind, whether express
9  * or implied.
10  */
11
12 /*
13  * The CardBus support is very preliminary.  Preallocating space is
14  * the way to go but will require some change in card services to
15  * make it useful.  Eventually this will ensure that we can put
16  * multiple CB bridges behind multiple P2P bridges.  For now, at
17  * least it ensures that we place the CB bridge BAR and assigned
18  * initial bus numbers.  I definitely need to do something about
19  * the lack of 16-bit I/O support. -MDP
20  */
21
22 #include <linux/kernel.h>
23 #include <linux/init.h>
24 #include <linux/pci.h>
25
26 #include <asm/pci-bridge.h>
27
28 #define PCIAUTO_IDE_MODE_MASK           0x05
29
30 #undef DEBUG
31
32 #ifdef DEBUG
33 #define DBG(x...) printk(x)
34 #else
35 #define DBG(x...)
36 #endif /* DEBUG */
37
38 static int pciauto_upper_iospc;
39 static int pciauto_upper_memspc;
40
41 void __init pciauto_setup_bars(struct pci_controller *hose,
42                 int current_bus,
43                 int pci_devfn,
44                 int bar_limit)
45 {
46         int bar_response, bar_size, bar_value;
47         int bar, addr_mask;
48         int * upper_limit;
49         int found_mem64 = 0;
50
51         DBG("PCI Autoconfig: Found Bus %d, Device %d, Function %d\n",
52                 current_bus, PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn) );
53
54         for (bar = PCI_BASE_ADDRESS_0; bar <= bar_limit; bar+=4) {
55                 /* Tickle the BAR and get the response */
56                 early_write_config_dword(hose,
57                                 current_bus,
58                                 pci_devfn,
59                                 bar,
60                                 0xffffffff);
61                 early_read_config_dword(hose,
62                                 current_bus,
63                                 pci_devfn,
64                                 bar,
65                                 &bar_response);
66
67                 /* If BAR is not implemented go to the next BAR */
68                 if (!bar_response)
69                         continue;
70
71                 /* Check the BAR type and set our address mask */
72                 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
73                         addr_mask = PCI_BASE_ADDRESS_IO_MASK;
74                         upper_limit = &pciauto_upper_iospc;
75                         DBG("PCI Autoconfig: BAR 0x%x, I/O, ", bar);
76                 } else {
77                         if ( (bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
78                         PCI_BASE_ADDRESS_MEM_TYPE_64)
79                                 found_mem64 = 1;
80
81                         addr_mask = PCI_BASE_ADDRESS_MEM_MASK;  
82                         upper_limit = &pciauto_upper_memspc;
83                         DBG("PCI Autoconfig: BAR 0x%x, Mem ", bar);
84                 }
85
86                 /* Calculate requested size */
87                 bar_size = ~(bar_response & addr_mask) + 1;
88
89                 /* Allocate a base address */
90                 bar_value = (*upper_limit - bar_size) & ~(bar_size - 1);
91
92                 /* Write it out and update our limit */
93                 early_write_config_dword(hose,
94                                 current_bus,
95                                 pci_devfn,
96                                 bar,
97                                 bar_value);
98
99                 *upper_limit = bar_value;
100
101                 /*
102                  * If we are a 64-bit decoder then increment to the
103                  * upper 32 bits of the bar and force it to locate
104                  * in the lower 4GB of memory.
105                  */
106                 if (found_mem64) {
107                         bar += 4;
108                         early_write_config_dword(hose,
109                                         current_bus,
110                                         pci_devfn,
111                                         bar,
112                                         0x00000000);
113                         found_mem64 = 0;
114                 }
115
116                 DBG("size=0x%x, address=0x%x\n",
117                         bar_size, bar_value);
118         }
119
120 }
121
122 void __init pciauto_prescan_setup_bridge(struct pci_controller *hose,
123                 int current_bus,
124                 int pci_devfn,
125                 int sub_bus,
126                 int *iosave,
127                 int *memsave)
128 {
129         /* Configure bus number registers */
130         early_write_config_byte(hose,
131                         current_bus,
132                         pci_devfn,
133                         PCI_PRIMARY_BUS,
134                         current_bus);
135         early_write_config_byte(hose,
136                         current_bus,
137                         pci_devfn,
138                         PCI_SECONDARY_BUS,
139                         sub_bus + 1);
140         early_write_config_byte(hose,
141                         current_bus,
142                         pci_devfn,
143                         PCI_SUBORDINATE_BUS,
144                         0xff);
145
146         /* Round memory allocator to 1MB boundary */
147         pciauto_upper_memspc &= ~(0x100000 - 1);
148         *memsave = pciauto_upper_memspc;
149
150         /* Round I/O allocator to 4KB boundary */
151         pciauto_upper_iospc &= ~(0x1000 - 1);
152         *iosave = pciauto_upper_iospc;
153
154         /* Set up memory and I/O filter limits, assume 32-bit I/O space */
155         early_write_config_word(hose,
156                         current_bus,
157                         pci_devfn,
158                         PCI_MEMORY_LIMIT,
159                         ((pciauto_upper_memspc - 1) & 0xfff00000) >> 16);
160         early_write_config_byte(hose,
161                         current_bus,
162                         pci_devfn,
163                         PCI_IO_LIMIT,
164                         ((pciauto_upper_iospc - 1) & 0x0000f000) >> 8);
165         early_write_config_word(hose,
166                         current_bus,
167                         pci_devfn,
168                         PCI_IO_LIMIT_UPPER16,
169                         ((pciauto_upper_iospc - 1) & 0xffff0000) >> 16);
170
171         /* Zero upper 32 bits of prefetchable base/limit */
172         early_write_config_dword(hose,
173                         current_bus,
174                         pci_devfn,
175                         PCI_PREF_BASE_UPPER32,
176                         0);
177         early_write_config_dword(hose,
178                         current_bus,
179                         pci_devfn,
180                         PCI_PREF_LIMIT_UPPER32,
181                         0);
182 }
183
184 void __init pciauto_postscan_setup_bridge(struct pci_controller *hose,
185                 int current_bus,
186                 int pci_devfn,
187                 int sub_bus,
188                 int *iosave,
189                 int *memsave)
190 {
191         int cmdstat;
192
193         /* Configure bus number registers */
194         early_write_config_byte(hose,
195                         current_bus,
196                         pci_devfn,
197                         PCI_SUBORDINATE_BUS,
198                         sub_bus);
199
200         /*
201          * Round memory allocator to 1MB boundary.
202          * If no space used, allocate minimum.
203          */
204         pciauto_upper_memspc &= ~(0x100000 - 1);
205         if (*memsave == pciauto_upper_memspc)
206                 pciauto_upper_memspc -= 0x00100000;
207
208         early_write_config_word(hose,
209                         current_bus,
210                         pci_devfn,
211                         PCI_MEMORY_BASE,
212                         pciauto_upper_memspc >> 16);
213
214         /* Allocate 1MB for pre-fretch */
215         early_write_config_word(hose,
216                         current_bus,
217                         pci_devfn,
218                         PCI_PREF_MEMORY_LIMIT,
219                         ((pciauto_upper_memspc - 1) & 0xfff00000) >> 16);
220
221         pciauto_upper_memspc -= 0x100000;
222
223         early_write_config_word(hose,
224                         current_bus,
225                         pci_devfn,
226                         PCI_PREF_MEMORY_BASE,
227                         pciauto_upper_memspc >> 16);
228
229         /* Round I/O allocator to 4KB boundary */
230         pciauto_upper_iospc &= ~(0x1000 - 1);
231         if (*iosave == pciauto_upper_iospc)
232                 pciauto_upper_iospc -= 0x1000;
233
234         early_write_config_byte(hose,
235                         current_bus,
236                         pci_devfn,
237                         PCI_IO_BASE,
238                         (pciauto_upper_iospc & 0x0000f000) >> 8);
239         early_write_config_word(hose,
240                         current_bus,
241                         pci_devfn,
242                         PCI_IO_BASE_UPPER16,
243                         pciauto_upper_iospc >> 16);
244
245         /* Enable memory and I/O accesses, enable bus master */
246         early_read_config_dword(hose,
247                         current_bus,
248                         pci_devfn,
249                         PCI_COMMAND,
250                         &cmdstat);
251         early_write_config_dword(hose,
252                         current_bus,
253                         pci_devfn,
254                         PCI_COMMAND,
255                         cmdstat |
256                         PCI_COMMAND_IO |
257                         PCI_COMMAND_MEMORY |
258                         PCI_COMMAND_MASTER);
259 }
260
261 void __init pciauto_prescan_setup_cardbus_bridge(struct pci_controller *hose,
262                 int current_bus,
263                 int pci_devfn,
264                 int sub_bus,
265                 int *iosave,
266                 int *memsave)
267 {
268         /* Configure bus number registers */
269         early_write_config_byte(hose,
270                         current_bus,
271                         pci_devfn,
272                         PCI_PRIMARY_BUS,
273                         current_bus);
274         early_write_config_byte(hose,
275                         current_bus,
276                         pci_devfn,
277                         PCI_SECONDARY_BUS,
278                         sub_bus + 1);
279         early_write_config_byte(hose,
280                         current_bus,
281                         pci_devfn,
282                         PCI_SUBORDINATE_BUS,
283                         0xff);
284
285         /* Round memory allocator to 4KB boundary */
286         pciauto_upper_memspc &= ~(0x1000 - 1);
287         *memsave = pciauto_upper_memspc;
288
289         /* Round I/O allocator to 4 byte boundary */
290         pciauto_upper_iospc &= ~(0x4 - 1);
291         *iosave = pciauto_upper_iospc;
292
293         /* Set up memory and I/O filter limits, assume 32-bit I/O space */
294         early_write_config_dword(hose,
295                         current_bus,
296                         pci_devfn,
297                         0x20,
298                         pciauto_upper_memspc - 1);
299         early_write_config_dword(hose,
300                         current_bus,
301                         pci_devfn,
302                         0x30,
303                         pciauto_upper_iospc - 1);
304 }
305
306 void __init pciauto_postscan_setup_cardbus_bridge(struct pci_controller *hose,
307                 int current_bus,
308                 int pci_devfn,
309                 int sub_bus,
310                 int *iosave,
311                 int *memsave)
312 {
313         int cmdstat;
314
315         /*
316          * Configure subordinate bus number.  The PCI subsystem
317          * bus scan will renumber buses (reserving three additional
318          * for this PCI<->CardBus bridge for the case where a CardBus
319          * adapter contains a P2P or CB2CB bridge.
320          */
321         early_write_config_byte(hose,
322                         current_bus,
323                         pci_devfn,
324                         PCI_SUBORDINATE_BUS,
325                         sub_bus);
326
327         /*
328          * Reserve an additional 4MB for mem space and 16KB for
329          * I/O space.  This should cover any additional space
330          * requirement of unusual CardBus devices with
331          * additional bridges that can consume more address space.
332          *
333          * Although pcmcia-cs currently will reprogram bridge
334          * windows, the goal is to add an option to leave them
335          * alone and use the bridge window ranges as the regions
336          * that are searched for free resources upon hot-insertion
337          * of a device.  This will allow a PCI<->CardBus bridge
338          * configured by this routine to happily live behind a
339          * P2P bridge in a system.
340          */
341         pciauto_upper_memspc -= 0x00400000;
342         pciauto_upper_iospc -= 0x00004000;
343
344         /* Round memory allocator to 4KB boundary */
345         pciauto_upper_memspc &= ~(0x1000 - 1);
346
347         early_write_config_dword(hose,
348                         current_bus,
349                         pci_devfn,
350                         0x1c,
351                         pciauto_upper_memspc);
352
353         /* Round I/O allocator to 4 byte boundary */
354         pciauto_upper_iospc &= ~(0x4 - 1);
355         early_write_config_dword(hose,
356                         current_bus,
357                         pci_devfn,
358                         0x2c,
359                         pciauto_upper_iospc);
360
361         /* Enable memory and I/O accesses, enable bus master */
362         early_read_config_dword(hose,
363                         current_bus,
364                         pci_devfn,
365                         PCI_COMMAND,
366                         &cmdstat);
367         early_write_config_dword(hose,
368                         current_bus,
369                         pci_devfn,
370                         PCI_COMMAND,
371                         cmdstat |
372                         PCI_COMMAND_IO |
373                         PCI_COMMAND_MEMORY |
374                         PCI_COMMAND_MASTER);
375 }
376
377 int __init pciauto_bus_scan(struct pci_controller *hose, int current_bus)
378 {
379         int sub_bus, pci_devfn, pci_class, cmdstat, found_multi = 0;
380         unsigned short vid;
381         unsigned char header_type;
382
383         /*
384          * Fetch our I/O and memory space upper boundaries used
385          * to allocated base addresses on this hose.
386          */
387         if (current_bus == hose->first_busno) {
388                 pciauto_upper_iospc = hose->io_space.end + 1;
389                 pciauto_upper_memspc = hose->mem_space.end + 1;
390         }
391
392         sub_bus = current_bus;
393
394         for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) {
395                 /* Skip our host bridge */
396                 if ( (current_bus == hose->first_busno) && (pci_devfn == 0) )
397                         continue;
398
399                 if (PCI_FUNC(pci_devfn) && !found_multi)
400                         continue;
401
402                 /* If config space read fails from this device, move on */
403                 if (early_read_config_byte(hose,
404                                 current_bus,
405                                 pci_devfn,
406                                 PCI_HEADER_TYPE,
407                                 &header_type))
408                         continue;
409
410                 if (!PCI_FUNC(pci_devfn))
411                         found_multi = header_type & 0x80;
412
413                 early_read_config_word(hose,
414                                 current_bus,
415                                 pci_devfn,
416                                 PCI_VENDOR_ID,
417                                 &vid);
418
419                 if (vid != 0xffff) {
420                         early_read_config_dword(hose,
421                                         current_bus,
422                                         pci_devfn,
423                                         PCI_CLASS_REVISION, &pci_class);
424                         if ( (pci_class >> 16) == PCI_CLASS_BRIDGE_PCI ) {
425                                 int iosave, memsave;
426
427                                 DBG("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_SLOT(pci_devfn));
428                                 /* Allocate PCI I/O and/or memory space */
429                                 pciauto_setup_bars(hose,
430                                                 current_bus,
431                                                 pci_devfn,
432                                                 PCI_BASE_ADDRESS_1);
433
434                                 pciauto_prescan_setup_bridge(hose,
435                                                 current_bus,
436                                                 pci_devfn,
437                                                 sub_bus,
438                                                 &iosave,
439                                                 &memsave);
440                                 sub_bus = pciauto_bus_scan(hose, sub_bus+1);
441                                 pciauto_postscan_setup_bridge(hose,
442                                                 current_bus,
443                                                 pci_devfn,
444                                                 sub_bus,
445                                                 &iosave,
446                                                 &memsave);
447                         } else if ((pci_class >> 16) == PCI_CLASS_BRIDGE_CARDBUS) {
448                                 int iosave, memsave;
449
450                                 DBG("PCI Autoconfig: Found CardBus bridge, device %d function %d\n", PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn));
451                                 /* Place CardBus Socket/ExCA registers */
452                                 pciauto_setup_bars(hose,
453                                                 current_bus,
454                                                 pci_devfn,
455                                                 PCI_BASE_ADDRESS_0);
456
457                                 pciauto_prescan_setup_cardbus_bridge(hose,
458                                                 current_bus,
459                                                 pci_devfn,
460                                                 sub_bus,
461                                                 &iosave,
462                                                 &memsave);
463                                 sub_bus = pciauto_bus_scan(hose, sub_bus+1);
464                                 pciauto_postscan_setup_cardbus_bridge(hose,
465                                                 current_bus,
466                                                 pci_devfn,
467                                                 sub_bus,
468                                                 &iosave,
469                                                 &memsave);
470                         } else {
471                                 if ((pci_class >> 16) == PCI_CLASS_STORAGE_IDE) {
472                                         unsigned char prg_iface;
473
474                                         early_read_config_byte(hose,
475                                                         current_bus,
476                                                         pci_devfn,
477                                                         PCI_CLASS_PROG,
478                                                         &prg_iface);
479                                         if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) {
480                                                 DBG("PCI Autoconfig: Skipping legacy mode IDE controller\n");
481                                                 continue;
482                                         }
483                                 }
484                                 /* Allocate PCI I/O and/or memory space */
485                                 pciauto_setup_bars(hose,
486                                                 current_bus,
487                                                 pci_devfn,
488                                                 PCI_BASE_ADDRESS_5);
489
490                                 /*
491                                  * Enable some standard settings
492                                  */
493                                 early_read_config_dword(hose,
494                                                 current_bus,
495                                                 pci_devfn,
496                                                 PCI_COMMAND,
497                                                 &cmdstat);
498                                 early_write_config_dword(hose,
499                                                 current_bus,
500                                                 pci_devfn,
501                                                 PCI_COMMAND,
502                                                 cmdstat |
503                                                 PCI_COMMAND_IO |
504                                                 PCI_COMMAND_MEMORY |
505                                                 PCI_COMMAND_MASTER);
506                                 early_write_config_byte(hose,
507                                                 current_bus,
508                                                 pci_devfn,
509                                                 PCI_LATENCY_TIMER,
510                                                 0x80);
511                         }
512                 }
513         }
514         return sub_bus;
515 }