2 * Core routines and tables shareable across OS platforms.
4 * Copyright (c) 1994-2002 Justin T. Gibbs.
5 * Copyright (c) 2000-2003 Adaptec Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
15 * substantially similar to the "NO WARRANTY" disclaimer below
16 * ("Disclaimer") and any redistribution must be conditioned upon
17 * including a substantially similar Disclaimer requirement for further
18 * binary redistribution.
19 * 3. Neither the names of the above-listed copyright holders nor the names
20 * of any contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
23 * Alternatively, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2 as published by the Free
25 * Software Foundation.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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38 * POSSIBILITY OF SUCH DAMAGES.
40 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.c#250 $
44 #include "aic79xx_osm.h"
45 #include "aic79xx_inline.h"
46 #include "aicasm/aicasm_insformat.h"
48 #include <dev/aic7xxx/aic79xx_osm.h>
49 #include <dev/aic7xxx/aic79xx_inline.h>
50 #include <dev/aic7xxx/aicasm/aicasm_insformat.h>
54 /***************************** Lookup Tables **********************************/
55 char *ahd_chip_names[] =
62 static const u_int num_chip_names = NUM_ELEMENTS(ahd_chip_names);
65 * Hardware error codes.
67 struct ahd_hard_error_entry {
72 static struct ahd_hard_error_entry ahd_hard_errors[] = {
73 { DSCTMOUT, "Discard Timer has timed out" },
74 { ILLOPCODE, "Illegal Opcode in sequencer program" },
75 { SQPARERR, "Sequencer Parity Error" },
76 { DPARERR, "Data-path Parity Error" },
77 { MPARERR, "Scratch or SCB Memory Parity Error" },
78 { CIOPARERR, "CIOBUS Parity Error" },
80 static const u_int num_errors = NUM_ELEMENTS(ahd_hard_errors);
82 static struct ahd_phase_table_entry ahd_phase_table[] =
84 { P_DATAOUT, MSG_NOOP, "in Data-out phase" },
85 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" },
86 { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" },
87 { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" },
88 { P_COMMAND, MSG_NOOP, "in Command phase" },
89 { P_MESGOUT, MSG_NOOP, "in Message-out phase" },
90 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" },
91 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" },
92 { P_BUSFREE, MSG_NOOP, "while idle" },
93 { 0, MSG_NOOP, "in unknown phase" }
97 * In most cases we only wish to itterate over real phases, so
98 * exclude the last element from the count.
100 static const u_int num_phases = NUM_ELEMENTS(ahd_phase_table) - 1;
102 /* Our Sequencer Program */
103 #include "aic79xx_seq.h"
105 /**************************** Function Declarations ***************************/
106 static void ahd_handle_transmission_error(struct ahd_softc *ahd);
107 static void ahd_handle_lqiphase_error(struct ahd_softc *ahd,
109 static int ahd_handle_pkt_busfree(struct ahd_softc *ahd,
111 static int ahd_handle_nonpkt_busfree(struct ahd_softc *ahd);
112 static void ahd_handle_proto_violation(struct ahd_softc *ahd);
113 static void ahd_force_renegotiation(struct ahd_softc *ahd,
114 struct ahd_devinfo *devinfo);
116 static struct ahd_tmode_tstate*
117 ahd_alloc_tstate(struct ahd_softc *ahd,
118 u_int scsi_id, char channel);
119 #ifdef AHD_TARGET_MODE
120 static void ahd_free_tstate(struct ahd_softc *ahd,
121 u_int scsi_id, char channel, int force);
123 static void ahd_devlimited_syncrate(struct ahd_softc *ahd,
124 struct ahd_initiator_tinfo *,
128 static void ahd_update_neg_table(struct ahd_softc *ahd,
129 struct ahd_devinfo *devinfo,
130 struct ahd_transinfo *tinfo);
131 static void ahd_update_pending_scbs(struct ahd_softc *ahd);
132 static void ahd_fetch_devinfo(struct ahd_softc *ahd,
133 struct ahd_devinfo *devinfo);
134 static void ahd_scb_devinfo(struct ahd_softc *ahd,
135 struct ahd_devinfo *devinfo,
137 static void ahd_setup_initiator_msgout(struct ahd_softc *ahd,
138 struct ahd_devinfo *devinfo,
140 static void ahd_build_transfer_msg(struct ahd_softc *ahd,
141 struct ahd_devinfo *devinfo);
142 static void ahd_construct_sdtr(struct ahd_softc *ahd,
143 struct ahd_devinfo *devinfo,
144 u_int period, u_int offset);
145 static void ahd_construct_wdtr(struct ahd_softc *ahd,
146 struct ahd_devinfo *devinfo,
148 static void ahd_construct_ppr(struct ahd_softc *ahd,
149 struct ahd_devinfo *devinfo,
150 u_int period, u_int offset,
151 u_int bus_width, u_int ppr_options);
152 static void ahd_clear_msg_state(struct ahd_softc *ahd);
153 static void ahd_handle_message_phase(struct ahd_softc *ahd);
159 static int ahd_sent_msg(struct ahd_softc *ahd, ahd_msgtype type,
160 u_int msgval, int full);
161 static int ahd_parse_msg(struct ahd_softc *ahd,
162 struct ahd_devinfo *devinfo);
163 static int ahd_handle_msg_reject(struct ahd_softc *ahd,
164 struct ahd_devinfo *devinfo);
165 static void ahd_handle_ign_wide_residue(struct ahd_softc *ahd,
166 struct ahd_devinfo *devinfo);
167 static void ahd_reinitialize_dataptrs(struct ahd_softc *ahd);
168 static void ahd_handle_devreset(struct ahd_softc *ahd,
169 struct ahd_devinfo *devinfo,
170 u_int lun, cam_status status,
171 char *message, int verbose_level);
172 #ifdef AHD_TARGET_MODE
173 static void ahd_setup_target_msgin(struct ahd_softc *ahd,
174 struct ahd_devinfo *devinfo,
178 static u_int ahd_sglist_size(struct ahd_softc *ahd);
179 static u_int ahd_sglist_allocsize(struct ahd_softc *ahd);
180 static bus_dmamap_callback_t
182 static void ahd_initialize_hscbs(struct ahd_softc *ahd);
183 static int ahd_init_scbdata(struct ahd_softc *ahd);
184 static void ahd_fini_scbdata(struct ahd_softc *ahd);
185 static void ahd_setup_iocell_workaround(struct ahd_softc *ahd);
186 static void ahd_iocell_first_selection(struct ahd_softc *ahd);
187 static void ahd_add_col_list(struct ahd_softc *ahd,
188 struct scb *scb, u_int col_idx);
189 static void ahd_rem_col_list(struct ahd_softc *ahd,
191 static void ahd_chip_init(struct ahd_softc *ahd);
192 static void ahd_qinfifo_requeue(struct ahd_softc *ahd,
193 struct scb *prev_scb,
195 static int ahd_qinfifo_count(struct ahd_softc *ahd);
196 static int ahd_search_scb_list(struct ahd_softc *ahd, int target,
197 char channel, int lun, u_int tag,
198 role_t role, uint32_t status,
199 ahd_search_action action,
200 u_int *list_head, u_int *list_tail,
202 static void ahd_stitch_tid_list(struct ahd_softc *ahd,
203 u_int tid_prev, u_int tid_cur,
205 static void ahd_add_scb_to_free_list(struct ahd_softc *ahd,
207 static u_int ahd_rem_wscb(struct ahd_softc *ahd, u_int scbid,
208 u_int prev, u_int next, u_int tid);
209 static void ahd_reset_current_bus(struct ahd_softc *ahd);
210 static ahd_callback_t ahd_reset_poll;
211 static ahd_callback_t ahd_stat_timer;
213 static void ahd_dumpseq(struct ahd_softc *ahd);
215 static void ahd_loadseq(struct ahd_softc *ahd);
216 static int ahd_check_patch(struct ahd_softc *ahd,
217 struct patch **start_patch,
218 u_int start_instr, u_int *skip_addr);
219 static u_int ahd_resolve_seqaddr(struct ahd_softc *ahd,
221 static void ahd_download_instr(struct ahd_softc *ahd,
222 u_int instrptr, uint8_t *dconsts);
223 static int ahd_probe_stack_size(struct ahd_softc *ahd);
224 static int ahd_scb_active_in_fifo(struct ahd_softc *ahd,
226 static void ahd_run_data_fifo(struct ahd_softc *ahd,
229 #ifdef AHD_TARGET_MODE
230 static void ahd_queue_lstate_event(struct ahd_softc *ahd,
231 struct ahd_tmode_lstate *lstate,
235 static void ahd_update_scsiid(struct ahd_softc *ahd,
237 static int ahd_handle_target_cmd(struct ahd_softc *ahd,
238 struct target_cmd *cmd);
241 /******************************** Private Inlines *****************************/
242 static __inline void ahd_assert_atn(struct ahd_softc *ahd);
243 static __inline int ahd_currently_packetized(struct ahd_softc *ahd);
244 static __inline int ahd_set_active_fifo(struct ahd_softc *ahd);
247 ahd_assert_atn(struct ahd_softc *ahd)
249 ahd_outb(ahd, SCSISIGO, ATNO);
253 * Determine if the current connection has a packetized
254 * agreement. This does not necessarily mean that we
255 * are currently in a packetized transfer. We could
256 * just as easily be sending or receiving a message.
259 ahd_currently_packetized(struct ahd_softc *ahd)
261 ahd_mode_state saved_modes;
264 saved_modes = ahd_save_modes(ahd);
265 if ((ahd->bugs & AHD_PKTIZED_STATUS_BUG) != 0) {
267 * The packetized bit refers to the last
268 * connection, not the current one. Check
269 * for non-zero LQISTATE instead.
271 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
272 packetized = ahd_inb(ahd, LQISTATE) != 0;
274 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
275 packetized = ahd_inb(ahd, LQISTAT2) & PACKETIZED;
277 ahd_restore_modes(ahd, saved_modes);
282 ahd_set_active_fifo(struct ahd_softc *ahd)
286 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
287 active_fifo = ahd_inb(ahd, DFFSTAT) & CURRFIFO;
288 switch (active_fifo) {
291 ahd_set_modes(ahd, active_fifo, active_fifo);
298 /************************* Sequencer Execution Control ************************/
300 * Restart the sequencer program from address zero
303 ahd_restart(struct ahd_softc *ahd)
308 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
310 /* No more pending messages */
311 ahd_clear_msg_state(ahd);
312 ahd_outb(ahd, SCSISIGO, 0); /* De-assert BSY */
313 ahd_outb(ahd, MSG_OUT, MSG_NOOP); /* No message to send */
314 ahd_outb(ahd, SXFRCTL1, ahd_inb(ahd, SXFRCTL1) & ~BITBUCKET);
315 ahd_outb(ahd, SEQINTCTL, 0);
316 ahd_outb(ahd, LASTPHASE, P_BUSFREE);
317 ahd_outb(ahd, SEQ_FLAGS, 0);
318 ahd_outb(ahd, SAVED_SCSIID, 0xFF);
319 ahd_outb(ahd, SAVED_LUN, 0xFF);
322 * Ensure that the sequencer's idea of TQINPOS
323 * matches our own. The sequencer increments TQINPOS
324 * only after it sees a DMA complete and a reset could
325 * occur before the increment leaving the kernel to believe
326 * the command arrived but the sequencer to not.
328 ahd_outb(ahd, TQINPOS, ahd->tqinfifonext);
330 /* Always allow reselection */
331 ahd_outb(ahd, SCSISEQ1,
332 ahd_inb(ahd, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP));
333 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
336 * Clear any pending sequencer interrupt. It is no
337 * longer relevant since we're resetting the Program
340 ahd_outb(ahd, CLRINT, CLRSEQINT);
342 ahd_outb(ahd, SEQCTL0, FASTMODE|SEQRESET);
347 ahd_clear_fifo(struct ahd_softc *ahd, u_int fifo)
349 ahd_mode_state saved_modes;
352 if ((ahd_debug & AHD_SHOW_FIFOS) != 0)
353 printf("%s: Clearing FIFO %d\n", ahd_name(ahd), fifo);
355 saved_modes = ahd_save_modes(ahd);
356 ahd_set_modes(ahd, fifo, fifo);
357 ahd_outb(ahd, DFFSXFRCTL, RSTCHN|CLRSHCNT);
358 if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0)
359 ahd_outb(ahd, CCSGCTL, CCSGRESET);
360 ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR);
361 ahd_outb(ahd, SG_STATE, 0);
362 ahd_restore_modes(ahd, saved_modes);
365 /************************* Input/Output Queues ********************************/
367 * Flush and completed commands that are sitting in the command
368 * complete queues down on the chip but have yet to be dma'ed back up.
371 ahd_flush_qoutfifo(struct ahd_softc *ahd)
374 ahd_mode_state saved_modes;
380 saved_modes = ahd_save_modes(ahd);
383 * Flush the good status FIFO for completed packetized commands.
385 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
386 saved_scbptr = ahd_get_scbptr(ahd);
387 while ((ahd_inb(ahd, LQISTAT2) & LQIGSAVAIL) != 0) {
391 scbid = ahd_inw(ahd, GSFIFO);
392 scb = ahd_lookup_scb(ahd, scbid);
394 printf("%s: Warning - GSFIFO SCB %d invalid\n",
395 ahd_name(ahd), scbid);
399 * Determine if this transaction is still active in
400 * any FIFO. If it is, we must flush that FIFO to
401 * the host before completing the command.
405 for (i = 0; i < 2; i++) {
406 /* Toggle to the other mode. */
408 ahd_set_modes(ahd, fifo_mode, fifo_mode);
410 if (ahd_scb_active_in_fifo(ahd, scb) == 0)
413 ahd_run_data_fifo(ahd, scb);
416 * Running this FIFO may cause a CFG4DATA for
417 * this same transaction to assert in the other
418 * FIFO or a new snapshot SAVEPTRS interrupt
419 * in this FIFO. Even running a FIFO may not
420 * clear the transaction if we are still waiting
421 * for data to drain to the host. We must loop
422 * until the transaction is not active in either
423 * FIFO just to be sure. Reset our loop counter
424 * so we will visit both FIFOs again before
425 * declaring this transaction finished. We
426 * also delay a bit so that status has a chance
427 * to change before we look at this FIFO again.
432 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
433 ahd_set_scbptr(ahd, scbid);
434 if ((ahd_inb_scbram(ahd, SCB_SGPTR) & SG_LIST_NULL) == 0
435 && ((ahd_inb_scbram(ahd, SCB_SGPTR) & SG_FULL_RESID) != 0
436 || (ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR)
437 & SG_LIST_NULL) != 0)) {
441 * The transfer completed with a residual.
442 * Place this SCB on the complete DMA list
443 * so that we update our in-core copy of the
444 * SCB before completing the command.
446 ahd_outb(ahd, SCB_SCSI_STATUS, 0);
447 ahd_outb(ahd, SCB_SGPTR,
448 ahd_inb_scbram(ahd, SCB_SGPTR)
450 ahd_outw(ahd, SCB_TAG, scbid);
451 ahd_outw(ahd, SCB_NEXT_COMPLETE, SCB_LIST_NULL);
452 comp_head = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD);
453 if (SCBID_IS_NULL(comp_head)) {
454 ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, scbid);
455 ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, scbid);
459 tail = ahd_inw(ahd, COMPLETE_DMA_SCB_TAIL);
460 ahd_set_scbptr(ahd, tail);
461 ahd_outw(ahd, SCB_NEXT_COMPLETE, scbid);
462 ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, scbid);
463 ahd_set_scbptr(ahd, scbid);
466 ahd_complete_scb(ahd, scb);
468 ahd_set_scbptr(ahd, saved_scbptr);
471 * Setup for command channel portion of flush.
473 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
476 * Wait for any inprogress DMA to complete and clear DMA state
477 * if this if for an SCB in the qinfifo.
479 while (((ccscbctl = ahd_inb(ahd, CCSCBCTL)) & (CCARREN|CCSCBEN)) != 0) {
481 if ((ccscbctl & (CCSCBDIR|CCARREN)) == (CCSCBDIR|CCARREN)) {
482 if ((ccscbctl & ARRDONE) != 0)
484 } else if ((ccscbctl & CCSCBDONE) != 0)
489 * We leave the sequencer to cleanup in the case of DMA's to
490 * update the qoutfifo. In all other cases (DMA's to the
491 * chip or a push of an SCB from the COMPLETE_DMA_SCB list),
492 * we disable the DMA engine so that the sequencer will not
493 * attempt to handle the DMA completion.
495 if ((ccscbctl & CCSCBDIR) != 0 || (ccscbctl & ARRDONE) != 0)
496 ahd_outb(ahd, CCSCBCTL, ccscbctl & ~(CCARREN|CCSCBEN));
499 * Complete any SCBs that just finished
500 * being DMA'ed into the qoutfifo.
502 ahd_run_qoutfifo(ahd);
504 saved_scbptr = ahd_get_scbptr(ahd);
506 * Manually update/complete any completed SCBs that are waiting to be
507 * DMA'ed back up to the host.
509 scbid = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD);
510 while (!SCBID_IS_NULL(scbid)) {
514 ahd_set_scbptr(ahd, scbid);
515 next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
516 scb = ahd_lookup_scb(ahd, scbid);
518 printf("%s: Warning - DMA-up and complete "
519 "SCB %d invalid\n", ahd_name(ahd), scbid);
522 hscb_ptr = (uint8_t *)scb->hscb;
523 for (i = 0; i < sizeof(struct hardware_scb); i++)
524 *hscb_ptr++ = ahd_inb_scbram(ahd, SCB_BASE + i);
526 ahd_complete_scb(ahd, scb);
529 ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, SCB_LIST_NULL);
530 ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, SCB_LIST_NULL);
532 scbid = ahd_inw(ahd, COMPLETE_ON_QFREEZE_HEAD);
533 while (!SCBID_IS_NULL(scbid)) {
535 ahd_set_scbptr(ahd, scbid);
536 next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
537 scb = ahd_lookup_scb(ahd, scbid);
539 printf("%s: Warning - Complete Qfrz SCB %d invalid\n",
540 ahd_name(ahd), scbid);
544 ahd_complete_scb(ahd, scb);
547 ahd_outw(ahd, COMPLETE_ON_QFREEZE_HEAD, SCB_LIST_NULL);
549 scbid = ahd_inw(ahd, COMPLETE_SCB_HEAD);
550 while (!SCBID_IS_NULL(scbid)) {
552 ahd_set_scbptr(ahd, scbid);
553 next_scbid = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
554 scb = ahd_lookup_scb(ahd, scbid);
556 printf("%s: Warning - Complete SCB %d invalid\n",
557 ahd_name(ahd), scbid);
561 ahd_complete_scb(ahd, scb);
564 ahd_outw(ahd, COMPLETE_SCB_HEAD, SCB_LIST_NULL);
569 ahd_set_scbptr(ahd, saved_scbptr);
570 ahd_restore_modes(ahd, saved_modes);
571 ahd->flags |= AHD_UPDATE_PEND_CMDS;
575 * Determine if an SCB for a packetized transaction
576 * is active in a FIFO.
579 ahd_scb_active_in_fifo(struct ahd_softc *ahd, struct scb *scb)
583 * The FIFO is only active for our transaction if
584 * the SCBPTR matches the SCB's ID and the firmware
585 * has installed a handler for the FIFO or we have
586 * a pending SAVEPTRS or CFG4DATA interrupt.
588 if (ahd_get_scbptr(ahd) != SCB_GET_TAG(scb)
589 || ((ahd_inb(ahd, LONGJMP_ADDR+1) & INVALID_ADDR) != 0
590 && (ahd_inb(ahd, SEQINTSRC) & (CFG4DATA|SAVEPTRS)) == 0))
597 * Run a data fifo to completion for a transaction we know
598 * has completed across the SCSI bus (good status has been
599 * received). We are already set to the correct FIFO mode
600 * on entry to this routine.
602 * This function attempts to operate exactly as the firmware
603 * would when running this FIFO. Care must be taken to update
604 * this routine any time the firmware's FIFO algorithm is
608 ahd_run_data_fifo(struct ahd_softc *ahd, struct scb *scb)
612 seqintsrc = ahd_inb(ahd, SEQINTSRC);
613 if ((seqintsrc & CFG4DATA) != 0) {
618 * Clear full residual flag.
620 sgptr = ahd_inl_scbram(ahd, SCB_SGPTR) & ~SG_FULL_RESID;
621 ahd_outb(ahd, SCB_SGPTR, sgptr);
624 * Load datacnt and address.
626 datacnt = ahd_inl_scbram(ahd, SCB_DATACNT);
627 if ((datacnt & AHD_DMA_LAST_SEG) != 0) {
629 ahd_outb(ahd, SG_STATE, 0);
631 ahd_outb(ahd, SG_STATE, LOADING_NEEDED);
632 ahd_outq(ahd, HADDR, ahd_inq_scbram(ahd, SCB_DATAPTR));
633 ahd_outl(ahd, HCNT, datacnt & AHD_SG_LEN_MASK);
634 ahd_outb(ahd, SG_CACHE_PRE, sgptr);
635 ahd_outb(ahd, DFCNTRL, PRELOADEN|SCSIEN|HDMAEN);
638 * Initialize Residual Fields.
640 ahd_outb(ahd, SCB_RESIDUAL_DATACNT+3, datacnt >> 24);
641 ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr & SG_PTR_MASK);
644 * Mark the SCB as having a FIFO in use.
646 ahd_outb(ahd, SCB_FIFO_USE_COUNT,
647 ahd_inb_scbram(ahd, SCB_FIFO_USE_COUNT) + 1);
650 * Install a "fake" handler for this FIFO.
652 ahd_outw(ahd, LONGJMP_ADDR, 0);
655 * Notify the hardware that we have satisfied
656 * this sequencer interrupt.
658 ahd_outb(ahd, CLRSEQINTSRC, CLRCFG4DATA);
659 } else if ((seqintsrc & SAVEPTRS) != 0) {
663 if ((ahd_inb(ahd, LONGJMP_ADDR+1)&INVALID_ADDR) != 0) {
665 * Snapshot Save Pointers. All that
666 * is necessary to clear the snapshot
673 * Disable S/G fetch so the DMA engine
674 * is available to future users.
676 if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0)
677 ahd_outb(ahd, CCSGCTL, 0);
678 ahd_outb(ahd, SG_STATE, 0);
681 * Flush the data FIFO. Strickly only
682 * necessary for Rev A parts.
684 ahd_outb(ahd, DFCNTRL, ahd_inb(ahd, DFCNTRL) | FIFOFLUSH);
687 * Calculate residual.
689 sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR);
690 resid = ahd_inl(ahd, SHCNT);
691 resid |= ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT+3) << 24;
692 ahd_outl(ahd, SCB_RESIDUAL_DATACNT, resid);
693 if ((ahd_inb(ahd, SG_CACHE_SHADOW) & LAST_SEG) == 0) {
695 * Must back up to the correct S/G element.
696 * Typically this just means resetting our
697 * low byte to the offset in the SG_CACHE,
698 * but if we wrapped, we have to correct
699 * the other bytes of the sgptr too.
701 if ((ahd_inb(ahd, SG_CACHE_SHADOW) & 0x80) != 0
702 && (sgptr & 0x80) == 0)
705 sgptr |= ahd_inb(ahd, SG_CACHE_SHADOW)
707 ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr);
708 ahd_outb(ahd, SCB_RESIDUAL_DATACNT + 3, 0);
709 } else if ((resid & AHD_SG_LEN_MASK) == 0) {
710 ahd_outb(ahd, SCB_RESIDUAL_SGPTR,
711 sgptr | SG_LIST_NULL);
716 ahd_outq(ahd, SCB_DATAPTR, ahd_inq(ahd, SHADDR));
717 ahd_outl(ahd, SCB_DATACNT, resid);
718 ahd_outl(ahd, SCB_SGPTR, sgptr);
719 ahd_outb(ahd, CLRSEQINTSRC, CLRSAVEPTRS);
720 ahd_outb(ahd, SEQIMODE,
721 ahd_inb(ahd, SEQIMODE) | ENSAVEPTRS);
723 * If the data is to the SCSI bus, we are
724 * done, otherwise wait for FIFOEMP.
726 if ((ahd_inb(ahd, DFCNTRL) & DIRECTION) != 0)
728 } else if ((ahd_inb(ahd, SG_STATE) & LOADING_NEEDED) != 0) {
735 * Disable S/G fetch so the DMA engine
736 * is available to future users. We won't
737 * be using the DMA engine to load segments.
739 if ((ahd_inb(ahd, SG_STATE) & FETCH_INPROG) != 0) {
740 ahd_outb(ahd, CCSGCTL, 0);
741 ahd_outb(ahd, SG_STATE, LOADING_NEEDED);
745 * Wait for the DMA engine to notice that the
746 * host transfer is enabled and that there is
747 * space in the S/G FIFO for new segments before
748 * loading more segments.
750 if ((ahd_inb(ahd, DFSTATUS) & PRELOAD_AVAIL) != 0
751 && (ahd_inb(ahd, DFCNTRL) & HDMAENACK) != 0) {
754 * Determine the offset of the next S/G
757 sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR);
758 sgptr &= SG_PTR_MASK;
759 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
760 struct ahd_dma64_seg *sg;
762 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
763 data_addr = sg->addr;
765 sgptr += sizeof(*sg);
767 struct ahd_dma_seg *sg;
769 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
770 data_addr = sg->len & AHD_SG_HIGH_ADDR_MASK;
772 data_addr |= sg->addr;
774 sgptr += sizeof(*sg);
778 * Update residual information.
780 ahd_outb(ahd, SCB_RESIDUAL_DATACNT+3, data_len >> 24);
781 ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr);
786 if (data_len & AHD_DMA_LAST_SEG) {
788 ahd_outb(ahd, SG_STATE, 0);
790 ahd_outq(ahd, HADDR, data_addr);
791 ahd_outl(ahd, HCNT, data_len & AHD_SG_LEN_MASK);
792 ahd_outb(ahd, SG_CACHE_PRE, sgptr & 0xFF);
795 * Advertise the segment to the hardware.
797 dfcntrl = ahd_inb(ahd, DFCNTRL)|PRELOADEN|HDMAEN;
798 if ((ahd->features & AHD_NEW_DFCNTRL_OPTS) != 0) {
800 * Use SCSIENWRDIS so that SCSIEN
801 * is never modified by this
804 dfcntrl |= SCSIENWRDIS;
806 ahd_outb(ahd, DFCNTRL, dfcntrl);
808 } else if ((ahd_inb(ahd, SG_CACHE_SHADOW) & LAST_SEG_DONE) != 0) {
811 * Transfer completed to the end of SG list
812 * and has flushed to the host.
814 ahd_outb(ahd, SCB_SGPTR,
815 ahd_inb_scbram(ahd, SCB_SGPTR) | SG_LIST_NULL);
817 } else if ((ahd_inb(ahd, DFSTATUS) & FIFOEMP) != 0) {
820 * Clear any handler for this FIFO, decrement
821 * the FIFO use count for the SCB, and release
824 ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR);
825 ahd_outb(ahd, SCB_FIFO_USE_COUNT,
826 ahd_inb_scbram(ahd, SCB_FIFO_USE_COUNT) - 1);
827 ahd_outb(ahd, DFFSXFRCTL, CLRCHN);
832 * Look for entries in the QoutFIFO that have completed.
833 * The valid_tag completion field indicates the validity
834 * of the entry - the valid value toggles each time through
835 * the queue. We use the sg_status field in the completion
836 * entry to avoid referencing the hscb if the completion
837 * occurred with no errors and no residual. sg_status is
838 * a copy of the first byte (little endian) of the sgptr
842 ahd_run_qoutfifo(struct ahd_softc *ahd)
844 struct ahd_completion *completion;
848 if ((ahd->flags & AHD_RUNNING_QOUTFIFO) != 0)
849 panic("ahd_run_qoutfifo recursion");
850 ahd->flags |= AHD_RUNNING_QOUTFIFO;
851 ahd_sync_qoutfifo(ahd, BUS_DMASYNC_POSTREAD);
853 completion = &ahd->qoutfifo[ahd->qoutfifonext];
855 if (completion->valid_tag != ahd->qoutfifonext_valid_tag)
858 scb_index = ahd_le16toh(completion->tag);
859 scb = ahd_lookup_scb(ahd, scb_index);
861 printf("%s: WARNING no command for scb %d "
862 "(cmdcmplt)\nQOUTPOS = %d\n",
863 ahd_name(ahd), scb_index,
865 ahd_dump_card_state(ahd);
866 } else if ((completion->sg_status & SG_STATUS_VALID) != 0) {
867 ahd_handle_scb_status(ahd, scb);
872 ahd->qoutfifonext = (ahd->qoutfifonext+1) & (AHD_QOUT_SIZE-1);
873 if (ahd->qoutfifonext == 0)
874 ahd->qoutfifonext_valid_tag ^= QOUTFIFO_ENTRY_VALID;
876 ahd->flags &= ~AHD_RUNNING_QOUTFIFO;
879 /************************* Interrupt Handling *********************************/
881 ahd_handle_hwerrint(struct ahd_softc *ahd)
884 * Some catastrophic hardware error has occurred.
885 * Print it for the user and disable the controller.
890 error = ahd_inb(ahd, ERROR);
891 for (i = 0; i < num_errors; i++) {
892 if ((error & ahd_hard_errors[i].errno) != 0)
893 printf("%s: hwerrint, %s\n",
894 ahd_name(ahd), ahd_hard_errors[i].errmesg);
897 ahd_dump_card_state(ahd);
900 /* Tell everyone that this HBA is no longer available */
901 ahd_abort_scbs(ahd, CAM_TARGET_WILDCARD, ALL_CHANNELS,
902 CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN,
905 /* Tell the system that this controller has gone away. */
910 ahd_handle_seqint(struct ahd_softc *ahd, u_int intstat)
915 * Save the sequencer interrupt code and clear the SEQINT
916 * bit. We will unpause the sequencer, if appropriate,
917 * after servicing the request.
919 seqintcode = ahd_inb(ahd, SEQINTCODE);
920 ahd_outb(ahd, CLRINT, CLRSEQINT);
921 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) {
923 * Unpause the sequencer and let it clear
924 * SEQINT by writing NO_SEQINT to it. This
925 * will cause the sequencer to be paused again,
926 * which is the expected state of this routine.
929 while (!ahd_is_paused(ahd))
931 ahd_outb(ahd, CLRINT, CLRSEQINT);
933 ahd_update_modes(ahd);
935 if ((ahd_debug & AHD_SHOW_MISC) != 0)
936 printf("%s: Handle Seqint Called for code %d\n",
937 ahd_name(ahd), seqintcode);
939 switch (seqintcode) {
940 case ENTERING_NONPACK:
945 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK),
946 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK));
947 scbid = ahd_get_scbptr(ahd);
948 scb = ahd_lookup_scb(ahd, scbid);
951 * Somehow need to know if this
952 * is from a selection or reselection.
953 * From that, we can determine target
954 * ID so we at least have an I_T nexus.
957 ahd_outb(ahd, SAVED_SCSIID, scb->hscb->scsiid);
958 ahd_outb(ahd, SAVED_LUN, scb->hscb->lun);
959 ahd_outb(ahd, SEQ_FLAGS, 0x0);
961 if ((ahd_inb(ahd, LQISTAT2) & LQIPHASE_OUTPKT) != 0
962 && (ahd_inb(ahd, SCSISIGO) & ATNO) != 0) {
964 * Phase change after read stream with
965 * CRC error with P0 asserted on last
969 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0)
970 printf("%s: Assuming LQIPHASE_NLQ with "
971 "P0 assertion\n", ahd_name(ahd));
975 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0)
976 printf("%s: Entering NONPACK\n", ahd_name(ahd));
981 printf("%s: Invalid Sequencer interrupt occurred, "
982 "resetting channel.\n",
985 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0)
986 ahd_dump_card_state(ahd);
988 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
995 scbid = ahd_get_scbptr(ahd);
996 scb = ahd_lookup_scb(ahd, scbid);
998 ahd_print_path(ahd, scb);
1000 printf("%s: ", ahd_name(ahd));
1001 printf("SCB %d Packetized Status Overrun", scbid);
1002 ahd_dump_card_state(ahd);
1003 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1006 case CFG4ISTAT_INTR:
1011 scbid = ahd_get_scbptr(ahd);
1012 scb = ahd_lookup_scb(ahd, scbid);
1014 ahd_dump_card_state(ahd);
1015 printf("CFG4ISTAT: Free SCB %d referenced", scbid);
1016 panic("For safety");
1018 ahd_outq(ahd, HADDR, scb->sense_busaddr);
1019 ahd_outw(ahd, HCNT, AHD_SENSE_BUFSIZE);
1020 ahd_outb(ahd, HCNT + 2, 0);
1021 ahd_outb(ahd, SG_CACHE_PRE, SG_LAST_SEG);
1022 ahd_outb(ahd, DFCNTRL, PRELOADEN|SCSIEN|HDMAEN);
1029 bus_phase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK;
1030 printf("%s: ILLEGAL_PHASE 0x%x\n",
1031 ahd_name(ahd), bus_phase);
1033 switch (bus_phase) {
1041 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1042 printf("%s: Issued Bus Reset.\n", ahd_name(ahd));
1046 struct ahd_devinfo devinfo;
1048 struct ahd_initiator_tinfo *targ_info;
1049 struct ahd_tmode_tstate *tstate;
1050 struct ahd_transinfo *tinfo;
1054 * If a target takes us into the command phase
1055 * assume that it has been externally reset and
1056 * has thus lost our previous packetized negotiation
1057 * agreement. Since we have not sent an identify
1058 * message and may not have fully qualified the
1059 * connection, we change our command to TUR, assert
1060 * ATN and ABORT the task when we go to message in
1061 * phase. The OSM will see the REQUEUE_REQUEST
1062 * status and retry the command.
1064 scbid = ahd_get_scbptr(ahd);
1065 scb = ahd_lookup_scb(ahd, scbid);
1067 printf("Invalid phase with no valid SCB. "
1068 "Resetting bus.\n");
1069 ahd_reset_channel(ahd, 'A',
1070 /*Initiate Reset*/TRUE);
1073 ahd_compile_devinfo(&devinfo, SCB_GET_OUR_ID(scb),
1074 SCB_GET_TARGET(ahd, scb),
1076 SCB_GET_CHANNEL(ahd, scb),
1078 targ_info = ahd_fetch_transinfo(ahd,
1083 tinfo = &targ_info->curr;
1084 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
1085 AHD_TRANS_ACTIVE, /*paused*/TRUE);
1086 ahd_set_syncrate(ahd, &devinfo, /*period*/0,
1087 /*offset*/0, /*ppr_options*/0,
1088 AHD_TRANS_ACTIVE, /*paused*/TRUE);
1089 ahd_outb(ahd, SCB_CDB_STORE, 0);
1090 ahd_outb(ahd, SCB_CDB_STORE+1, 0);
1091 ahd_outb(ahd, SCB_CDB_STORE+2, 0);
1092 ahd_outb(ahd, SCB_CDB_STORE+3, 0);
1093 ahd_outb(ahd, SCB_CDB_STORE+4, 0);
1094 ahd_outb(ahd, SCB_CDB_STORE+5, 0);
1095 ahd_outb(ahd, SCB_CDB_LEN, 6);
1096 scb->hscb->control &= ~(TAG_ENB|SCB_TAG_TYPE);
1097 scb->hscb->control |= MK_MESSAGE;
1098 ahd_outb(ahd, SCB_CONTROL, scb->hscb->control);
1099 ahd_outb(ahd, MSG_OUT, HOST_MSG);
1100 ahd_outb(ahd, SAVED_SCSIID, scb->hscb->scsiid);
1102 * The lun is 0, regardless of the SCB's lun
1103 * as we have not sent an identify message.
1105 ahd_outb(ahd, SAVED_LUN, 0);
1106 ahd_outb(ahd, SEQ_FLAGS, 0);
1107 ahd_assert_atn(ahd);
1108 scb->flags &= ~SCB_PACKETIZED;
1109 scb->flags |= SCB_ABORT|SCB_CMDPHASE_ABORT;
1110 ahd_freeze_devq(ahd, scb);
1111 ahd_set_transaction_status(scb, CAM_REQUEUE_REQ);
1112 ahd_freeze_scb(scb);
1115 * Allow the sequencer to continue with
1116 * non-pack processing.
1118 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1119 ahd_outb(ahd, CLRLQOINT1, CLRLQOPHACHGINPKT);
1120 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) {
1121 ahd_outb(ahd, CLRLQOINT1, 0);
1124 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) {
1125 ahd_print_path(ahd, scb);
1126 printf("Unexpected command phase from "
1127 "packetized target\n");
1141 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) {
1142 printf("%s: CFG4OVERRUN mode = %x\n", ahd_name(ahd),
1143 ahd_inb(ahd, MODE_PTR));
1146 scb_index = ahd_get_scbptr(ahd);
1147 scb = ahd_lookup_scb(ahd, scb_index);
1150 * Attempt to transfer to an SCB that is
1153 ahd_assert_atn(ahd);
1154 ahd_outb(ahd, MSG_OUT, HOST_MSG);
1155 ahd->msgout_buf[0] = MSG_ABORT_TASK;
1156 ahd->msgout_len = 1;
1157 ahd->msgout_index = 0;
1158 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
1160 * Clear status received flag to prevent any
1161 * attempt to complete this bogus SCB.
1163 ahd_outb(ahd, SCB_CONTROL,
1164 ahd_inb_scbram(ahd, SCB_CONTROL)
1169 case DUMP_CARD_STATE:
1171 ahd_dump_card_state(ahd);
1177 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) {
1178 printf("%s: PDATA_REINIT - DFCNTRL = 0x%x "
1179 "SG_CACHE_SHADOW = 0x%x\n",
1180 ahd_name(ahd), ahd_inb(ahd, DFCNTRL),
1181 ahd_inb(ahd, SG_CACHE_SHADOW));
1184 ahd_reinitialize_dataptrs(ahd);
1189 struct ahd_devinfo devinfo;
1192 * The sequencer has encountered a message phase
1193 * that requires host assistance for completion.
1194 * While handling the message phase(s), we will be
1195 * notified by the sequencer after each byte is
1196 * transfered so we can track bus phase changes.
1198 * If this is the first time we've seen a HOST_MSG_LOOP
1199 * interrupt, initialize the state of the host message
1202 ahd_fetch_devinfo(ahd, &devinfo);
1203 if (ahd->msg_type == MSG_TYPE_NONE) {
1208 bus_phase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK;
1209 if (bus_phase != P_MESGIN
1210 && bus_phase != P_MESGOUT) {
1211 printf("ahd_intr: HOST_MSG_LOOP bad "
1212 "phase 0x%x\n", bus_phase);
1214 * Probably transitioned to bus free before
1215 * we got here. Just punt the message.
1217 ahd_dump_card_state(ahd);
1218 ahd_clear_intstat(ahd);
1223 scb_index = ahd_get_scbptr(ahd);
1224 scb = ahd_lookup_scb(ahd, scb_index);
1225 if (devinfo.role == ROLE_INITIATOR) {
1226 if (bus_phase == P_MESGOUT)
1227 ahd_setup_initiator_msgout(ahd,
1232 MSG_TYPE_INITIATOR_MSGIN;
1233 ahd->msgin_index = 0;
1236 #ifdef AHD_TARGET_MODE
1238 if (bus_phase == P_MESGOUT) {
1240 MSG_TYPE_TARGET_MSGOUT;
1241 ahd->msgin_index = 0;
1244 ahd_setup_target_msgin(ahd,
1251 ahd_handle_message_phase(ahd);
1256 /* Ensure we don't leave the selection hardware on */
1257 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
1258 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO);
1260 printf("%s:%c:%d: no active SCB for reconnecting "
1261 "target - issuing BUS DEVICE RESET\n",
1262 ahd_name(ahd), 'A', ahd_inb(ahd, SELID) >> 4);
1263 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
1264 "REG0 == 0x%x ACCUM = 0x%x\n",
1265 ahd_inb(ahd, SAVED_SCSIID), ahd_inb(ahd, SAVED_LUN),
1266 ahd_inw(ahd, REG0), ahd_inb(ahd, ACCUM));
1267 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
1269 ahd_inb(ahd, SEQ_FLAGS), ahd_get_scbptr(ahd),
1270 ahd_find_busy_tcl(ahd,
1271 BUILD_TCL(ahd_inb(ahd, SAVED_SCSIID),
1272 ahd_inb(ahd, SAVED_LUN))),
1273 ahd_inw(ahd, SINDEX));
1274 printf("SELID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
1275 "SCB_CONTROL == 0x%x\n",
1276 ahd_inb(ahd, SELID), ahd_inb_scbram(ahd, SCB_SCSIID),
1277 ahd_inb_scbram(ahd, SCB_LUN),
1278 ahd_inb_scbram(ahd, SCB_CONTROL));
1279 printf("SCSIBUS[0] == 0x%x, SCSISIGI == 0x%x\n",
1280 ahd_inb(ahd, SCSIBUS), ahd_inb(ahd, SCSISIGI));
1281 printf("SXFRCTL0 == 0x%x\n", ahd_inb(ahd, SXFRCTL0));
1282 printf("SEQCTL0 == 0x%x\n", ahd_inb(ahd, SEQCTL0));
1283 ahd_dump_card_state(ahd);
1284 ahd->msgout_buf[0] = MSG_BUS_DEV_RESET;
1285 ahd->msgout_len = 1;
1286 ahd->msgout_index = 0;
1287 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
1288 ahd_outb(ahd, MSG_OUT, HOST_MSG);
1289 ahd_assert_atn(ahd);
1292 case PROTO_VIOLATION:
1294 ahd_handle_proto_violation(ahd);
1299 struct ahd_devinfo devinfo;
1301 ahd_fetch_devinfo(ahd, &devinfo);
1302 ahd_handle_ign_wide_residue(ahd, &devinfo);
1309 lastphase = ahd_inb(ahd, LASTPHASE);
1310 printf("%s:%c:%d: unknown scsi bus phase %x, "
1311 "lastphase = 0x%x. Attempting to continue\n",
1313 SCSIID_TARGET(ahd, ahd_inb(ahd, SAVED_SCSIID)),
1314 lastphase, ahd_inb(ahd, SCSISIGI));
1317 case MISSED_BUSFREE:
1321 lastphase = ahd_inb(ahd, LASTPHASE);
1322 printf("%s:%c:%d: Missed busfree. "
1323 "Lastphase = 0x%x, Curphase = 0x%x\n",
1325 SCSIID_TARGET(ahd, ahd_inb(ahd, SAVED_SCSIID)),
1326 lastphase, ahd_inb(ahd, SCSISIGI));
1333 * When the sequencer detects an overrun, it
1334 * places the controller in "BITBUCKET" mode
1335 * and allows the target to complete its transfer.
1336 * Unfortunately, none of the counters get updated
1337 * when the controller is in this mode, so we have
1338 * no way of knowing how large the overrun was.
1346 scbindex = ahd_get_scbptr(ahd);
1347 scb = ahd_lookup_scb(ahd, scbindex);
1349 lastphase = ahd_inb(ahd, LASTPHASE);
1350 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) {
1351 ahd_print_path(ahd, scb);
1352 printf("data overrun detected %s. Tag == 0x%x.\n",
1353 ahd_lookup_phase_entry(lastphase)->phasemsg,
1355 ahd_print_path(ahd, scb);
1356 printf("%s seen Data Phase. Length = %ld. "
1358 ahd_inb(ahd, SEQ_FLAGS) & DPHASE
1359 ? "Have" : "Haven't",
1360 ahd_get_transfer_length(scb), scb->sg_count);
1361 ahd_dump_sglist(scb);
1366 * Set this and it will take effect when the
1367 * target does a command complete.
1369 ahd_freeze_devq(ahd, scb);
1370 ahd_set_transaction_status(scb, CAM_DATA_RUN_ERR);
1371 ahd_freeze_scb(scb);
1376 struct ahd_devinfo devinfo;
1380 ahd_fetch_devinfo(ahd, &devinfo);
1381 printf("%s:%c:%d:%d: Attempt to issue message failed\n",
1382 ahd_name(ahd), devinfo.channel, devinfo.target,
1384 scbid = ahd_get_scbptr(ahd);
1385 scb = ahd_lookup_scb(ahd, scbid);
1387 && (scb->flags & SCB_RECOVERY_SCB) != 0)
1389 * Ensure that we didn't put a second instance of this
1390 * SCB into the QINFIFO.
1392 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb),
1393 SCB_GET_CHANNEL(ahd, scb),
1394 SCB_GET_LUN(scb), SCB_GET_TAG(scb),
1395 ROLE_INITIATOR, /*status*/0,
1397 ahd_outb(ahd, SCB_CONTROL,
1398 ahd_inb_scbram(ahd, SCB_CONTROL) & ~MK_MESSAGE);
1401 case TASKMGMT_FUNC_COMPLETE:
1406 scbid = ahd_get_scbptr(ahd);
1407 scb = ahd_lookup_scb(ahd, scbid);
1413 ahd_print_path(ahd, scb);
1414 printf("Task Management Func 0x%x Complete\n",
1415 scb->hscb->task_management);
1416 lun = CAM_LUN_WILDCARD;
1417 tag = SCB_LIST_NULL;
1419 switch (scb->hscb->task_management) {
1420 case SIU_TASKMGMT_ABORT_TASK:
1421 tag = SCB_GET_TAG(scb);
1422 case SIU_TASKMGMT_ABORT_TASK_SET:
1423 case SIU_TASKMGMT_CLEAR_TASK_SET:
1424 lun = scb->hscb->lun;
1425 error = CAM_REQ_ABORTED;
1426 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb),
1427 'A', lun, tag, ROLE_INITIATOR,
1430 case SIU_TASKMGMT_LUN_RESET:
1431 lun = scb->hscb->lun;
1432 case SIU_TASKMGMT_TARGET_RESET:
1434 struct ahd_devinfo devinfo;
1436 ahd_scb_devinfo(ahd, &devinfo, scb);
1437 error = CAM_BDR_SENT;
1438 ahd_handle_devreset(ahd, &devinfo, lun,
1440 lun != CAM_LUN_WILDCARD
1443 /*verbose_level*/0);
1447 panic("Unexpected TaskMgmt Func\n");
1453 case TASKMGMT_CMD_CMPLT_OKAY:
1459 * An ABORT TASK TMF failed to be delivered before
1460 * the targeted command completed normally.
1462 scbid = ahd_get_scbptr(ahd);
1463 scb = ahd_lookup_scb(ahd, scbid);
1466 * Remove the second instance of this SCB from
1467 * the QINFIFO if it is still there.
1469 ahd_print_path(ahd, scb);
1470 printf("SCB completes before TMF\n");
1472 * Handle losing the race. Wait until any
1473 * current selection completes. We will then
1474 * set the TMF back to zero in this SCB so that
1475 * the sequencer doesn't bother to issue another
1476 * sequencer interrupt for its completion.
1478 while ((ahd_inb(ahd, SCSISEQ0) & ENSELO) != 0
1479 && (ahd_inb(ahd, SSTAT0) & SELDO) == 0
1480 && (ahd_inb(ahd, SSTAT1) & SELTO) == 0)
1482 ahd_outb(ahd, SCB_TASK_MANAGEMENT, 0);
1483 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb),
1484 SCB_GET_CHANNEL(ahd, scb),
1485 SCB_GET_LUN(scb), SCB_GET_TAG(scb),
1486 ROLE_INITIATOR, /*status*/0,
1495 printf("%s: Tracepoint %d\n", ahd_name(ahd),
1496 seqintcode - TRACEPOINT0);
1501 ahd_handle_hwerrint(ahd);
1504 printf("%s: Unexpected SEQINTCODE %d\n", ahd_name(ahd),
1509 * The sequencer is paused immediately on
1510 * a SEQINT, so we should restart it when
1517 ahd_handle_scsiint(struct ahd_softc *ahd, u_int intstat)
1528 ahd_update_modes(ahd);
1529 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1531 status3 = ahd_inb(ahd, SSTAT3) & (NTRAMPERR|OSRAMPERR);
1532 status0 = ahd_inb(ahd, SSTAT0) & (IOERR|OVERRUN|SELDI|SELDO);
1533 status = ahd_inb(ahd, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
1534 lqistat1 = ahd_inb(ahd, LQISTAT1);
1535 lqostat0 = ahd_inb(ahd, LQOSTAT0);
1536 busfreetime = ahd_inb(ahd, SSTAT2) & BUSFREETIME;
1537 if ((status0 & (SELDI|SELDO)) != 0) {
1540 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
1541 simode0 = ahd_inb(ahd, SIMODE0);
1542 status0 &= simode0 & (IOERR|OVERRUN|SELDI|SELDO);
1543 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1545 scbid = ahd_get_scbptr(ahd);
1546 scb = ahd_lookup_scb(ahd, scbid);
1548 && (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) != 0)
1551 if ((status0 & IOERR) != 0) {
1554 now_lvd = ahd_inb(ahd, SBLKCTL) & ENAB40;
1555 printf("%s: Transceiver State Has Changed to %s mode\n",
1556 ahd_name(ahd), now_lvd ? "LVD" : "SE");
1557 ahd_outb(ahd, CLRSINT0, CLRIOERR);
1559 * A change in I/O mode is equivalent to a bus reset.
1561 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1563 ahd_setup_iocell_workaround(ahd);
1565 } else if ((status0 & OVERRUN) != 0) {
1567 printf("%s: SCSI offset overrun detected. Resetting bus.\n",
1569 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1570 } else if ((status & SCSIRSTI) != 0) {
1572 printf("%s: Someone reset channel A\n", ahd_name(ahd));
1573 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/FALSE);
1574 } else if ((status & SCSIPERR) != 0) {
1576 /* Make sure the sequencer is in a safe location. */
1577 ahd_clear_critical_section(ahd);
1579 ahd_handle_transmission_error(ahd);
1580 } else if (lqostat0 != 0) {
1582 printf("%s: lqostat0 == 0x%x!\n", ahd_name(ahd), lqostat0);
1583 ahd_outb(ahd, CLRLQOINT0, lqostat0);
1584 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0)
1585 ahd_outb(ahd, CLRLQOINT1, 0);
1586 } else if ((status & SELTO) != 0) {
1589 /* Stop the selection */
1590 ahd_outb(ahd, SCSISEQ0, 0);
1592 /* Make sure the sequencer is in a safe location. */
1593 ahd_clear_critical_section(ahd);
1595 /* No more pending messages */
1596 ahd_clear_msg_state(ahd);
1598 /* Clear interrupt state */
1599 ahd_outb(ahd, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR);
1602 * Although the driver does not care about the
1603 * 'Selection in Progress' status bit, the busy
1604 * LED does. SELINGO is only cleared by a sucessfull
1605 * selection, so we must manually clear it to insure
1606 * the LED turns off just incase no future successful
1607 * selections occur (e.g. no devices on the bus).
1609 ahd_outb(ahd, CLRSINT0, CLRSELINGO);
1611 scbid = ahd_inw(ahd, WAITING_TID_HEAD);
1612 scb = ahd_lookup_scb(ahd, scbid);
1614 printf("%s: ahd_intr - referenced scb not "
1615 "valid during SELTO scb(0x%x)\n",
1616 ahd_name(ahd), scbid);
1617 ahd_dump_card_state(ahd);
1619 struct ahd_devinfo devinfo;
1621 if ((ahd_debug & AHD_SHOW_SELTO) != 0) {
1622 ahd_print_path(ahd, scb);
1623 printf("Saw Selection Timeout for SCB 0x%x\n",
1627 ahd_scb_devinfo(ahd, &devinfo, scb);
1628 ahd_set_transaction_status(scb, CAM_SEL_TIMEOUT);
1629 ahd_freeze_devq(ahd, scb);
1632 * Cancel any pending transactions on the device
1633 * now that it seems to be missing. This will
1634 * also revert us to async/narrow transfers until
1635 * we can renegotiate with the device.
1637 ahd_handle_devreset(ahd, &devinfo,
1640 "Selection Timeout",
1641 /*verbose_level*/1);
1643 ahd_outb(ahd, CLRINT, CLRSCSIINT);
1644 ahd_iocell_first_selection(ahd);
1646 } else if ((status0 & (SELDI|SELDO)) != 0) {
1648 ahd_iocell_first_selection(ahd);
1650 } else if (status3 != 0) {
1651 printf("%s: SCSI Cell parity error SSTAT3 == 0x%x\n",
1652 ahd_name(ahd), status3);
1653 ahd_outb(ahd, CLRSINT3, status3);
1654 } else if ((lqistat1 & (LQIPHASE_LQ|LQIPHASE_NLQ)) != 0) {
1656 /* Make sure the sequencer is in a safe location. */
1657 ahd_clear_critical_section(ahd);
1659 ahd_handle_lqiphase_error(ahd, lqistat1);
1660 } else if ((lqistat1 & LQICRCI_NLQ) != 0) {
1662 * This status can be delayed during some
1663 * streaming operations. The SCSIPHASE
1664 * handler has already dealt with this case
1665 * so just clear the error.
1667 ahd_outb(ahd, CLRLQIINT1, CLRLQICRCI_NLQ);
1668 } else if ((status & BUSFREE) != 0
1669 || (lqistat1 & LQOBUSFREE) != 0) {
1677 * Clear our selection hardware as soon as possible.
1678 * We may have an entry in the waiting Q for this target,
1679 * that is affected by this busfree and we don't want to
1680 * go about selecting the target while we handle the event.
1682 ahd_outb(ahd, SCSISEQ0, 0);
1684 /* Make sure the sequencer is in a safe location. */
1685 ahd_clear_critical_section(ahd);
1688 * Determine what we were up to at the time of
1691 mode = AHD_MODE_SCSI;
1692 busfreetime = ahd_inb(ahd, SSTAT2) & BUSFREETIME;
1693 lqostat1 = ahd_inb(ahd, LQOSTAT1);
1694 switch (busfreetime) {
1701 mode = busfreetime == BUSFREE_DFF0
1702 ? AHD_MODE_DFF0 : AHD_MODE_DFF1;
1703 ahd_set_modes(ahd, mode, mode);
1704 scbid = ahd_get_scbptr(ahd);
1705 scb = ahd_lookup_scb(ahd, scbid);
1707 printf("%s: Invalid SCB %d in DFF%d "
1708 "during unexpected busfree\n",
1709 ahd_name(ahd), scbid, mode);
1712 packetized = (scb->flags & SCB_PACKETIZED) != 0;
1722 packetized = (lqostat1 & LQOBUSFREE) != 0;
1724 && ahd_inb(ahd, LASTPHASE) == P_BUSFREE
1725 && (ahd_inb(ahd, SSTAT0) & SELDI) == 0
1726 && ((ahd_inb(ahd, SSTAT0) & SELDO) == 0
1727 || (ahd_inb(ahd, SCSISEQ0) & ENSELO) == 0))
1729 * Assume packetized if we are not
1730 * on the bus in a non-packetized
1731 * capacity and any pending selection
1732 * was a packetized selection.
1739 if ((ahd_debug & AHD_SHOW_MISC) != 0)
1740 printf("Saw Busfree. Busfreetime = 0x%x.\n",
1744 * Busfrees that occur in non-packetized phases are
1745 * handled by the nonpkt_busfree handler.
1747 if (packetized && ahd_inb(ahd, LASTPHASE) == P_BUSFREE) {
1748 restart = ahd_handle_pkt_busfree(ahd, busfreetime);
1751 restart = ahd_handle_nonpkt_busfree(ahd);
1754 * Clear the busfree interrupt status. The setting of
1755 * the interrupt is a pulse, so in a perfect world, we
1756 * would not need to muck with the ENBUSFREE logic. This
1757 * would ensure that if the bus moves on to another
1758 * connection, busfree protection is still in force. If
1759 * BUSFREEREV is broken, however, we must manually clear
1760 * the ENBUSFREE if the busfree occurred during a non-pack
1761 * connection so that we don't get false positives during
1762 * future, packetized, connections.
1764 ahd_outb(ahd, CLRSINT1, CLRBUSFREE);
1766 && (ahd->bugs & AHD_BUSFREEREV_BUG) != 0)
1767 ahd_outb(ahd, SIMODE1,
1768 ahd_inb(ahd, SIMODE1) & ~ENBUSFREE);
1771 ahd_clear_fifo(ahd, mode);
1773 ahd_clear_msg_state(ahd);
1774 ahd_outb(ahd, CLRINT, CLRSCSIINT);
1781 printf("%s: Missing case in ahd_handle_scsiint. status = %x\n",
1782 ahd_name(ahd), status);
1783 ahd_dump_card_state(ahd);
1784 ahd_clear_intstat(ahd);
1790 ahd_handle_transmission_error(struct ahd_softc *ahd)
1804 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1805 lqistat1 = ahd_inb(ahd, LQISTAT1) & ~(LQIPHASE_LQ|LQIPHASE_NLQ);
1806 lqistat2 = ahd_inb(ahd, LQISTAT2);
1807 if ((lqistat1 & (LQICRCI_NLQ|LQICRCI_LQ)) == 0
1808 && (ahd->bugs & AHD_NLQICRC_DELAYED_BUG) != 0) {
1811 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
1812 lqistate = ahd_inb(ahd, LQISTATE);
1813 if ((lqistate >= 0x1E && lqistate <= 0x24)
1814 || (lqistate == 0x29)) {
1816 if ((ahd_debug & AHD_SHOW_RECOVERY) != 0) {
1817 printf("%s: NLQCRC found via LQISTATE\n",
1821 lqistat1 |= LQICRCI_NLQ;
1823 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1826 ahd_outb(ahd, CLRLQIINT1, lqistat1);
1827 lastphase = ahd_inb(ahd, LASTPHASE);
1828 curphase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK;
1829 perrdiag = ahd_inb(ahd, PERRDIAG);
1830 msg_out = MSG_INITIATOR_DET_ERR;
1831 ahd_outb(ahd, CLRSINT1, CLRSCSIPERR);
1834 * Try to find the SCB associated with this error.
1838 || (lqistat1 & LQICRCI_NLQ) != 0) {
1839 if ((lqistat1 & (LQICRCI_NLQ|LQIOVERI_NLQ)) != 0)
1840 ahd_set_active_fifo(ahd);
1841 scbid = ahd_get_scbptr(ahd);
1842 scb = ahd_lookup_scb(ahd, scbid);
1843 if (scb != NULL && SCB_IS_SILENT(scb))
1848 if (silent == FALSE) {
1849 printf("%s: Transmission error detected\n", ahd_name(ahd));
1850 ahd_lqistat1_print(lqistat1, &cur_col, 50);
1851 ahd_lastphase_print(lastphase, &cur_col, 50);
1852 ahd_scsisigi_print(curphase, &cur_col, 50);
1853 ahd_perrdiag_print(perrdiag, &cur_col, 50);
1855 ahd_dump_card_state(ahd);
1858 if ((lqistat1 & (LQIOVERI_LQ|LQIOVERI_NLQ)) != 0) {
1859 if (silent == FALSE) {
1860 printf("%s: Gross protocol error during incoming "
1861 "packet. lqistat1 == 0x%x. Resetting bus.\n",
1862 ahd_name(ahd), lqistat1);
1864 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1866 } else if ((lqistat1 & LQICRCI_LQ) != 0) {
1868 * A CRC error has been detected on an incoming LQ.
1869 * The bus is currently hung on the last ACK.
1870 * Hit LQIRETRY to release the last ack, and
1871 * wait for the sequencer to determine that ATNO
1872 * is asserted while in message out to take us
1873 * to our host message loop. No NONPACKREQ or
1874 * LQIPHASE type errors will occur in this
1875 * scenario. After this first LQIRETRY, the LQI
1876 * manager will be in ISELO where it will
1877 * happily sit until another packet phase begins.
1878 * Unexpected bus free detection is enabled
1879 * through any phases that occur after we release
1880 * this last ack until the LQI manager sees a
1881 * packet phase. This implies we may have to
1882 * ignore a perfectly valid "unexected busfree"
1883 * after our "initiator detected error" message is
1884 * sent. A busfree is the expected response after
1885 * we tell the target that it's L_Q was corrupted.
1886 * (SPI4R09 10.7.3.3.3)
1888 ahd_outb(ahd, LQCTL2, LQIRETRY);
1889 printf("LQIRetry for LQICRCI_LQ to release ACK\n");
1890 } else if ((lqistat1 & LQICRCI_NLQ) != 0) {
1892 * We detected a CRC error in a NON-LQ packet.
1893 * The hardware has varying behavior in this situation
1894 * depending on whether this packet was part of a
1898 * The hardware has already acked the complete packet.
1899 * If the target honors our outstanding ATN condition,
1900 * we should be (or soon will be) in MSGOUT phase.
1901 * This will trigger the LQIPHASE_LQ status bit as the
1902 * hardware was expecting another LQ. Unexpected
1903 * busfree detection is enabled. Once LQIPHASE_LQ is
1904 * true (first entry into host message loop is much
1905 * the same), we must clear LQIPHASE_LQ and hit
1906 * LQIRETRY so the hardware is ready to handle
1907 * a future LQ. NONPACKREQ will not be asserted again
1908 * once we hit LQIRETRY until another packet is
1909 * processed. The target may either go busfree
1910 * or start another packet in response to our message.
1912 * Read Streaming P0 asserted:
1913 * If we raise ATN and the target completes the entire
1914 * stream (P0 asserted during the last packet), the
1915 * hardware will ack all data and return to the ISTART
1916 * state. When the target reponds to our ATN condition,
1917 * LQIPHASE_LQ will be asserted. We should respond to
1918 * this with an LQIRETRY to prepare for any future
1919 * packets. NONPACKREQ will not be asserted again
1920 * once we hit LQIRETRY until another packet is
1921 * processed. The target may either go busfree or
1922 * start another packet in response to our message.
1923 * Busfree detection is enabled.
1925 * Read Streaming P0 not asserted:
1926 * If we raise ATN and the target transitions to
1927 * MSGOUT in or after a packet where P0 is not
1928 * asserted, the hardware will assert LQIPHASE_NLQ.
1929 * We should respond to the LQIPHASE_NLQ with an
1930 * LQIRETRY. Should the target stay in a non-pkt
1931 * phase after we send our message, the hardware
1932 * will assert LQIPHASE_LQ. Recovery is then just as
1933 * listed above for the read streaming with P0 asserted.
1934 * Busfree detection is enabled.
1936 if (silent == FALSE)
1937 printf("LQICRC_NLQ\n");
1939 printf("%s: No SCB valid for LQICRC_NLQ. "
1940 "Resetting bus\n", ahd_name(ahd));
1941 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1944 } else if ((lqistat1 & LQIBADLQI) != 0) {
1945 printf("Need to handle BADLQI!\n");
1946 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
1948 } else if ((perrdiag & (PARITYERR|PREVPHASE)) == PARITYERR) {
1949 if ((curphase & ~P_DATAIN_DT) != 0) {
1950 /* Ack the byte. So we can continue. */
1951 if (silent == FALSE)
1952 printf("Acking %s to clear perror\n",
1953 ahd_lookup_phase_entry(curphase)->phasemsg);
1954 ahd_inb(ahd, SCSIDAT);
1957 if (curphase == P_MESGIN)
1958 msg_out = MSG_PARITY_ERROR;
1962 * We've set the hardware to assert ATN if we
1963 * get a parity error on "in" phases, so all we
1964 * need to do is stuff the message buffer with
1965 * the appropriate message. "In" phases have set
1966 * mesg_out to something other than MSG_NOP.
1968 ahd->send_msg_perror = msg_out;
1969 if (scb != NULL && msg_out == MSG_INITIATOR_DET_ERR)
1970 scb->flags |= SCB_TRANSMISSION_ERROR;
1971 ahd_outb(ahd, MSG_OUT, HOST_MSG);
1972 ahd_outb(ahd, CLRINT, CLRSCSIINT);
1977 ahd_handle_lqiphase_error(struct ahd_softc *ahd, u_int lqistat1)
1980 * Clear the sources of the interrupts.
1982 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
1983 ahd_outb(ahd, CLRLQIINT1, lqistat1);
1986 * If the "illegal" phase changes were in response
1987 * to our ATN to flag a CRC error, AND we ended up
1988 * on packet boundaries, clear the error, restart the
1989 * LQI manager as appropriate, and go on our merry
1990 * way toward sending the message. Otherwise, reset
1991 * the bus to clear the error.
1993 ahd_set_active_fifo(ahd);
1994 if ((ahd_inb(ahd, SCSISIGO) & ATNO) != 0
1995 && (ahd_inb(ahd, MDFFSTAT) & DLZERO) != 0) {
1996 if ((lqistat1 & LQIPHASE_LQ) != 0) {
1997 printf("LQIRETRY for LQIPHASE_LQ\n");
1998 ahd_outb(ahd, LQCTL2, LQIRETRY);
1999 } else if ((lqistat1 & LQIPHASE_NLQ) != 0) {
2000 printf("LQIRETRY for LQIPHASE_NLQ\n");
2001 ahd_outb(ahd, LQCTL2, LQIRETRY);
2003 panic("ahd_handle_lqiphase_error: No phase errors\n");
2004 ahd_dump_card_state(ahd);
2005 ahd_outb(ahd, CLRINT, CLRSCSIINT);
2008 printf("Reseting Channel for LQI Phase error\n");
2009 ahd_dump_card_state(ahd);
2010 ahd_reset_channel(ahd, 'A', /*Initiate Reset*/TRUE);
2015 * Packetized unexpected or expected busfree.
2016 * Entered in mode based on busfreetime.
2019 ahd_handle_pkt_busfree(struct ahd_softc *ahd, u_int busfreetime)
2023 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK),
2024 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK));
2025 lqostat1 = ahd_inb(ahd, LQOSTAT1);
2026 if ((lqostat1 & LQOBUSFREE) != 0) {
2035 * The LQO manager detected an unexpected busfree
2038 * 1) During an outgoing LQ.
2039 * 2) After an outgoing LQ but before the first
2040 * REQ of the command packet.
2041 * 3) During an outgoing command packet.
2043 * In all cases, CURRSCB is pointing to the
2044 * SCB that encountered the failure. Clean
2045 * up the queue, clear SELDO and LQOBUSFREE,
2046 * and allow the sequencer to restart the select
2047 * out at its lesure.
2049 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
2050 scbid = ahd_inw(ahd, CURRSCB);
2051 scb = ahd_lookup_scb(ahd, scbid);
2053 panic("SCB not valid during LQOBUSFREE");
2057 ahd_outb(ahd, CLRLQOINT1, CLRLQOBUSFREE);
2058 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0)
2059 ahd_outb(ahd, CLRLQOINT1, 0);
2060 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO);
2061 ahd_flush_device_writes(ahd);
2062 ahd_outb(ahd, CLRSINT0, CLRSELDO);
2065 * Return the LQO manager to its idle loop. It will
2066 * not do this automatically if the busfree occurs
2067 * after the first REQ of either the LQ or command
2068 * packet or between the LQ and command packet.
2070 ahd_outb(ahd, LQCTL2, ahd_inb(ahd, LQCTL2) | LQOTOIDLE);
2073 * Update the waiting for selection queue so
2074 * we restart on the correct SCB.
2076 waiting_h = ahd_inw(ahd, WAITING_TID_HEAD);
2077 saved_scbptr = ahd_get_scbptr(ahd);
2078 if (waiting_h != scbid) {
2080 ahd_outw(ahd, WAITING_TID_HEAD, scbid);
2081 waiting_t = ahd_inw(ahd, WAITING_TID_TAIL);
2082 if (waiting_t == waiting_h) {
2083 ahd_outw(ahd, WAITING_TID_TAIL, scbid);
2084 next = SCB_LIST_NULL;
2086 ahd_set_scbptr(ahd, waiting_h);
2087 next = ahd_inw_scbram(ahd, SCB_NEXT2);
2089 ahd_set_scbptr(ahd, scbid);
2090 ahd_outw(ahd, SCB_NEXT2, next);
2092 ahd_set_scbptr(ahd, saved_scbptr);
2093 if (scb->crc_retry_count < AHD_MAX_LQ_CRC_ERRORS) {
2094 if (SCB_IS_SILENT(scb) == FALSE) {
2095 ahd_print_path(ahd, scb);
2096 printf("Probable outgoing LQ CRC error. "
2097 "Retrying command\n");
2099 scb->crc_retry_count++;
2101 ahd_set_transaction_status(scb, CAM_UNCOR_PARITY);
2102 ahd_freeze_scb(scb);
2103 ahd_freeze_devq(ahd, scb);
2105 /* Return unpausing the sequencer. */
2107 } else if ((ahd_inb(ahd, PERRDIAG) & PARITYERR) != 0) {
2109 * Ignore what are really parity errors that
2110 * occur on the last REQ of a free running
2111 * clock prior to going busfree. Some drives
2112 * do not properly active negate just before
2113 * going busfree resulting in a parity glitch.
2115 ahd_outb(ahd, CLRSINT1, CLRSCSIPERR|CLRBUSFREE);
2117 if ((ahd_debug & AHD_SHOW_MASKED_ERRORS) != 0)
2118 printf("%s: Parity on last REQ detected "
2119 "during busfree phase.\n",
2122 /* Return unpausing the sequencer. */
2125 if (ahd->src_mode != AHD_MODE_SCSI) {
2129 scbid = ahd_get_scbptr(ahd);
2130 scb = ahd_lookup_scb(ahd, scbid);
2131 ahd_print_path(ahd, scb);
2132 printf("Unexpected PKT busfree condition\n");
2133 ahd_dump_card_state(ahd);
2134 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb), 'A',
2135 SCB_GET_LUN(scb), SCB_GET_TAG(scb),
2136 ROLE_INITIATOR, CAM_UNEXP_BUSFREE);
2138 /* Return restarting the sequencer. */
2141 printf("%s: Unexpected PKT busfree condition\n", ahd_name(ahd));
2142 ahd_dump_card_state(ahd);
2143 /* Restart the sequencer. */
2148 * Non-packetized unexpected or expected busfree.
2151 ahd_handle_nonpkt_busfree(struct ahd_softc *ahd)
2153 struct ahd_devinfo devinfo;
2159 u_int initiator_role_id;
2165 * Look at what phase we were last in. If its message out,
2166 * chances are pretty good that the busfree was in response
2167 * to one of our abort requests.
2169 lastphase = ahd_inb(ahd, LASTPHASE);
2170 saved_scsiid = ahd_inb(ahd, SAVED_SCSIID);
2171 saved_lun = ahd_inb(ahd, SAVED_LUN);
2172 target = SCSIID_TARGET(ahd, saved_scsiid);
2173 initiator_role_id = SCSIID_OUR_ID(saved_scsiid);
2174 ahd_compile_devinfo(&devinfo, initiator_role_id,
2175 target, saved_lun, 'A', ROLE_INITIATOR);
2178 scbid = ahd_get_scbptr(ahd);
2179 scb = ahd_lookup_scb(ahd, scbid);
2181 && (ahd_inb(ahd, SEQ_FLAGS) & NOT_IDENTIFIED) != 0)
2184 ppr_busfree = (ahd->msg_flags & MSG_FLAG_EXPECT_PPR_BUSFREE) != 0;
2185 if (lastphase == P_MESGOUT) {
2188 tag = SCB_LIST_NULL;
2189 if (ahd_sent_msg(ahd, AHDMSG_1B, MSG_ABORT_TAG, TRUE)
2190 || ahd_sent_msg(ahd, AHDMSG_1B, MSG_ABORT, TRUE)) {
2195 ahd_print_devinfo(ahd, &devinfo);
2196 printf("Abort for unidentified "
2197 "connection completed.\n");
2198 /* restart the sequencer. */
2201 sent_msg = ahd->msgout_buf[ahd->msgout_index - 1];
2202 ahd_print_path(ahd, scb);
2203 printf("SCB %d - Abort%s Completed.\n",
2205 sent_msg == MSG_ABORT_TAG ? "" : " Tag");
2207 if (sent_msg == MSG_ABORT_TAG)
2208 tag = SCB_GET_TAG(scb);
2210 if ((scb->flags & SCB_CMDPHASE_ABORT) != 0) {
2212 * This abort is in response to an
2213 * unexpected switch to command phase
2214 * for a packetized connection. Since
2215 * the identify message was never sent,
2216 * "saved lun" is 0. We really want to
2217 * abort only the SCB that encountered
2218 * this error, which could have a different
2219 * lun. The SCB will be retried so the OS
2220 * will see the UA after renegotiating to
2223 tag = SCB_GET_TAG(scb);
2224 saved_lun = scb->hscb->lun;
2226 found = ahd_abort_scbs(ahd, target, 'A', saved_lun,
2227 tag, ROLE_INITIATOR,
2229 printf("found == 0x%x\n", found);
2231 } else if (ahd_sent_msg(ahd, AHDMSG_1B,
2232 MSG_BUS_DEV_RESET, TRUE)) {
2235 * Don't mark the user's request for this BDR
2236 * as completing with CAM_BDR_SENT. CAM3
2237 * specifies CAM_REQ_CMP.
2240 && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV
2241 && ahd_match_scb(ahd, scb, target, 'A',
2242 CAM_LUN_WILDCARD, SCB_LIST_NULL,
2244 ahd_set_transaction_status(scb, CAM_REQ_CMP);
2246 ahd_handle_devreset(ahd, &devinfo, CAM_LUN_WILDCARD,
2247 CAM_BDR_SENT, "Bus Device Reset",
2248 /*verbose_level*/0);
2250 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, FALSE)
2251 && ppr_busfree == 0) {
2252 struct ahd_initiator_tinfo *tinfo;
2253 struct ahd_tmode_tstate *tstate;
2258 * If the previous negotiation was packetized,
2259 * this could be because the device has been
2260 * reset without our knowledge. Force our
2261 * current negotiation to async and retry the
2262 * negotiation. Otherwise retry the command
2263 * with non-ppr negotiation.
2266 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2267 printf("PPR negotiation rejected busfree.\n");
2269 tinfo = ahd_fetch_transinfo(ahd, devinfo.channel,
2271 devinfo.target, &tstate);
2272 if ((tinfo->curr.ppr_options & MSG_EXT_PPR_IU_REQ)!=0) {
2273 ahd_set_width(ahd, &devinfo,
2274 MSG_EXT_WDTR_BUS_8_BIT,
2277 ahd_set_syncrate(ahd, &devinfo,
2278 /*period*/0, /*offset*/0,
2283 * The expect PPR busfree handler below
2284 * will effect the retry and necessary
2288 tinfo->curr.transport_version = 2;
2289 tinfo->goal.transport_version = 2;
2290 tinfo->goal.ppr_options = 0;
2292 * Remove any SCBs in the waiting for selection
2293 * queue that may also be for this target so
2294 * that command ordering is preserved.
2296 ahd_freeze_devq(ahd, scb);
2297 ahd_qinfifo_requeue_tail(ahd, scb);
2300 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, FALSE)
2301 && ppr_busfree == 0) {
2303 * Negotiation Rejected. Go-narrow and
2307 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2308 printf("WDTR negotiation rejected busfree.\n");
2310 ahd_set_width(ahd, &devinfo,
2311 MSG_EXT_WDTR_BUS_8_BIT,
2312 AHD_TRANS_CUR|AHD_TRANS_GOAL,
2315 * Remove any SCBs in the waiting for selection
2316 * queue that may also be for this target so that
2317 * command ordering is preserved.
2319 ahd_freeze_devq(ahd, scb);
2320 ahd_qinfifo_requeue_tail(ahd, scb);
2322 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, FALSE)
2323 && ppr_busfree == 0) {
2325 * Negotiation Rejected. Go-async and
2329 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2330 printf("SDTR negotiation rejected busfree.\n");
2332 ahd_set_syncrate(ahd, &devinfo,
2333 /*period*/0, /*offset*/0,
2335 AHD_TRANS_CUR|AHD_TRANS_GOAL,
2338 * Remove any SCBs in the waiting for selection
2339 * queue that may also be for this target so that
2340 * command ordering is preserved.
2342 ahd_freeze_devq(ahd, scb);
2343 ahd_qinfifo_requeue_tail(ahd, scb);
2345 } else if ((ahd->msg_flags & MSG_FLAG_EXPECT_IDE_BUSFREE) != 0
2346 && ahd_sent_msg(ahd, AHDMSG_1B,
2347 MSG_INITIATOR_DET_ERR, TRUE)) {
2350 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2351 printf("Expected IDE Busfree\n");
2354 } else if ((ahd->msg_flags & MSG_FLAG_EXPECT_QASREJ_BUSFREE)
2355 && ahd_sent_msg(ahd, AHDMSG_1B,
2356 MSG_MESSAGE_REJECT, TRUE)) {
2359 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2360 printf("Expected QAS Reject Busfree\n");
2367 * The busfree required flag is honored at the end of
2368 * the message phases. We check it last in case we
2369 * had to send some other message that caused a busfree.
2372 && (lastphase == P_MESGIN || lastphase == P_MESGOUT)
2373 && ((ahd->msg_flags & MSG_FLAG_EXPECT_PPR_BUSFREE) != 0)) {
2375 ahd_freeze_devq(ahd, scb);
2376 ahd_set_transaction_status(scb, CAM_REQUEUE_REQ);
2377 ahd_freeze_scb(scb);
2378 if ((ahd->msg_flags & MSG_FLAG_IU_REQ_CHANGED) != 0) {
2379 ahd_abort_scbs(ahd, SCB_GET_TARGET(ahd, scb),
2380 SCB_GET_CHANNEL(ahd, scb),
2381 SCB_GET_LUN(scb), SCB_LIST_NULL,
2382 ROLE_INITIATOR, CAM_REQ_ABORTED);
2385 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
2386 printf("PPR Negotiation Busfree.\n");
2392 if (printerror != 0) {
2399 if ((scb->hscb->control & TAG_ENB) != 0)
2400 tag = SCB_GET_TAG(scb);
2402 tag = SCB_LIST_NULL;
2403 ahd_print_path(ahd, scb);
2404 aborted = ahd_abort_scbs(ahd, target, 'A',
2405 SCB_GET_LUN(scb), tag,
2410 * We had not fully identified this connection,
2411 * so we cannot abort anything.
2413 printf("%s: ", ahd_name(ahd));
2415 printf("Unexpected busfree %s, %d SCBs aborted, "
2416 "PRGMCNT == 0x%x\n",
2417 ahd_lookup_phase_entry(lastphase)->phasemsg,
2419 ahd_inw(ahd, PRGMCNT));
2420 ahd_dump_card_state(ahd);
2421 if (lastphase != P_BUSFREE)
2422 ahd_force_renegotiation(ahd, &devinfo);
2424 /* Always restart the sequencer. */
2429 ahd_handle_proto_violation(struct ahd_softc *ahd)
2431 struct ahd_devinfo devinfo;
2439 ahd_fetch_devinfo(ahd, &devinfo);
2440 scbid = ahd_get_scbptr(ahd);
2441 scb = ahd_lookup_scb(ahd, scbid);
2442 seq_flags = ahd_inb(ahd, SEQ_FLAGS);
2443 curphase = ahd_inb(ahd, SCSISIGI) & PHASE_MASK;
2444 lastphase = ahd_inb(ahd, LASTPHASE);
2445 if ((seq_flags & NOT_IDENTIFIED) != 0) {
2448 * The reconnecting target either did not send an
2449 * identify message, or did, but we didn't find an SCB
2452 ahd_print_devinfo(ahd, &devinfo);
2453 printf("Target did not send an IDENTIFY message. "
2454 "LASTPHASE = 0x%x.\n", lastphase);
2456 } else if (scb == NULL) {
2458 * We don't seem to have an SCB active for this
2459 * transaction. Print an error and reset the bus.
2461 ahd_print_devinfo(ahd, &devinfo);
2462 printf("No SCB found during protocol violation\n");
2463 goto proto_violation_reset;
2465 ahd_set_transaction_status(scb, CAM_SEQUENCE_FAIL);
2466 if ((seq_flags & NO_CDB_SENT) != 0) {
2467 ahd_print_path(ahd, scb);
2468 printf("No or incomplete CDB sent to device.\n");
2469 } else if ((ahd_inb_scbram(ahd, SCB_CONTROL)
2470 & STATUS_RCVD) == 0) {
2472 * The target never bothered to provide status to
2473 * us prior to completing the command. Since we don't
2474 * know the disposition of this command, we must attempt
2475 * to abort it. Assert ATN and prepare to send an abort
2478 ahd_print_path(ahd, scb);
2479 printf("Completed command without status.\n");
2481 ahd_print_path(ahd, scb);
2482 printf("Unknown protocol violation.\n");
2483 ahd_dump_card_state(ahd);
2486 if ((lastphase & ~P_DATAIN_DT) == 0
2487 || lastphase == P_COMMAND) {
2488 proto_violation_reset:
2490 * Target either went directly to data
2491 * phase or didn't respond to our ATN.
2492 * The only safe thing to do is to blow
2493 * it away with a bus reset.
2495 found = ahd_reset_channel(ahd, 'A', TRUE);
2496 printf("%s: Issued Channel %c Bus Reset. "
2497 "%d SCBs aborted\n", ahd_name(ahd), 'A', found);
2500 * Leave the selection hardware off in case
2501 * this abort attempt will affect yet to
2504 ahd_outb(ahd, SCSISEQ0,
2505 ahd_inb(ahd, SCSISEQ0) & ~ENSELO);
2506 ahd_assert_atn(ahd);
2507 ahd_outb(ahd, MSG_OUT, HOST_MSG);
2509 ahd_print_devinfo(ahd, &devinfo);
2510 ahd->msgout_buf[0] = MSG_ABORT_TASK;
2511 ahd->msgout_len = 1;
2512 ahd->msgout_index = 0;
2513 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2515 ahd_print_path(ahd, scb);
2516 scb->flags |= SCB_ABORT;
2518 printf("Protocol violation %s. Attempting to abort.\n",
2519 ahd_lookup_phase_entry(curphase)->phasemsg);
2524 * Force renegotiation to occur the next time we initiate
2525 * a command to the current device.
2528 ahd_force_renegotiation(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
2530 struct ahd_initiator_tinfo *targ_info;
2531 struct ahd_tmode_tstate *tstate;
2534 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
2535 ahd_print_devinfo(ahd, devinfo);
2536 printf("Forcing renegotiation\n");
2539 targ_info = ahd_fetch_transinfo(ahd,
2541 devinfo->our_scsiid,
2544 ahd_update_neg_request(ahd, devinfo, tstate,
2545 targ_info, AHD_NEG_IF_NON_ASYNC);
2548 #define AHD_MAX_STEPS 2000
2550 ahd_clear_critical_section(struct ahd_softc *ahd)
2552 ahd_mode_state saved_modes;
2564 if (ahd->num_critical_sections == 0)
2577 saved_modes = ahd_save_modes(ahd);
2583 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
2584 seqaddr = ahd_inw(ahd, CURADDR);
2586 cs = ahd->critical_sections;
2587 for (i = 0; i < ahd->num_critical_sections; i++, cs++) {
2589 if (cs->begin < seqaddr && cs->end >= seqaddr)
2593 if (i == ahd->num_critical_sections)
2596 if (steps > AHD_MAX_STEPS) {
2597 printf("%s: Infinite loop in critical section\n"
2598 "%s: First Instruction 0x%x now 0x%x\n",
2599 ahd_name(ahd), ahd_name(ahd), first_instr,
2601 ahd_dump_card_state(ahd);
2602 panic("critical section loop");
2607 if ((ahd_debug & AHD_SHOW_MISC) != 0)
2608 printf("%s: Single stepping at 0x%x\n", ahd_name(ahd),
2611 if (stepping == FALSE) {
2613 first_instr = seqaddr;
2614 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
2615 simode0 = ahd_inb(ahd, SIMODE0);
2616 simode3 = ahd_inb(ahd, SIMODE3);
2617 lqimode0 = ahd_inb(ahd, LQIMODE0);
2618 lqimode1 = ahd_inb(ahd, LQIMODE1);
2619 lqomode0 = ahd_inb(ahd, LQOMODE0);
2620 lqomode1 = ahd_inb(ahd, LQOMODE1);
2621 ahd_outb(ahd, SIMODE0, 0);
2622 ahd_outb(ahd, SIMODE3, 0);
2623 ahd_outb(ahd, LQIMODE0, 0);
2624 ahd_outb(ahd, LQIMODE1, 0);
2625 ahd_outb(ahd, LQOMODE0, 0);
2626 ahd_outb(ahd, LQOMODE1, 0);
2627 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
2628 simode1 = ahd_inb(ahd, SIMODE1);
2630 * We don't clear ENBUSFREE. Unfortunately
2631 * we cannot re-enable busfree detection within
2632 * the current connection, so we must leave it
2633 * on while single stepping.
2635 ahd_outb(ahd, SIMODE1, simode1 & ENBUSFREE);
2636 ahd_outb(ahd, SEQCTL0, ahd_inb(ahd, SEQCTL0) | STEP);
2639 ahd_outb(ahd, CLRSINT1, CLRBUSFREE);
2640 ahd_outb(ahd, CLRINT, CLRSCSIINT);
2641 ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode);
2642 ahd_outb(ahd, HCNTRL, ahd->unpause);
2643 while (!ahd_is_paused(ahd))
2645 ahd_update_modes(ahd);
2648 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
2649 ahd_outb(ahd, SIMODE0, simode0);
2650 ahd_outb(ahd, SIMODE3, simode3);
2651 ahd_outb(ahd, LQIMODE0, lqimode0);
2652 ahd_outb(ahd, LQIMODE1, lqimode1);
2653 ahd_outb(ahd, LQOMODE0, lqomode0);
2654 ahd_outb(ahd, LQOMODE1, lqomode1);
2655 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
2656 ahd_outb(ahd, SEQCTL0, ahd_inb(ahd, SEQCTL0) & ~STEP);
2657 ahd_outb(ahd, SIMODE1, simode1);
2659 * SCSIINT seems to glitch occassionally when
2660 * the interrupt masks are restored. Clear SCSIINT
2661 * one more time so that only persistent errors
2662 * are seen as a real interrupt.
2664 ahd_outb(ahd, CLRINT, CLRSCSIINT);
2666 ahd_restore_modes(ahd, saved_modes);
2670 * Clear any pending interrupt status.
2673 ahd_clear_intstat(struct ahd_softc *ahd)
2675 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK),
2676 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK));
2677 /* Clear any interrupt conditions this may have caused */
2678 ahd_outb(ahd, CLRLQIINT0, CLRLQIATNQAS|CLRLQICRCT1|CLRLQICRCT2
2679 |CLRLQIBADLQT|CLRLQIATNLQ|CLRLQIATNCMD);
2680 ahd_outb(ahd, CLRLQIINT1, CLRLQIPHASE_LQ|CLRLQIPHASE_NLQ|CLRLIQABORT
2681 |CLRLQICRCI_LQ|CLRLQICRCI_NLQ|CLRLQIBADLQI
2682 |CLRLQIOVERI_LQ|CLRLQIOVERI_NLQ|CLRNONPACKREQ);
2683 ahd_outb(ahd, CLRLQOINT0, CLRLQOTARGSCBPERR|CLRLQOSTOPT2|CLRLQOATNLQ
2684 |CLRLQOATNPKT|CLRLQOTCRC);
2685 ahd_outb(ahd, CLRLQOINT1, CLRLQOINITSCBPERR|CLRLQOSTOPI2|CLRLQOBADQAS
2686 |CLRLQOBUSFREE|CLRLQOPHACHGINPKT);
2687 if ((ahd->bugs & AHD_CLRLQO_AUTOCLR_BUG) != 0) {
2688 ahd_outb(ahd, CLRLQOINT0, 0);
2689 ahd_outb(ahd, CLRLQOINT1, 0);
2691 ahd_outb(ahd, CLRSINT3, CLRNTRAMPERR|CLROSRAMPERR);
2692 ahd_outb(ahd, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI
2693 |CLRBUSFREE|CLRSCSIPERR|CLRREQINIT);
2694 ahd_outb(ahd, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO
2695 |CLRIOERR|CLROVERRUN);
2696 ahd_outb(ahd, CLRINT, CLRSCSIINT);
2699 /**************************** Debugging Routines ******************************/
2701 uint32_t ahd_debug = AHD_DEBUG_OPTS;
2704 ahd_print_scb(struct scb *scb)
2706 struct hardware_scb *hscb;
2710 printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n",
2716 printf("Shared Data: ");
2717 for (i = 0; i < sizeof(hscb->shared_data.idata.cdb); i++)
2718 printf("%#02x", hscb->shared_data.idata.cdb[i]);
2719 printf(" dataptr:%#x%x datacnt:%#x sgptr:%#x tag:%#x\n",
2720 (uint32_t)((ahd_le64toh(hscb->dataptr) >> 32) & 0xFFFFFFFF),
2721 (uint32_t)(ahd_le64toh(hscb->dataptr) & 0xFFFFFFFF),
2722 ahd_le32toh(hscb->datacnt),
2723 ahd_le32toh(hscb->sgptr),
2725 ahd_dump_sglist(scb);
2729 ahd_dump_sglist(struct scb *scb)
2733 if (scb->sg_count > 0) {
2734 if ((scb->ahd_softc->flags & AHD_64BIT_ADDRESSING) != 0) {
2735 struct ahd_dma64_seg *sg_list;
2737 sg_list = (struct ahd_dma64_seg*)scb->sg_list;
2738 for (i = 0; i < scb->sg_count; i++) {
2742 addr = ahd_le64toh(sg_list[i].addr);
2743 len = ahd_le32toh(sg_list[i].len);
2744 printf("sg[%d] - Addr 0x%x%x : Length %d%s\n",
2746 (uint32_t)((addr >> 32) & 0xFFFFFFFF),
2747 (uint32_t)(addr & 0xFFFFFFFF),
2748 sg_list[i].len & AHD_SG_LEN_MASK,
2749 (sg_list[i].len & AHD_DMA_LAST_SEG)
2753 struct ahd_dma_seg *sg_list;
2755 sg_list = (struct ahd_dma_seg*)scb->sg_list;
2756 for (i = 0; i < scb->sg_count; i++) {
2759 len = ahd_le32toh(sg_list[i].len);
2760 printf("sg[%d] - Addr 0x%x%x : Length %d%s\n",
2762 (len & AHD_SG_HIGH_ADDR_MASK) >> 24,
2763 ahd_le32toh(sg_list[i].addr),
2764 len & AHD_SG_LEN_MASK,
2765 len & AHD_DMA_LAST_SEG ? " Last" : "");
2771 /************************* Transfer Negotiation *******************************/
2773 * Allocate per target mode instance (ID we respond to as a target)
2774 * transfer negotiation data structures.
2776 static struct ahd_tmode_tstate *
2777 ahd_alloc_tstate(struct ahd_softc *ahd, u_int scsi_id, char channel)
2779 struct ahd_tmode_tstate *master_tstate;
2780 struct ahd_tmode_tstate *tstate;
2783 master_tstate = ahd->enabled_targets[ahd->our_id];
2784 if (ahd->enabled_targets[scsi_id] != NULL
2785 && ahd->enabled_targets[scsi_id] != master_tstate)
2786 panic("%s: ahd_alloc_tstate - Target already allocated",
2788 tstate = malloc(sizeof(*tstate), M_DEVBUF, M_NOWAIT);
2793 * If we have allocated a master tstate, copy user settings from
2794 * the master tstate (taken from SRAM or the EEPROM) for this
2795 * channel, but reset our current and goal settings to async/narrow
2796 * until an initiator talks to us.
2798 if (master_tstate != NULL) {
2799 memcpy(tstate, master_tstate, sizeof(*tstate));
2800 memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns));
2801 for (i = 0; i < 16; i++) {
2802 memset(&tstate->transinfo[i].curr, 0,
2803 sizeof(tstate->transinfo[i].curr));
2804 memset(&tstate->transinfo[i].goal, 0,
2805 sizeof(tstate->transinfo[i].goal));
2808 memset(tstate, 0, sizeof(*tstate));
2809 ahd->enabled_targets[scsi_id] = tstate;
2813 #ifdef AHD_TARGET_MODE
2815 * Free per target mode instance (ID we respond to as a target)
2816 * transfer negotiation data structures.
2819 ahd_free_tstate(struct ahd_softc *ahd, u_int scsi_id, char channel, int force)
2821 struct ahd_tmode_tstate *tstate;
2824 * Don't clean up our "master" tstate.
2825 * It has our default user settings.
2827 if (scsi_id == ahd->our_id
2831 tstate = ahd->enabled_targets[scsi_id];
2833 free(tstate, M_DEVBUF);
2834 ahd->enabled_targets[scsi_id] = NULL;
2839 * Called when we have an active connection to a target on the bus,
2840 * this function finds the nearest period to the input period limited
2841 * by the capabilities of the bus connectivity of and sync settings for
2845 ahd_devlimited_syncrate(struct ahd_softc *ahd,
2846 struct ahd_initiator_tinfo *tinfo,
2847 u_int *period, u_int *ppr_options, role_t role)
2849 struct ahd_transinfo *transinfo;
2852 if ((ahd_inb(ahd, SBLKCTL) & ENAB40) != 0
2853 && (ahd_inb(ahd, SSTAT2) & EXP_ACTIVE) == 0) {
2854 maxsync = AHD_SYNCRATE_PACED;
2856 maxsync = AHD_SYNCRATE_ULTRA;
2857 /* Can't do DT related options on an SE bus */
2858 *ppr_options &= MSG_EXT_PPR_QAS_REQ;
2861 * Never allow a value higher than our current goal
2862 * period otherwise we may allow a target initiated
2863 * negotiation to go above the limit as set by the
2864 * user. In the case of an initiator initiated
2865 * sync negotiation, we limit based on the user
2866 * setting. This allows the system to still accept
2867 * incoming negotiations even if target initiated
2868 * negotiation is not performed.
2870 if (role == ROLE_TARGET)
2871 transinfo = &tinfo->user;
2873 transinfo = &tinfo->goal;
2874 *ppr_options &= (transinfo->ppr_options|MSG_EXT_PPR_PCOMP_EN);
2875 if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) {
2876 maxsync = MAX(maxsync, AHD_SYNCRATE_ULTRA2);
2877 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
2879 if (transinfo->period == 0) {
2883 *period = MAX(*period, transinfo->period);
2884 ahd_find_syncrate(ahd, period, ppr_options, maxsync);
2889 * Look up the valid period to SCSIRATE conversion in our table.
2890 * Return the period and offset that should be sent to the target
2891 * if this was the beginning of an SDTR.
2894 ahd_find_syncrate(struct ahd_softc *ahd, u_int *period,
2895 u_int *ppr_options, u_int maxsync)
2897 if (*period < maxsync)
2900 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) != 0
2901 && *period > AHD_SYNCRATE_MIN_DT)
2902 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
2904 if (*period > AHD_SYNCRATE_MIN)
2907 /* Honor PPR option conformance rules. */
2908 if (*period > AHD_SYNCRATE_PACED)
2909 *ppr_options &= ~MSG_EXT_PPR_RTI;
2911 if ((*ppr_options & MSG_EXT_PPR_IU_REQ) == 0)
2912 *ppr_options &= (MSG_EXT_PPR_DT_REQ|MSG_EXT_PPR_QAS_REQ);
2914 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0)
2915 *ppr_options &= MSG_EXT_PPR_QAS_REQ;
2917 /* Skip all PACED only entries if IU is not available */
2918 if ((*ppr_options & MSG_EXT_PPR_IU_REQ) == 0
2919 && *period < AHD_SYNCRATE_DT)
2920 *period = AHD_SYNCRATE_DT;
2922 /* Skip all DT only entries if DT is not available */
2923 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0
2924 && *period < AHD_SYNCRATE_ULTRA2)
2925 *period = AHD_SYNCRATE_ULTRA2;
2929 * Truncate the given synchronous offset to a value the
2930 * current adapter type and syncrate are capable of.
2933 ahd_validate_offset(struct ahd_softc *ahd,
2934 struct ahd_initiator_tinfo *tinfo,
2935 u_int period, u_int *offset, int wide,
2940 /* Limit offset to what we can do */
2943 else if (period <= AHD_SYNCRATE_PACED) {
2944 if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0)
2945 maxoffset = MAX_OFFSET_PACED_BUG;
2947 maxoffset = MAX_OFFSET_PACED;
2949 maxoffset = MAX_OFFSET_NON_PACED;
2950 *offset = MIN(*offset, maxoffset);
2951 if (tinfo != NULL) {
2952 if (role == ROLE_TARGET)
2953 *offset = MIN(*offset, tinfo->user.offset);
2955 *offset = MIN(*offset, tinfo->goal.offset);
2960 * Truncate the given transfer width parameter to a value the
2961 * current adapter type is capable of.
2964 ahd_validate_width(struct ahd_softc *ahd, struct ahd_initiator_tinfo *tinfo,
2965 u_int *bus_width, role_t role)
2967 switch (*bus_width) {
2969 if (ahd->features & AHD_WIDE) {
2971 *bus_width = MSG_EXT_WDTR_BUS_16_BIT;
2975 case MSG_EXT_WDTR_BUS_8_BIT:
2976 *bus_width = MSG_EXT_WDTR_BUS_8_BIT;
2979 if (tinfo != NULL) {
2980 if (role == ROLE_TARGET)
2981 *bus_width = MIN(tinfo->user.width, *bus_width);
2983 *bus_width = MIN(tinfo->goal.width, *bus_width);
2988 * Update the bitmask of targets for which the controller should
2989 * negotiate with at the next convenient oportunity. This currently
2990 * means the next time we send the initial identify messages for
2991 * a new transaction.
2994 ahd_update_neg_request(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
2995 struct ahd_tmode_tstate *tstate,
2996 struct ahd_initiator_tinfo *tinfo, ahd_neg_type neg_type)
2998 u_int auto_negotiate_orig;
3000 auto_negotiate_orig = tstate->auto_negotiate;
3001 if (neg_type == AHD_NEG_ALWAYS) {
3003 * Force our "current" settings to be
3004 * unknown so that unless a bus reset
3005 * occurs the need to renegotiate is
3006 * recorded persistently.
3008 if ((ahd->features & AHD_WIDE) != 0)
3009 tinfo->curr.width = AHD_WIDTH_UNKNOWN;
3010 tinfo->curr.period = AHD_PERIOD_UNKNOWN;
3011 tinfo->curr.offset = AHD_OFFSET_UNKNOWN;
3013 if (tinfo->curr.period != tinfo->goal.period
3014 || tinfo->curr.width != tinfo->goal.width
3015 || tinfo->curr.offset != tinfo->goal.offset
3016 || tinfo->curr.ppr_options != tinfo->goal.ppr_options
3017 || (neg_type == AHD_NEG_IF_NON_ASYNC
3018 && (tinfo->goal.offset != 0
3019 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT
3020 || tinfo->goal.ppr_options != 0)))
3021 tstate->auto_negotiate |= devinfo->target_mask;
3023 tstate->auto_negotiate &= ~devinfo->target_mask;
3025 return (auto_negotiate_orig != tstate->auto_negotiate);
3029 * Update the user/goal/curr tables of synchronous negotiation
3030 * parameters as well as, in the case of a current or active update,
3031 * any data structures on the host controller. In the case of an
3032 * active update, the specified target is currently talking to us on
3033 * the bus, so the transfer parameter update must take effect
3037 ahd_set_syncrate(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3038 u_int period, u_int offset, u_int ppr_options,
3039 u_int type, int paused)
3041 struct ahd_initiator_tinfo *tinfo;
3042 struct ahd_tmode_tstate *tstate;
3049 active = (type & AHD_TRANS_ACTIVE) == AHD_TRANS_ACTIVE;
3052 if (period == 0 || offset == 0) {
3057 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid,
3058 devinfo->target, &tstate);
3060 if ((type & AHD_TRANS_USER) != 0) {
3061 tinfo->user.period = period;
3062 tinfo->user.offset = offset;
3063 tinfo->user.ppr_options = ppr_options;
3066 if ((type & AHD_TRANS_GOAL) != 0) {
3067 tinfo->goal.period = period;
3068 tinfo->goal.offset = offset;
3069 tinfo->goal.ppr_options = ppr_options;
3072 old_period = tinfo->curr.period;
3073 old_offset = tinfo->curr.offset;
3074 old_ppr = tinfo->curr.ppr_options;
3076 if ((type & AHD_TRANS_CUR) != 0
3077 && (old_period != period
3078 || old_offset != offset
3079 || old_ppr != ppr_options)) {
3083 tinfo->curr.period = period;
3084 tinfo->curr.offset = offset;
3085 tinfo->curr.ppr_options = ppr_options;
3087 ahd_send_async(ahd, devinfo->channel, devinfo->target,
3088 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
3093 printf("%s: target %d synchronous with "
3094 "period = 0x%x, offset = 0x%x",
3095 ahd_name(ahd), devinfo->target,
3098 if ((ppr_options & MSG_EXT_PPR_RD_STRM) != 0) {
3102 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0) {
3103 printf("%s", options ? "|DT" : "(DT");
3106 if ((ppr_options & MSG_EXT_PPR_IU_REQ) != 0) {
3107 printf("%s", options ? "|IU" : "(IU");
3110 if ((ppr_options & MSG_EXT_PPR_RTI) != 0) {
3111 printf("%s", options ? "|RTI" : "(RTI");
3114 if ((ppr_options & MSG_EXT_PPR_QAS_REQ) != 0) {
3115 printf("%s", options ? "|QAS" : "(QAS");
3123 printf("%s: target %d using "
3124 "asynchronous transfers%s\n",
3125 ahd_name(ahd), devinfo->target,
3126 (ppr_options & MSG_EXT_PPR_QAS_REQ) != 0
3132 * Always refresh the neg-table to handle the case of the
3133 * sequencer setting the ENATNO bit for a MK_MESSAGE request.
3134 * We will always renegotiate in that case if this is a
3135 * packetized request. Also manage the busfree expected flag
3136 * from this common routine so that we catch changes due to
3137 * WDTR or SDTR messages.
3139 if ((type & AHD_TRANS_CUR) != 0) {
3142 ahd_update_neg_table(ahd, devinfo, &tinfo->curr);
3145 if (ahd->msg_type != MSG_TYPE_NONE) {
3146 if ((old_ppr & MSG_EXT_PPR_IU_REQ)
3147 != (ppr_options & MSG_EXT_PPR_IU_REQ)) {
3149 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
3150 ahd_print_devinfo(ahd, devinfo);
3151 printf("Expecting IU Change busfree\n");
3154 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE
3155 | MSG_FLAG_IU_REQ_CHANGED;
3157 if ((old_ppr & MSG_EXT_PPR_IU_REQ) != 0) {
3159 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
3160 printf("PPR with IU_REQ outstanding\n");
3162 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE;
3167 update_needed += ahd_update_neg_request(ahd, devinfo, tstate,
3168 tinfo, AHD_NEG_TO_GOAL);
3170 if (update_needed && active)
3171 ahd_update_pending_scbs(ahd);
3175 * Update the user/goal/curr tables of wide negotiation
3176 * parameters as well as, in the case of a current or active update,
3177 * any data structures on the host controller. In the case of an
3178 * active update, the specified target is currently talking to us on
3179 * the bus, so the transfer parameter update must take effect
3183 ahd_set_width(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3184 u_int width, u_int type, int paused)
3186 struct ahd_initiator_tinfo *tinfo;
3187 struct ahd_tmode_tstate *tstate;
3192 active = (type & AHD_TRANS_ACTIVE) == AHD_TRANS_ACTIVE;
3194 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid,
3195 devinfo->target, &tstate);
3197 if ((type & AHD_TRANS_USER) != 0)
3198 tinfo->user.width = width;
3200 if ((type & AHD_TRANS_GOAL) != 0)
3201 tinfo->goal.width = width;
3203 oldwidth = tinfo->curr.width;
3204 if ((type & AHD_TRANS_CUR) != 0 && oldwidth != width) {
3208 tinfo->curr.width = width;
3209 ahd_send_async(ahd, devinfo->channel, devinfo->target,
3210 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
3212 printf("%s: target %d using %dbit transfers\n",
3213 ahd_name(ahd), devinfo->target,
3214 8 * (0x01 << width));
3218 if ((type & AHD_TRANS_CUR) != 0) {
3221 ahd_update_neg_table(ahd, devinfo, &tinfo->curr);
3226 update_needed += ahd_update_neg_request(ahd, devinfo, tstate,
3227 tinfo, AHD_NEG_TO_GOAL);
3228 if (update_needed && active)
3229 ahd_update_pending_scbs(ahd);
3234 * Update the current state of tagged queuing for a given target.
3237 ahd_set_tags(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3240 ahd_platform_set_tags(ahd, devinfo, alg);
3241 ahd_send_async(ahd, devinfo->channel, devinfo->target,
3242 devinfo->lun, AC_TRANSFER_NEG, &alg);
3246 ahd_update_neg_table(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3247 struct ahd_transinfo *tinfo)
3249 ahd_mode_state saved_modes;
3254 u_int saved_negoaddr;
3255 uint8_t iocell_opts[sizeof(ahd->iocell_opts)];
3257 saved_modes = ahd_save_modes(ahd);
3258 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
3260 saved_negoaddr = ahd_inb(ahd, NEGOADDR);
3261 ahd_outb(ahd, NEGOADDR, devinfo->target);
3262 period = tinfo->period;
3263 offset = tinfo->offset;
3264 memcpy(iocell_opts, ahd->iocell_opts, sizeof(ahd->iocell_opts));
3265 ppr_opts = tinfo->ppr_options & (MSG_EXT_PPR_QAS_REQ|MSG_EXT_PPR_DT_REQ
3266 |MSG_EXT_PPR_IU_REQ|MSG_EXT_PPR_RTI);
3269 period = AHD_SYNCRATE_ASYNC;
3270 if (period == AHD_SYNCRATE_160) {
3272 if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0) {
3274 * When the SPI4 spec was finalized, PACE transfers
3275 * was not made a configurable option in the PPR
3276 * message. Instead it is assumed to be enabled for
3277 * any syncrate faster than 80MHz. Nevertheless,
3278 * Harpoon2A4 allows this to be configurable.
3280 * Harpoon2A4 also assumes at most 2 data bytes per
3281 * negotiated REQ/ACK offset. Paced transfers take
3282 * 4, so we must adjust our offset.
3284 ppr_opts |= PPROPT_PACE;
3288 * Harpoon2A assumed that there would be a
3289 * fallback rate between 160MHz and 80Mhz,
3290 * so 7 is used as the period factor rather
3291 * than 8 for 160MHz.
3293 period = AHD_SYNCRATE_REVA_160;
3295 if ((tinfo->ppr_options & MSG_EXT_PPR_PCOMP_EN) == 0)
3296 iocell_opts[AHD_PRECOMP_SLEW_INDEX] &=
3300 * Precomp should be disabled for non-paced transfers.
3302 iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_PRECOMP_MASK;
3304 if ((ahd->features & AHD_NEW_IOCELL_OPTS) != 0
3305 && (ppr_opts & MSG_EXT_PPR_DT_REQ) != 0
3306 && (ppr_opts & MSG_EXT_PPR_IU_REQ) == 0) {
3308 * Slow down our CRC interval to be
3309 * compatible with non-packetized
3310 * U160 devices that can't handle a
3311 * CRC at full speed.
3313 con_opts |= ENSLOWCRC;
3316 if ((ahd->bugs & AHD_PACED_NEGTABLE_BUG) != 0) {
3318 * On H2A4, revert to a slower slewrate
3319 * on non-paced transfers.
3321 iocell_opts[AHD_PRECOMP_SLEW_INDEX] &=
3326 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_PRECOMP_SLEW);
3327 ahd_outb(ahd, ANNEXDAT, iocell_opts[AHD_PRECOMP_SLEW_INDEX]);
3328 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_AMPLITUDE);
3329 ahd_outb(ahd, ANNEXDAT, iocell_opts[AHD_AMPLITUDE_INDEX]);
3331 ahd_outb(ahd, NEGPERIOD, period);
3332 ahd_outb(ahd, NEGPPROPTS, ppr_opts);
3333 ahd_outb(ahd, NEGOFFSET, offset);
3335 if (tinfo->width == MSG_EXT_WDTR_BUS_16_BIT)
3336 con_opts |= WIDEXFER;
3339 * Slow down our CRC interval to be
3340 * compatible with packetized U320 devices
3341 * that can't handle a CRC at full speed
3343 if (ahd->features & AHD_AIC79XXB_SLOWCRC) {
3344 con_opts |= ENSLOWCRC;
3348 * During packetized transfers, the target will
3349 * give us the oportunity to send command packets
3350 * without us asserting attention.
3352 if ((tinfo->ppr_options & MSG_EXT_PPR_IU_REQ) == 0)
3353 con_opts |= ENAUTOATNO;
3354 ahd_outb(ahd, NEGCONOPTS, con_opts);
3355 ahd_outb(ahd, NEGOADDR, saved_negoaddr);
3356 ahd_restore_modes(ahd, saved_modes);
3360 * When the transfer settings for a connection change, setup for
3361 * negotiation in pending SCBs to effect the change as quickly as
3362 * possible. We also cancel any negotiations that are scheduled
3363 * for inflight SCBs that have not been started yet.
3366 ahd_update_pending_scbs(struct ahd_softc *ahd)
3368 struct scb *pending_scb;
3369 int pending_scb_count;
3372 ahd_mode_state saved_modes;
3375 * Traverse the pending SCB list and ensure that all of the
3376 * SCBs there have the proper settings. We can only safely
3377 * clear the negotiation required flag (setting requires the
3378 * execution queue to be modified) and this is only possible
3379 * if we are not already attempting to select out for this
3380 * SCB. For this reason, all callers only call this routine
3381 * if we are changing the negotiation settings for the currently
3382 * active transaction on the bus.
3384 pending_scb_count = 0;
3385 LIST_FOREACH(pending_scb, &ahd->pending_scbs, pending_links) {
3386 struct ahd_devinfo devinfo;
3387 struct ahd_initiator_tinfo *tinfo;
3388 struct ahd_tmode_tstate *tstate;
3390 ahd_scb_devinfo(ahd, &devinfo, pending_scb);
3391 tinfo = ahd_fetch_transinfo(ahd, devinfo.channel,
3393 devinfo.target, &tstate);
3394 if ((tstate->auto_negotiate & devinfo.target_mask) == 0
3395 && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) {
3396 pending_scb->flags &= ~SCB_AUTO_NEGOTIATE;
3397 pending_scb->hscb->control &= ~MK_MESSAGE;
3399 ahd_sync_scb(ahd, pending_scb,
3400 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
3401 pending_scb_count++;
3404 if (pending_scb_count == 0)
3407 if (ahd_is_paused(ahd)) {
3415 * Force the sequencer to reinitialize the selection for
3416 * the command at the head of the execution queue if it
3417 * has already been setup. The negotiation changes may
3418 * effect whether we select-out with ATN. It is only
3419 * safe to clear ENSELO when the bus is not free and no
3420 * selection is in progres or completed.
3422 saved_modes = ahd_save_modes(ahd);
3423 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
3424 if ((ahd_inb(ahd, SCSISIGI) & BSYI) != 0
3425 && (ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) == 0)
3426 ahd_outb(ahd, SCSISEQ0, ahd_inb(ahd, SCSISEQ0) & ~ENSELO);
3427 saved_scbptr = ahd_get_scbptr(ahd);
3428 /* Ensure that the hscbs down on the card match the new information */
3429 LIST_FOREACH(pending_scb, &ahd->pending_scbs, pending_links) {
3433 scb_tag = SCB_GET_TAG(pending_scb);
3434 ahd_set_scbptr(ahd, scb_tag);
3435 control = ahd_inb_scbram(ahd, SCB_CONTROL);
3436 control &= ~MK_MESSAGE;
3437 control |= pending_scb->hscb->control & MK_MESSAGE;
3438 ahd_outb(ahd, SCB_CONTROL, control);
3440 ahd_set_scbptr(ahd, saved_scbptr);
3441 ahd_restore_modes(ahd, saved_modes);
3447 /**************************** Pathing Information *****************************/
3449 ahd_fetch_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
3451 ahd_mode_state saved_modes;
3456 saved_modes = ahd_save_modes(ahd);
3457 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
3459 if (ahd_inb(ahd, SSTAT0) & TARGET)
3462 role = ROLE_INITIATOR;
3464 if (role == ROLE_TARGET
3465 && (ahd_inb(ahd, SEQ_FLAGS) & CMDPHASE_PENDING) != 0) {
3466 /* We were selected, so pull our id from TARGIDIN */
3467 our_id = ahd_inb(ahd, TARGIDIN) & OID;
3468 } else if (role == ROLE_TARGET)
3469 our_id = ahd_inb(ahd, TOWNID);
3471 our_id = ahd_inb(ahd, IOWNID);
3473 saved_scsiid = ahd_inb(ahd, SAVED_SCSIID);
3474 ahd_compile_devinfo(devinfo,
3476 SCSIID_TARGET(ahd, saved_scsiid),
3477 ahd_inb(ahd, SAVED_LUN),
3478 SCSIID_CHANNEL(ahd, saved_scsiid),
3480 ahd_restore_modes(ahd, saved_modes);
3484 ahd_print_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
3486 printf("%s:%c:%d:%d: ", ahd_name(ahd), 'A',
3487 devinfo->target, devinfo->lun);
3490 struct ahd_phase_table_entry*
3491 ahd_lookup_phase_entry(int phase)
3493 struct ahd_phase_table_entry *entry;
3494 struct ahd_phase_table_entry *last_entry;
3497 * num_phases doesn't include the default entry which
3498 * will be returned if the phase doesn't match.
3500 last_entry = &ahd_phase_table[num_phases];
3501 for (entry = ahd_phase_table; entry < last_entry; entry++) {
3502 if (phase == entry->phase)
3509 ahd_compile_devinfo(struct ahd_devinfo *devinfo, u_int our_id, u_int target,
3510 u_int lun, char channel, role_t role)
3512 devinfo->our_scsiid = our_id;
3513 devinfo->target = target;
3515 devinfo->target_offset = target;
3516 devinfo->channel = channel;
3517 devinfo->role = role;
3519 devinfo->target_offset += 8;
3520 devinfo->target_mask = (0x01 << devinfo->target_offset);
3524 ahd_scb_devinfo(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3530 our_id = SCSIID_OUR_ID(scb->hscb->scsiid);
3531 role = ROLE_INITIATOR;
3532 if ((scb->hscb->control & TARGET_SCB) != 0)
3534 ahd_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahd, scb),
3535 SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahd, scb), role);
3539 /************************ Message Phase Processing ****************************/
3541 * When an initiator transaction with the MK_MESSAGE flag either reconnects
3542 * or enters the initial message out phase, we are interrupted. Fill our
3543 * outgoing message buffer with the appropriate message and beging handing
3544 * the message phase(s) manually.
3547 ahd_setup_initiator_msgout(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3551 * To facilitate adding multiple messages together,
3552 * each routine should increment the index and len
3553 * variables instead of setting them explicitly.
3555 ahd->msgout_index = 0;
3556 ahd->msgout_len = 0;
3558 if (ahd_currently_packetized(ahd))
3559 ahd->msg_flags |= MSG_FLAG_PACKETIZED;
3561 if (ahd->send_msg_perror
3562 && ahd_inb(ahd, MSG_OUT) == HOST_MSG) {
3563 ahd->msgout_buf[ahd->msgout_index++] = ahd->send_msg_perror;
3565 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
3567 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
3568 printf("Setting up for Parity Error delivery\n");
3571 } else if (scb == NULL) {
3572 printf("%s: WARNING. No pending message for "
3573 "I_T msgin. Issuing NO-OP\n", ahd_name(ahd));
3574 ahd->msgout_buf[ahd->msgout_index++] = MSG_NOOP;
3576 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
3580 if ((scb->flags & SCB_DEVICE_RESET) == 0
3581 && (scb->flags & SCB_PACKETIZED) == 0
3582 && ahd_inb(ahd, MSG_OUT) == MSG_IDENTIFYFLAG) {
3585 identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb);
3586 if ((scb->hscb->control & DISCENB) != 0)
3587 identify_msg |= MSG_IDENTIFY_DISCFLAG;
3588 ahd->msgout_buf[ahd->msgout_index++] = identify_msg;
3591 if ((scb->hscb->control & TAG_ENB) != 0) {
3592 ahd->msgout_buf[ahd->msgout_index++] =
3593 scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE);
3594 ahd->msgout_buf[ahd->msgout_index++] = SCB_GET_TAG(scb);
3595 ahd->msgout_len += 2;
3599 if (scb->flags & SCB_DEVICE_RESET) {
3600 ahd->msgout_buf[ahd->msgout_index++] = MSG_BUS_DEV_RESET;
3602 ahd_print_path(ahd, scb);
3603 printf("Bus Device Reset Message Sent\n");
3605 * Clear our selection hardware in advance of
3606 * the busfree. We may have an entry in the waiting
3607 * Q for this target, and we don't want to go about
3608 * selecting while we handle the busfree and blow it
3611 ahd_outb(ahd, SCSISEQ0, 0);
3612 } else if ((scb->flags & SCB_ABORT) != 0) {
3614 if ((scb->hscb->control & TAG_ENB) != 0) {
3615 ahd->msgout_buf[ahd->msgout_index++] = MSG_ABORT_TAG;
3617 ahd->msgout_buf[ahd->msgout_index++] = MSG_ABORT;
3620 ahd_print_path(ahd, scb);
3621 printf("Abort%s Message Sent\n",
3622 (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : "");
3624 * Clear our selection hardware in advance of
3625 * the busfree. We may have an entry in the waiting
3626 * Q for this target, and we don't want to go about
3627 * selecting while we handle the busfree and blow it
3630 ahd_outb(ahd, SCSISEQ0, 0);
3631 } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) {
3632 ahd_build_transfer_msg(ahd, devinfo);
3634 * Clear our selection hardware in advance of potential
3635 * PPR IU status change busfree. We may have an entry in
3636 * the waiting Q for this target, and we don't want to go
3637 * about selecting while we handle the busfree and blow
3640 ahd_outb(ahd, SCSISEQ0, 0);
3642 printf("ahd_intr: AWAITING_MSG for an SCB that "
3643 "does not have a waiting message\n");
3644 printf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid,
3645 devinfo->target_mask);
3646 panic("SCB = %d, SCB Control = %x:%x, MSG_OUT = %x "
3647 "SCB flags = %x", SCB_GET_TAG(scb), scb->hscb->control,
3648 ahd_inb_scbram(ahd, SCB_CONTROL), ahd_inb(ahd, MSG_OUT),
3653 * Clear the MK_MESSAGE flag from the SCB so we aren't
3654 * asked to send this message again.
3656 ahd_outb(ahd, SCB_CONTROL,
3657 ahd_inb_scbram(ahd, SCB_CONTROL) & ~MK_MESSAGE);
3658 scb->hscb->control &= ~MK_MESSAGE;
3659 ahd->msgout_index = 0;
3660 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
3664 * Build an appropriate transfer negotiation message for the
3665 * currently active target.
3668 ahd_build_transfer_msg(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
3671 * We need to initiate transfer negotiations.
3672 * If our current and goal settings are identical,
3673 * we want to renegotiate due to a check condition.
3675 struct ahd_initiator_tinfo *tinfo;
3676 struct ahd_tmode_tstate *tstate;
3684 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid,
3685 devinfo->target, &tstate);
3687 * Filter our period based on the current connection.
3688 * If we can't perform DT transfers on this segment (not in LVD
3689 * mode for instance), then our decision to issue a PPR message
3692 period = tinfo->goal.period;
3693 offset = tinfo->goal.offset;
3694 ppr_options = tinfo->goal.ppr_options;
3695 /* Target initiated PPR is not allowed in the SCSI spec */
3696 if (devinfo->role == ROLE_TARGET)
3698 ahd_devlimited_syncrate(ahd, tinfo, &period,
3699 &ppr_options, devinfo->role);
3700 dowide = tinfo->curr.width != tinfo->goal.width;
3701 dosync = tinfo->curr.offset != offset || tinfo->curr.period != period;
3703 * Only use PPR if we have options that need it, even if the device
3704 * claims to support it. There might be an expander in the way
3707 doppr = ppr_options != 0;
3709 if (!dowide && !dosync && !doppr) {
3710 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT;
3711 dosync = tinfo->goal.offset != 0;
3714 if (!dowide && !dosync && !doppr) {
3716 * Force async with a WDTR message if we have a wide bus,
3717 * or just issue an SDTR with a 0 offset.
3719 if ((ahd->features & AHD_WIDE) != 0)
3725 ahd_print_devinfo(ahd, devinfo);
3726 printf("Ensuring async\n");
3729 /* Target initiated PPR is not allowed in the SCSI spec */
3730 if (devinfo->role == ROLE_TARGET)
3734 * Both the PPR message and SDTR message require the
3735 * goal syncrate to be limited to what the target device
3736 * is capable of handling (based on whether an LVD->SE
3737 * expander is on the bus), so combine these two cases.
3738 * Regardless, guarantee that if we are using WDTR and SDTR
3739 * messages that WDTR comes first.
3741 if (doppr || (dosync && !dowide)) {
3743 offset = tinfo->goal.offset;
3744 ahd_validate_offset(ahd, tinfo, period, &offset,
3745 doppr ? tinfo->goal.width
3746 : tinfo->curr.width,
3749 ahd_construct_ppr(ahd, devinfo, period, offset,
3750 tinfo->goal.width, ppr_options);
3752 ahd_construct_sdtr(ahd, devinfo, period, offset);
3755 ahd_construct_wdtr(ahd, devinfo, tinfo->goal.width);
3760 * Build a synchronous negotiation message in our message
3761 * buffer based on the input parameters.
3764 ahd_construct_sdtr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3765 u_int period, u_int offset)
3768 period = AHD_ASYNC_XFER_PERIOD;
3769 ahd->msgout_index += spi_populate_sync_msg(
3770 ahd->msgout_buf + ahd->msgout_index, period, offset);
3771 ahd->msgout_len += 5;
3773 printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n",
3774 ahd_name(ahd), devinfo->channel, devinfo->target,
3775 devinfo->lun, period, offset);
3780 * Build a wide negotiateion message in our message
3781 * buffer based on the input parameters.
3784 ahd_construct_wdtr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3787 ahd->msgout_index += spi_populate_width_msg(
3788 ahd->msgout_buf + ahd->msgout_index, bus_width);
3789 ahd->msgout_len += 4;
3791 printf("(%s:%c:%d:%d): Sending WDTR %x\n",
3792 ahd_name(ahd), devinfo->channel, devinfo->target,
3793 devinfo->lun, bus_width);
3798 * Build a parallel protocol request message in our message
3799 * buffer based on the input parameters.
3802 ahd_construct_ppr(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
3803 u_int period, u_int offset, u_int bus_width,
3807 * Always request precompensation from
3808 * the other target if we are running
3809 * at paced syncrates.
3811 if (period <= AHD_SYNCRATE_PACED)
3812 ppr_options |= MSG_EXT_PPR_PCOMP_EN;
3814 period = AHD_ASYNC_XFER_PERIOD;
3815 ahd->msgout_index += spi_populate_ppr_msg(
3816 ahd->msgout_buf + ahd->msgout_index, period, offset,
3817 bus_width, ppr_options);
3818 ahd->msgout_len += 8;
3820 printf("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, "
3821 "offset %x, ppr_options %x\n", ahd_name(ahd),
3822 devinfo->channel, devinfo->target, devinfo->lun,
3823 bus_width, period, offset, ppr_options);
3828 * Clear any active message state.
3831 ahd_clear_msg_state(struct ahd_softc *ahd)
3833 ahd_mode_state saved_modes;
3835 saved_modes = ahd_save_modes(ahd);
3836 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
3837 ahd->send_msg_perror = 0;
3838 ahd->msg_flags = MSG_FLAG_NONE;
3839 ahd->msgout_len = 0;
3840 ahd->msgin_index = 0;
3841 ahd->msg_type = MSG_TYPE_NONE;
3842 if ((ahd_inb(ahd, SCSISIGO) & ATNO) != 0) {
3844 * The target didn't care to respond to our
3845 * message request, so clear ATN.
3847 ahd_outb(ahd, CLRSINT1, CLRATNO);
3849 ahd_outb(ahd, MSG_OUT, MSG_NOOP);
3850 ahd_outb(ahd, SEQ_FLAGS2,
3851 ahd_inb(ahd, SEQ_FLAGS2) & ~TARGET_MSG_PENDING);
3852 ahd_restore_modes(ahd, saved_modes);
3856 * Manual message loop handler.
3859 ahd_handle_message_phase(struct ahd_softc *ahd)
3861 struct ahd_devinfo devinfo;
3865 ahd_fetch_devinfo(ahd, &devinfo);
3866 end_session = FALSE;
3867 bus_phase = ahd_inb(ahd, LASTPHASE);
3869 if ((ahd_inb(ahd, LQISTAT2) & LQIPHASE_OUTPKT) != 0) {
3870 printf("LQIRETRY for LQIPHASE_OUTPKT\n");
3871 ahd_outb(ahd, LQCTL2, LQIRETRY);
3874 switch (ahd->msg_type) {
3875 case MSG_TYPE_INITIATOR_MSGOUT:
3881 if (ahd->msgout_len == 0 && ahd->send_msg_perror == 0)
3882 panic("HOST_MSG_LOOP interrupt with no active message");
3885 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
3886 ahd_print_devinfo(ahd, &devinfo);
3887 printf("INITIATOR_MSG_OUT");
3890 phasemis = bus_phase != P_MESGOUT;
3893 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
3894 printf(" PHASEMIS %s\n",
3895 ahd_lookup_phase_entry(bus_phase)
3899 if (bus_phase == P_MESGIN) {
3901 * Change gears and see if
3902 * this messages is of interest to
3903 * us or should be passed back to
3906 ahd_outb(ahd, CLRSINT1, CLRATNO);
3907 ahd->send_msg_perror = 0;
3908 ahd->msg_type = MSG_TYPE_INITIATOR_MSGIN;
3909 ahd->msgin_index = 0;
3916 if (ahd->send_msg_perror) {
3917 ahd_outb(ahd, CLRSINT1, CLRATNO);
3918 ahd_outb(ahd, CLRSINT1, CLRREQINIT);
3920 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
3921 printf(" byte 0x%x\n", ahd->send_msg_perror);
3924 * If we are notifying the target of a CRC error
3925 * during packetized operations, the target is
3926 * within its rights to acknowledge our message
3929 if ((ahd->msg_flags & MSG_FLAG_PACKETIZED) != 0
3930 && ahd->send_msg_perror == MSG_INITIATOR_DET_ERR)
3931 ahd->msg_flags |= MSG_FLAG_EXPECT_IDE_BUSFREE;
3933 ahd_outb(ahd, RETURN_2, ahd->send_msg_perror);
3934 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_WRITE);
3938 msgdone = ahd->msgout_index == ahd->msgout_len;
3941 * The target has requested a retry.
3942 * Re-assert ATN, reset our message index to
3945 ahd->msgout_index = 0;
3946 ahd_assert_atn(ahd);
3949 lastbyte = ahd->msgout_index == (ahd->msgout_len - 1);
3951 /* Last byte is signified by dropping ATN */
3952 ahd_outb(ahd, CLRSINT1, CLRATNO);
3956 * Clear our interrupt status and present
3957 * the next byte on the bus.
3959 ahd_outb(ahd, CLRSINT1, CLRREQINIT);
3961 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
3962 printf(" byte 0x%x\n",
3963 ahd->msgout_buf[ahd->msgout_index]);
3965 ahd_outb(ahd, RETURN_2, ahd->msgout_buf[ahd->msgout_index++]);
3966 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_WRITE);
3969 case MSG_TYPE_INITIATOR_MSGIN:
3975 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
3976 ahd_print_devinfo(ahd, &devinfo);
3977 printf("INITIATOR_MSG_IN");
3980 phasemis = bus_phase != P_MESGIN;
3983 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
3984 printf(" PHASEMIS %s\n",
3985 ahd_lookup_phase_entry(bus_phase)
3989 ahd->msgin_index = 0;
3990 if (bus_phase == P_MESGOUT
3991 && (ahd->send_msg_perror != 0
3992 || (ahd->msgout_len != 0
3993 && ahd->msgout_index == 0))) {
3994 ahd->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
4001 /* Pull the byte in without acking it */
4002 ahd->msgin_buf[ahd->msgin_index] = ahd_inb(ahd, SCSIBUS);
4004 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
4005 printf(" byte 0x%x\n",
4006 ahd->msgin_buf[ahd->msgin_index]);
4009 message_done = ahd_parse_msg(ahd, &devinfo);
4013 * Clear our incoming message buffer in case there
4014 * is another message following this one.
4016 ahd->msgin_index = 0;
4019 * If this message illicited a response,
4020 * assert ATN so the target takes us to the
4021 * message out phase.
4023 if (ahd->msgout_len != 0) {
4025 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0) {
4026 ahd_print_devinfo(ahd, &devinfo);
4027 printf("Asserting ATN for response\n");
4030 ahd_assert_atn(ahd);
4035 if (message_done == MSGLOOP_TERMINATED) {
4039 ahd_outb(ahd, CLRSINT1, CLRREQINIT);
4040 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_READ);
4044 case MSG_TYPE_TARGET_MSGIN:
4050 * By default, the message loop will continue.
4052 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_TARG);
4054 if (ahd->msgout_len == 0)
4055 panic("Target MSGIN with no active message");
4058 * If we interrupted a mesgout session, the initiator
4059 * will not know this until our first REQ. So, we
4060 * only honor mesgout requests after we've sent our
4063 if ((ahd_inb(ahd, SCSISIGI) & ATNI) != 0
4064 && ahd->msgout_index > 0)
4065 msgout_request = TRUE;
4067 msgout_request = FALSE;
4069 if (msgout_request) {
4072 * Change gears and see if
4073 * this messages is of interest to
4074 * us or should be passed back to
4077 ahd->msg_type = MSG_TYPE_TARGET_MSGOUT;
4078 ahd_outb(ahd, SCSISIGO, P_MESGOUT | BSYO);
4079 ahd->msgin_index = 0;
4080 /* Dummy read to REQ for first byte */
4081 ahd_inb(ahd, SCSIDAT);
4082 ahd_outb(ahd, SXFRCTL0,
4083 ahd_inb(ahd, SXFRCTL0) | SPIOEN);
4087 msgdone = ahd->msgout_index == ahd->msgout_len;
4089 ahd_outb(ahd, SXFRCTL0,
4090 ahd_inb(ahd, SXFRCTL0) & ~SPIOEN);
4096 * Present the next byte on the bus.
4098 ahd_outb(ahd, SXFRCTL0, ahd_inb(ahd, SXFRCTL0) | SPIOEN);
4099 ahd_outb(ahd, SCSIDAT, ahd->msgout_buf[ahd->msgout_index++]);
4102 case MSG_TYPE_TARGET_MSGOUT:
4108 * By default, the message loop will continue.
4110 ahd_outb(ahd, RETURN_1, CONT_MSG_LOOP_TARG);
4113 * The initiator signals that this is
4114 * the last byte by dropping ATN.
4116 lastbyte = (ahd_inb(ahd, SCSISIGI) & ATNI) == 0;
4119 * Read the latched byte, but turn off SPIOEN first
4120 * so that we don't inadvertently cause a REQ for the
4123 ahd_outb(ahd, SXFRCTL0, ahd_inb(ahd, SXFRCTL0) & ~SPIOEN);
4124 ahd->msgin_buf[ahd->msgin_index] = ahd_inb(ahd, SCSIDAT);
4125 msgdone = ahd_parse_msg(ahd, &devinfo);
4126 if (msgdone == MSGLOOP_TERMINATED) {
4128 * The message is *really* done in that it caused
4129 * us to go to bus free. The sequencer has already
4130 * been reset at this point, so pull the ejection
4139 * XXX Read spec about initiator dropping ATN too soon
4140 * and use msgdone to detect it.
4142 if (msgdone == MSGLOOP_MSGCOMPLETE) {
4143 ahd->msgin_index = 0;
4146 * If this message illicited a response, transition
4147 * to the Message in phase and send it.
4149 if (ahd->msgout_len != 0) {
4150 ahd_outb(ahd, SCSISIGO, P_MESGIN | BSYO);
4151 ahd_outb(ahd, SXFRCTL0,
4152 ahd_inb(ahd, SXFRCTL0) | SPIOEN);
4153 ahd->msg_type = MSG_TYPE_TARGET_MSGIN;
4154 ahd->msgin_index = 0;
4162 /* Ask for the next byte. */
4163 ahd_outb(ahd, SXFRCTL0,
4164 ahd_inb(ahd, SXFRCTL0) | SPIOEN);
4170 panic("Unknown REQINIT message type");
4174 if ((ahd->msg_flags & MSG_FLAG_PACKETIZED) != 0) {
4175 printf("%s: Returning to Idle Loop\n",
4177 ahd_clear_msg_state(ahd);
4180 * Perform the equivalent of a clear_target_state.
4182 ahd_outb(ahd, LASTPHASE, P_BUSFREE);
4183 ahd_outb(ahd, SEQ_FLAGS, NOT_IDENTIFIED|NO_CDB_SENT);
4184 ahd_outb(ahd, SEQCTL0, FASTMODE|SEQRESET);
4186 ahd_clear_msg_state(ahd);
4187 ahd_outb(ahd, RETURN_1, EXIT_MSG_LOOP);
4193 * See if we sent a particular extended message to the target.
4194 * If "full" is true, return true only if the target saw the full
4195 * message. If "full" is false, return true if the target saw at
4196 * least the first byte of the message.
4199 ahd_sent_msg(struct ahd_softc *ahd, ahd_msgtype type, u_int msgval, int full)
4207 while (index < ahd->msgout_len) {
4208 if (ahd->msgout_buf[index] == MSG_EXTENDED) {
4211 end_index = index + 1 + ahd->msgout_buf[index + 1];
4212 if (ahd->msgout_buf[index+2] == msgval
4213 && type == AHDMSG_EXT) {
4216 if (ahd->msgout_index > end_index)
4218 } else if (ahd->msgout_index > index)
4222 } else if (ahd->msgout_buf[index] >= MSG_SIMPLE_TASK
4223 && ahd->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) {
4225 /* Skip tag type and tag id or residue param*/
4228 /* Single byte message */
4229 if (type == AHDMSG_1B
4230 && ahd->msgout_index > index
4231 && (ahd->msgout_buf[index] == msgval
4232 || ((ahd->msgout_buf[index] & MSG_IDENTIFYFLAG) != 0
4233 && msgval == MSG_IDENTIFYFLAG)))
4245 * Wait for a complete incoming message, parse it, and respond accordingly.
4248 ahd_parse_msg(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
4250 struct ahd_initiator_tinfo *tinfo;
4251 struct ahd_tmode_tstate *tstate;
4256 done = MSGLOOP_IN_PROG;
4259 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel, devinfo->our_scsiid,
4260 devinfo->target, &tstate);
4263 * Parse as much of the message as is available,
4264 * rejecting it if we don't support it. When
4265 * the entire message is available and has been
4266 * handled, return MSGLOOP_MSGCOMPLETE, indicating
4267 * that we have parsed an entire message.
4269 * In the case of extended messages, we accept the length
4270 * byte outright and perform more checking once we know the
4271 * extended message type.
4273 switch (ahd->msgin_buf[0]) {
4274 case MSG_DISCONNECT:
4275 case MSG_SAVEDATAPOINTER:
4276 case MSG_CMDCOMPLETE:
4277 case MSG_RESTOREPOINTERS:
4278 case MSG_IGN_WIDE_RESIDUE:
4280 * End our message loop as these are messages
4281 * the sequencer handles on its own.
4283 done = MSGLOOP_TERMINATED;
4285 case MSG_MESSAGE_REJECT:
4286 response = ahd_handle_msg_reject(ahd, devinfo);
4289 done = MSGLOOP_MSGCOMPLETE;
4293 /* Wait for enough of the message to begin validation */
4294 if (ahd->msgin_index < 2)
4296 switch (ahd->msgin_buf[2]) {
4304 if (ahd->msgin_buf[1] != MSG_EXT_SDTR_LEN) {
4310 * Wait until we have both args before validating
4311 * and acting on this message.
4313 * Add one to MSG_EXT_SDTR_LEN to account for
4314 * the extended message preamble.
4316 if (ahd->msgin_index < (MSG_EXT_SDTR_LEN + 1))
4319 period = ahd->msgin_buf[3];
4321 saved_offset = offset = ahd->msgin_buf[4];
4322 ahd_devlimited_syncrate(ahd, tinfo, &period,
4323 &ppr_options, devinfo->role);
4324 ahd_validate_offset(ahd, tinfo, period, &offset,
4325 tinfo->curr.width, devinfo->role);
4327 printf("(%s:%c:%d:%d): Received "
4328 "SDTR period %x, offset %x\n\t"
4329 "Filtered to period %x, offset %x\n",
4330 ahd_name(ahd), devinfo->channel,
4331 devinfo->target, devinfo->lun,
4332 ahd->msgin_buf[3], saved_offset,
4335 ahd_set_syncrate(ahd, devinfo, period,
4336 offset, ppr_options,
4337 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
4341 * See if we initiated Sync Negotiation
4342 * and didn't have to fall down to async
4345 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, TRUE)) {
4347 if (saved_offset != offset) {
4348 /* Went too low - force async */
4353 * Send our own SDTR in reply
4356 && devinfo->role == ROLE_INITIATOR) {
4357 printf("(%s:%c:%d:%d): Target "
4359 ahd_name(ahd), devinfo->channel,
4360 devinfo->target, devinfo->lun);
4362 ahd->msgout_index = 0;
4363 ahd->msgout_len = 0;
4364 ahd_construct_sdtr(ahd, devinfo,
4366 ahd->msgout_index = 0;
4369 done = MSGLOOP_MSGCOMPLETE;
4376 u_int sending_reply;
4378 sending_reply = FALSE;
4379 if (ahd->msgin_buf[1] != MSG_EXT_WDTR_LEN) {
4385 * Wait until we have our arg before validating
4386 * and acting on this message.
4388 * Add one to MSG_EXT_WDTR_LEN to account for
4389 * the extended message preamble.
4391 if (ahd->msgin_index < (MSG_EXT_WDTR_LEN + 1))
4394 bus_width = ahd->msgin_buf[3];
4395 saved_width = bus_width;
4396 ahd_validate_width(ahd, tinfo, &bus_width,
4399 printf("(%s:%c:%d:%d): Received WDTR "
4400 "%x filtered to %x\n",
4401 ahd_name(ahd), devinfo->channel,
4402 devinfo->target, devinfo->lun,
4403 saved_width, bus_width);
4406 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, TRUE)) {
4408 * Don't send a WDTR back to the
4409 * target, since we asked first.
4410 * If the width went higher than our
4411 * request, reject it.
4413 if (saved_width > bus_width) {
4415 printf("(%s:%c:%d:%d): requested %dBit "
4416 "transfers. Rejecting...\n",
4417 ahd_name(ahd), devinfo->channel,
4418 devinfo->target, devinfo->lun,
4419 8 * (0x01 << bus_width));
4424 * Send our own WDTR in reply
4427 && devinfo->role == ROLE_INITIATOR) {
4428 printf("(%s:%c:%d:%d): Target "
4430 ahd_name(ahd), devinfo->channel,
4431 devinfo->target, devinfo->lun);
4433 ahd->msgout_index = 0;
4434 ahd->msgout_len = 0;
4435 ahd_construct_wdtr(ahd, devinfo, bus_width);
4436 ahd->msgout_index = 0;
4438 sending_reply = TRUE;
4441 * After a wide message, we are async, but
4442 * some devices don't seem to honor this portion
4443 * of the spec. Force a renegotiation of the
4444 * sync component of our transfer agreement even
4445 * if our goal is async. By updating our width
4446 * after forcing the negotiation, we avoid
4447 * renegotiating for width.
4449 ahd_update_neg_request(ahd, devinfo, tstate,
4450 tinfo, AHD_NEG_ALWAYS);
4451 ahd_set_width(ahd, devinfo, bus_width,
4452 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
4454 if (sending_reply == FALSE && reject == FALSE) {
4457 * We will always have an SDTR to send.
4459 ahd->msgout_index = 0;
4460 ahd->msgout_len = 0;
4461 ahd_build_transfer_msg(ahd, devinfo);
4462 ahd->msgout_index = 0;
4465 done = MSGLOOP_MSGCOMPLETE;
4476 u_int saved_ppr_options;
4478 if (ahd->msgin_buf[1] != MSG_EXT_PPR_LEN) {
4484 * Wait until we have all args before validating
4485 * and acting on this message.
4487 * Add one to MSG_EXT_PPR_LEN to account for
4488 * the extended message preamble.
4490 if (ahd->msgin_index < (MSG_EXT_PPR_LEN + 1))
4493 period = ahd->msgin_buf[3];
4494 offset = ahd->msgin_buf[5];
4495 bus_width = ahd->msgin_buf[6];
4496 saved_width = bus_width;
4497 ppr_options = ahd->msgin_buf[7];
4499 * According to the spec, a DT only
4500 * period factor with no DT option
4501 * set implies async.
4503 if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0
4506 saved_ppr_options = ppr_options;
4507 saved_offset = offset;
4510 * Transfer options are only available if we
4511 * are negotiating wide.
4514 ppr_options &= MSG_EXT_PPR_QAS_REQ;
4516 ahd_validate_width(ahd, tinfo, &bus_width,
4518 ahd_devlimited_syncrate(ahd, tinfo, &period,
4519 &ppr_options, devinfo->role);
4520 ahd_validate_offset(ahd, tinfo, period, &offset,
4521 bus_width, devinfo->role);
4523 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, TRUE)) {
4525 * If we are unable to do any of the
4526 * requested options (we went too low),
4527 * then we'll have to reject the message.
4529 if (saved_width > bus_width
4530 || saved_offset != offset
4531 || saved_ppr_options != ppr_options) {
4539 if (devinfo->role != ROLE_TARGET)
4540 printf("(%s:%c:%d:%d): Target "
4542 ahd_name(ahd), devinfo->channel,
4543 devinfo->target, devinfo->lun);
4545 printf("(%s:%c:%d:%d): Initiator "
4547 ahd_name(ahd), devinfo->channel,
4548 devinfo->target, devinfo->lun);
4549 ahd->msgout_index = 0;
4550 ahd->msgout_len = 0;
4551 ahd_construct_ppr(ahd, devinfo, period, offset,
4552 bus_width, ppr_options);
4553 ahd->msgout_index = 0;
4557 printf("(%s:%c:%d:%d): Received PPR width %x, "
4558 "period %x, offset %x,options %x\n"
4559 "\tFiltered to width %x, period %x, "
4560 "offset %x, options %x\n",
4561 ahd_name(ahd), devinfo->channel,
4562 devinfo->target, devinfo->lun,
4563 saved_width, ahd->msgin_buf[3],
4564 saved_offset, saved_ppr_options,
4565 bus_width, period, offset, ppr_options);
4567 ahd_set_width(ahd, devinfo, bus_width,
4568 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
4570 ahd_set_syncrate(ahd, devinfo, period,
4571 offset, ppr_options,
4572 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
4575 done = MSGLOOP_MSGCOMPLETE;
4579 /* Unknown extended message. Reject it. */
4585 #ifdef AHD_TARGET_MODE
4586 case MSG_BUS_DEV_RESET:
4587 ahd_handle_devreset(ahd, devinfo, CAM_LUN_WILDCARD,
4589 "Bus Device Reset Received",
4590 /*verbose_level*/0);
4592 done = MSGLOOP_TERMINATED;
4596 case MSG_CLEAR_QUEUE:
4600 /* Target mode messages */
4601 if (devinfo->role != ROLE_TARGET) {
4605 tag = SCB_LIST_NULL;
4606 if (ahd->msgin_buf[0] == MSG_ABORT_TAG)
4607 tag = ahd_inb(ahd, INITIATOR_TAG);
4608 ahd_abort_scbs(ahd, devinfo->target, devinfo->channel,
4609 devinfo->lun, tag, ROLE_TARGET,
4612 tstate = ahd->enabled_targets[devinfo->our_scsiid];
4613 if (tstate != NULL) {
4614 struct ahd_tmode_lstate* lstate;
4616 lstate = tstate->enabled_luns[devinfo->lun];
4617 if (lstate != NULL) {
4618 ahd_queue_lstate_event(ahd, lstate,
4619 devinfo->our_scsiid,
4622 ahd_send_lstate_events(ahd, lstate);
4626 done = MSGLOOP_TERMINATED;
4630 case MSG_QAS_REQUEST:
4632 if ((ahd_debug & AHD_SHOW_MESSAGES) != 0)
4633 printf("%s: QAS request. SCSISIGI == 0x%x\n",
4634 ahd_name(ahd), ahd_inb(ahd, SCSISIGI));
4636 ahd->msg_flags |= MSG_FLAG_EXPECT_QASREJ_BUSFREE;
4638 case MSG_TERM_IO_PROC:
4646 * Setup to reject the message.
4648 ahd->msgout_index = 0;
4649 ahd->msgout_len = 1;
4650 ahd->msgout_buf[0] = MSG_MESSAGE_REJECT;
4651 done = MSGLOOP_MSGCOMPLETE;
4655 if (done != MSGLOOP_IN_PROG && !response)
4656 /* Clear the outgoing message buffer */
4657 ahd->msgout_len = 0;
4663 * Process a message reject message.
4666 ahd_handle_msg_reject(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
4669 * What we care about here is if we had an
4670 * outstanding SDTR or WDTR message for this
4671 * target. If we did, this is a signal that
4672 * the target is refusing negotiation.
4675 struct ahd_initiator_tinfo *tinfo;
4676 struct ahd_tmode_tstate *tstate;
4681 scb_index = ahd_get_scbptr(ahd);
4682 scb = ahd_lookup_scb(ahd, scb_index);
4683 tinfo = ahd_fetch_transinfo(ahd, devinfo->channel,
4684 devinfo->our_scsiid,
4685 devinfo->target, &tstate);
4686 /* Might be necessary */
4687 last_msg = ahd_inb(ahd, LAST_MSG);
4689 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) {
4690 if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_PPR, /*full*/TRUE)
4691 && tinfo->goal.period <= AHD_SYNCRATE_PACED) {
4693 * Target may not like our SPI-4 PPR Options.
4694 * Attempt to negotiate 80MHz which will turn
4695 * off these options.
4698 printf("(%s:%c:%d:%d): PPR Rejected. "
4699 "Trying simple U160 PPR\n",
4700 ahd_name(ahd), devinfo->channel,
4701 devinfo->target, devinfo->lun);
4703 tinfo->goal.period = AHD_SYNCRATE_DT;
4704 tinfo->goal.ppr_options &= MSG_EXT_PPR_IU_REQ
4705 | MSG_EXT_PPR_QAS_REQ
4706 | MSG_EXT_PPR_DT_REQ;
4709 * Target does not support the PPR message.
4710 * Attempt to negotiate SPI-2 style.
4713 printf("(%s:%c:%d:%d): PPR Rejected. "
4714 "Trying WDTR/SDTR\n",
4715 ahd_name(ahd), devinfo->channel,
4716 devinfo->target, devinfo->lun);
4718 tinfo->goal.ppr_options = 0;
4719 tinfo->curr.transport_version = 2;
4720 tinfo->goal.transport_version = 2;
4722 ahd->msgout_index = 0;
4723 ahd->msgout_len = 0;
4724 ahd_build_transfer_msg(ahd, devinfo);
4725 ahd->msgout_index = 0;
4727 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) {
4729 /* note 8bit xfers */
4730 printf("(%s:%c:%d:%d): refuses WIDE negotiation. Using "
4731 "8bit transfers\n", ahd_name(ahd),
4732 devinfo->channel, devinfo->target, devinfo->lun);
4733 ahd_set_width(ahd, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
4734 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
4737 * No need to clear the sync rate. If the target
4738 * did not accept the command, our syncrate is
4739 * unaffected. If the target started the negotiation,
4740 * but rejected our response, we already cleared the
4741 * sync rate before sending our WDTR.
4743 if (tinfo->goal.offset != tinfo->curr.offset) {
4745 /* Start the sync negotiation */
4746 ahd->msgout_index = 0;
4747 ahd->msgout_len = 0;
4748 ahd_build_transfer_msg(ahd, devinfo);
4749 ahd->msgout_index = 0;
4752 } else if (ahd_sent_msg(ahd, AHDMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) {
4753 /* note asynch xfers and clear flag */
4754 ahd_set_syncrate(ahd, devinfo, /*period*/0,
4755 /*offset*/0, /*ppr_options*/0,
4756 AHD_TRANS_ACTIVE|AHD_TRANS_GOAL,
4758 printf("(%s:%c:%d:%d): refuses synchronous negotiation. "
4759 "Using asynchronous transfers\n",
4760 ahd_name(ahd), devinfo->channel,
4761 devinfo->target, devinfo->lun);
4762 } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) {
4766 tag_type = (scb->hscb->control & MSG_SIMPLE_TASK);
4768 if (tag_type == MSG_SIMPLE_TASK) {
4769 printf("(%s:%c:%d:%d): refuses tagged commands. "
4770 "Performing non-tagged I/O\n", ahd_name(ahd),
4771 devinfo->channel, devinfo->target, devinfo->lun);
4772 ahd_set_tags(ahd, devinfo, AHD_QUEUE_NONE);
4775 printf("(%s:%c:%d:%d): refuses %s tagged commands. "
4776 "Performing simple queue tagged I/O only\n",
4777 ahd_name(ahd), devinfo->channel, devinfo->target,
4778 devinfo->lun, tag_type == MSG_ORDERED_TASK
4779 ? "ordered" : "head of queue");
4780 ahd_set_tags(ahd, devinfo, AHD_QUEUE_BASIC);
4785 * Resend the identify for this CCB as the target
4786 * may believe that the selection is invalid otherwise.
4788 ahd_outb(ahd, SCB_CONTROL,
4789 ahd_inb_scbram(ahd, SCB_CONTROL) & mask);
4790 scb->hscb->control &= mask;
4791 ahd_set_transaction_tag(scb, /*enabled*/FALSE,
4792 /*type*/MSG_SIMPLE_TASK);
4793 ahd_outb(ahd, MSG_OUT, MSG_IDENTIFYFLAG);
4794 ahd_assert_atn(ahd);
4795 ahd_busy_tcl(ahd, BUILD_TCL(scb->hscb->scsiid, devinfo->lun),
4799 * Requeue all tagged commands for this target
4800 * currently in our posession so they can be
4801 * converted to untagged commands.
4803 ahd_search_qinfifo(ahd, SCB_GET_TARGET(ahd, scb),
4804 SCB_GET_CHANNEL(ahd, scb),
4805 SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL,
4806 ROLE_INITIATOR, CAM_REQUEUE_REQ,
4808 } else if (ahd_sent_msg(ahd, AHDMSG_1B, MSG_IDENTIFYFLAG, TRUE)) {
4810 * Most likely the device believes that we had
4811 * previously negotiated packetized.
4813 ahd->msg_flags |= MSG_FLAG_EXPECT_PPR_BUSFREE
4814 | MSG_FLAG_IU_REQ_CHANGED;
4816 ahd_force_renegotiation(ahd, devinfo);
4817 ahd->msgout_index = 0;
4818 ahd->msgout_len = 0;
4819 ahd_build_transfer_msg(ahd, devinfo);
4820 ahd->msgout_index = 0;
4824 * Otherwise, we ignore it.
4826 printf("%s:%c:%d: Message reject for %x -- ignored\n",
4827 ahd_name(ahd), devinfo->channel, devinfo->target,
4834 * Process an ingnore wide residue message.
4837 ahd_handle_ign_wide_residue(struct ahd_softc *ahd, struct ahd_devinfo *devinfo)
4842 scb_index = ahd_get_scbptr(ahd);
4843 scb = ahd_lookup_scb(ahd, scb_index);
4845 * XXX Actually check data direction in the sequencer?
4846 * Perhaps add datadir to some spare bits in the hscb?
4848 if ((ahd_inb(ahd, SEQ_FLAGS) & DPHASE) == 0
4849 || ahd_get_transfer_dir(scb) != CAM_DIR_IN) {
4851 * Ignore the message if we haven't
4852 * seen an appropriate data phase yet.
4856 * If the residual occurred on the last
4857 * transfer and the transfer request was
4858 * expected to end on an odd count, do
4859 * nothing. Otherwise, subtract a byte
4860 * and update the residual count accordingly.
4864 sgptr = ahd_inb_scbram(ahd, SCB_RESIDUAL_SGPTR);
4865 if ((sgptr & SG_LIST_NULL) != 0
4866 && (ahd_inb_scbram(ahd, SCB_TASK_ATTRIBUTE)
4867 & SCB_XFERLEN_ODD) != 0) {
4869 * If the residual occurred on the last
4870 * transfer and the transfer request was
4871 * expected to end on an odd count, do
4879 /* Pull in the rest of the sgptr */
4880 sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR);
4881 data_cnt = ahd_inl_scbram(ahd, SCB_RESIDUAL_DATACNT);
4882 if ((sgptr & SG_LIST_NULL) != 0) {
4884 * The residual data count is not updated
4885 * for the command run to completion case.
4886 * Explicitly zero the count.
4888 data_cnt &= ~AHD_SG_LEN_MASK;
4890 data_addr = ahd_inq(ahd, SHADDR);
4893 sgptr &= SG_PTR_MASK;
4894 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
4895 struct ahd_dma64_seg *sg;
4897 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
4900 * The residual sg ptr points to the next S/G
4901 * to load so we must go back one.
4904 sglen = ahd_le32toh(sg->len) & AHD_SG_LEN_MASK;
4905 if (sg != scb->sg_list
4906 && sglen < (data_cnt & AHD_SG_LEN_MASK)) {
4909 sglen = ahd_le32toh(sg->len);
4911 * Preserve High Address and SG_LIST
4912 * bits while setting the count to 1.
4914 data_cnt = 1|(sglen&(~AHD_SG_LEN_MASK));
4915 data_addr = ahd_le64toh(sg->addr)
4916 + (sglen & AHD_SG_LEN_MASK)
4920 * Increment sg so it points to the
4924 sgptr = ahd_sg_virt_to_bus(ahd, scb,
4928 struct ahd_dma_seg *sg;
4930 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
4933 * The residual sg ptr points to the next S/G
4934 * to load so we must go back one.
4937 sglen = ahd_le32toh(sg->len) & AHD_SG_LEN_MASK;
4938 if (sg != scb->sg_list
4939 && sglen < (data_cnt & AHD_SG_LEN_MASK)) {
4942 sglen = ahd_le32toh(sg->len);
4944 * Preserve High Address and SG_LIST
4945 * bits while setting the count to 1.
4947 data_cnt = 1|(sglen&(~AHD_SG_LEN_MASK));
4948 data_addr = ahd_le32toh(sg->addr)
4949 + (sglen & AHD_SG_LEN_MASK)
4953 * Increment sg so it points to the
4957 sgptr = ahd_sg_virt_to_bus(ahd, scb,
4962 * Toggle the "oddness" of the transfer length
4963 * to handle this mid-transfer ignore wide
4964 * residue. This ensures that the oddness is
4965 * correct for subsequent data transfers.
4967 ahd_outb(ahd, SCB_TASK_ATTRIBUTE,
4968 ahd_inb_scbram(ahd, SCB_TASK_ATTRIBUTE)
4971 ahd_outl(ahd, SCB_RESIDUAL_SGPTR, sgptr);
4972 ahd_outl(ahd, SCB_RESIDUAL_DATACNT, data_cnt);
4974 * The FIFO's pointers will be updated if/when the
4975 * sequencer re-enters a data phase.
4983 * Reinitialize the data pointers for the active transfer
4984 * based on its current residual.
4987 ahd_reinitialize_dataptrs(struct ahd_softc *ahd)
4990 ahd_mode_state saved_modes;
4997 AHD_ASSERT_MODES(ahd, AHD_MODE_DFF0_MSK|AHD_MODE_DFF1_MSK,
4998 AHD_MODE_DFF0_MSK|AHD_MODE_DFF1_MSK);
5000 scb_index = ahd_get_scbptr(ahd);
5001 scb = ahd_lookup_scb(ahd, scb_index);
5004 * Release and reacquire the FIFO so we
5005 * have a clean slate.
5007 ahd_outb(ahd, DFFSXFRCTL, CLRCHN);
5009 while (--wait && !(ahd_inb(ahd, MDFFSTAT) & FIFOFREE))
5012 ahd_print_path(ahd, scb);
5013 printf("ahd_reinitialize_dataptrs: Forcing FIFO free.\n");
5014 ahd_outb(ahd, DFFSXFRCTL, RSTCHN|CLRSHCNT);
5016 saved_modes = ahd_save_modes(ahd);
5017 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
5018 ahd_outb(ahd, DFFSTAT,
5019 ahd_inb(ahd, DFFSTAT)
5020 | (saved_modes == 0x11 ? CURRFIFO_1 : CURRFIFO_0));
5023 * Determine initial values for data_addr and data_cnt
5024 * for resuming the data phase.
5026 sgptr = ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR);
5027 sgptr &= SG_PTR_MASK;
5029 resid = (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT + 2) << 16)
5030 | (ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT + 1) << 8)
5031 | ahd_inb_scbram(ahd, SCB_RESIDUAL_DATACNT);
5033 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0) {
5034 struct ahd_dma64_seg *sg;
5036 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
5038 /* The residual sg_ptr always points to the next sg */
5041 dataptr = ahd_le64toh(sg->addr)
5042 + (ahd_le32toh(sg->len) & AHD_SG_LEN_MASK)
5044 ahd_outl(ahd, HADDR + 4, dataptr >> 32);
5046 struct ahd_dma_seg *sg;
5048 sg = ahd_sg_bus_to_virt(ahd, scb, sgptr);
5050 /* The residual sg_ptr always points to the next sg */
5053 dataptr = ahd_le32toh(sg->addr)
5054 + (ahd_le32toh(sg->len) & AHD_SG_LEN_MASK)
5056 ahd_outb(ahd, HADDR + 4,
5057 (ahd_le32toh(sg->len) & ~AHD_SG_LEN_MASK) >> 24);
5059 ahd_outl(ahd, HADDR, dataptr);
5060 ahd_outb(ahd, HCNT + 2, resid >> 16);
5061 ahd_outb(ahd, HCNT + 1, resid >> 8);
5062 ahd_outb(ahd, HCNT, resid);
5066 * Handle the effects of issuing a bus device reset message.
5069 ahd_handle_devreset(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
5070 u_int lun, cam_status status, char *message,
5073 #ifdef AHD_TARGET_MODE
5074 struct ahd_tmode_tstate* tstate;
5078 found = ahd_abort_scbs(ahd, devinfo->target, devinfo->channel,
5079 lun, SCB_LIST_NULL, devinfo->role,
5082 #ifdef AHD_TARGET_MODE
5084 * Send an immediate notify ccb to all target mord peripheral
5085 * drivers affected by this action.
5087 tstate = ahd->enabled_targets[devinfo->our_scsiid];
5088 if (tstate != NULL) {
5092 if (lun != CAM_LUN_WILDCARD) {
5094 max_lun = AHD_NUM_LUNS - 1;
5099 for (cur_lun <= max_lun; cur_lun++) {
5100 struct ahd_tmode_lstate* lstate;
5102 lstate = tstate->enabled_luns[cur_lun];
5106 ahd_queue_lstate_event(ahd, lstate, devinfo->our_scsiid,
5107 MSG_BUS_DEV_RESET, /*arg*/0);
5108 ahd_send_lstate_events(ahd, lstate);
5114 * Go back to async/narrow transfers and renegotiate.
5116 ahd_set_width(ahd, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
5117 AHD_TRANS_CUR, /*paused*/TRUE);
5118 ahd_set_syncrate(ahd, devinfo, /*period*/0, /*offset*/0,
5119 /*ppr_options*/0, AHD_TRANS_CUR,
5122 if (status != CAM_SEL_TIMEOUT)
5123 ahd_send_async(ahd, devinfo->channel, devinfo->target,
5124 CAM_LUN_WILDCARD, AC_SENT_BDR, NULL);
5126 if (message != NULL && bootverbose)
5127 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahd_name(ahd),
5128 message, devinfo->channel, devinfo->target, found);
5131 #ifdef AHD_TARGET_MODE
5133 ahd_setup_target_msgin(struct ahd_softc *ahd, struct ahd_devinfo *devinfo,
5138 * To facilitate adding multiple messages together,
5139 * each routine should increment the index and len
5140 * variables instead of setting them explicitly.
5142 ahd->msgout_index = 0;
5143 ahd->msgout_len = 0;
5145 if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0)
5146 ahd_build_transfer_msg(ahd, devinfo);
5148 panic("ahd_intr: AWAITING target message with no message");
5150 ahd->msgout_index = 0;
5151 ahd->msg_type = MSG_TYPE_TARGET_MSGIN;
5154 /**************************** Initialization **********************************/
5156 ahd_sglist_size(struct ahd_softc *ahd)
5158 bus_size_t list_size;
5160 list_size = sizeof(struct ahd_dma_seg) * AHD_NSEG;
5161 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0)
5162 list_size = sizeof(struct ahd_dma64_seg) * AHD_NSEG;
5167 * Calculate the optimum S/G List allocation size. S/G elements used
5168 * for a given transaction must be physically contiguous. Assume the
5169 * OS will allocate full pages to us, so it doesn't make sense to request
5173 ahd_sglist_allocsize(struct ahd_softc *ahd)
5175 bus_size_t sg_list_increment;
5176 bus_size_t sg_list_size;
5177 bus_size_t max_list_size;
5178 bus_size_t best_list_size;
5180 /* Start out with the minimum required for AHD_NSEG. */
5181 sg_list_increment = ahd_sglist_size(ahd);
5182 sg_list_size = sg_list_increment;
5184 /* Get us as close as possible to a page in size. */
5185 while ((sg_list_size + sg_list_increment) <= PAGE_SIZE)
5186 sg_list_size += sg_list_increment;
5189 * Try to reduce the amount of wastage by allocating
5192 best_list_size = sg_list_size;
5193 max_list_size = roundup(sg_list_increment, PAGE_SIZE);
5194 if (max_list_size < 4 * PAGE_SIZE)
5195 max_list_size = 4 * PAGE_SIZE;
5196 if (max_list_size > (AHD_SCB_MAX_ALLOC * sg_list_increment))
5197 max_list_size = (AHD_SCB_MAX_ALLOC * sg_list_increment);
5198 while ((sg_list_size + sg_list_increment) <= max_list_size
5199 && (sg_list_size % PAGE_SIZE) != 0) {
5201 bus_size_t best_mod;
5203 sg_list_size += sg_list_increment;
5204 new_mod = sg_list_size % PAGE_SIZE;
5205 best_mod = best_list_size % PAGE_SIZE;
5206 if (new_mod > best_mod || new_mod == 0) {
5207 best_list_size = sg_list_size;
5210 return (best_list_size);
5214 * Allocate a controller structure for a new device
5215 * and perform initial initializion.
5218 ahd_alloc(void *platform_arg, char *name)
5220 struct ahd_softc *ahd;
5223 ahd = malloc(sizeof(*ahd), M_DEVBUF, M_NOWAIT);
5225 printf("aic7xxx: cannot malloc softc!\n");
5226 free(name, M_DEVBUF);
5230 ahd = device_get_softc((device_t)platform_arg);
5232 memset(ahd, 0, sizeof(*ahd));
5233 ahd->seep_config = malloc(sizeof(*ahd->seep_config),
5234 M_DEVBUF, M_NOWAIT);
5235 if (ahd->seep_config == NULL) {
5237 free(ahd, M_DEVBUF);
5239 free(name, M_DEVBUF);
5242 LIST_INIT(&ahd->pending_scbs);
5243 /* We don't know our unit number until the OSM sets it */
5246 ahd->description = NULL;
5247 ahd->bus_description = NULL;
5249 ahd->chip = AHD_NONE;
5250 ahd->features = AHD_FENONE;
5251 ahd->bugs = AHD_BUGNONE;
5252 ahd->flags = AHD_SPCHK_ENB_A|AHD_RESET_BUS_A|AHD_TERM_ENB_A
5253 | AHD_EXTENDED_TRANS_A|AHD_STPWLEVEL_A;
5254 ahd_timer_init(&ahd->reset_timer);
5255 ahd_timer_init(&ahd->stat_timer);
5256 ahd->int_coalescing_timer = AHD_INT_COALESCING_TIMER_DEFAULT;
5257 ahd->int_coalescing_maxcmds = AHD_INT_COALESCING_MAXCMDS_DEFAULT;
5258 ahd->int_coalescing_mincmds = AHD_INT_COALESCING_MINCMDS_DEFAULT;
5259 ahd->int_coalescing_threshold = AHD_INT_COALESCING_THRESHOLD_DEFAULT;
5260 ahd->int_coalescing_stop_threshold =
5261 AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT;
5263 if (ahd_platform_alloc(ahd, platform_arg) != 0) {
5268 if ((ahd_debug & AHD_SHOW_MEMORY) != 0) {
5269 printf("%s: scb size = 0x%x, hscb size = 0x%x\n",
5270 ahd_name(ahd), (u_int)sizeof(struct scb),
5271 (u_int)sizeof(struct hardware_scb));
5278 ahd_softc_init(struct ahd_softc *ahd)
5287 ahd_set_unit(struct ahd_softc *ahd, int unit)
5293 ahd_set_name(struct ahd_softc *ahd, char *name)
5295 if (ahd->name != NULL)
5296 free(ahd->name, M_DEVBUF);
5301 ahd_free(struct ahd_softc *ahd)
5305 switch (ahd->init_level) {
5311 ahd_dmamap_unload(ahd, ahd->shared_data_dmat,
5312 ahd->shared_data_map.dmamap);
5315 ahd_dmamem_free(ahd, ahd->shared_data_dmat, ahd->qoutfifo,
5316 ahd->shared_data_map.dmamap);
5317 ahd_dmamap_destroy(ahd, ahd->shared_data_dmat,
5318 ahd->shared_data_map.dmamap);
5321 ahd_dma_tag_destroy(ahd, ahd->shared_data_dmat);
5324 ahd_dma_tag_destroy(ahd, ahd->buffer_dmat);
5332 ahd_dma_tag_destroy(ahd, ahd->parent_dmat);
5334 ahd_platform_free(ahd);
5335 ahd_fini_scbdata(ahd);
5336 for (i = 0; i < AHD_NUM_TARGETS; i++) {
5337 struct ahd_tmode_tstate *tstate;
5339 tstate = ahd->enabled_targets[i];
5340 if (tstate != NULL) {
5341 #ifdef AHD_TARGET_MODE
5344 for (j = 0; j < AHD_NUM_LUNS; j++) {
5345 struct ahd_tmode_lstate *lstate;
5347 lstate = tstate->enabled_luns[j];
5348 if (lstate != NULL) {
5349 xpt_free_path(lstate->path);
5350 free(lstate, M_DEVBUF);
5354 free(tstate, M_DEVBUF);
5357 #ifdef AHD_TARGET_MODE
5358 if (ahd->black_hole != NULL) {
5359 xpt_free_path(ahd->black_hole->path);
5360 free(ahd->black_hole, M_DEVBUF);
5363 if (ahd->name != NULL)
5364 free(ahd->name, M_DEVBUF);
5365 if (ahd->seep_config != NULL)
5366 free(ahd->seep_config, M_DEVBUF);
5367 if (ahd->saved_stack != NULL)
5368 free(ahd->saved_stack, M_DEVBUF);
5370 free(ahd, M_DEVBUF);
5376 ahd_shutdown(void *arg)
5378 struct ahd_softc *ahd;
5380 ahd = (struct ahd_softc *)arg;
5383 * Stop periodic timer callbacks.
5385 ahd_timer_stop(&ahd->reset_timer);
5386 ahd_timer_stop(&ahd->stat_timer);
5388 /* This will reset most registers to 0, but not all */
5389 ahd_reset(ahd, /*reinit*/FALSE);
5393 * Reset the controller and record some information about it
5394 * that is only available just after a reset. If "reinit" is
5395 * non-zero, this reset occured after initial configuration
5396 * and the caller requests that the chip be fully reinitialized
5397 * to a runable state. Chip interrupts are *not* enabled after
5398 * a reinitialization. The caller must enable interrupts via
5399 * ahd_intr_enable().
5402 ahd_reset(struct ahd_softc *ahd, int reinit)
5409 * Preserve the value of the SXFRCTL1 register for all channels.
5410 * It contains settings that affect termination and we don't want
5411 * to disturb the integrity of the bus.
5414 ahd_update_modes(ahd);
5415 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
5416 sxfrctl1 = ahd_inb(ahd, SXFRCTL1);
5418 cmd = ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/2);
5419 if ((ahd->bugs & AHD_PCIX_CHIPRST_BUG) != 0) {
5424 * During the assertion of CHIPRST, the chip
5425 * does not disable its parity logic prior to
5426 * the start of the reset. This may cause a
5427 * parity error to be detected and thus a
5428 * spurious SERR or PERR assertion. Disble
5429 * PERR and SERR responses during the CHIPRST.
5431 mod_cmd = cmd & ~(PCIM_CMD_PERRESPEN|PCIM_CMD_SERRESPEN);
5432 ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND,
5433 mod_cmd, /*bytes*/2);
5435 ahd_outb(ahd, HCNTRL, CHIPRST | ahd->pause);
5438 * Ensure that the reset has finished. We delay 1000us
5439 * prior to reading the register to make sure the chip
5440 * has sufficiently completed its reset to handle register
5446 } while (--wait && !(ahd_inb(ahd, HCNTRL) & CHIPRSTACK));
5449 printf("%s: WARNING - Failed chip reset! "
5450 "Trying to initialize anyway.\n", ahd_name(ahd));
5452 ahd_outb(ahd, HCNTRL, ahd->pause);
5454 if ((ahd->bugs & AHD_PCIX_CHIPRST_BUG) != 0) {
5456 * Clear any latched PCI error status and restore
5457 * previous SERR and PERR response enables.
5459 ahd_pci_write_config(ahd->dev_softc, PCIR_STATUS + 1,
5461 ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND,
5466 * Mode should be SCSI after a chip reset, but lets
5467 * set it just to be safe. We touch the MODE_PTR
5468 * register directly so as to bypass the lazy update
5469 * code in ahd_set_modes().
5471 ahd_known_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
5472 ahd_outb(ahd, MODE_PTR,
5473 ahd_build_mode_state(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI));
5478 * We must always initialize STPWEN to 1 before we
5479 * restore the saved values. STPWEN is initialized
5480 * to a tri-state condition which can only be cleared
5483 ahd_outb(ahd, SXFRCTL1, sxfrctl1|STPWEN);
5484 ahd_outb(ahd, SXFRCTL1, sxfrctl1);
5486 /* Determine chip configuration */
5487 ahd->features &= ~AHD_WIDE;
5488 if ((ahd_inb(ahd, SBLKCTL) & SELWIDE) != 0)
5489 ahd->features |= AHD_WIDE;
5492 * If a recovery action has forced a chip reset,
5493 * re-initialize the chip to our liking.
5502 * Determine the number of SCBs available on the controller
5505 ahd_probe_scbs(struct ahd_softc *ahd) {
5508 AHD_ASSERT_MODES(ahd, ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK),
5509 ~(AHD_MODE_UNKNOWN_MSK|AHD_MODE_CFG_MSK));
5510 for (i = 0; i < AHD_SCB_MAX; i++) {
5513 ahd_set_scbptr(ahd, i);
5514 ahd_outw(ahd, SCB_BASE, i);
5515 for (j = 2; j < 64; j++)
5516 ahd_outb(ahd, SCB_BASE+j, 0);
5517 /* Start out life as unallocated (needing an abort) */
5518 ahd_outb(ahd, SCB_CONTROL, MK_MESSAGE);
5519 if (ahd_inw_scbram(ahd, SCB_BASE) != i)
5521 ahd_set_scbptr(ahd, 0);
5522 if (ahd_inw_scbram(ahd, SCB_BASE) != 0)
5529 ahd_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
5533 baddr = (dma_addr_t *)arg;
5534 *baddr = segs->ds_addr;
5538 ahd_initialize_hscbs(struct ahd_softc *ahd)
5542 for (i = 0; i < ahd->scb_data.maxhscbs; i++) {
5543 ahd_set_scbptr(ahd, i);
5545 /* Clear the control byte. */
5546 ahd_outb(ahd, SCB_CONTROL, 0);
5548 /* Set the next pointer */
5549 ahd_outw(ahd, SCB_NEXT, SCB_LIST_NULL);
5554 ahd_init_scbdata(struct ahd_softc *ahd)
5556 struct scb_data *scb_data;
5559 scb_data = &ahd->scb_data;
5560 TAILQ_INIT(&scb_data->free_scbs);
5561 for (i = 0; i < AHD_NUM_TARGETS * AHD_NUM_LUNS_NONPKT; i++)
5562 LIST_INIT(&scb_data->free_scb_lists[i]);
5563 LIST_INIT(&scb_data->any_dev_free_scb_list);
5564 SLIST_INIT(&scb_data->hscb_maps);
5565 SLIST_INIT(&scb_data->sg_maps);
5566 SLIST_INIT(&scb_data->sense_maps);
5568 /* Determine the number of hardware SCBs and initialize them */
5569 scb_data->maxhscbs = ahd_probe_scbs(ahd);
5570 if (scb_data->maxhscbs == 0) {
5571 printf("%s: No SCB space found\n", ahd_name(ahd));
5575 ahd_initialize_hscbs(ahd);
5578 * Create our DMA tags. These tags define the kinds of device
5579 * accessible memory allocations and memory mappings we will
5580 * need to perform during normal operation.
5582 * Unless we need to further restrict the allocation, we rely
5583 * on the restrictions of the parent dmat, hence the common
5584 * use of MAXADDR and MAXSIZE.
5587 /* DMA tag for our hardware scb structures */
5588 if (ahd_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1,
5589 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
5590 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
5591 /*highaddr*/BUS_SPACE_MAXADDR,
5592 /*filter*/NULL, /*filterarg*/NULL,
5593 PAGE_SIZE, /*nsegments*/1,
5594 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
5595 /*flags*/0, &scb_data->hscb_dmat) != 0) {
5599 scb_data->init_level++;
5601 /* DMA tag for our S/G structures. */
5602 if (ahd_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/8,
5603 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
5604 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
5605 /*highaddr*/BUS_SPACE_MAXADDR,
5606 /*filter*/NULL, /*filterarg*/NULL,
5607 ahd_sglist_allocsize(ahd), /*nsegments*/1,
5608 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
5609 /*flags*/0, &scb_data->sg_dmat) != 0) {
5613 if ((ahd_debug & AHD_SHOW_MEMORY) != 0)
5614 printf("%s: ahd_sglist_allocsize = 0x%x\n", ahd_name(ahd),
5615 ahd_sglist_allocsize(ahd));
5618 scb_data->init_level++;
5620 /* DMA tag for our sense buffers. We allocate in page sized chunks */
5621 if (ahd_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1,
5622 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
5623 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
5624 /*highaddr*/BUS_SPACE_MAXADDR,
5625 /*filter*/NULL, /*filterarg*/NULL,
5626 PAGE_SIZE, /*nsegments*/1,
5627 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
5628 /*flags*/0, &scb_data->sense_dmat) != 0) {
5632 scb_data->init_level++;
5634 /* Perform initial CCB allocation */
5635 ahd_alloc_scbs(ahd);
5637 if (scb_data->numscbs == 0) {
5638 printf("%s: ahd_init_scbdata - "
5639 "Unable to allocate initial scbs\n",
5645 * Note that we were successfull
5655 ahd_find_scb_by_tag(struct ahd_softc *ahd, u_int tag)
5660 * Look on the pending list.
5662 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) {
5663 if (SCB_GET_TAG(scb) == tag)
5668 * Then on all of the collision free lists.
5670 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) {
5671 struct scb *list_scb;
5675 if (SCB_GET_TAG(list_scb) == tag)
5677 list_scb = LIST_NEXT(list_scb, collision_links);
5682 * And finally on the generic free list.
5684 LIST_FOREACH(scb, &ahd->scb_data.any_dev_free_scb_list, links.le) {
5685 if (SCB_GET_TAG(scb) == tag)
5693 ahd_fini_scbdata(struct ahd_softc *ahd)
5695 struct scb_data *scb_data;
5697 scb_data = &ahd->scb_data;
5698 if (scb_data == NULL)
5701 switch (scb_data->init_level) {
5705 struct map_node *sns_map;
5707 while ((sns_map = SLIST_FIRST(&scb_data->sense_maps)) != NULL) {
5708 SLIST_REMOVE_HEAD(&scb_data->sense_maps, links);
5709 ahd_dmamap_unload(ahd, scb_data->sense_dmat,
5711 ahd_dmamem_free(ahd, scb_data->sense_dmat,
5712 sns_map->vaddr, sns_map->dmamap);
5713 free(sns_map, M_DEVBUF);
5715 ahd_dma_tag_destroy(ahd, scb_data->sense_dmat);
5720 struct map_node *sg_map;
5722 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps)) != NULL) {
5723 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links);
5724 ahd_dmamap_unload(ahd, scb_data->sg_dmat,
5726 ahd_dmamem_free(ahd, scb_data->sg_dmat,
5727 sg_map->vaddr, sg_map->dmamap);
5728 free(sg_map, M_DEVBUF);
5730 ahd_dma_tag_destroy(ahd, scb_data->sg_dmat);
5735 struct map_node *hscb_map;
5737 while ((hscb_map = SLIST_FIRST(&scb_data->hscb_maps)) != NULL) {
5738 SLIST_REMOVE_HEAD(&scb_data->hscb_maps, links);
5739 ahd_dmamap_unload(ahd, scb_data->hscb_dmat,
5741 ahd_dmamem_free(ahd, scb_data->hscb_dmat,
5742 hscb_map->vaddr, hscb_map->dmamap);
5743 free(hscb_map, M_DEVBUF);
5745 ahd_dma_tag_destroy(ahd, scb_data->hscb_dmat);
5758 * DSP filter Bypass must be enabled until the first selection
5759 * after a change in bus mode (Razor #491 and #493).
5762 ahd_setup_iocell_workaround(struct ahd_softc *ahd)
5764 ahd_mode_state saved_modes;
5766 saved_modes = ahd_save_modes(ahd);
5767 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
5768 ahd_outb(ahd, DSPDATACTL, ahd_inb(ahd, DSPDATACTL)
5769 | BYPASSENAB | RCVROFFSTDIS | XMITOFFSTDIS);
5770 ahd_outb(ahd, SIMODE0, ahd_inb(ahd, SIMODE0) | (ENSELDO|ENSELDI));
5772 if ((ahd_debug & AHD_SHOW_MISC) != 0)
5773 printf("%s: Setting up iocell workaround\n", ahd_name(ahd));
5775 ahd_restore_modes(ahd, saved_modes);
5776 ahd->flags &= ~AHD_HAD_FIRST_SEL;
5780 ahd_iocell_first_selection(struct ahd_softc *ahd)
5782 ahd_mode_state saved_modes;
5785 if ((ahd->flags & AHD_HAD_FIRST_SEL) != 0)
5787 saved_modes = ahd_save_modes(ahd);
5788 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
5789 sblkctl = ahd_inb(ahd, SBLKCTL);
5790 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
5792 if ((ahd_debug & AHD_SHOW_MISC) != 0)
5793 printf("%s: iocell first selection\n", ahd_name(ahd));
5795 if ((sblkctl & ENAB40) != 0) {
5796 ahd_outb(ahd, DSPDATACTL,
5797 ahd_inb(ahd, DSPDATACTL) & ~BYPASSENAB);
5799 if ((ahd_debug & AHD_SHOW_MISC) != 0)
5800 printf("%s: BYPASS now disabled\n", ahd_name(ahd));
5803 ahd_outb(ahd, SIMODE0, ahd_inb(ahd, SIMODE0) & ~(ENSELDO|ENSELDI));
5804 ahd_outb(ahd, CLRINT, CLRSCSIINT);
5805 ahd_restore_modes(ahd, saved_modes);
5806 ahd->flags |= AHD_HAD_FIRST_SEL;
5809 /*************************** SCB Management ***********************************/
5811 ahd_add_col_list(struct ahd_softc *ahd, struct scb *scb, u_int col_idx)
5813 struct scb_list *free_list;
5814 struct scb_tailq *free_tailq;
5815 struct scb *first_scb;
5817 scb->flags |= SCB_ON_COL_LIST;
5818 AHD_SET_SCB_COL_IDX(scb, col_idx);
5819 free_list = &ahd->scb_data.free_scb_lists[col_idx];
5820 free_tailq = &ahd->scb_data.free_scbs;
5821 first_scb = LIST_FIRST(free_list);
5822 if (first_scb != NULL) {
5823 LIST_INSERT_AFTER(first_scb, scb, collision_links);
5825 LIST_INSERT_HEAD(free_list, scb, collision_links);
5826 TAILQ_INSERT_TAIL(free_tailq, scb, links.tqe);
5831 ahd_rem_col_list(struct ahd_softc *ahd, struct scb *scb)
5833 struct scb_list *free_list;
5834 struct scb_tailq *free_tailq;
5835 struct scb *first_scb;
5838 scb->flags &= ~SCB_ON_COL_LIST;
5839 col_idx = AHD_GET_SCB_COL_IDX(ahd, scb);
5840 free_list = &ahd->scb_data.free_scb_lists[col_idx];
5841 free_tailq = &ahd->scb_data.free_scbs;
5842 first_scb = LIST_FIRST(free_list);
5843 if (first_scb == scb) {
5844 struct scb *next_scb;
5847 * Maintain order in the collision free
5848 * lists for fairness if this device has
5849 * other colliding tags active.
5851 next_scb = LIST_NEXT(scb, collision_links);
5852 if (next_scb != NULL) {
5853 TAILQ_INSERT_AFTER(free_tailq, scb,
5854 next_scb, links.tqe);
5856 TAILQ_REMOVE(free_tailq, scb, links.tqe);
5858 LIST_REMOVE(scb, collision_links);
5862 * Get a free scb. If there are none, see if we can allocate a new SCB.
5865 ahd_get_scb(struct ahd_softc *ahd, u_int col_idx)
5872 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) {
5873 if (AHD_GET_SCB_COL_IDX(ahd, scb) != col_idx) {
5874 ahd_rem_col_list(ahd, scb);
5878 if ((scb = LIST_FIRST(&ahd->scb_data.any_dev_free_scb_list)) == NULL) {
5882 ahd_alloc_scbs(ahd);
5885 LIST_REMOVE(scb, links.le);
5886 if (col_idx != AHD_NEVER_COL_IDX
5887 && (scb->col_scb != NULL)
5888 && (scb->col_scb->flags & SCB_ACTIVE) == 0) {
5889 LIST_REMOVE(scb->col_scb, links.le);
5890 ahd_add_col_list(ahd, scb->col_scb, col_idx);
5893 scb->flags |= SCB_ACTIVE;
5898 * Return an SCB resource to the free list.
5901 ahd_free_scb(struct ahd_softc *ahd, struct scb *scb)
5904 /* Clean up for the next user */
5905 scb->flags = SCB_FLAG_NONE;
5906 scb->hscb->control = 0;
5907 ahd->scb_data.scbindex[SCB_GET_TAG(scb)] = NULL;
5909 if (scb->col_scb == NULL) {
5912 * No collision possible. Just free normally.
5914 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list,
5916 } else if ((scb->col_scb->flags & SCB_ON_COL_LIST) != 0) {
5919 * The SCB we might have collided with is on
5920 * a free collision list. Put both SCBs on
5923 ahd_rem_col_list(ahd, scb->col_scb);
5924 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list,
5926 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list,
5927 scb->col_scb, links.le);
5928 } else if ((scb->col_scb->flags
5929 & (SCB_PACKETIZED|SCB_ACTIVE)) == SCB_ACTIVE
5930 && (scb->col_scb->hscb->control & TAG_ENB) != 0) {
5933 * The SCB we might collide with on the next allocation
5934 * is still active in a non-packetized, tagged, context.
5935 * Put us on the SCB collision list.
5937 ahd_add_col_list(ahd, scb,
5938 AHD_GET_SCB_COL_IDX(ahd, scb->col_scb));
5941 * The SCB we might collide with on the next allocation
5942 * is either active in a packetized context, or free.
5943 * Since we can't collide, put this SCB on the generic
5946 LIST_INSERT_HEAD(&ahd->scb_data.any_dev_free_scb_list,
5950 ahd_platform_scb_free(ahd, scb);
5954 ahd_alloc_scbs(struct ahd_softc *ahd)
5956 struct scb_data *scb_data;
5957 struct scb *next_scb;
5958 struct hardware_scb *hscb;
5959 struct map_node *hscb_map;
5960 struct map_node *sg_map;
5961 struct map_node *sense_map;
5963 uint8_t *sense_data;
5964 dma_addr_t hscb_busaddr;
5965 dma_addr_t sg_busaddr;
5966 dma_addr_t sense_busaddr;
5970 scb_data = &ahd->scb_data;
5971 if (scb_data->numscbs >= AHD_SCB_MAX_ALLOC)
5972 /* Can't allocate any more */
5975 if (scb_data->scbs_left != 0) {
5978 offset = (PAGE_SIZE / sizeof(*hscb)) - scb_data->scbs_left;
5979 hscb_map = SLIST_FIRST(&scb_data->hscb_maps);
5980 hscb = &((struct hardware_scb *)hscb_map->vaddr)[offset];
5981 hscb_busaddr = hscb_map->physaddr + (offset * sizeof(*hscb));
5983 hscb_map = malloc(sizeof(*hscb_map), M_DEVBUF, M_NOWAIT);
5985 if (hscb_map == NULL)
5988 /* Allocate the next batch of hardware SCBs */
5989 if (ahd_dmamem_alloc(ahd, scb_data->hscb_dmat,
5990 (void **)&hscb_map->vaddr,
5991 BUS_DMA_NOWAIT, &hscb_map->dmamap) != 0) {
5992 free(hscb_map, M_DEVBUF);
5996 SLIST_INSERT_HEAD(&scb_data->hscb_maps, hscb_map, links);
5998 ahd_dmamap_load(ahd, scb_data->hscb_dmat, hscb_map->dmamap,
5999 hscb_map->vaddr, PAGE_SIZE, ahd_dmamap_cb,
6000 &hscb_map->physaddr, /*flags*/0);
6002 hscb = (struct hardware_scb *)hscb_map->vaddr;
6003 hscb_busaddr = hscb_map->physaddr;
6004 scb_data->scbs_left = PAGE_SIZE / sizeof(*hscb);
6007 if (scb_data->sgs_left != 0) {
6010 offset = ((ahd_sglist_allocsize(ahd) / ahd_sglist_size(ahd))
6011 - scb_data->sgs_left) * ahd_sglist_size(ahd);
6012 sg_map = SLIST_FIRST(&scb_data->sg_maps);
6013 segs = sg_map->vaddr + offset;
6014 sg_busaddr = sg_map->physaddr + offset;
6016 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT);
6021 /* Allocate the next batch of S/G lists */
6022 if (ahd_dmamem_alloc(ahd, scb_data->sg_dmat,
6023 (void **)&sg_map->vaddr,
6024 BUS_DMA_NOWAIT, &sg_map->dmamap) != 0) {
6025 free(sg_map, M_DEVBUF);
6029 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links);
6031 ahd_dmamap_load(ahd, scb_data->sg_dmat, sg_map->dmamap,
6032 sg_map->vaddr, ahd_sglist_allocsize(ahd),
6033 ahd_dmamap_cb, &sg_map->physaddr, /*flags*/0);
6035 segs = sg_map->vaddr;
6036 sg_busaddr = sg_map->physaddr;
6037 scb_data->sgs_left =
6038 ahd_sglist_allocsize(ahd) / ahd_sglist_size(ahd);
6040 if (ahd_debug & AHD_SHOW_MEMORY)
6041 printf("Mapped SG data\n");
6045 if (scb_data->sense_left != 0) {
6048 offset = PAGE_SIZE - (AHD_SENSE_BUFSIZE * scb_data->sense_left);
6049 sense_map = SLIST_FIRST(&scb_data->sense_maps);
6050 sense_data = sense_map->vaddr + offset;
6051 sense_busaddr = sense_map->physaddr + offset;
6053 sense_map = malloc(sizeof(*sense_map), M_DEVBUF, M_NOWAIT);
6055 if (sense_map == NULL)
6058 /* Allocate the next batch of sense buffers */
6059 if (ahd_dmamem_alloc(ahd, scb_data->sense_dmat,
6060 (void **)&sense_map->vaddr,
6061 BUS_DMA_NOWAIT, &sense_map->dmamap) != 0) {
6062 free(sense_map, M_DEVBUF);
6066 SLIST_INSERT_HEAD(&scb_data->sense_maps, sense_map, links);
6068 ahd_dmamap_load(ahd, scb_data->sense_dmat, sense_map->dmamap,
6069 sense_map->vaddr, PAGE_SIZE, ahd_dmamap_cb,
6070 &sense_map->physaddr, /*flags*/0);
6072 sense_data = sense_map->vaddr;
6073 sense_busaddr = sense_map->physaddr;
6074 scb_data->sense_left = PAGE_SIZE / AHD_SENSE_BUFSIZE;
6076 if (ahd_debug & AHD_SHOW_MEMORY)
6077 printf("Mapped sense data\n");
6081 newcount = MIN(scb_data->sense_left, scb_data->scbs_left);
6082 newcount = MIN(newcount, scb_data->sgs_left);
6083 newcount = MIN(newcount, (AHD_SCB_MAX_ALLOC - scb_data->numscbs));
6084 for (i = 0; i < newcount; i++) {
6085 struct scb_platform_data *pdata;
6091 next_scb = (struct scb *)malloc(sizeof(*next_scb),
6092 M_DEVBUF, M_NOWAIT);
6093 if (next_scb == NULL)
6096 pdata = (struct scb_platform_data *)malloc(sizeof(*pdata),
6097 M_DEVBUF, M_NOWAIT);
6098 if (pdata == NULL) {
6099 free(next_scb, M_DEVBUF);
6102 next_scb->platform_data = pdata;
6103 next_scb->hscb_map = hscb_map;
6104 next_scb->sg_map = sg_map;
6105 next_scb->sense_map = sense_map;
6106 next_scb->sg_list = segs;
6107 next_scb->sense_data = sense_data;
6108 next_scb->sense_busaddr = sense_busaddr;
6109 memset(hscb, 0, sizeof(*hscb));
6110 next_scb->hscb = hscb;
6111 hscb->hscb_busaddr = ahd_htole32(hscb_busaddr);
6114 * The sequencer always starts with the second entry.
6115 * The first entry is embedded in the scb.
6117 next_scb->sg_list_busaddr = sg_busaddr;
6118 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0)
6119 next_scb->sg_list_busaddr
6120 += sizeof(struct ahd_dma64_seg);
6122 next_scb->sg_list_busaddr += sizeof(struct ahd_dma_seg);
6123 next_scb->ahd_softc = ahd;
6124 next_scb->flags = SCB_FLAG_NONE;
6126 error = ahd_dmamap_create(ahd, ahd->buffer_dmat, /*flags*/0,
6129 free(next_scb, M_DEVBUF);
6130 free(pdata, M_DEVBUF);
6134 next_scb->hscb->tag = ahd_htole16(scb_data->numscbs);
6135 col_tag = scb_data->numscbs ^ 0x100;
6136 next_scb->col_scb = ahd_find_scb_by_tag(ahd, col_tag);
6137 if (next_scb->col_scb != NULL)
6138 next_scb->col_scb->col_scb = next_scb;
6139 ahd_free_scb(ahd, next_scb);
6141 hscb_busaddr += sizeof(*hscb);
6142 segs += ahd_sglist_size(ahd);
6143 sg_busaddr += ahd_sglist_size(ahd);
6144 sense_data += AHD_SENSE_BUFSIZE;
6145 sense_busaddr += AHD_SENSE_BUFSIZE;
6146 scb_data->numscbs++;
6147 scb_data->sense_left--;
6148 scb_data->scbs_left--;
6149 scb_data->sgs_left--;
6154 ahd_controller_info(struct ahd_softc *ahd, char *buf)
6160 len = sprintf(buf, "%s: ", ahd_chip_names[ahd->chip & AHD_CHIPID_MASK]);
6163 speed = "Ultra320 ";
6164 if ((ahd->features & AHD_WIDE) != 0) {
6169 len = sprintf(buf, "%s%sChannel %c, SCSI Id=%d, ",
6170 speed, type, ahd->channel, ahd->our_id);
6173 sprintf(buf, "%s, %d SCBs", ahd->bus_description,
6174 ahd->scb_data.maxhscbs);
6177 static const char *channel_strings[] = {
6184 static const char *termstat_strings[] = {
6185 "Terminated Correctly",
6192 * Start the board, ready for normal operation
6195 ahd_init(struct ahd_softc *ahd)
6197 uint8_t *next_vaddr;
6198 dma_addr_t next_baddr;
6199 size_t driver_data_size;
6203 uint8_t current_sensing;
6206 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
6208 ahd->stack_size = ahd_probe_stack_size(ahd);
6209 ahd->saved_stack = malloc(ahd->stack_size * sizeof(uint16_t),
6210 M_DEVBUF, M_NOWAIT);
6211 if (ahd->saved_stack == NULL)
6215 * Verify that the compiler hasn't over-agressively
6216 * padded important structures.
6218 if (sizeof(struct hardware_scb) != 64)
6219 panic("Hardware SCB size is incorrect");
6222 if ((ahd_debug & AHD_DEBUG_SEQUENCER) != 0)
6223 ahd->flags |= AHD_SEQUENCER_DEBUG;
6227 * Default to allowing initiator operations.
6229 ahd->flags |= AHD_INITIATORROLE;
6232 * Only allow target mode features if this unit has them enabled.
6234 if ((AHD_TMODE_ENABLE & (0x1 << ahd->unit)) == 0)
6235 ahd->features &= ~AHD_TARGETMODE;
6238 /* DMA tag for mapping buffers into device visible space. */
6239 if (ahd_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1,
6240 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
6241 /*lowaddr*/ahd->flags & AHD_39BIT_ADDRESSING
6242 ? (dma_addr_t)0x7FFFFFFFFFULL
6243 : BUS_SPACE_MAXADDR_32BIT,
6244 /*highaddr*/BUS_SPACE_MAXADDR,
6245 /*filter*/NULL, /*filterarg*/NULL,
6246 /*maxsize*/(AHD_NSEG - 1) * PAGE_SIZE,
6247 /*nsegments*/AHD_NSEG,
6248 /*maxsegsz*/AHD_MAXTRANSFER_SIZE,
6249 /*flags*/BUS_DMA_ALLOCNOW,
6250 &ahd->buffer_dmat) != 0) {
6258 * DMA tag for our command fifos and other data in system memory
6259 * the card's sequencer must be able to access. For initiator
6260 * roles, we need to allocate space for the qoutfifo. When providing
6261 * for the target mode role, we must additionally provide space for
6262 * the incoming target command fifo.
6264 driver_data_size = AHD_SCB_MAX * sizeof(*ahd->qoutfifo)
6265 + sizeof(struct hardware_scb);
6266 if ((ahd->features & AHD_TARGETMODE) != 0)
6267 driver_data_size += AHD_TMODE_CMDS * sizeof(struct target_cmd);
6268 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0)
6269 driver_data_size += PKT_OVERRUN_BUFSIZE;
6270 if (ahd_dma_tag_create(ahd, ahd->parent_dmat, /*alignment*/1,
6271 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
6272 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
6273 /*highaddr*/BUS_SPACE_MAXADDR,
6274 /*filter*/NULL, /*filterarg*/NULL,
6277 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
6278 /*flags*/0, &ahd->shared_data_dmat) != 0) {
6284 /* Allocation of driver data */
6285 if (ahd_dmamem_alloc(ahd, ahd->shared_data_dmat,
6286 (void **)&ahd->shared_data_map.vaddr,
6288 &ahd->shared_data_map.dmamap) != 0) {
6294 /* And permanently map it in */
6295 ahd_dmamap_load(ahd, ahd->shared_data_dmat, ahd->shared_data_map.dmamap,
6296 ahd->shared_data_map.vaddr, driver_data_size,
6297 ahd_dmamap_cb, &ahd->shared_data_map.physaddr,
6299 ahd->qoutfifo = (struct ahd_completion *)ahd->shared_data_map.vaddr;
6300 next_vaddr = (uint8_t *)&ahd->qoutfifo[AHD_QOUT_SIZE];
6301 next_baddr = ahd->shared_data_map.physaddr
6302 + AHD_QOUT_SIZE*sizeof(struct ahd_completion);
6303 if ((ahd->features & AHD_TARGETMODE) != 0) {
6304 ahd->targetcmds = (struct target_cmd *)next_vaddr;
6305 next_vaddr += AHD_TMODE_CMDS * sizeof(struct target_cmd);
6306 next_baddr += AHD_TMODE_CMDS * sizeof(struct target_cmd);
6309 if ((ahd->bugs & AHD_PKT_BITBUCKET_BUG) != 0) {
6310 ahd->overrun_buf = next_vaddr;
6311 next_vaddr += PKT_OVERRUN_BUFSIZE;
6312 next_baddr += PKT_OVERRUN_BUFSIZE;
6316 * We need one SCB to serve as the "next SCB". Since the
6317 * tag identifier in this SCB will never be used, there is
6318 * no point in using a valid HSCB tag from an SCB pulled from
6319 * the standard free pool. So, we allocate this "sentinel"
6320 * specially from the DMA safe memory chunk used for the QOUTFIFO.
6322 ahd->next_queued_hscb = (struct hardware_scb *)next_vaddr;
6323 ahd->next_queued_hscb_map = &ahd->shared_data_map;
6324 ahd->next_queued_hscb->hscb_busaddr = ahd_htole32(next_baddr);
6328 /* Allocate SCB data now that buffer_dmat is initialized */
6329 if (ahd_init_scbdata(ahd) != 0)
6332 if ((ahd->flags & AHD_INITIATORROLE) == 0)
6333 ahd->flags &= ~AHD_RESET_BUS_A;
6336 * Before committing these settings to the chip, give
6337 * the OSM one last chance to modify our configuration.
6339 ahd_platform_init(ahd);
6341 /* Bring up the chip. */
6344 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
6346 if ((ahd->flags & AHD_CURRENT_SENSING) == 0)
6350 * Verify termination based on current draw and
6351 * warn user if the bus is over/under terminated.
6353 error = ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL,
6356 printf("%s: current sensing timeout 1\n", ahd_name(ahd));
6359 for (i = 20, fstat = FLX_FSTAT_BUSY;
6360 (fstat & FLX_FSTAT_BUSY) != 0 && i; i--) {
6361 error = ahd_read_flexport(ahd, FLXADDR_FLEXSTAT, &fstat);
6363 printf("%s: current sensing timeout 2\n",
6369 printf("%s: Timedout during current-sensing test\n",
6374 /* Latch Current Sensing status. */
6375 error = ahd_read_flexport(ahd, FLXADDR_CURRENT_STAT, ¤t_sensing);
6377 printf("%s: current sensing timeout 3\n", ahd_name(ahd));
6381 /* Diable current sensing. */
6382 ahd_write_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, 0);
6385 if ((ahd_debug & AHD_SHOW_TERMCTL) != 0) {
6386 printf("%s: current_sensing == 0x%x\n",
6387 ahd_name(ahd), current_sensing);
6391 for (i = 0; i < 4; i++, current_sensing >>= FLX_CSTAT_SHIFT) {
6394 term_stat = (current_sensing & FLX_CSTAT_MASK);
6395 switch (term_stat) {
6396 case FLX_CSTAT_OVER:
6397 case FLX_CSTAT_UNDER:
6399 case FLX_CSTAT_INVALID:
6400 case FLX_CSTAT_OKAY:
6401 if (warn_user == 0 && bootverbose == 0)
6403 printf("%s: %s Channel %s\n", ahd_name(ahd),
6404 channel_strings[i], termstat_strings[term_stat]);
6409 printf("%s: WARNING. Termination is not configured correctly.\n"
6410 "%s: WARNING. SCSI bus operations may FAIL.\n",
6411 ahd_name(ahd), ahd_name(ahd));
6415 ahd_timer_reset(&ahd->stat_timer, AHD_STAT_UPDATE_US,
6416 ahd_stat_timer, ahd);
6421 * (Re)initialize chip state after a chip reset.
6424 ahd_chip_init(struct ahd_softc *ahd)
6428 u_int scsiseq_template;
6433 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
6435 * Take the LED out of diagnostic mode
6437 ahd_outb(ahd, SBLKCTL, ahd_inb(ahd, SBLKCTL) & ~(DIAGLEDEN|DIAGLEDON));
6440 * Return HS_MAILBOX to its default value.
6442 ahd->hs_mailbox = 0;
6443 ahd_outb(ahd, HS_MAILBOX, 0);
6445 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1. */
6446 ahd_outb(ahd, IOWNID, ahd->our_id);
6447 ahd_outb(ahd, TOWNID, ahd->our_id);
6448 sxfrctl1 = (ahd->flags & AHD_TERM_ENB_A) != 0 ? STPWEN : 0;
6449 sxfrctl1 |= (ahd->flags & AHD_SPCHK_ENB_A) != 0 ? ENSPCHK : 0;
6450 if ((ahd->bugs & AHD_LONG_SETIMO_BUG)
6451 && (ahd->seltime != STIMESEL_MIN)) {
6453 * The selection timer duration is twice as long
6454 * as it should be. Halve it by adding "1" to
6455 * the user specified setting.
6457 sxfrctl1 |= ahd->seltime + STIMESEL_BUG_ADJ;
6459 sxfrctl1 |= ahd->seltime;
6462 ahd_outb(ahd, SXFRCTL0, DFON);
6463 ahd_outb(ahd, SXFRCTL1, sxfrctl1|ahd->seltime|ENSTIMER|ACTNEGEN);
6464 ahd_outb(ahd, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
6467 * Now that termination is set, wait for up
6468 * to 500ms for our transceivers to settle. If
6469 * the adapter does not have a cable attached,
6470 * the transceivers may never settle, so don't
6471 * complain if we fail here.
6474 (ahd_inb(ahd, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait;
6478 /* Clear any false bus resets due to the transceivers settling */
6479 ahd_outb(ahd, CLRSINT1, CLRSCSIRSTI);
6480 ahd_outb(ahd, CLRINT, CLRSCSIINT);
6482 /* Initialize mode specific S/G state. */
6483 for (i = 0; i < 2; i++) {
6484 ahd_set_modes(ahd, AHD_MODE_DFF0 + i, AHD_MODE_DFF0 + i);
6485 ahd_outb(ahd, LONGJMP_ADDR + 1, INVALID_ADDR);
6486 ahd_outb(ahd, SG_STATE, 0);
6487 ahd_outb(ahd, CLRSEQINTSRC, 0xFF);
6488 ahd_outb(ahd, SEQIMODE,
6489 ENSAVEPTRS|ENCFG4DATA|ENCFG4ISTAT
6490 |ENCFG4TSTAT|ENCFG4ICMD|ENCFG4TCMD);
6493 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
6494 ahd_outb(ahd, DSCOMMAND0, ahd_inb(ahd, DSCOMMAND0)|MPARCKEN|CACHETHEN);
6495 ahd_outb(ahd, DFF_THRSH, RD_DFTHRSH_75|WR_DFTHRSH_75);
6496 ahd_outb(ahd, SIMODE0, ENIOERR|ENOVERRUN);
6497 ahd_outb(ahd, SIMODE3, ENNTRAMPERR|ENOSRAMPERR);
6498 if ((ahd->bugs & AHD_BUSFREEREV_BUG) != 0) {
6499 ahd_outb(ahd, OPTIONMODE, AUTOACKEN|AUTO_MSGOUT_DE);
6501 ahd_outb(ahd, OPTIONMODE, AUTOACKEN|BUSFREEREV|AUTO_MSGOUT_DE);
6503 ahd_outb(ahd, SCSCHKN, CURRFIFODEF|WIDERESEN|SHVALIDSTDIS);
6504 if ((ahd->chip & AHD_BUS_MASK) == AHD_PCIX)
6506 * Do not issue a target abort when a split completion
6507 * error occurs. Let our PCIX interrupt handler deal
6508 * with it instead. H2A4 Razor #625
6510 ahd_outb(ahd, PCIXCTL, ahd_inb(ahd, PCIXCTL) | SPLTSTADIS);
6512 if ((ahd->bugs & AHD_LQOOVERRUN_BUG) != 0)
6513 ahd_outb(ahd, LQOSCSCTL, LQONOCHKOVER);
6516 * Tweak IOCELL settings.
6518 if ((ahd->flags & AHD_HP_BOARD) != 0) {
6519 for (i = 0; i < NUMDSPS; i++) {
6520 ahd_outb(ahd, DSPSELECT, i);
6521 ahd_outb(ahd, WRTBIASCTL, WRTBIASCTL_HP_DEFAULT);
6524 if ((ahd_debug & AHD_SHOW_MISC) != 0)
6525 printf("%s: WRTBIASCTL now 0x%x\n", ahd_name(ahd),
6526 WRTBIASCTL_HP_DEFAULT);
6529 ahd_setup_iocell_workaround(ahd);
6532 * Enable LQI Manager interrupts.
6534 ahd_outb(ahd, LQIMODE1, ENLQIPHASE_LQ|ENLQIPHASE_NLQ|ENLIQABORT
6535 | ENLQICRCI_LQ|ENLQICRCI_NLQ|ENLQIBADLQI
6536 | ENLQIOVERI_LQ|ENLQIOVERI_NLQ);
6537 ahd_outb(ahd, LQOMODE0, ENLQOATNLQ|ENLQOATNPKT|ENLQOTCRC);
6539 * We choose to have the sequencer catch LQOPHCHGINPKT errors
6540 * manually for the command phase at the start of a packetized
6541 * selection case. ENLQOBUSFREE should be made redundant by
6542 * the BUSFREE interrupt, but it seems that some LQOBUSFREE
6543 * events fail to assert the BUSFREE interrupt so we must
6544 * also enable LQOBUSFREE interrupts.
6546 ahd_outb(ahd, LQOMODE1, ENLQOBUSFREE);
6549 * Setup sequencer interrupt handlers.
6551 ahd_outw(ahd, INTVEC1_ADDR, ahd_resolve_seqaddr(ahd, LABEL_seq_isr));
6552 ahd_outw(ahd, INTVEC2_ADDR, ahd_resolve_seqaddr(ahd, LABEL_timer_isr));
6555 * Setup SCB Offset registers.
6557 if ((ahd->bugs & AHD_PKT_LUN_BUG) != 0) {
6558 ahd_outb(ahd, LUNPTR, offsetof(struct hardware_scb,
6561 ahd_outb(ahd, LUNPTR, offsetof(struct hardware_scb, lun));
6563 ahd_outb(ahd, CMDLENPTR, offsetof(struct hardware_scb, cdb_len));
6564 ahd_outb(ahd, ATTRPTR, offsetof(struct hardware_scb, task_attribute));
6565 ahd_outb(ahd, FLAGPTR, offsetof(struct hardware_scb, task_management));
6566 ahd_outb(ahd, CMDPTR, offsetof(struct hardware_scb,
6567 shared_data.idata.cdb));
6568 ahd_outb(ahd, QNEXTPTR,
6569 offsetof(struct hardware_scb, next_hscb_busaddr));
6570 ahd_outb(ahd, ABRTBITPTR, MK_MESSAGE_BIT_OFFSET);
6571 ahd_outb(ahd, ABRTBYTEPTR, offsetof(struct hardware_scb, control));
6572 if ((ahd->bugs & AHD_PKT_LUN_BUG) != 0) {
6573 ahd_outb(ahd, LUNLEN,
6574 sizeof(ahd->next_queued_hscb->pkt_long_lun) - 1);
6576 ahd_outb(ahd, LUNLEN, LUNLEN_SINGLE_LEVEL_LUN);
6578 ahd_outb(ahd, CDBLIMIT, SCB_CDB_LEN_PTR - 1);
6579 ahd_outb(ahd, MAXCMD, 0xFF);
6580 ahd_outb(ahd, SCBAUTOPTR,
6581 AUSCBPTR_EN | offsetof(struct hardware_scb, tag));
6583 /* We haven't been enabled for target mode yet. */
6584 ahd_outb(ahd, MULTARGID, 0);
6585 ahd_outb(ahd, MULTARGID + 1, 0);
6587 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
6588 /* Initialize the negotiation table. */
6589 if ((ahd->features & AHD_NEW_IOCELL_OPTS) == 0) {
6591 * Clear the spare bytes in the neg table to avoid
6592 * spurious parity errors.
6594 for (target = 0; target < AHD_NUM_TARGETS; target++) {
6595 ahd_outb(ahd, NEGOADDR, target);
6596 ahd_outb(ahd, ANNEXCOL, AHD_ANNEXCOL_PER_DEV0);
6597 for (i = 0; i < AHD_NUM_PER_DEV_ANNEXCOLS; i++)
6598 ahd_outb(ahd, ANNEXDAT, 0);
6601 for (target = 0; target < AHD_NUM_TARGETS; target++) {
6602 struct ahd_devinfo devinfo;
6603 struct ahd_initiator_tinfo *tinfo;
6604 struct ahd_tmode_tstate *tstate;
6606 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id,
6608 ahd_compile_devinfo(&devinfo, ahd->our_id,
6609 target, CAM_LUN_WILDCARD,
6610 'A', ROLE_INITIATOR);
6611 ahd_update_neg_table(ahd, &devinfo, &tinfo->curr);
6614 ahd_outb(ahd, CLRSINT3, NTRAMPERR|OSRAMPERR);
6615 ahd_outb(ahd, CLRINT, CLRSCSIINT);
6617 #ifdef NEEDS_MORE_TESTING
6619 * Always enable abort on incoming L_Qs if this feature is
6620 * supported. We use this to catch invalid SCB references.
6622 if ((ahd->bugs & AHD_ABORT_LQI_BUG) == 0)
6623 ahd_outb(ahd, LQCTL1, ABORTPENDING);
6626 ahd_outb(ahd, LQCTL1, 0);
6628 /* All of our queues are empty */
6629 ahd->qoutfifonext = 0;
6630 ahd->qoutfifonext_valid_tag = QOUTFIFO_ENTRY_VALID;
6631 ahd_outb(ahd, QOUTFIFO_ENTRY_VALID_TAG, QOUTFIFO_ENTRY_VALID);
6632 for (i = 0; i < AHD_QOUT_SIZE; i++)
6633 ahd->qoutfifo[i].valid_tag = 0;
6634 ahd_sync_qoutfifo(ahd, BUS_DMASYNC_PREREAD);
6636 ahd->qinfifonext = 0;
6637 for (i = 0; i < AHD_QIN_SIZE; i++)
6638 ahd->qinfifo[i] = SCB_LIST_NULL;
6640 if ((ahd->features & AHD_TARGETMODE) != 0) {
6641 /* All target command blocks start out invalid. */
6642 for (i = 0; i < AHD_TMODE_CMDS; i++)
6643 ahd->targetcmds[i].cmd_valid = 0;
6644 ahd_sync_tqinfifo(ahd, BUS_DMASYNC_PREREAD);
6645 ahd->tqinfifonext = 1;
6646 ahd_outb(ahd, KERNEL_TQINPOS, ahd->tqinfifonext - 1);
6647 ahd_outb(ahd, TQINPOS, ahd->tqinfifonext);
6650 /* Initialize Scratch Ram. */
6651 ahd_outb(ahd, SEQ_FLAGS, 0);
6652 ahd_outb(ahd, SEQ_FLAGS2, 0);
6654 /* We don't have any waiting selections */
6655 ahd_outw(ahd, WAITING_TID_HEAD, SCB_LIST_NULL);
6656 ahd_outw(ahd, WAITING_TID_TAIL, SCB_LIST_NULL);
6657 ahd_outw(ahd, MK_MESSAGE_SCB, SCB_LIST_NULL);
6658 ahd_outw(ahd, MK_MESSAGE_SCSIID, 0xFF);
6659 for (i = 0; i < AHD_NUM_TARGETS; i++)
6660 ahd_outw(ahd, WAITING_SCB_TAILS + (2 * i), SCB_LIST_NULL);
6663 * Nobody is waiting to be DMAed into the QOUTFIFO.
6665 ahd_outw(ahd, COMPLETE_SCB_HEAD, SCB_LIST_NULL);
6666 ahd_outw(ahd, COMPLETE_SCB_DMAINPROG_HEAD, SCB_LIST_NULL);
6667 ahd_outw(ahd, COMPLETE_DMA_SCB_HEAD, SCB_LIST_NULL);
6668 ahd_outw(ahd, COMPLETE_DMA_SCB_TAIL, SCB_LIST_NULL);
6669 ahd_outw(ahd, COMPLETE_ON_QFREEZE_HEAD, SCB_LIST_NULL);
6672 * The Freeze Count is 0.
6674 ahd->qfreeze_cnt = 0;
6675 ahd_outw(ahd, QFREEZE_COUNT, 0);
6676 ahd_outw(ahd, KERNEL_QFREEZE_COUNT, 0);
6679 * Tell the sequencer where it can find our arrays in memory.
6681 busaddr = ahd->shared_data_map.physaddr;
6682 ahd_outl(ahd, SHARED_DATA_ADDR, busaddr);
6683 ahd_outl(ahd, QOUTFIFO_NEXT_ADDR, busaddr);
6686 * Setup the allowed SCSI Sequences based on operational mode.
6687 * If we are a target, we'll enable select in operations once
6688 * we've had a lun enabled.
6690 scsiseq_template = ENAUTOATNP;
6691 if ((ahd->flags & AHD_INITIATORROLE) != 0)
6692 scsiseq_template |= ENRSELI;
6693 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq_template);
6695 /* There are no busy SCBs yet. */
6696 for (target = 0; target < AHD_NUM_TARGETS; target++) {
6699 for (lun = 0; lun < AHD_NUM_LUNS_NONPKT; lun++)
6700 ahd_unbusy_tcl(ahd, BUILD_TCL_RAW(target, 'A', lun));
6704 * Initialize the group code to command length table.
6705 * Vendor Unique codes are set to 0 so we only capture
6706 * the first byte of the cdb. These can be overridden
6707 * when target mode is enabled.
6709 ahd_outb(ahd, CMDSIZE_TABLE, 5);
6710 ahd_outb(ahd, CMDSIZE_TABLE + 1, 9);
6711 ahd_outb(ahd, CMDSIZE_TABLE + 2, 9);
6712 ahd_outb(ahd, CMDSIZE_TABLE + 3, 0);
6713 ahd_outb(ahd, CMDSIZE_TABLE + 4, 15);
6714 ahd_outb(ahd, CMDSIZE_TABLE + 5, 11);
6715 ahd_outb(ahd, CMDSIZE_TABLE + 6, 0);
6716 ahd_outb(ahd, CMDSIZE_TABLE + 7, 0);
6718 /* Tell the sequencer of our initial queue positions */
6719 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
6720 ahd_outb(ahd, QOFF_CTLSTA, SCB_QSIZE_512);
6721 ahd->qinfifonext = 0;
6722 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext);
6723 ahd_set_hescb_qoff(ahd, 0);
6724 ahd_set_snscb_qoff(ahd, 0);
6725 ahd_set_sescb_qoff(ahd, 0);
6726 ahd_set_sdscb_qoff(ahd, 0);
6729 * Tell the sequencer which SCB will be the next one it receives.
6731 busaddr = ahd_le32toh(ahd->next_queued_hscb->hscb_busaddr);
6732 ahd_outl(ahd, NEXT_QUEUED_SCB_ADDR, busaddr);
6735 * Default to coalescing disabled.
6737 ahd_outw(ahd, INT_COALESCING_CMDCOUNT, 0);
6738 ahd_outw(ahd, CMDS_PENDING, 0);
6739 ahd_update_coalescing_values(ahd, ahd->int_coalescing_timer,
6740 ahd->int_coalescing_maxcmds,
6741 ahd->int_coalescing_mincmds);
6742 ahd_enable_coalescing(ahd, FALSE);
6745 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
6747 if (ahd->features & AHD_AIC79XXB_SLOWCRC) {
6748 u_int negodat3 = ahd_inb(ahd, NEGCONOPTS);
6750 negodat3 |= ENSLOWCRC;
6751 ahd_outb(ahd, NEGCONOPTS, negodat3);
6752 negodat3 = ahd_inb(ahd, NEGCONOPTS);
6753 if (!(negodat3 & ENSLOWCRC))
6754 printf("aic79xx: failed to set the SLOWCRC bit\n");
6756 printf("aic79xx: SLOWCRC bit set\n");
6761 * Setup default device and controller settings.
6762 * This should only be called if our probe has
6763 * determined that no configuration data is available.
6766 ahd_default_config(struct ahd_softc *ahd)
6773 * Allocate a tstate to house information for our
6774 * initiator presence on the bus as well as the user
6775 * data for any target mode initiator.
6777 if (ahd_alloc_tstate(ahd, ahd->our_id, 'A') == NULL) {
6778 printf("%s: unable to allocate ahd_tmode_tstate. "
6779 "Failing attach\n", ahd_name(ahd));
6783 for (targ = 0; targ < AHD_NUM_TARGETS; targ++) {
6784 struct ahd_devinfo devinfo;
6785 struct ahd_initiator_tinfo *tinfo;
6786 struct ahd_tmode_tstate *tstate;
6787 uint16_t target_mask;
6789 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id,
6792 * We support SPC2 and SPI4.
6794 tinfo->user.protocol_version = 4;
6795 tinfo->user.transport_version = 4;
6797 target_mask = 0x01 << targ;
6798 ahd->user_discenable |= target_mask;
6799 tstate->discenable |= target_mask;
6800 ahd->user_tagenable |= target_mask;
6801 #ifdef AHD_FORCE_160
6802 tinfo->user.period = AHD_SYNCRATE_DT;
6804 tinfo->user.period = AHD_SYNCRATE_160;
6806 tinfo->user.offset = MAX_OFFSET;
6807 tinfo->user.ppr_options = MSG_EXT_PPR_RD_STRM
6808 | MSG_EXT_PPR_WR_FLOW
6809 | MSG_EXT_PPR_HOLD_MCS
6810 | MSG_EXT_PPR_IU_REQ
6811 | MSG_EXT_PPR_QAS_REQ
6812 | MSG_EXT_PPR_DT_REQ;
6813 if ((ahd->features & AHD_RTI) != 0)
6814 tinfo->user.ppr_options |= MSG_EXT_PPR_RTI;
6816 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
6819 * Start out Async/Narrow/Untagged and with
6820 * conservative protocol support.
6822 tinfo->goal.protocol_version = 2;
6823 tinfo->goal.transport_version = 2;
6824 tinfo->curr.protocol_version = 2;
6825 tinfo->curr.transport_version = 2;
6826 ahd_compile_devinfo(&devinfo, ahd->our_id,
6827 targ, CAM_LUN_WILDCARD,
6828 'A', ROLE_INITIATOR);
6829 tstate->tagenable &= ~target_mask;
6830 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
6831 AHD_TRANS_CUR|AHD_TRANS_GOAL, /*paused*/TRUE);
6832 ahd_set_syncrate(ahd, &devinfo, /*period*/0, /*offset*/0,
6833 /*ppr_options*/0, AHD_TRANS_CUR|AHD_TRANS_GOAL,
6840 * Parse device configuration information.
6843 ahd_parse_cfgdata(struct ahd_softc *ahd, struct seeprom_config *sc)
6848 max_targ = sc->max_targets & CFMAXTARG;
6849 ahd->our_id = sc->brtime_id & CFSCSIID;
6852 * Allocate a tstate to house information for our
6853 * initiator presence on the bus as well as the user
6854 * data for any target mode initiator.
6856 if (ahd_alloc_tstate(ahd, ahd->our_id, 'A') == NULL) {
6857 printf("%s: unable to allocate ahd_tmode_tstate. "
6858 "Failing attach\n", ahd_name(ahd));
6862 for (targ = 0; targ < max_targ; targ++) {
6863 struct ahd_devinfo devinfo;
6864 struct ahd_initiator_tinfo *tinfo;
6865 struct ahd_transinfo *user_tinfo;
6866 struct ahd_tmode_tstate *tstate;
6867 uint16_t target_mask;
6869 tinfo = ahd_fetch_transinfo(ahd, 'A', ahd->our_id,
6871 user_tinfo = &tinfo->user;
6874 * We support SPC2 and SPI4.
6876 tinfo->user.protocol_version = 4;
6877 tinfo->user.transport_version = 4;
6879 target_mask = 0x01 << targ;
6880 ahd->user_discenable &= ~target_mask;
6881 tstate->discenable &= ~target_mask;
6882 ahd->user_tagenable &= ~target_mask;
6883 if (sc->device_flags[targ] & CFDISC) {
6884 tstate->discenable |= target_mask;
6885 ahd->user_discenable |= target_mask;
6886 ahd->user_tagenable |= target_mask;
6889 * Cannot be packetized without disconnection.
6891 sc->device_flags[targ] &= ~CFPACKETIZED;
6894 user_tinfo->ppr_options = 0;
6895 user_tinfo->period = (sc->device_flags[targ] & CFXFER);
6896 if (user_tinfo->period < CFXFER_ASYNC) {
6897 if (user_tinfo->period <= AHD_PERIOD_10MHz)
6898 user_tinfo->ppr_options |= MSG_EXT_PPR_DT_REQ;
6899 user_tinfo->offset = MAX_OFFSET;
6901 user_tinfo->offset = 0;
6902 user_tinfo->period = AHD_ASYNC_XFER_PERIOD;
6904 #ifdef AHD_FORCE_160
6905 if (user_tinfo->period <= AHD_SYNCRATE_160)
6906 user_tinfo->period = AHD_SYNCRATE_DT;
6909 if ((sc->device_flags[targ] & CFPACKETIZED) != 0) {
6910 user_tinfo->ppr_options |= MSG_EXT_PPR_RD_STRM
6911 | MSG_EXT_PPR_WR_FLOW
6912 | MSG_EXT_PPR_HOLD_MCS
6913 | MSG_EXT_PPR_IU_REQ;
6914 if ((ahd->features & AHD_RTI) != 0)
6915 user_tinfo->ppr_options |= MSG_EXT_PPR_RTI;
6918 if ((sc->device_flags[targ] & CFQAS) != 0)
6919 user_tinfo->ppr_options |= MSG_EXT_PPR_QAS_REQ;
6921 if ((sc->device_flags[targ] & CFWIDEB) != 0)
6922 user_tinfo->width = MSG_EXT_WDTR_BUS_16_BIT;
6924 user_tinfo->width = MSG_EXT_WDTR_BUS_8_BIT;
6926 if ((ahd_debug & AHD_SHOW_MISC) != 0)
6927 printf("(%d): %x:%x:%x:%x\n", targ, user_tinfo->width,
6928 user_tinfo->period, user_tinfo->offset,
6929 user_tinfo->ppr_options);
6932 * Start out Async/Narrow/Untagged and with
6933 * conservative protocol support.
6935 tstate->tagenable &= ~target_mask;
6936 tinfo->goal.protocol_version = 2;
6937 tinfo->goal.transport_version = 2;
6938 tinfo->curr.protocol_version = 2;
6939 tinfo->curr.transport_version = 2;
6940 ahd_compile_devinfo(&devinfo, ahd->our_id,
6941 targ, CAM_LUN_WILDCARD,
6942 'A', ROLE_INITIATOR);
6943 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
6944 AHD_TRANS_CUR|AHD_TRANS_GOAL, /*paused*/TRUE);
6945 ahd_set_syncrate(ahd, &devinfo, /*period*/0, /*offset*/0,
6946 /*ppr_options*/0, AHD_TRANS_CUR|AHD_TRANS_GOAL,
6950 ahd->flags &= ~AHD_SPCHK_ENB_A;
6951 if (sc->bios_control & CFSPARITY)
6952 ahd->flags |= AHD_SPCHK_ENB_A;
6954 ahd->flags &= ~AHD_RESET_BUS_A;
6955 if (sc->bios_control & CFRESETB)
6956 ahd->flags |= AHD_RESET_BUS_A;
6958 ahd->flags &= ~AHD_EXTENDED_TRANS_A;
6959 if (sc->bios_control & CFEXTEND)
6960 ahd->flags |= AHD_EXTENDED_TRANS_A;
6962 ahd->flags &= ~AHD_BIOS_ENABLED;
6963 if ((sc->bios_control & CFBIOSSTATE) == CFBS_ENABLED)
6964 ahd->flags |= AHD_BIOS_ENABLED;
6966 ahd->flags &= ~AHD_STPWLEVEL_A;
6967 if ((sc->adapter_control & CFSTPWLEVEL) != 0)
6968 ahd->flags |= AHD_STPWLEVEL_A;
6974 * Parse device configuration information.
6977 ahd_parse_vpddata(struct ahd_softc *ahd, struct vpd_config *vpd)
6981 error = ahd_verify_vpd_cksum(vpd);
6984 if ((vpd->bios_flags & VPDBOOTHOST) != 0)
6985 ahd->flags |= AHD_BOOT_CHANNEL;
6990 ahd_intr_enable(struct ahd_softc *ahd, int enable)
6994 hcntrl = ahd_inb(ahd, HCNTRL);
6996 ahd->pause &= ~INTEN;
6997 ahd->unpause &= ~INTEN;
7000 ahd->pause |= INTEN;
7001 ahd->unpause |= INTEN;
7003 ahd_outb(ahd, HCNTRL, hcntrl);
7007 ahd_update_coalescing_values(struct ahd_softc *ahd, u_int timer, u_int maxcmds,
7010 if (timer > AHD_TIMER_MAX_US)
7011 timer = AHD_TIMER_MAX_US;
7012 ahd->int_coalescing_timer = timer;
7014 if (maxcmds > AHD_INT_COALESCING_MAXCMDS_MAX)
7015 maxcmds = AHD_INT_COALESCING_MAXCMDS_MAX;
7016 if (mincmds > AHD_INT_COALESCING_MINCMDS_MAX)
7017 mincmds = AHD_INT_COALESCING_MINCMDS_MAX;
7018 ahd->int_coalescing_maxcmds = maxcmds;
7019 ahd_outw(ahd, INT_COALESCING_TIMER, timer / AHD_TIMER_US_PER_TICK);
7020 ahd_outb(ahd, INT_COALESCING_MAXCMDS, -maxcmds);
7021 ahd_outb(ahd, INT_COALESCING_MINCMDS, -mincmds);
7025 ahd_enable_coalescing(struct ahd_softc *ahd, int enable)
7028 ahd->hs_mailbox &= ~ENINT_COALESCE;
7030 ahd->hs_mailbox |= ENINT_COALESCE;
7031 ahd_outb(ahd, HS_MAILBOX, ahd->hs_mailbox);
7032 ahd_flush_device_writes(ahd);
7033 ahd_run_qoutfifo(ahd);
7037 * Ensure that the card is paused in a location
7038 * outside of all critical sections and that all
7039 * pending work is completed prior to returning.
7040 * This routine should only be called from outside
7041 * an interrupt context.
7044 ahd_pause_and_flushwork(struct ahd_softc *ahd)
7050 ahd->flags |= AHD_ALL_INTERRUPTS;
7053 * Freeze the outgoing selections. We do this only
7054 * until we are safely paused without further selections
7058 ahd_outw(ahd, KERNEL_QFREEZE_COUNT, ahd->qfreeze_cnt);
7059 ahd_outb(ahd, SEQ_FLAGS2, ahd_inb(ahd, SEQ_FLAGS2) | SELECTOUT_QFROZEN);
7064 * Give the sequencer some time to service
7065 * any active selections.
7071 intstat = ahd_inb(ahd, INTSTAT);
7072 if ((intstat & INT_PEND) == 0) {
7073 ahd_clear_critical_section(ahd);
7074 intstat = ahd_inb(ahd, INTSTAT);
7077 && (intstat != 0xFF || (ahd->features & AHD_REMOVABLE) == 0)
7078 && ((intstat & INT_PEND) != 0
7079 || (ahd_inb(ahd, SCSISEQ0) & ENSELO) != 0
7080 || (ahd_inb(ahd, SSTAT0) & (SELDO|SELINGO)) != 0));
7082 if (maxloops == 0) {
7083 printf("Infinite interrupt loop, INTSTAT = %x",
7084 ahd_inb(ahd, INTSTAT));
7087 ahd_outw(ahd, KERNEL_QFREEZE_COUNT, ahd->qfreeze_cnt);
7089 ahd_flush_qoutfifo(ahd);
7091 ahd->flags &= ~AHD_ALL_INTERRUPTS;
7095 ahd_suspend(struct ahd_softc *ahd)
7098 ahd_pause_and_flushwork(ahd);
7100 if (LIST_FIRST(&ahd->pending_scbs) != NULL) {
7109 ahd_resume(struct ahd_softc *ahd)
7112 ahd_reset(ahd, /*reinit*/TRUE);
7113 ahd_intr_enable(ahd, TRUE);
7118 /************************** Busy Target Table *********************************/
7120 * Set SCBPTR to the SCB that contains the busy
7121 * table entry for TCL. Return the offset into
7122 * the SCB that contains the entry for TCL.
7123 * saved_scbid is dereferenced and set to the
7124 * scbid that should be restored once manipualtion
7125 * of the TCL entry is complete.
7127 static __inline u_int
7128 ahd_index_busy_tcl(struct ahd_softc *ahd, u_int *saved_scbid, u_int tcl)
7131 * Index to the SCB that contains the busy entry.
7133 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
7134 *saved_scbid = ahd_get_scbptr(ahd);
7135 ahd_set_scbptr(ahd, TCL_LUN(tcl)
7136 | ((TCL_TARGET_OFFSET(tcl) & 0xC) << 4));
7139 * And now calculate the SCB offset to the entry.
7140 * Each entry is 2 bytes wide, hence the
7141 * multiplication by 2.
7143 return (((TCL_TARGET_OFFSET(tcl) & 0x3) << 1) + SCB_DISCONNECTED_LISTS);
7147 * Return the untagged transaction id for a given target/channel lun.
7150 ahd_find_busy_tcl(struct ahd_softc *ahd, u_int tcl)
7156 scb_offset = ahd_index_busy_tcl(ahd, &saved_scbptr, tcl);
7157 scbid = ahd_inw_scbram(ahd, scb_offset);
7158 ahd_set_scbptr(ahd, saved_scbptr);
7163 ahd_busy_tcl(struct ahd_softc *ahd, u_int tcl, u_int scbid)
7168 scb_offset = ahd_index_busy_tcl(ahd, &saved_scbptr, tcl);
7169 ahd_outw(ahd, scb_offset, scbid);
7170 ahd_set_scbptr(ahd, saved_scbptr);
7173 /************************** SCB and SCB queue management **********************/
7175 ahd_match_scb(struct ahd_softc *ahd, struct scb *scb, int target,
7176 char channel, int lun, u_int tag, role_t role)
7178 int targ = SCB_GET_TARGET(ahd, scb);
7179 char chan = SCB_GET_CHANNEL(ahd, scb);
7180 int slun = SCB_GET_LUN(scb);
7183 match = ((chan == channel) || (channel == ALL_CHANNELS));
7185 match = ((targ == target) || (target == CAM_TARGET_WILDCARD));
7187 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD));
7189 #ifdef AHD_TARGET_MODE
7192 group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code);
7193 if (role == ROLE_INITIATOR) {
7194 match = (group != XPT_FC_GROUP_TMODE)
7195 && ((tag == SCB_GET_TAG(scb))
7196 || (tag == SCB_LIST_NULL));
7197 } else if (role == ROLE_TARGET) {
7198 match = (group == XPT_FC_GROUP_TMODE)
7199 && ((tag == scb->io_ctx->csio.tag_id)
7200 || (tag == SCB_LIST_NULL));
7202 #else /* !AHD_TARGET_MODE */
7203 match = ((tag == SCB_GET_TAG(scb)) || (tag == SCB_LIST_NULL));
7204 #endif /* AHD_TARGET_MODE */
7211 ahd_freeze_devq(struct ahd_softc *ahd, struct scb *scb)
7217 target = SCB_GET_TARGET(ahd, scb);
7218 lun = SCB_GET_LUN(scb);
7219 channel = SCB_GET_CHANNEL(ahd, scb);
7221 ahd_search_qinfifo(ahd, target, channel, lun,
7222 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN,
7223 CAM_REQUEUE_REQ, SEARCH_COMPLETE);
7225 ahd_platform_freeze_devq(ahd, scb);
7229 ahd_qinfifo_requeue_tail(struct ahd_softc *ahd, struct scb *scb)
7231 struct scb *prev_scb;
7232 ahd_mode_state saved_modes;
7234 saved_modes = ahd_save_modes(ahd);
7235 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
7237 if (ahd_qinfifo_count(ahd) != 0) {
7241 prev_pos = AHD_QIN_WRAP(ahd->qinfifonext - 1);
7242 prev_tag = ahd->qinfifo[prev_pos];
7243 prev_scb = ahd_lookup_scb(ahd, prev_tag);
7245 ahd_qinfifo_requeue(ahd, prev_scb, scb);
7246 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext);
7247 ahd_restore_modes(ahd, saved_modes);
7251 ahd_qinfifo_requeue(struct ahd_softc *ahd, struct scb *prev_scb,
7254 if (prev_scb == NULL) {
7257 busaddr = ahd_le32toh(scb->hscb->hscb_busaddr);
7258 ahd_outl(ahd, NEXT_QUEUED_SCB_ADDR, busaddr);
7260 prev_scb->hscb->next_hscb_busaddr = scb->hscb->hscb_busaddr;
7261 ahd_sync_scb(ahd, prev_scb,
7262 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
7264 ahd->qinfifo[AHD_QIN_WRAP(ahd->qinfifonext)] = SCB_GET_TAG(scb);
7266 scb->hscb->next_hscb_busaddr = ahd->next_queued_hscb->hscb_busaddr;
7267 ahd_sync_scb(ahd, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
7271 ahd_qinfifo_count(struct ahd_softc *ahd)
7275 u_int wrap_qinfifonext;
7277 AHD_ASSERT_MODES(ahd, AHD_MODE_CCHAN_MSK, AHD_MODE_CCHAN_MSK);
7278 qinpos = ahd_get_snscb_qoff(ahd);
7279 wrap_qinpos = AHD_QIN_WRAP(qinpos);
7280 wrap_qinfifonext = AHD_QIN_WRAP(ahd->qinfifonext);
7281 if (wrap_qinfifonext >= wrap_qinpos)
7282 return (wrap_qinfifonext - wrap_qinpos);
7284 return (wrap_qinfifonext
7285 + NUM_ELEMENTS(ahd->qinfifo) - wrap_qinpos);
7289 ahd_reset_cmds_pending(struct ahd_softc *ahd)
7292 ahd_mode_state saved_modes;
7295 saved_modes = ahd_save_modes(ahd);
7296 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
7299 * Don't count any commands as outstanding that the
7300 * sequencer has already marked for completion.
7302 ahd_flush_qoutfifo(ahd);
7305 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) {
7308 ahd_outw(ahd, CMDS_PENDING, pending_cmds - ahd_qinfifo_count(ahd));
7309 ahd_restore_modes(ahd, saved_modes);
7310 ahd->flags &= ~AHD_UPDATE_PEND_CMDS;
7314 ahd_done_with_status(struct ahd_softc *ahd, struct scb *scb, uint32_t status)
7319 ostat = ahd_get_transaction_status(scb);
7320 if (ostat == CAM_REQ_INPROG)
7321 ahd_set_transaction_status(scb, status);
7322 cstat = ahd_get_transaction_status(scb);
7323 if (cstat != CAM_REQ_CMP)
7324 ahd_freeze_scb(scb);
7329 ahd_search_qinfifo(struct ahd_softc *ahd, int target, char channel,
7330 int lun, u_int tag, role_t role, uint32_t status,
7331 ahd_search_action action)
7334 struct scb *mk_msg_scb;
7335 struct scb *prev_scb;
7336 ahd_mode_state saved_modes;
7349 /* Must be in CCHAN mode */
7350 saved_modes = ahd_save_modes(ahd);
7351 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
7354 * Halt any pending SCB DMA. The sequencer will reinitiate
7355 * this dma if the qinfifo is not empty once we unpause.
7357 if ((ahd_inb(ahd, CCSCBCTL) & (CCARREN|CCSCBEN|CCSCBDIR))
7358 == (CCARREN|CCSCBEN|CCSCBDIR)) {
7359 ahd_outb(ahd, CCSCBCTL,
7360 ahd_inb(ahd, CCSCBCTL) & ~(CCARREN|CCSCBEN));
7361 while ((ahd_inb(ahd, CCSCBCTL) & (CCARREN|CCSCBEN)) != 0)
7364 /* Determine sequencer's position in the qinfifo. */
7365 qintail = AHD_QIN_WRAP(ahd->qinfifonext);
7366 qinstart = ahd_get_snscb_qoff(ahd);
7367 qinpos = AHD_QIN_WRAP(qinstart);
7371 if (action == SEARCH_PRINT) {
7372 printf("qinstart = %d qinfifonext = %d\nQINFIFO:",
7373 qinstart, ahd->qinfifonext);
7377 * Start with an empty queue. Entries that are not chosen
7378 * for removal will be re-added to the queue as we go.
7380 ahd->qinfifonext = qinstart;
7381 busaddr = ahd_le32toh(ahd->next_queued_hscb->hscb_busaddr);
7382 ahd_outl(ahd, NEXT_QUEUED_SCB_ADDR, busaddr);
7384 while (qinpos != qintail) {
7385 scb = ahd_lookup_scb(ahd, ahd->qinfifo[qinpos]);
7387 printf("qinpos = %d, SCB index = %d\n",
7388 qinpos, ahd->qinfifo[qinpos]);
7392 if (ahd_match_scb(ahd, scb, target, channel, lun, tag, role)) {
7394 * We found an scb that needs to be acted on.
7398 case SEARCH_COMPLETE:
7399 if ((scb->flags & SCB_ACTIVE) == 0)
7400 printf("Inactive SCB in qinfifo\n");
7401 ahd_done_with_status(ahd, scb, status);
7406 printf(" 0x%x", ahd->qinfifo[qinpos]);
7409 ahd_qinfifo_requeue(ahd, prev_scb, scb);
7414 ahd_qinfifo_requeue(ahd, prev_scb, scb);
7417 qinpos = AHD_QIN_WRAP(qinpos+1);
7420 ahd_set_hnscb_qoff(ahd, ahd->qinfifonext);
7422 if (action == SEARCH_PRINT)
7423 printf("\nWAITING_TID_QUEUES:\n");
7426 * Search waiting for selection lists. We traverse the
7427 * list of "their ids" waiting for selection and, if
7428 * appropriate, traverse the SCBs of each "their id"
7429 * looking for matches.
7431 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
7432 seq_flags2 = ahd_inb(ahd, SEQ_FLAGS2);
7433 if ((seq_flags2 & PENDING_MK_MESSAGE) != 0) {
7434 scbid = ahd_inw(ahd, MK_MESSAGE_SCB);
7435 mk_msg_scb = ahd_lookup_scb(ahd, scbid);
7438 savedscbptr = ahd_get_scbptr(ahd);
7439 tid_next = ahd_inw(ahd, WAITING_TID_HEAD);
7440 tid_prev = SCB_LIST_NULL;
7442 for (scbid = tid_next; !SCBID_IS_NULL(scbid); scbid = tid_next) {
7447 if (targets > AHD_NUM_TARGETS)
7448 panic("TID LIST LOOP");
7450 if (scbid >= ahd->scb_data.numscbs) {
7451 printf("%s: Waiting TID List inconsistency. "
7452 "SCB index == 0x%x, yet numscbs == 0x%x.",
7453 ahd_name(ahd), scbid, ahd->scb_data.numscbs);
7454 ahd_dump_card_state(ahd);
7455 panic("for safety");
7457 scb = ahd_lookup_scb(ahd, scbid);
7459 printf("%s: SCB = 0x%x Not Active!\n",
7460 ahd_name(ahd), scbid);
7461 panic("Waiting TID List traversal\n");
7463 ahd_set_scbptr(ahd, scbid);
7464 tid_next = ahd_inw_scbram(ahd, SCB_NEXT2);
7465 if (ahd_match_scb(ahd, scb, target, channel, CAM_LUN_WILDCARD,
7466 SCB_LIST_NULL, ROLE_UNKNOWN) == 0) {
7472 * We found a list of scbs that needs to be searched.
7474 if (action == SEARCH_PRINT)
7475 printf(" %d ( ", SCB_GET_TARGET(ahd, scb));
7477 found += ahd_search_scb_list(ahd, target, channel,
7478 lun, tag, role, status,
7479 action, &tid_head, &tid_tail,
7480 SCB_GET_TARGET(ahd, scb));
7482 * Check any MK_MESSAGE SCB that is still waiting to
7483 * enter this target's waiting for selection queue.
7485 if (mk_msg_scb != NULL
7486 && ahd_match_scb(ahd, mk_msg_scb, target, channel,
7490 * We found an scb that needs to be acted on.
7494 case SEARCH_COMPLETE:
7495 if ((mk_msg_scb->flags & SCB_ACTIVE) == 0)
7496 printf("Inactive SCB pending MK_MSG\n");
7497 ahd_done_with_status(ahd, mk_msg_scb, status);
7503 printf("Removing MK_MSG scb\n");
7506 * Reset our tail to the tail of the
7507 * main per-target list.
7509 tail_offset = WAITING_SCB_TAILS
7510 + (2 * SCB_GET_TARGET(ahd, mk_msg_scb));
7511 ahd_outw(ahd, tail_offset, tid_tail);
7513 seq_flags2 &= ~PENDING_MK_MESSAGE;
7514 ahd_outb(ahd, SEQ_FLAGS2, seq_flags2);
7515 ahd_outw(ahd, CMDS_PENDING,
7516 ahd_inw(ahd, CMDS_PENDING)-1);
7521 printf(" 0x%x", SCB_GET_TAG(scb));
7528 if (mk_msg_scb != NULL
7529 && SCBID_IS_NULL(tid_head)
7530 && ahd_match_scb(ahd, scb, target, channel, CAM_LUN_WILDCARD,
7531 SCB_LIST_NULL, ROLE_UNKNOWN)) {
7534 * When removing the last SCB for a target
7535 * queue with a pending MK_MESSAGE scb, we
7536 * must queue the MK_MESSAGE scb.
7538 printf("Queueing mk_msg_scb\n");
7539 tid_head = ahd_inw(ahd, MK_MESSAGE_SCB);
7540 seq_flags2 &= ~PENDING_MK_MESSAGE;
7541 ahd_outb(ahd, SEQ_FLAGS2, seq_flags2);
7544 if (tid_head != scbid)
7545 ahd_stitch_tid_list(ahd, tid_prev, tid_head, tid_next);
7546 if (!SCBID_IS_NULL(tid_head))
7547 tid_prev = tid_head;
7548 if (action == SEARCH_PRINT)
7552 /* Restore saved state. */
7553 ahd_set_scbptr(ahd, savedscbptr);
7554 ahd_restore_modes(ahd, saved_modes);
7559 ahd_search_scb_list(struct ahd_softc *ahd, int target, char channel,
7560 int lun, u_int tag, role_t role, uint32_t status,
7561 ahd_search_action action, u_int *list_head,
7562 u_int *list_tail, u_int tid)
7570 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
7572 prev = SCB_LIST_NULL;
7574 *list_tail = SCB_LIST_NULL;
7575 for (scbid = next; !SCBID_IS_NULL(scbid); scbid = next) {
7576 if (scbid >= ahd->scb_data.numscbs) {
7577 printf("%s:SCB List inconsistency. "
7578 "SCB == 0x%x, yet numscbs == 0x%x.",
7579 ahd_name(ahd), scbid, ahd->scb_data.numscbs);
7580 ahd_dump_card_state(ahd);
7581 panic("for safety");
7583 scb = ahd_lookup_scb(ahd, scbid);
7585 printf("%s: SCB = %d Not Active!\n",
7586 ahd_name(ahd), scbid);
7587 panic("Waiting List traversal\n");
7589 ahd_set_scbptr(ahd, scbid);
7591 next = ahd_inw_scbram(ahd, SCB_NEXT);
7592 if (ahd_match_scb(ahd, scb, target, channel,
7593 lun, SCB_LIST_NULL, role) == 0) {
7599 case SEARCH_COMPLETE:
7600 if ((scb->flags & SCB_ACTIVE) == 0)
7601 printf("Inactive SCB in Waiting List\n");
7602 ahd_done_with_status(ahd, scb, status);
7605 ahd_rem_wscb(ahd, scbid, prev, next, tid);
7607 if (SCBID_IS_NULL(prev))
7611 printf("0x%x ", scbid);
7616 if (found > AHD_SCB_MAX)
7617 panic("SCB LIST LOOP");
7619 if (action == SEARCH_COMPLETE
7620 || action == SEARCH_REMOVE)
7621 ahd_outw(ahd, CMDS_PENDING, ahd_inw(ahd, CMDS_PENDING) - found);
7626 ahd_stitch_tid_list(struct ahd_softc *ahd, u_int tid_prev,
7627 u_int tid_cur, u_int tid_next)
7629 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
7631 if (SCBID_IS_NULL(tid_cur)) {
7633 /* Bypass current TID list */
7634 if (SCBID_IS_NULL(tid_prev)) {
7635 ahd_outw(ahd, WAITING_TID_HEAD, tid_next);
7637 ahd_set_scbptr(ahd, tid_prev);
7638 ahd_outw(ahd, SCB_NEXT2, tid_next);
7640 if (SCBID_IS_NULL(tid_next))
7641 ahd_outw(ahd, WAITING_TID_TAIL, tid_prev);
7644 /* Stitch through tid_cur */
7645 if (SCBID_IS_NULL(tid_prev)) {
7646 ahd_outw(ahd, WAITING_TID_HEAD, tid_cur);
7648 ahd_set_scbptr(ahd, tid_prev);
7649 ahd_outw(ahd, SCB_NEXT2, tid_cur);
7651 ahd_set_scbptr(ahd, tid_cur);
7652 ahd_outw(ahd, SCB_NEXT2, tid_next);
7654 if (SCBID_IS_NULL(tid_next))
7655 ahd_outw(ahd, WAITING_TID_TAIL, tid_cur);
7660 * Manipulate the waiting for selection list and return the
7661 * scb that follows the one that we remove.
7664 ahd_rem_wscb(struct ahd_softc *ahd, u_int scbid,
7665 u_int prev, u_int next, u_int tid)
7669 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
7670 if (!SCBID_IS_NULL(prev)) {
7671 ahd_set_scbptr(ahd, prev);
7672 ahd_outw(ahd, SCB_NEXT, next);
7676 * SCBs that have MK_MESSAGE set in them may
7677 * cause the tail pointer to be updated without
7678 * setting the next pointer of the previous tail.
7679 * Only clear the tail if the removed SCB was
7682 tail_offset = WAITING_SCB_TAILS + (2 * tid);
7683 if (SCBID_IS_NULL(next)
7684 && ahd_inw(ahd, tail_offset) == scbid)
7685 ahd_outw(ahd, tail_offset, prev);
7687 ahd_add_scb_to_free_list(ahd, scbid);
7692 * Add the SCB as selected by SCBPTR onto the on chip list of
7693 * free hardware SCBs. This list is empty/unused if we are not
7694 * performing SCB paging.
7697 ahd_add_scb_to_free_list(struct ahd_softc *ahd, u_int scbid)
7699 /* XXX Need some other mechanism to designate "free". */
7701 * Invalidate the tag so that our abort
7702 * routines don't think it's active.
7703 ahd_outb(ahd, SCB_TAG, SCB_LIST_NULL);
7707 /******************************** Error Handling ******************************/
7709 * Abort all SCBs that match the given description (target/channel/lun/tag),
7710 * setting their status to the passed in status if the status has not already
7711 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer
7712 * is paused before it is called.
7715 ahd_abort_scbs(struct ahd_softc *ahd, int target, char channel,
7716 int lun, u_int tag, role_t role, uint32_t status)
7719 struct scb *scbp_next;
7725 ahd_mode_state saved_modes;
7727 /* restore this when we're done */
7728 saved_modes = ahd_save_modes(ahd);
7729 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
7731 found = ahd_search_qinfifo(ahd, target, channel, lun, SCB_LIST_NULL,
7732 role, CAM_REQUEUE_REQ, SEARCH_COMPLETE);
7735 * Clean out the busy target table for any untagged commands.
7739 if (target != CAM_TARGET_WILDCARD) {
7746 if (lun == CAM_LUN_WILDCARD) {
7748 maxlun = AHD_NUM_LUNS_NONPKT;
7749 } else if (lun >= AHD_NUM_LUNS_NONPKT) {
7750 minlun = maxlun = 0;
7756 if (role != ROLE_TARGET) {
7757 for (;i < maxtarget; i++) {
7758 for (j = minlun;j < maxlun; j++) {
7762 tcl = BUILD_TCL_RAW(i, 'A', j);
7763 scbid = ahd_find_busy_tcl(ahd, tcl);
7764 scbp = ahd_lookup_scb(ahd, scbid);
7766 || ahd_match_scb(ahd, scbp, target, channel,
7767 lun, tag, role) == 0)
7769 ahd_unbusy_tcl(ahd, BUILD_TCL_RAW(i, 'A', j));
7775 * Don't abort commands that have already completed,
7776 * but haven't quite made it up to the host yet.
7778 ahd_flush_qoutfifo(ahd);
7781 * Go through the pending CCB list and look for
7782 * commands for this target that are still active.
7783 * These are other tagged commands that were
7784 * disconnected when the reset occurred.
7786 scbp_next = LIST_FIRST(&ahd->pending_scbs);
7787 while (scbp_next != NULL) {
7789 scbp_next = LIST_NEXT(scbp, pending_links);
7790 if (ahd_match_scb(ahd, scbp, target, channel, lun, tag, role)) {
7793 ostat = ahd_get_transaction_status(scbp);
7794 if (ostat == CAM_REQ_INPROG)
7795 ahd_set_transaction_status(scbp, status);
7796 if (ahd_get_transaction_status(scbp) != CAM_REQ_CMP)
7797 ahd_freeze_scb(scbp);
7798 if ((scbp->flags & SCB_ACTIVE) == 0)
7799 printf("Inactive SCB on pending list\n");
7800 ahd_done(ahd, scbp);
7804 ahd_restore_modes(ahd, saved_modes);
7805 ahd_platform_abort_scbs(ahd, target, channel, lun, tag, role, status);
7806 ahd->flags |= AHD_UPDATE_PEND_CMDS;
7811 ahd_reset_current_bus(struct ahd_softc *ahd)
7815 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
7816 ahd_outb(ahd, SIMODE1, ahd_inb(ahd, SIMODE1) & ~ENSCSIRST);
7817 scsiseq = ahd_inb(ahd, SCSISEQ0) & ~(ENSELO|ENARBO|SCSIRSTO);
7818 ahd_outb(ahd, SCSISEQ0, scsiseq | SCSIRSTO);
7819 ahd_flush_device_writes(ahd);
7820 ahd_delay(AHD_BUSRESET_DELAY);
7821 /* Turn off the bus reset */
7822 ahd_outb(ahd, SCSISEQ0, scsiseq);
7823 ahd_flush_device_writes(ahd);
7824 ahd_delay(AHD_BUSRESET_DELAY);
7825 if ((ahd->bugs & AHD_SCSIRST_BUG) != 0) {
7828 * Certain chip state is not cleared for
7829 * SCSI bus resets that we initiate, so
7830 * we must reset the chip.
7832 ahd_reset(ahd, /*reinit*/TRUE);
7833 ahd_intr_enable(ahd, /*enable*/TRUE);
7834 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
7837 ahd_clear_intstat(ahd);
7841 ahd_reset_channel(struct ahd_softc *ahd, char channel, int initiate_reset)
7843 struct ahd_devinfo devinfo;
7851 ahd->pending_device = NULL;
7853 ahd_compile_devinfo(&devinfo,
7854 CAM_TARGET_WILDCARD,
7855 CAM_TARGET_WILDCARD,
7857 channel, ROLE_UNKNOWN);
7860 /* Make sure the sequencer is in a safe location. */
7861 ahd_clear_critical_section(ahd);
7863 #ifdef AHD_TARGET_MODE
7864 if ((ahd->flags & AHD_TARGETROLE) != 0) {
7865 ahd_run_tqinfifo(ahd, /*paused*/TRUE);
7868 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
7871 * Disable selections so no automatic hardware
7872 * functions will modify chip state.
7874 ahd_outb(ahd, SCSISEQ0, 0);
7875 ahd_outb(ahd, SCSISEQ1, 0);
7878 * Safely shut down our DMA engines. Always start with
7879 * the FIFO that is not currently active (if any are
7880 * actively connected).
7882 next_fifo = fifo = ahd_inb(ahd, DFFSTAT) & CURRFIFO;
7883 if (next_fifo > CURRFIFO_1)
7884 /* If disconneced, arbitrarily start with FIFO1. */
7885 next_fifo = fifo = 0;
7887 next_fifo ^= CURRFIFO_1;
7888 ahd_set_modes(ahd, next_fifo, next_fifo);
7889 ahd_outb(ahd, DFCNTRL,
7890 ahd_inb(ahd, DFCNTRL) & ~(SCSIEN|HDMAEN));
7891 while ((ahd_inb(ahd, DFCNTRL) & HDMAENACK) != 0)
7894 * Set CURRFIFO to the now inactive channel.
7896 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
7897 ahd_outb(ahd, DFFSTAT, next_fifo);
7898 } while (next_fifo != fifo);
7901 * Reset the bus if we are initiating this reset
7903 ahd_clear_msg_state(ahd);
7904 ahd_outb(ahd, SIMODE1,
7905 ahd_inb(ahd, SIMODE1) & ~(ENBUSFREE|ENSCSIRST));
7908 ahd_reset_current_bus(ahd);
7910 ahd_clear_intstat(ahd);
7913 * Clean up all the state information for the
7914 * pending transactions on this bus.
7916 found = ahd_abort_scbs(ahd, CAM_TARGET_WILDCARD, channel,
7917 CAM_LUN_WILDCARD, SCB_LIST_NULL,
7918 ROLE_UNKNOWN, CAM_SCSI_BUS_RESET);
7921 * Cleanup anything left in the FIFOs.
7923 ahd_clear_fifo(ahd, 0);
7924 ahd_clear_fifo(ahd, 1);
7927 * Revert to async/narrow transfers until we renegotiate.
7929 max_scsiid = (ahd->features & AHD_WIDE) ? 15 : 7;
7930 for (target = 0; target <= max_scsiid; target++) {
7932 if (ahd->enabled_targets[target] == NULL)
7934 for (initiator = 0; initiator <= max_scsiid; initiator++) {
7935 struct ahd_devinfo devinfo;
7937 ahd_compile_devinfo(&devinfo, target, initiator,
7940 ahd_set_width(ahd, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
7941 AHD_TRANS_CUR, /*paused*/TRUE);
7942 ahd_set_syncrate(ahd, &devinfo, /*period*/0,
7943 /*offset*/0, /*ppr_options*/0,
7944 AHD_TRANS_CUR, /*paused*/TRUE);
7948 #ifdef AHD_TARGET_MODE
7949 max_scsiid = (ahd->features & AHD_WIDE) ? 15 : 7;
7952 * Send an immediate notify ccb to all target more peripheral
7953 * drivers affected by this action.
7955 for (target = 0; target <= max_scsiid; target++) {
7956 struct ahd_tmode_tstate* tstate;
7959 tstate = ahd->enabled_targets[target];
7962 for (lun = 0; lun < AHD_NUM_LUNS; lun++) {
7963 struct ahd_tmode_lstate* lstate;
7965 lstate = tstate->enabled_luns[lun];
7969 ahd_queue_lstate_event(ahd, lstate, CAM_TARGET_WILDCARD,
7970 EVENT_TYPE_BUS_RESET, /*arg*/0);
7971 ahd_send_lstate_events(ahd, lstate);
7975 /* Notify the XPT that a bus reset occurred */
7976 ahd_send_async(ahd, devinfo.channel, CAM_TARGET_WILDCARD,
7977 CAM_LUN_WILDCARD, AC_BUS_RESET, NULL);
7980 * Freeze the SIMQ until our poller can determine that
7981 * the bus reset has really gone away. We set the initial
7982 * timer to 0 to have the check performed as soon as possible
7983 * from the timer context.
7985 if ((ahd->flags & AHD_RESET_POLL_ACTIVE) == 0) {
7986 ahd->flags |= AHD_RESET_POLL_ACTIVE;
7987 ahd_freeze_simq(ahd);
7988 ahd_timer_reset(&ahd->reset_timer, 0, ahd_reset_poll, ahd);
7994 #define AHD_RESET_POLL_US 1000
7996 ahd_reset_poll(void *arg)
7998 struct ahd_softc *ahd = arg;
8004 ahd_update_modes(ahd);
8005 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
8006 ahd_outb(ahd, CLRSINT1, CLRSCSIRSTI);
8007 if ((ahd_inb(ahd, SSTAT1) & SCSIRSTI) != 0) {
8008 ahd_timer_reset(&ahd->reset_timer, AHD_RESET_POLL_US,
8009 ahd_reset_poll, ahd);
8011 ahd_unlock(ahd, &s);
8015 /* Reset is now low. Complete chip reinitialization. */
8016 ahd_outb(ahd, SIMODE1, ahd_inb(ahd, SIMODE1) | ENSCSIRST);
8017 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE);
8018 ahd_outb(ahd, SCSISEQ1, scsiseq1 & (ENSELI|ENRSELI|ENAUTOATNP));
8020 ahd->flags &= ~AHD_RESET_POLL_ACTIVE;
8021 ahd_unlock(ahd, &s);
8022 ahd_release_simq(ahd);
8025 /**************************** Statistics Processing ***************************/
8027 ahd_stat_timer(void *arg)
8029 struct ahd_softc *ahd = arg;
8035 enint_coal = ahd->hs_mailbox & ENINT_COALESCE;
8036 if (ahd->cmdcmplt_total > ahd->int_coalescing_threshold)
8037 enint_coal |= ENINT_COALESCE;
8038 else if (ahd->cmdcmplt_total < ahd->int_coalescing_stop_threshold)
8039 enint_coal &= ~ENINT_COALESCE;
8041 if (enint_coal != (ahd->hs_mailbox & ENINT_COALESCE)) {
8042 ahd_enable_coalescing(ahd, enint_coal);
8044 if ((ahd_debug & AHD_SHOW_INT_COALESCING) != 0)
8045 printf("%s: Interrupt coalescing "
8046 "now %sabled. Cmds %d\n",
8048 (enint_coal & ENINT_COALESCE) ? "en" : "dis",
8049 ahd->cmdcmplt_total);
8053 ahd->cmdcmplt_bucket = (ahd->cmdcmplt_bucket+1) & (AHD_STAT_BUCKETS-1);
8054 ahd->cmdcmplt_total -= ahd->cmdcmplt_counts[ahd->cmdcmplt_bucket];
8055 ahd->cmdcmplt_counts[ahd->cmdcmplt_bucket] = 0;
8056 ahd_timer_reset(&ahd->stat_timer, AHD_STAT_UPDATE_US,
8057 ahd_stat_timer, ahd);
8058 ahd_unlock(ahd, &s);
8061 /****************************** Status Processing *****************************/
8063 ahd_handle_scb_status(struct ahd_softc *ahd, struct scb *scb)
8065 if (scb->hscb->shared_data.istatus.scsi_status != 0) {
8066 ahd_handle_scsi_status(ahd, scb);
8068 ahd_calc_residual(ahd, scb);
8074 ahd_handle_scsi_status(struct ahd_softc *ahd, struct scb *scb)
8076 struct hardware_scb *hscb;
8080 * The sequencer freezes its select-out queue
8081 * anytime a SCSI status error occurs. We must
8082 * handle the error and increment our qfreeze count
8083 * to allow the sequencer to continue. We don't
8084 * bother clearing critical sections here since all
8085 * operations are on data structures that the sequencer
8086 * is not touching once the queue is frozen.
8090 if (ahd_is_paused(ahd)) {
8097 /* Freeze the queue until the client sees the error. */
8098 ahd_freeze_devq(ahd, scb);
8099 ahd_freeze_scb(scb);
8101 ahd_outw(ahd, KERNEL_QFREEZE_COUNT, ahd->qfreeze_cnt);
8106 /* Don't want to clobber the original sense code */
8107 if ((scb->flags & SCB_SENSE) != 0) {
8109 * Clear the SCB_SENSE Flag and perform
8110 * a normal command completion.
8112 scb->flags &= ~SCB_SENSE;
8113 ahd_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
8117 ahd_set_transaction_status(scb, CAM_SCSI_STATUS_ERROR);
8118 ahd_set_scsi_status(scb, hscb->shared_data.istatus.scsi_status);
8119 switch (hscb->shared_data.istatus.scsi_status) {
8120 case STATUS_PKT_SENSE:
8122 struct scsi_status_iu_header *siu;
8124 ahd_sync_sense(ahd, scb, BUS_DMASYNC_POSTREAD);
8125 siu = (struct scsi_status_iu_header *)scb->sense_data;
8126 ahd_set_scsi_status(scb, siu->status);
8128 if ((ahd_debug & AHD_SHOW_SENSE) != 0) {
8129 ahd_print_path(ahd, scb);
8130 printf("SCB 0x%x Received PKT Status of 0x%x\n",
8131 SCB_GET_TAG(scb), siu->status);
8132 printf("\tflags = 0x%x, sense len = 0x%x, "
8134 siu->flags, scsi_4btoul(siu->sense_length),
8135 scsi_4btoul(siu->pkt_failures_length));
8138 if ((siu->flags & SIU_RSPVALID) != 0) {
8139 ahd_print_path(ahd, scb);
8140 if (scsi_4btoul(siu->pkt_failures_length) < 4) {
8141 printf("Unable to parse pkt_failures\n");
8144 switch (SIU_PKTFAIL_CODE(siu)) {
8146 printf("No packet failure found\n");
8148 case SIU_PFC_CIU_FIELDS_INVALID:
8149 printf("Invalid Command IU Field\n");
8151 case SIU_PFC_TMF_NOT_SUPPORTED:
8152 printf("TMF not supportd\n");
8154 case SIU_PFC_TMF_FAILED:
8155 printf("TMF failed\n");
8157 case SIU_PFC_INVALID_TYPE_CODE:
8158 printf("Invalid L_Q Type code\n");
8160 case SIU_PFC_ILLEGAL_REQUEST:
8161 printf("Illegal request\n");
8166 if (siu->status == SCSI_STATUS_OK)
8167 ahd_set_transaction_status(scb,
8170 if ((siu->flags & SIU_SNSVALID) != 0) {
8171 scb->flags |= SCB_PKT_SENSE;
8173 if ((ahd_debug & AHD_SHOW_SENSE) != 0)
8174 printf("Sense data available\n");
8180 case SCSI_STATUS_CMD_TERMINATED:
8181 case SCSI_STATUS_CHECK_COND:
8183 struct ahd_devinfo devinfo;
8184 struct ahd_dma_seg *sg;
8185 struct scsi_sense *sc;
8186 struct ahd_initiator_tinfo *targ_info;
8187 struct ahd_tmode_tstate *tstate;
8188 struct ahd_transinfo *tinfo;
8190 if (ahd_debug & AHD_SHOW_SENSE) {
8191 ahd_print_path(ahd, scb);
8192 printf("SCB %d: requests Check Status\n",
8197 if (ahd_perform_autosense(scb) == 0)
8200 ahd_compile_devinfo(&devinfo, SCB_GET_OUR_ID(scb),
8201 SCB_GET_TARGET(ahd, scb),
8203 SCB_GET_CHANNEL(ahd, scb),
8205 targ_info = ahd_fetch_transinfo(ahd,
8210 tinfo = &targ_info->curr;
8212 sc = (struct scsi_sense *)hscb->shared_data.idata.cdb;
8214 * Save off the residual if there is one.
8216 ahd_update_residual(ahd, scb);
8218 if (ahd_debug & AHD_SHOW_SENSE) {
8219 ahd_print_path(ahd, scb);
8220 printf("Sending Sense\n");
8224 sg = ahd_sg_setup(ahd, scb, sg, ahd_get_sense_bufaddr(ahd, scb),
8225 ahd_get_sense_bufsize(ahd, scb),
8227 sc->opcode = REQUEST_SENSE;
8229 if (tinfo->protocol_version <= SCSI_REV_2
8230 && SCB_GET_LUN(scb) < 8)
8231 sc->byte2 = SCB_GET_LUN(scb) << 5;
8234 sc->length = ahd_get_sense_bufsize(ahd, scb);
8238 * We can't allow the target to disconnect.
8239 * This will be an untagged transaction and
8240 * having the target disconnect will make this
8241 * transaction indestinguishable from outstanding
8242 * tagged transactions.
8247 * This request sense could be because the
8248 * the device lost power or in some other
8249 * way has lost our transfer negotiations.
8250 * Renegotiate if appropriate. Unit attention
8251 * errors will be reported before any data
8254 if (ahd_get_residual(scb) == ahd_get_transfer_length(scb)) {
8255 ahd_update_neg_request(ahd, &devinfo,
8257 AHD_NEG_IF_NON_ASYNC);
8259 if (tstate->auto_negotiate & devinfo.target_mask) {
8260 hscb->control |= MK_MESSAGE;
8262 ~(SCB_NEGOTIATE|SCB_ABORT|SCB_DEVICE_RESET);
8263 scb->flags |= SCB_AUTO_NEGOTIATE;
8265 hscb->cdb_len = sizeof(*sc);
8266 ahd_setup_data_scb(ahd, scb);
8267 scb->flags |= SCB_SENSE;
8268 ahd_queue_scb(ahd, scb);
8271 case SCSI_STATUS_OK:
8272 printf("%s: Interrupted for staus of 0???\n",
8282 * Calculate the residual for a just completed SCB.
8285 ahd_calc_residual(struct ahd_softc *ahd, struct scb *scb)
8287 struct hardware_scb *hscb;
8288 struct initiator_status *spkt;
8290 uint32_t resid_sgptr;
8296 * SG_STATUS_VALID clear in sgptr.
8297 * 2) Transferless command
8298 * 3) Never performed any transfers.
8299 * sgptr has SG_FULL_RESID set.
8300 * 4) No residual but target did not
8301 * save data pointers after the
8302 * last transfer, so sgptr was
8304 * 5) We have a partial residual.
8305 * Use residual_sgptr to determine
8310 sgptr = ahd_le32toh(hscb->sgptr);
8311 if ((sgptr & SG_STATUS_VALID) == 0)
8314 sgptr &= ~SG_STATUS_VALID;
8316 if ((sgptr & SG_LIST_NULL) != 0)
8321 * Residual fields are the same in both
8322 * target and initiator status packets,
8323 * so we can always use the initiator fields
8324 * regardless of the role for this SCB.
8326 spkt = &hscb->shared_data.istatus;
8327 resid_sgptr = ahd_le32toh(spkt->residual_sgptr);
8328 if ((sgptr & SG_FULL_RESID) != 0) {
8330 resid = ahd_get_transfer_length(scb);
8331 } else if ((resid_sgptr & SG_LIST_NULL) != 0) {
8334 } else if ((resid_sgptr & SG_OVERRUN_RESID) != 0) {
8335 ahd_print_path(ahd, scb);
8336 printf("data overrun detected Tag == 0x%x.\n",
8338 ahd_freeze_devq(ahd, scb);
8339 ahd_set_transaction_status(scb, CAM_DATA_RUN_ERR);
8340 ahd_freeze_scb(scb);
8342 } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) {
8343 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr);
8346 struct ahd_dma_seg *sg;
8349 * Remainder of the SG where the transfer
8352 resid = ahd_le32toh(spkt->residual_datacnt) & AHD_SG_LEN_MASK;
8353 sg = ahd_sg_bus_to_virt(ahd, scb, resid_sgptr & SG_PTR_MASK);
8355 /* The residual sg_ptr always points to the next sg */
8359 * Add up the contents of all residual
8360 * SG segments that are after the SG where
8361 * the transfer stopped.
8363 while ((ahd_le32toh(sg->len) & AHD_DMA_LAST_SEG) == 0) {
8365 resid += ahd_le32toh(sg->len) & AHD_SG_LEN_MASK;
8368 if ((scb->flags & SCB_SENSE) == 0)
8369 ahd_set_residual(scb, resid);
8371 ahd_set_sense_residual(scb, resid);
8374 if ((ahd_debug & AHD_SHOW_MISC) != 0) {
8375 ahd_print_path(ahd, scb);
8376 printf("Handled %sResidual of %d bytes\n",
8377 (scb->flags & SCB_SENSE) ? "Sense " : "", resid);
8382 /******************************* Target Mode **********************************/
8383 #ifdef AHD_TARGET_MODE
8385 * Add a target mode event to this lun's queue
8388 ahd_queue_lstate_event(struct ahd_softc *ahd, struct ahd_tmode_lstate *lstate,
8389 u_int initiator_id, u_int event_type, u_int event_arg)
8391 struct ahd_tmode_event *event;
8394 xpt_freeze_devq(lstate->path, /*count*/1);
8395 if (lstate->event_w_idx >= lstate->event_r_idx)
8396 pending = lstate->event_w_idx - lstate->event_r_idx;
8398 pending = AHD_TMODE_EVENT_BUFFER_SIZE + 1
8399 - (lstate->event_r_idx - lstate->event_w_idx);
8401 if (event_type == EVENT_TYPE_BUS_RESET
8402 || event_type == MSG_BUS_DEV_RESET) {
8404 * Any earlier events are irrelevant, so reset our buffer.
8405 * This has the effect of allowing us to deal with reset
8406 * floods (an external device holding down the reset line)
8407 * without losing the event that is really interesting.
8409 lstate->event_r_idx = 0;
8410 lstate->event_w_idx = 0;
8411 xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE);
8414 if (pending == AHD_TMODE_EVENT_BUFFER_SIZE) {
8415 xpt_print_path(lstate->path);
8416 printf("immediate event %x:%x lost\n",
8417 lstate->event_buffer[lstate->event_r_idx].event_type,
8418 lstate->event_buffer[lstate->event_r_idx].event_arg);
8419 lstate->event_r_idx++;
8420 if (lstate->event_r_idx == AHD_TMODE_EVENT_BUFFER_SIZE)
8421 lstate->event_r_idx = 0;
8422 xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE);
8425 event = &lstate->event_buffer[lstate->event_w_idx];
8426 event->initiator_id = initiator_id;
8427 event->event_type = event_type;
8428 event->event_arg = event_arg;
8429 lstate->event_w_idx++;
8430 if (lstate->event_w_idx == AHD_TMODE_EVENT_BUFFER_SIZE)
8431 lstate->event_w_idx = 0;
8435 * Send any target mode events queued up waiting
8436 * for immediate notify resources.
8439 ahd_send_lstate_events(struct ahd_softc *ahd, struct ahd_tmode_lstate *lstate)
8441 struct ccb_hdr *ccbh;
8442 struct ccb_immed_notify *inot;
8444 while (lstate->event_r_idx != lstate->event_w_idx
8445 && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) {
8446 struct ahd_tmode_event *event;
8448 event = &lstate->event_buffer[lstate->event_r_idx];
8449 SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle);
8450 inot = (struct ccb_immed_notify *)ccbh;
8451 switch (event->event_type) {
8452 case EVENT_TYPE_BUS_RESET:
8453 ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN;
8456 ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN;
8457 inot->message_args[0] = event->event_type;
8458 inot->message_args[1] = event->event_arg;
8461 inot->initiator_id = event->initiator_id;
8462 inot->sense_len = 0;
8463 xpt_done((union ccb *)inot);
8464 lstate->event_r_idx++;
8465 if (lstate->event_r_idx == AHD_TMODE_EVENT_BUFFER_SIZE)
8466 lstate->event_r_idx = 0;
8471 /******************** Sequencer Program Patching/Download *********************/
8475 ahd_dumpseq(struct ahd_softc* ahd)
8482 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
8483 ahd_outw(ahd, PRGMCNT, 0);
8484 for (i = 0; i < max_prog; i++) {
8485 uint8_t ins_bytes[4];
8487 ahd_insb(ahd, SEQRAM, ins_bytes, 4);
8488 printf("0x%08x\n", ins_bytes[0] << 24
8489 | ins_bytes[1] << 16
8497 ahd_loadseq(struct ahd_softc *ahd)
8499 struct cs cs_table[num_critical_sections];
8500 u_int begin_set[num_critical_sections];
8501 u_int end_set[num_critical_sections];
8502 struct patch *cur_patch;
8508 u_int sg_prefetch_cnt;
8509 u_int sg_prefetch_cnt_limit;
8510 u_int sg_prefetch_align;
8512 u_int cacheline_mask;
8513 uint8_t download_consts[DOWNLOAD_CONST_COUNT];
8516 printf("%s: Downloading Sequencer Program...",
8519 #if DOWNLOAD_CONST_COUNT != 8
8520 #error "Download Const Mismatch"
8523 * Start out with 0 critical sections
8524 * that apply to this firmware load.
8528 memset(begin_set, 0, sizeof(begin_set));
8529 memset(end_set, 0, sizeof(end_set));
8532 * Setup downloadable constant table.
8534 * The computation for the S/G prefetch variables is
8535 * a bit complicated. We would like to always fetch
8536 * in terms of cachelined sized increments. However,
8537 * if the cacheline is not an even multiple of the
8538 * SG element size or is larger than our SG RAM, using
8539 * just the cache size might leave us with only a portion
8540 * of an SG element at the tail of a prefetch. If the
8541 * cacheline is larger than our S/G prefetch buffer less
8542 * the size of an SG element, we may round down to a cacheline
8543 * that doesn't contain any or all of the S/G of interest
8544 * within the bounds of our S/G ram. Provide variables to
8545 * the sequencer that will allow it to handle these edge
8548 /* Start by aligning to the nearest cacheline. */
8549 sg_prefetch_align = ahd->pci_cachesize;
8550 if (sg_prefetch_align == 0)
8551 sg_prefetch_align = 8;
8552 /* Round down to the nearest power of 2. */
8553 while (powerof2(sg_prefetch_align) == 0)
8554 sg_prefetch_align--;
8556 cacheline_mask = sg_prefetch_align - 1;
8559 * If the cacheline boundary is greater than half our prefetch RAM
8560 * we risk not being able to fetch even a single complete S/G
8561 * segment if we align to that boundary.
8563 if (sg_prefetch_align > CCSGADDR_MAX/2)
8564 sg_prefetch_align = CCSGADDR_MAX/2;
8565 /* Start by fetching a single cacheline. */
8566 sg_prefetch_cnt = sg_prefetch_align;
8568 * Increment the prefetch count by cachelines until
8569 * at least one S/G element will fit.
8571 sg_size = sizeof(struct ahd_dma_seg);
8572 if ((ahd->flags & AHD_64BIT_ADDRESSING) != 0)
8573 sg_size = sizeof(struct ahd_dma64_seg);
8574 while (sg_prefetch_cnt < sg_size)
8575 sg_prefetch_cnt += sg_prefetch_align;
8577 * If the cacheline is not an even multiple of
8578 * the S/G size, we may only get a partial S/G when
8579 * we align. Add a cacheline if this is the case.
8581 if ((sg_prefetch_align % sg_size) != 0
8582 && (sg_prefetch_cnt < CCSGADDR_MAX))
8583 sg_prefetch_cnt += sg_prefetch_align;
8585 * Lastly, compute a value that the sequencer can use
8586 * to determine if the remainder of the CCSGRAM buffer
8587 * has a full S/G element in it.
8589 sg_prefetch_cnt_limit = -(sg_prefetch_cnt - sg_size + 1);
8590 download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt;
8591 download_consts[SG_PREFETCH_CNT_LIMIT] = sg_prefetch_cnt_limit;
8592 download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_align - 1);
8593 download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_align - 1);
8594 download_consts[SG_SIZEOF] = sg_size;
8595 download_consts[PKT_OVERRUN_BUFOFFSET] =
8596 (ahd->overrun_buf - (uint8_t *)ahd->qoutfifo) / 256;
8597 download_consts[SCB_TRANSFER_SIZE] = SCB_TRANSFER_SIZE_1BYTE_LUN;
8598 download_consts[CACHELINE_MASK] = cacheline_mask;
8599 cur_patch = patches;
8602 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
8603 ahd_outw(ahd, PRGMCNT, 0);
8605 for (i = 0; i < sizeof(seqprog)/4; i++) {
8606 if (ahd_check_patch(ahd, &cur_patch, i, &skip_addr) == 0) {
8608 * Don't download this instruction as it
8609 * is in a patch that was removed.
8614 * Move through the CS table until we find a CS
8615 * that might apply to this instruction.
8617 for (; cur_cs < num_critical_sections; cur_cs++) {
8618 if (critical_sections[cur_cs].end <= i) {
8619 if (begin_set[cs_count] == TRUE
8620 && end_set[cs_count] == FALSE) {
8621 cs_table[cs_count].end = downloaded;
8622 end_set[cs_count] = TRUE;
8627 if (critical_sections[cur_cs].begin <= i
8628 && begin_set[cs_count] == FALSE) {
8629 cs_table[cs_count].begin = downloaded;
8630 begin_set[cs_count] = TRUE;
8634 ahd_download_instr(ahd, i, download_consts);
8638 ahd->num_critical_sections = cs_count;
8639 if (cs_count != 0) {
8641 cs_count *= sizeof(struct cs);
8642 ahd->critical_sections = malloc(cs_count, M_DEVBUF, M_NOWAIT);
8643 if (ahd->critical_sections == NULL)
8644 panic("ahd_loadseq: Could not malloc");
8645 memcpy(ahd->critical_sections, cs_table, cs_count);
8647 ahd_outb(ahd, SEQCTL0, PERRORDIS|FAILDIS|FASTMODE);
8650 printf(" %d instructions downloaded\n", downloaded);
8651 printf("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n",
8652 ahd_name(ahd), ahd->features, ahd->bugs, ahd->flags);
8657 ahd_check_patch(struct ahd_softc *ahd, struct patch **start_patch,
8658 u_int start_instr, u_int *skip_addr)
8660 struct patch *cur_patch;
8661 struct patch *last_patch;
8664 num_patches = sizeof(patches)/sizeof(struct patch);
8665 last_patch = &patches[num_patches];
8666 cur_patch = *start_patch;
8668 while (cur_patch < last_patch && start_instr == cur_patch->begin) {
8670 if (cur_patch->patch_func(ahd) == 0) {
8672 /* Start rejecting code */
8673 *skip_addr = start_instr + cur_patch->skip_instr;
8674 cur_patch += cur_patch->skip_patch;
8676 /* Accepted this patch. Advance to the next
8677 * one and wait for our intruction pointer to
8684 *start_patch = cur_patch;
8685 if (start_instr < *skip_addr)
8686 /* Still skipping */
8693 ahd_resolve_seqaddr(struct ahd_softc *ahd, u_int address)
8695 struct patch *cur_patch;
8701 cur_patch = patches;
8704 for (i = 0; i < address;) {
8706 ahd_check_patch(ahd, &cur_patch, i, &skip_addr);
8708 if (skip_addr > i) {
8711 end_addr = MIN(address, skip_addr);
8712 address_offset += end_addr - i;
8718 return (address - address_offset);
8722 ahd_download_instr(struct ahd_softc *ahd, u_int instrptr, uint8_t *dconsts)
8724 union ins_formats instr;
8725 struct ins_format1 *fmt1_ins;
8726 struct ins_format3 *fmt3_ins;
8730 * The firmware is always compiled into a little endian format.
8732 instr.integer = ahd_le32toh(*(uint32_t*)&seqprog[instrptr * 4]);
8734 fmt1_ins = &instr.format1;
8737 /* Pull the opcode */
8738 opcode = instr.format1.opcode;
8749 fmt3_ins = &instr.format3;
8750 fmt3_ins->address = ahd_resolve_seqaddr(ahd, fmt3_ins->address);
8759 if (fmt1_ins->parity != 0) {
8760 fmt1_ins->immediate = dconsts[fmt1_ins->immediate];
8762 fmt1_ins->parity = 0;
8768 /* Calculate odd parity for the instruction */
8769 for (i = 0, count = 0; i < 31; i++) {
8773 if ((instr.integer & mask) != 0)
8776 if ((count & 0x01) == 0)
8777 instr.format1.parity = 1;
8779 /* The sequencer is a little endian cpu */
8780 instr.integer = ahd_htole32(instr.integer);
8781 ahd_outsb(ahd, SEQRAM, instr.bytes, 4);
8785 panic("Unknown opcode encountered in seq program");
8791 ahd_probe_stack_size(struct ahd_softc *ahd)
8800 * We avoid using 0 as a pattern to avoid
8801 * confusion if the stack implementation
8802 * "back-fills" with zeros when "poping'
8805 for (i = 1; i <= last_probe+1; i++) {
8806 ahd_outb(ahd, STACK, i & 0xFF);
8807 ahd_outb(ahd, STACK, (i >> 8) & 0xFF);
8811 for (i = last_probe+1; i > 0; i--) {
8814 stack_entry = ahd_inb(ahd, STACK)
8815 |(ahd_inb(ahd, STACK) << 8);
8816 if (stack_entry != i)
8822 return (last_probe);
8826 ahd_print_register(ahd_reg_parse_entry_t *table, u_int num_entries,
8827 const char *name, u_int address, u_int value,
8828 u_int *cur_column, u_int wrap_point)
8833 if (cur_column != NULL && *cur_column >= wrap_point) {
8837 printed = printf("%s[0x%x]", name, value);
8838 if (table == NULL) {
8839 printed += printf(" ");
8840 *cur_column += printed;
8844 while (printed_mask != 0xFF) {
8847 for (entry = 0; entry < num_entries; entry++) {
8848 if (((value & table[entry].mask)
8849 != table[entry].value)
8850 || ((printed_mask & table[entry].mask)
8851 == table[entry].mask))
8854 printed += printf("%s%s",
8855 printed_mask == 0 ? ":(" : "|",
8857 printed_mask |= table[entry].mask;
8861 if (entry >= num_entries)
8864 if (printed_mask != 0)
8865 printed += printf(") ");
8867 printed += printf(" ");
8868 if (cur_column != NULL)
8869 *cur_column += printed;
8874 ahd_dump_card_state(struct ahd_softc *ahd)
8877 ahd_mode_state saved_modes;
8881 u_int saved_scb_index;
8885 if (ahd_is_paused(ahd)) {
8891 saved_modes = ahd_save_modes(ahd);
8892 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
8893 printf(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n"
8894 "%s: Dumping Card State at program address 0x%x Mode 0x%x\n",
8896 ahd_inw(ahd, CURADDR),
8897 ahd_build_mode_state(ahd, ahd->saved_src_mode,
8898 ahd->saved_dst_mode));
8900 printf("Card was paused\n");
8902 if (ahd_check_cmdcmpltqueues(ahd))
8903 printf("Completions are pending\n");
8906 * Mode independent registers.
8909 ahd_intstat_print(ahd_inb(ahd, INTSTAT), &cur_col, 50);
8910 ahd_seloid_print(ahd_inb(ahd, SELOID), &cur_col, 50);
8911 ahd_selid_print(ahd_inb(ahd, SELID), &cur_col, 50);
8912 ahd_hs_mailbox_print(ahd_inb(ahd, LOCAL_HS_MAILBOX), &cur_col, 50);
8913 ahd_intctl_print(ahd_inb(ahd, INTCTL), &cur_col, 50);
8914 ahd_seqintstat_print(ahd_inb(ahd, SEQINTSTAT), &cur_col, 50);
8915 ahd_saved_mode_print(ahd_inb(ahd, SAVED_MODE), &cur_col, 50);
8916 ahd_dffstat_print(ahd_inb(ahd, DFFSTAT), &cur_col, 50);
8917 ahd_scsisigi_print(ahd_inb(ahd, SCSISIGI), &cur_col, 50);
8918 ahd_scsiphase_print(ahd_inb(ahd, SCSIPHASE), &cur_col, 50);
8919 ahd_scsibus_print(ahd_inb(ahd, SCSIBUS), &cur_col, 50);
8920 ahd_lastphase_print(ahd_inb(ahd, LASTPHASE), &cur_col, 50);
8921 ahd_scsiseq0_print(ahd_inb(ahd, SCSISEQ0), &cur_col, 50);
8922 ahd_scsiseq1_print(ahd_inb(ahd, SCSISEQ1), &cur_col, 50);
8923 ahd_seqctl0_print(ahd_inb(ahd, SEQCTL0), &cur_col, 50);
8924 ahd_seqintctl_print(ahd_inb(ahd, SEQINTCTL), &cur_col, 50);
8925 ahd_seq_flags_print(ahd_inb(ahd, SEQ_FLAGS), &cur_col, 50);
8926 ahd_seq_flags2_print(ahd_inb(ahd, SEQ_FLAGS2), &cur_col, 50);
8927 ahd_qfreeze_count_print(ahd_inw(ahd, QFREEZE_COUNT), &cur_col, 50);
8928 ahd_kernel_qfreeze_count_print(ahd_inw(ahd, KERNEL_QFREEZE_COUNT),
8930 ahd_mk_message_scb_print(ahd_inw(ahd, MK_MESSAGE_SCB), &cur_col, 50);
8931 ahd_mk_message_scsiid_print(ahd_inb(ahd, MK_MESSAGE_SCSIID),
8933 ahd_sstat0_print(ahd_inb(ahd, SSTAT0), &cur_col, 50);
8934 ahd_sstat1_print(ahd_inb(ahd, SSTAT1), &cur_col, 50);
8935 ahd_sstat2_print(ahd_inb(ahd, SSTAT2), &cur_col, 50);
8936 ahd_sstat3_print(ahd_inb(ahd, SSTAT3), &cur_col, 50);
8937 ahd_perrdiag_print(ahd_inb(ahd, PERRDIAG), &cur_col, 50);
8938 ahd_simode1_print(ahd_inb(ahd, SIMODE1), &cur_col, 50);
8939 ahd_lqistat0_print(ahd_inb(ahd, LQISTAT0), &cur_col, 50);
8940 ahd_lqistat1_print(ahd_inb(ahd, LQISTAT1), &cur_col, 50);
8941 ahd_lqistat2_print(ahd_inb(ahd, LQISTAT2), &cur_col, 50);
8942 ahd_lqostat0_print(ahd_inb(ahd, LQOSTAT0), &cur_col, 50);
8943 ahd_lqostat1_print(ahd_inb(ahd, LQOSTAT1), &cur_col, 50);
8944 ahd_lqostat2_print(ahd_inb(ahd, LQOSTAT2), &cur_col, 50);
8946 printf("\nSCB Count = %d CMDS_PENDING = %d LASTSCB 0x%x "
8947 "CURRSCB 0x%x NEXTSCB 0x%x\n",
8948 ahd->scb_data.numscbs, ahd_inw(ahd, CMDS_PENDING),
8949 ahd_inw(ahd, LASTSCB), ahd_inw(ahd, CURRSCB),
8950 ahd_inw(ahd, NEXTSCB));
8953 ahd_search_qinfifo(ahd, CAM_TARGET_WILDCARD, ALL_CHANNELS,
8954 CAM_LUN_WILDCARD, SCB_LIST_NULL,
8955 ROLE_UNKNOWN, /*status*/0, SEARCH_PRINT);
8956 saved_scb_index = ahd_get_scbptr(ahd);
8957 printf("Pending list:");
8959 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) {
8960 if (i++ > AHD_SCB_MAX)
8962 cur_col = printf("\n%3d FIFO_USE[0x%x] ", SCB_GET_TAG(scb),
8963 ahd_inb_scbram(ahd, SCB_FIFO_USE_COUNT));
8964 ahd_set_scbptr(ahd, SCB_GET_TAG(scb));
8965 ahd_scb_control_print(ahd_inb_scbram(ahd, SCB_CONTROL),
8967 ahd_scb_scsiid_print(ahd_inb_scbram(ahd, SCB_SCSIID),
8970 printf("\nTotal %d\n", i);
8972 printf("Kernel Free SCB list: ");
8974 TAILQ_FOREACH(scb, &ahd->scb_data.free_scbs, links.tqe) {
8975 struct scb *list_scb;
8979 printf("%d ", SCB_GET_TAG(list_scb));
8980 list_scb = LIST_NEXT(list_scb, collision_links);
8981 } while (list_scb && i++ < AHD_SCB_MAX);
8984 LIST_FOREACH(scb, &ahd->scb_data.any_dev_free_scb_list, links.le) {
8985 if (i++ > AHD_SCB_MAX)
8987 printf("%d ", SCB_GET_TAG(scb));
8991 printf("Sequencer Complete DMA-inprog list: ");
8992 scb_index = ahd_inw(ahd, COMPLETE_SCB_DMAINPROG_HEAD);
8994 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) {
8995 ahd_set_scbptr(ahd, scb_index);
8996 printf("%d ", scb_index);
8997 scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
9001 printf("Sequencer Complete list: ");
9002 scb_index = ahd_inw(ahd, COMPLETE_SCB_HEAD);
9004 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) {
9005 ahd_set_scbptr(ahd, scb_index);
9006 printf("%d ", scb_index);
9007 scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
9012 printf("Sequencer DMA-Up and Complete list: ");
9013 scb_index = ahd_inw(ahd, COMPLETE_DMA_SCB_HEAD);
9015 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) {
9016 ahd_set_scbptr(ahd, scb_index);
9017 printf("%d ", scb_index);
9018 scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
9021 printf("Sequencer On QFreeze and Complete list: ");
9022 scb_index = ahd_inw(ahd, COMPLETE_ON_QFREEZE_HEAD);
9024 while (!SCBID_IS_NULL(scb_index) && i++ < AHD_SCB_MAX) {
9025 ahd_set_scbptr(ahd, scb_index);
9026 printf("%d ", scb_index);
9027 scb_index = ahd_inw_scbram(ahd, SCB_NEXT_COMPLETE);
9030 ahd_set_scbptr(ahd, saved_scb_index);
9031 dffstat = ahd_inb(ahd, DFFSTAT);
9032 for (i = 0; i < 2; i++) {
9034 struct scb *fifo_scb;
9038 ahd_set_modes(ahd, AHD_MODE_DFF0 + i, AHD_MODE_DFF0 + i);
9039 fifo_scbptr = ahd_get_scbptr(ahd);
9040 printf("\n\n%s: FIFO%d %s, LONGJMP == 0x%x, SCB 0x%x\n",
9042 (dffstat & (FIFO0FREE << i)) ? "Free" : "Active",
9043 ahd_inw(ahd, LONGJMP_ADDR), fifo_scbptr);
9045 ahd_seqimode_print(ahd_inb(ahd, SEQIMODE), &cur_col, 50);
9046 ahd_seqintsrc_print(ahd_inb(ahd, SEQINTSRC), &cur_col, 50);
9047 ahd_dfcntrl_print(ahd_inb(ahd, DFCNTRL), &cur_col, 50);
9048 ahd_dfstatus_print(ahd_inb(ahd, DFSTATUS), &cur_col, 50);
9049 ahd_sg_cache_shadow_print(ahd_inb(ahd, SG_CACHE_SHADOW),
9051 ahd_sg_state_print(ahd_inb(ahd, SG_STATE), &cur_col, 50);
9052 ahd_dffsxfrctl_print(ahd_inb(ahd, DFFSXFRCTL), &cur_col, 50);
9053 ahd_soffcnt_print(ahd_inb(ahd, SOFFCNT), &cur_col, 50);
9054 ahd_mdffstat_print(ahd_inb(ahd, MDFFSTAT), &cur_col, 50);
9059 cur_col += printf("SHADDR = 0x%x%x, SHCNT = 0x%x ",
9060 ahd_inl(ahd, SHADDR+4),
9061 ahd_inl(ahd, SHADDR),
9062 (ahd_inb(ahd, SHCNT)
9063 | (ahd_inb(ahd, SHCNT + 1) << 8)
9064 | (ahd_inb(ahd, SHCNT + 2) << 16)));
9069 cur_col += printf("HADDR = 0x%x%x, HCNT = 0x%x ",
9070 ahd_inl(ahd, HADDR+4),
9071 ahd_inl(ahd, HADDR),
9073 | (ahd_inb(ahd, HCNT + 1) << 8)
9074 | (ahd_inb(ahd, HCNT + 2) << 16)));
9075 ahd_ccsgctl_print(ahd_inb(ahd, CCSGCTL), &cur_col, 50);
9077 if ((ahd_debug & AHD_SHOW_SG) != 0) {
9078 fifo_scb = ahd_lookup_scb(ahd, fifo_scbptr);
9079 if (fifo_scb != NULL)
9080 ahd_dump_sglist(fifo_scb);
9085 for (i = 0; i < 20; i++)
9086 printf("0x%x ", ahd_inb(ahd, LQIN + i));
9088 ahd_set_modes(ahd, AHD_MODE_CFG, AHD_MODE_CFG);
9089 printf("%s: LQISTATE = 0x%x, LQOSTATE = 0x%x, OPTIONMODE = 0x%x\n",
9090 ahd_name(ahd), ahd_inb(ahd, LQISTATE), ahd_inb(ahd, LQOSTATE),
9091 ahd_inb(ahd, OPTIONMODE));
9092 printf("%s: OS_SPACE_CNT = 0x%x MAXCMDCNT = 0x%x\n",
9093 ahd_name(ahd), ahd_inb(ahd, OS_SPACE_CNT),
9094 ahd_inb(ahd, MAXCMDCNT));
9095 printf("%s: SAVED_SCSIID = 0x%x SAVED_LUN = 0x%x\n",
9096 ahd_name(ahd), ahd_inb(ahd, SAVED_SCSIID),
9097 ahd_inb(ahd, SAVED_LUN));
9098 ahd_simode0_print(ahd_inb(ahd, SIMODE0), &cur_col, 50);
9100 ahd_set_modes(ahd, AHD_MODE_CCHAN, AHD_MODE_CCHAN);
9102 ahd_ccscbctl_print(ahd_inb(ahd, CCSCBCTL), &cur_col, 50);
9104 ahd_set_modes(ahd, ahd->saved_src_mode, ahd->saved_dst_mode);
9105 printf("%s: REG0 == 0x%x, SINDEX = 0x%x, DINDEX = 0x%x\n",
9106 ahd_name(ahd), ahd_inw(ahd, REG0), ahd_inw(ahd, SINDEX),
9107 ahd_inw(ahd, DINDEX));
9108 printf("%s: SCBPTR == 0x%x, SCB_NEXT == 0x%x, SCB_NEXT2 == 0x%x\n",
9109 ahd_name(ahd), ahd_get_scbptr(ahd),
9110 ahd_inw_scbram(ahd, SCB_NEXT),
9111 ahd_inw_scbram(ahd, SCB_NEXT2));
9112 printf("CDB %x %x %x %x %x %x\n",
9113 ahd_inb_scbram(ahd, SCB_CDB_STORE),
9114 ahd_inb_scbram(ahd, SCB_CDB_STORE+1),
9115 ahd_inb_scbram(ahd, SCB_CDB_STORE+2),
9116 ahd_inb_scbram(ahd, SCB_CDB_STORE+3),
9117 ahd_inb_scbram(ahd, SCB_CDB_STORE+4),
9118 ahd_inb_scbram(ahd, SCB_CDB_STORE+5));
9120 for (i = 0; i < ahd->stack_size; i++) {
9121 ahd->saved_stack[i] =
9122 ahd_inb(ahd, STACK)|(ahd_inb(ahd, STACK) << 8);
9123 printf(" 0x%x", ahd->saved_stack[i]);
9125 for (i = ahd->stack_size-1; i >= 0; i--) {
9126 ahd_outb(ahd, STACK, ahd->saved_stack[i] & 0xFF);
9127 ahd_outb(ahd, STACK, (ahd->saved_stack[i] >> 8) & 0xFF);
9129 printf("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n");
9130 ahd_restore_modes(ahd, saved_modes);
9136 ahd_dump_scbs(struct ahd_softc *ahd)
9138 ahd_mode_state saved_modes;
9139 u_int saved_scb_index;
9142 saved_modes = ahd_save_modes(ahd);
9143 ahd_set_modes(ahd, AHD_MODE_SCSI, AHD_MODE_SCSI);
9144 saved_scb_index = ahd_get_scbptr(ahd);
9145 for (i = 0; i < AHD_SCB_MAX; i++) {
9146 ahd_set_scbptr(ahd, i);
9148 printf("(CTRL 0x%x ID 0x%x N 0x%x N2 0x%x SG 0x%x, RSG 0x%x)\n",
9149 ahd_inb_scbram(ahd, SCB_CONTROL),
9150 ahd_inb_scbram(ahd, SCB_SCSIID),
9151 ahd_inw_scbram(ahd, SCB_NEXT),
9152 ahd_inw_scbram(ahd, SCB_NEXT2),
9153 ahd_inl_scbram(ahd, SCB_SGPTR),
9154 ahd_inl_scbram(ahd, SCB_RESIDUAL_SGPTR));
9157 ahd_set_scbptr(ahd, saved_scb_index);
9158 ahd_restore_modes(ahd, saved_modes);
9161 /**************************** Flexport Logic **********************************/
9163 * Read count 16bit words from 16bit word address start_addr from the
9164 * SEEPROM attached to the controller, into buf, using the controller's
9165 * SEEPROM reading state machine. Optionally treat the data as a byte
9166 * stream in terms of byte order.
9169 ahd_read_seeprom(struct ahd_softc *ahd, uint16_t *buf,
9170 u_int start_addr, u_int count, int bytestream)
9177 * If we never make it through the loop even once,
9178 * we were passed invalid arguments.
9181 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
9182 end_addr = start_addr + count;
9183 for (cur_addr = start_addr; cur_addr < end_addr; cur_addr++) {
9185 ahd_outb(ahd, SEEADR, cur_addr);
9186 ahd_outb(ahd, SEECTL, SEEOP_READ | SEESTART);
9188 error = ahd_wait_seeprom(ahd);
9191 if (bytestream != 0) {
9192 uint8_t *bytestream_ptr;
9194 bytestream_ptr = (uint8_t *)buf;
9195 *bytestream_ptr++ = ahd_inb(ahd, SEEDAT);
9196 *bytestream_ptr = ahd_inb(ahd, SEEDAT+1);
9199 * ahd_inw() already handles machine byte order.
9201 *buf = ahd_inw(ahd, SEEDAT);
9209 * Write count 16bit words from buf, into SEEPROM attache to the
9210 * controller starting at 16bit word address start_addr, using the
9211 * controller's SEEPROM writing state machine.
9214 ahd_write_seeprom(struct ahd_softc *ahd, uint16_t *buf,
9215 u_int start_addr, u_int count)
9222 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
9225 /* Place the chip into write-enable mode */
9226 ahd_outb(ahd, SEEADR, SEEOP_EWEN_ADDR);
9227 ahd_outb(ahd, SEECTL, SEEOP_EWEN | SEESTART);
9228 error = ahd_wait_seeprom(ahd);
9233 * Write the data. If we don't get throught the loop at
9234 * least once, the arguments were invalid.
9237 end_addr = start_addr + count;
9238 for (cur_addr = start_addr; cur_addr < end_addr; cur_addr++) {
9239 ahd_outw(ahd, SEEDAT, *buf++);
9240 ahd_outb(ahd, SEEADR, cur_addr);
9241 ahd_outb(ahd, SEECTL, SEEOP_WRITE | SEESTART);
9243 retval = ahd_wait_seeprom(ahd);
9251 ahd_outb(ahd, SEEADR, SEEOP_EWDS_ADDR);
9252 ahd_outb(ahd, SEECTL, SEEOP_EWDS | SEESTART);
9253 error = ahd_wait_seeprom(ahd);
9260 * Wait ~100us for the serial eeprom to satisfy our request.
9263 ahd_wait_seeprom(struct ahd_softc *ahd)
9268 while ((ahd_inb(ahd, SEESTAT) & (SEEARBACK|SEEBUSY)) != 0 && --cnt)
9277 * Validate the two checksums in the per_channel
9278 * vital product data struct.
9281 ahd_verify_vpd_cksum(struct vpd_config *vpd)
9288 vpdarray = (uint8_t *)vpd;
9289 maxaddr = offsetof(struct vpd_config, vpd_checksum);
9291 for (i = offsetof(struct vpd_config, resource_type); i < maxaddr; i++)
9292 checksum = checksum + vpdarray[i];
9294 || (-checksum & 0xFF) != vpd->vpd_checksum)
9298 maxaddr = offsetof(struct vpd_config, checksum);
9299 for (i = offsetof(struct vpd_config, default_target_flags);
9301 checksum = checksum + vpdarray[i];
9303 || (-checksum & 0xFF) != vpd->checksum)
9309 ahd_verify_cksum(struct seeprom_config *sc)
9316 maxaddr = (sizeof(*sc)/2) - 1;
9318 scarray = (uint16_t *)sc;
9320 for (i = 0; i < maxaddr; i++)
9321 checksum = checksum + scarray[i];
9323 || (checksum & 0xFFFF) != sc->checksum) {
9331 ahd_acquire_seeprom(struct ahd_softc *ahd)
9334 * We should be able to determine the SEEPROM type
9335 * from the flexport logic, but unfortunately not
9336 * all implementations have this logic and there is
9337 * no programatic method for determining if the logic
9345 error = ahd_read_flexport(ahd, FLXADDR_ROMSTAT_CURSENSECTL, &seetype);
9347 || ((seetype & FLX_ROMSTAT_SEECFG) == FLX_ROMSTAT_SEE_NONE))
9354 ahd_release_seeprom(struct ahd_softc *ahd)
9356 /* Currently a no-op */
9360 ahd_write_flexport(struct ahd_softc *ahd, u_int addr, u_int value)
9364 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
9366 panic("ahd_write_flexport: address out of range");
9367 ahd_outb(ahd, BRDCTL, BRDEN|(addr << 3));
9368 error = ahd_wait_flexport(ahd);
9371 ahd_outb(ahd, BRDDAT, value);
9372 ahd_flush_device_writes(ahd);
9373 ahd_outb(ahd, BRDCTL, BRDSTB|BRDEN|(addr << 3));
9374 ahd_flush_device_writes(ahd);
9375 ahd_outb(ahd, BRDCTL, BRDEN|(addr << 3));
9376 ahd_flush_device_writes(ahd);
9377 ahd_outb(ahd, BRDCTL, 0);
9378 ahd_flush_device_writes(ahd);
9383 ahd_read_flexport(struct ahd_softc *ahd, u_int addr, uint8_t *value)
9387 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
9389 panic("ahd_read_flexport: address out of range");
9390 ahd_outb(ahd, BRDCTL, BRDRW|BRDEN|(addr << 3));
9391 error = ahd_wait_flexport(ahd);
9394 *value = ahd_inb(ahd, BRDDAT);
9395 ahd_outb(ahd, BRDCTL, 0);
9396 ahd_flush_device_writes(ahd);
9401 * Wait at most 2 seconds for flexport arbitration to succeed.
9404 ahd_wait_flexport(struct ahd_softc *ahd)
9408 AHD_ASSERT_MODES(ahd, AHD_MODE_SCSI_MSK, AHD_MODE_SCSI_MSK);
9409 cnt = 1000000 * 2 / 5;
9410 while ((ahd_inb(ahd, BRDCTL) & FLXARBACK) == 0 && --cnt)
9418 /************************* Target Mode ****************************************/
9419 #ifdef AHD_TARGET_MODE
9421 ahd_find_tmode_devs(struct ahd_softc *ahd, struct cam_sim *sim, union ccb *ccb,
9422 struct ahd_tmode_tstate **tstate,
9423 struct ahd_tmode_lstate **lstate,
9424 int notfound_failure)
9427 if ((ahd->features & AHD_TARGETMODE) == 0)
9428 return (CAM_REQ_INVALID);
9431 * Handle the 'black hole' device that sucks up
9432 * requests to unattached luns on enabled targets.
9434 if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD
9435 && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) {
9437 *lstate = ahd->black_hole;
9441 max_id = (ahd->features & AHD_WIDE) ? 15 : 7;
9442 if (ccb->ccb_h.target_id > max_id)
9443 return (CAM_TID_INVALID);
9445 if (ccb->ccb_h.target_lun >= AHD_NUM_LUNS)
9446 return (CAM_LUN_INVALID);
9448 *tstate = ahd->enabled_targets[ccb->ccb_h.target_id];
9450 if (*tstate != NULL)
9452 (*tstate)->enabled_luns[ccb->ccb_h.target_lun];
9455 if (notfound_failure != 0 && *lstate == NULL)
9456 return (CAM_PATH_INVALID);
9458 return (CAM_REQ_CMP);
9462 ahd_handle_en_lun(struct ahd_softc *ahd, struct cam_sim *sim, union ccb *ccb)
9465 struct ahd_tmode_tstate *tstate;
9466 struct ahd_tmode_lstate *lstate;
9467 struct ccb_en_lun *cel;
9475 status = ahd_find_tmode_devs(ahd, sim, ccb, &tstate, &lstate,
9476 /*notfound_failure*/FALSE);
9478 if (status != CAM_REQ_CMP) {
9479 ccb->ccb_h.status = status;
9483 if ((ahd->features & AHD_MULTIROLE) != 0) {
9486 our_id = ahd->our_id;
9487 if (ccb->ccb_h.target_id != our_id) {
9488 if ((ahd->features & AHD_MULTI_TID) != 0
9489 && (ahd->flags & AHD_INITIATORROLE) != 0) {
9491 * Only allow additional targets if
9492 * the initiator role is disabled.
9493 * The hardware cannot handle a re-select-in
9494 * on the initiator id during a re-select-out
9495 * on a different target id.
9497 status = CAM_TID_INVALID;
9498 } else if ((ahd->flags & AHD_INITIATORROLE) != 0
9499 || ahd->enabled_luns > 0) {
9501 * Only allow our target id to change
9502 * if the initiator role is not configured
9503 * and there are no enabled luns which
9504 * are attached to the currently registered
9507 status = CAM_TID_INVALID;
9512 if (status != CAM_REQ_CMP) {
9513 ccb->ccb_h.status = status;
9518 * We now have an id that is valid.
9519 * If we aren't in target mode, switch modes.
9521 if ((ahd->flags & AHD_TARGETROLE) == 0
9522 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) {
9525 printf("Configuring Target Mode\n");
9527 if (LIST_FIRST(&ahd->pending_scbs) != NULL) {
9528 ccb->ccb_h.status = CAM_BUSY;
9529 ahd_unlock(ahd, &s);
9532 ahd->flags |= AHD_TARGETROLE;
9533 if ((ahd->features & AHD_MULTIROLE) == 0)
9534 ahd->flags &= ~AHD_INITIATORROLE;
9538 ahd_unlock(ahd, &s);
9541 target = ccb->ccb_h.target_id;
9542 lun = ccb->ccb_h.target_lun;
9543 channel = SIM_CHANNEL(ahd, sim);
9544 target_mask = 0x01 << target;
9548 if (cel->enable != 0) {
9551 /* Are we already enabled?? */
9552 if (lstate != NULL) {
9553 xpt_print_path(ccb->ccb_h.path);
9554 printf("Lun already enabled\n");
9555 ccb->ccb_h.status = CAM_LUN_ALRDY_ENA;
9559 if (cel->grp6_len != 0
9560 || cel->grp7_len != 0) {
9562 * Don't (yet?) support vendor
9563 * specific commands.
9565 ccb->ccb_h.status = CAM_REQ_INVALID;
9566 printf("Non-zero Group Codes\n");
9572 * Setup our data structures.
9574 if (target != CAM_TARGET_WILDCARD && tstate == NULL) {
9575 tstate = ahd_alloc_tstate(ahd, target, channel);
9576 if (tstate == NULL) {
9577 xpt_print_path(ccb->ccb_h.path);
9578 printf("Couldn't allocate tstate\n");
9579 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
9583 lstate = malloc(sizeof(*lstate), M_DEVBUF, M_NOWAIT);
9584 if (lstate == NULL) {
9585 xpt_print_path(ccb->ccb_h.path);
9586 printf("Couldn't allocate lstate\n");
9587 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
9590 memset(lstate, 0, sizeof(*lstate));
9591 status = xpt_create_path(&lstate->path, /*periph*/NULL,
9592 xpt_path_path_id(ccb->ccb_h.path),
9593 xpt_path_target_id(ccb->ccb_h.path),
9594 xpt_path_lun_id(ccb->ccb_h.path));
9595 if (status != CAM_REQ_CMP) {
9596 free(lstate, M_DEVBUF);
9597 xpt_print_path(ccb->ccb_h.path);
9598 printf("Couldn't allocate path\n");
9599 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
9602 SLIST_INIT(&lstate->accept_tios);
9603 SLIST_INIT(&lstate->immed_notifies);
9606 if (target != CAM_TARGET_WILDCARD) {
9607 tstate->enabled_luns[lun] = lstate;
9608 ahd->enabled_luns++;
9610 if ((ahd->features & AHD_MULTI_TID) != 0) {
9613 targid_mask = ahd_inw(ahd, TARGID);
9614 targid_mask |= target_mask;
9615 ahd_outw(ahd, TARGID, targid_mask);
9616 ahd_update_scsiid(ahd, targid_mask);
9621 channel = SIM_CHANNEL(ahd, sim);
9622 our_id = SIM_SCSI_ID(ahd, sim);
9625 * This can only happen if selections
9628 if (target != our_id) {
9633 sblkctl = ahd_inb(ahd, SBLKCTL);
9634 cur_channel = (sblkctl & SELBUSB)
9636 if ((ahd->features & AHD_TWIN) == 0)
9638 swap = cur_channel != channel;
9639 ahd->our_id = target;
9642 ahd_outb(ahd, SBLKCTL,
9645 ahd_outb(ahd, SCSIID, target);
9648 ahd_outb(ahd, SBLKCTL, sblkctl);
9652 ahd->black_hole = lstate;
9653 /* Allow select-in operations */
9654 if (ahd->black_hole != NULL && ahd->enabled_luns > 0) {
9655 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE);
9657 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq1);
9658 scsiseq1 = ahd_inb(ahd, SCSISEQ1);
9660 ahd_outb(ahd, SCSISEQ1, scsiseq1);
9663 ahd_unlock(ahd, &s);
9664 ccb->ccb_h.status = CAM_REQ_CMP;
9665 xpt_print_path(ccb->ccb_h.path);
9666 printf("Lun now enabled for target mode\n");
9671 if (lstate == NULL) {
9672 ccb->ccb_h.status = CAM_LUN_INVALID;
9678 ccb->ccb_h.status = CAM_REQ_CMP;
9679 LIST_FOREACH(scb, &ahd->pending_scbs, pending_links) {
9680 struct ccb_hdr *ccbh;
9682 ccbh = &scb->io_ctx->ccb_h;
9683 if (ccbh->func_code == XPT_CONT_TARGET_IO
9684 && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){
9685 printf("CTIO pending\n");
9686 ccb->ccb_h.status = CAM_REQ_INVALID;
9687 ahd_unlock(ahd, &s);
9692 if (SLIST_FIRST(&lstate->accept_tios) != NULL) {
9693 printf("ATIOs pending\n");
9694 ccb->ccb_h.status = CAM_REQ_INVALID;
9697 if (SLIST_FIRST(&lstate->immed_notifies) != NULL) {
9698 printf("INOTs pending\n");
9699 ccb->ccb_h.status = CAM_REQ_INVALID;
9702 if (ccb->ccb_h.status != CAM_REQ_CMP) {
9703 ahd_unlock(ahd, &s);
9707 xpt_print_path(ccb->ccb_h.path);
9708 printf("Target mode disabled\n");
9709 xpt_free_path(lstate->path);
9710 free(lstate, M_DEVBUF);
9713 /* Can we clean up the target too? */
9714 if (target != CAM_TARGET_WILDCARD) {
9715 tstate->enabled_luns[lun] = NULL;
9716 ahd->enabled_luns--;
9717 for (empty = 1, i = 0; i < 8; i++)
9718 if (tstate->enabled_luns[i] != NULL) {
9724 ahd_free_tstate(ahd, target, channel,
9726 if (ahd->features & AHD_MULTI_TID) {
9729 targid_mask = ahd_inw(ahd, TARGID);
9730 targid_mask &= ~target_mask;
9731 ahd_outw(ahd, TARGID, targid_mask);
9732 ahd_update_scsiid(ahd, targid_mask);
9737 ahd->black_hole = NULL;
9740 * We can't allow selections without
9741 * our black hole device.
9745 if (ahd->enabled_luns == 0) {
9746 /* Disallow select-in */
9749 scsiseq1 = ahd_inb(ahd, SCSISEQ_TEMPLATE);
9750 scsiseq1 &= ~ENSELI;
9751 ahd_outb(ahd, SCSISEQ_TEMPLATE, scsiseq1);
9752 scsiseq1 = ahd_inb(ahd, SCSISEQ1);
9753 scsiseq1 &= ~ENSELI;
9754 ahd_outb(ahd, SCSISEQ1, scsiseq1);
9756 if ((ahd->features & AHD_MULTIROLE) == 0) {
9757 printf("Configuring Initiator Mode\n");
9758 ahd->flags &= ~AHD_TARGETROLE;
9759 ahd->flags |= AHD_INITIATORROLE;
9764 * Unpaused. The extra unpause
9765 * that follows is harmless.
9770 ahd_unlock(ahd, &s);
9776 ahd_update_scsiid(struct ahd_softc *ahd, u_int targid_mask)
9782 if ((ahd->features & AHD_MULTI_TID) == 0)
9783 panic("ahd_update_scsiid called on non-multitid unit\n");
9786 * Since we will rely on the TARGID mask
9787 * for selection enables, ensure that OID
9788 * in SCSIID is not set to some other ID
9789 * that we don't want to allow selections on.
9791 if ((ahd->features & AHD_ULTRA2) != 0)
9792 scsiid = ahd_inb(ahd, SCSIID_ULTRA2);
9794 scsiid = ahd_inb(ahd, SCSIID);
9795 scsiid_mask = 0x1 << (scsiid & OID);
9796 if ((targid_mask & scsiid_mask) == 0) {
9799 /* ffs counts from 1 */
9800 our_id = ffs(targid_mask);
9802 our_id = ahd->our_id;
9808 if ((ahd->features & AHD_ULTRA2) != 0)
9809 ahd_outb(ahd, SCSIID_ULTRA2, scsiid);
9811 ahd_outb(ahd, SCSIID, scsiid);
9816 ahd_run_tqinfifo(struct ahd_softc *ahd, int paused)
9818 struct target_cmd *cmd;
9820 ahd_sync_tqinfifo(ahd, BUS_DMASYNC_POSTREAD);
9821 while ((cmd = &ahd->targetcmds[ahd->tqinfifonext])->cmd_valid != 0) {
9824 * Only advance through the queue if we
9825 * have the resources to process the command.
9827 if (ahd_handle_target_cmd(ahd, cmd) != 0)
9831 ahd_dmamap_sync(ahd, ahd->shared_data_dmat,
9832 ahd->shared_data_map.dmamap,
9833 ahd_targetcmd_offset(ahd, ahd->tqinfifonext),
9834 sizeof(struct target_cmd),
9835 BUS_DMASYNC_PREREAD);
9836 ahd->tqinfifonext++;
9839 * Lazily update our position in the target mode incoming
9840 * command queue as seen by the sequencer.
9842 if ((ahd->tqinfifonext & (HOST_TQINPOS - 1)) == 1) {
9845 hs_mailbox = ahd_inb(ahd, HS_MAILBOX);
9846 hs_mailbox &= ~HOST_TQINPOS;
9847 hs_mailbox |= ahd->tqinfifonext & HOST_TQINPOS;
9848 ahd_outb(ahd, HS_MAILBOX, hs_mailbox);
9854 ahd_handle_target_cmd(struct ahd_softc *ahd, struct target_cmd *cmd)
9856 struct ahd_tmode_tstate *tstate;
9857 struct ahd_tmode_lstate *lstate;
9858 struct ccb_accept_tio *atio;
9864 initiator = SCSIID_TARGET(ahd, cmd->scsiid);
9865 target = SCSIID_OUR_ID(cmd->scsiid);
9866 lun = (cmd->identify & MSG_IDENTIFY_LUNMASK);
9869 tstate = ahd->enabled_targets[target];
9872 lstate = tstate->enabled_luns[lun];
9875 * Commands for disabled luns go to the black hole driver.
9878 lstate = ahd->black_hole;
9880 atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios);
9882 ahd->flags |= AHD_TQINFIFO_BLOCKED;
9884 * Wait for more ATIOs from the peripheral driver for this lun.
9888 ahd->flags &= ~AHD_TQINFIFO_BLOCKED;
9890 if ((ahd_debug & AHD_SHOW_TQIN) != 0)
9891 printf("Incoming command from %d for %d:%d%s\n",
9892 initiator, target, lun,
9893 lstate == ahd->black_hole ? "(Black Holed)" : "");
9895 SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle);
9897 if (lstate == ahd->black_hole) {
9898 /* Fill in the wildcards */
9899 atio->ccb_h.target_id = target;
9900 atio->ccb_h.target_lun = lun;
9904 * Package it up and send it off to
9905 * whomever has this lun enabled.
9907 atio->sense_len = 0;
9908 atio->init_id = initiator;
9909 if (byte[0] != 0xFF) {
9910 /* Tag was included */
9911 atio->tag_action = *byte++;
9912 atio->tag_id = *byte++;
9913 atio->ccb_h.flags = CAM_TAG_ACTION_VALID;
9915 atio->ccb_h.flags = 0;
9919 /* Okay. Now determine the cdb size based on the command code */
9920 switch (*byte >> CMD_GROUP_CODE_SHIFT) {
9936 /* Only copy the opcode. */
9938 printf("Reserved or VU command code type encountered\n");
9942 memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len);
9944 atio->ccb_h.status |= CAM_CDB_RECVD;
9946 if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) {
9948 * We weren't allowed to disconnect.
9949 * We're hanging on the bus until a
9950 * continue target I/O comes in response
9951 * to this accept tio.
9954 if ((ahd_debug & AHD_SHOW_TQIN) != 0)
9955 printf("Received Immediate Command %d:%d:%d - %p\n",
9956 initiator, target, lun, ahd->pending_device);
9958 ahd->pending_device = lstate;
9959 ahd_freeze_ccb((union ccb *)atio);
9960 atio->ccb_h.flags |= CAM_DIS_DISCONNECT;
9962 xpt_done((union ccb*)atio);