2 * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
6 * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
7 * Copyright (C) 2006 Olof Johansson <olof@lixom.net>
9 * Dynamic DMA mapping support, pSeries-specific parts, both SMP and LPAR.
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 #include <linux/init.h>
28 #include <linux/types.h>
29 #include <linux/slab.h>
31 #include <linux/spinlock.h>
32 #include <linux/string.h>
33 #include <linux/pci.h>
34 #include <linux/dma-mapping.h>
38 #include <asm/iommu.h>
39 #include <asm/pci-bridge.h>
40 #include <asm/machdep.h>
41 #include <asm/abs_addr.h>
42 #include <asm/pSeries_reconfig.h>
43 #include <asm/firmware.h>
45 #include <asm/ppc-pci.h>
48 #include "plpar_wrappers.h"
52 static void tce_build_pSeries(struct iommu_table *tbl, long index,
53 long npages, unsigned long uaddr,
54 enum dma_data_direction direction)
60 proto_tce = TCE_PCI_READ; // Read allowed
62 if (direction != DMA_TO_DEVICE)
63 proto_tce |= TCE_PCI_WRITE;
65 tcep = ((u64 *)tbl->it_base) + index;
68 /* can't move this out since we might cross LMB boundary */
69 rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT;
70 *tcep = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT;
72 uaddr += TCE_PAGE_SIZE;
78 static void tce_free_pSeries(struct iommu_table *tbl, long index, long npages)
82 tcep = ((u64 *)tbl->it_base) + index;
88 static unsigned long tce_get_pseries(struct iommu_table *tbl, long index)
92 tcep = ((u64 *)tbl->it_base) + index;
97 static void tce_build_pSeriesLP(struct iommu_table *tbl, long tcenum,
98 long npages, unsigned long uaddr,
99 enum dma_data_direction direction)
105 rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT;
106 proto_tce = TCE_PCI_READ;
107 if (direction != DMA_TO_DEVICE)
108 proto_tce |= TCE_PCI_WRITE;
111 tce = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT;
112 rc = plpar_tce_put((u64)tbl->it_index, (u64)tcenum << 12, tce);
114 if (rc && printk_ratelimit()) {
115 printk("tce_build_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc);
116 printk("\tindex = 0x%lx\n", (u64)tbl->it_index);
117 printk("\ttcenum = 0x%lx\n", (u64)tcenum);
118 printk("\ttce val = 0x%lx\n", tce );
119 show_stack(current, (unsigned long *)__get_SP());
127 static DEFINE_PER_CPU(u64 *, tce_page) = NULL;
129 static void tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum,
130 long npages, unsigned long uaddr,
131 enum dma_data_direction direction)
140 return tce_build_pSeriesLP(tbl, tcenum, npages, uaddr,
143 tcep = __get_cpu_var(tce_page);
145 /* This is safe to do since interrupts are off when we're called
146 * from iommu_alloc{,_sg}()
149 tcep = (u64 *)__get_free_page(GFP_ATOMIC);
150 /* If allocation fails, fall back to the loop implementation */
152 return tce_build_pSeriesLP(tbl, tcenum, npages,
154 __get_cpu_var(tce_page) = tcep;
157 rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT;
158 proto_tce = TCE_PCI_READ;
159 if (direction != DMA_TO_DEVICE)
160 proto_tce |= TCE_PCI_WRITE;
162 /* We can map max one pageful of TCEs at a time */
165 * Set up the page with TCE data, looping through and setting
168 limit = min_t(long, npages, 4096/TCE_ENTRY_SIZE);
170 for (l = 0; l < limit; l++) {
171 tcep[l] = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT;
175 rc = plpar_tce_put_indirect((u64)tbl->it_index,
177 (u64)virt_to_abs(tcep),
182 } while (npages > 0 && !rc);
184 if (rc && printk_ratelimit()) {
185 printk("tce_buildmulti_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc);
186 printk("\tindex = 0x%lx\n", (u64)tbl->it_index);
187 printk("\tnpages = 0x%lx\n", (u64)npages);
188 printk("\ttce[0] val = 0x%lx\n", tcep[0]);
189 show_stack(current, (unsigned long *)__get_SP());
193 static void tce_free_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages)
198 rc = plpar_tce_put((u64)tbl->it_index, (u64)tcenum << 12, 0);
200 if (rc && printk_ratelimit()) {
201 printk("tce_free_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc);
202 printk("\tindex = 0x%lx\n", (u64)tbl->it_index);
203 printk("\ttcenum = 0x%lx\n", (u64)tcenum);
204 show_stack(current, (unsigned long *)__get_SP());
212 static void tce_freemulti_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages)
216 rc = plpar_tce_stuff((u64)tbl->it_index, (u64)tcenum << 12, 0, npages);
218 if (rc && printk_ratelimit()) {
219 printk("tce_freemulti_pSeriesLP: plpar_tce_stuff failed\n");
220 printk("\trc = %ld\n", rc);
221 printk("\tindex = 0x%lx\n", (u64)tbl->it_index);
222 printk("\tnpages = 0x%lx\n", (u64)npages);
223 show_stack(current, (unsigned long *)__get_SP());
227 static unsigned long tce_get_pSeriesLP(struct iommu_table *tbl, long tcenum)
230 unsigned long tce_ret;
232 rc = plpar_tce_get((u64)tbl->it_index, (u64)tcenum << 12, &tce_ret);
234 if (rc && printk_ratelimit()) {
235 printk("tce_get_pSeriesLP: plpar_tce_get failed. rc=%ld\n",
237 printk("\tindex = 0x%lx\n", (u64)tbl->it_index);
238 printk("\ttcenum = 0x%lx\n", (u64)tcenum);
239 show_stack(current, (unsigned long *)__get_SP());
246 static void iommu_table_setparms(struct pci_controller *phb,
247 struct device_node *dn,
248 struct iommu_table *tbl)
250 struct device_node *node;
251 const unsigned long *basep;
254 node = (struct device_node *)phb->arch_data;
256 basep = of_get_property(node, "linux,tce-base", NULL);
257 sizep = of_get_property(node, "linux,tce-size", NULL);
258 if (basep == NULL || sizep == NULL) {
259 printk(KERN_ERR "PCI_DMA: iommu_table_setparms: %s has "
260 "missing tce entries !\n", dn->full_name);
264 tbl->it_base = (unsigned long)__va(*basep);
266 #ifndef CONFIG_CRASH_DUMP
267 memset((void *)tbl->it_base, 0, *sizep);
270 tbl->it_busno = phb->bus->number;
272 /* Units of tce entries */
273 tbl->it_offset = phb->dma_window_base_cur >> IOMMU_PAGE_SHIFT;
275 /* Test if we are going over 2GB of DMA space */
276 if (phb->dma_window_base_cur + phb->dma_window_size > 0x80000000ul) {
277 udbg_printf("PCI_DMA: Unexpected number of IOAs under this PHB.\n");
278 panic("PCI_DMA: Unexpected number of IOAs under this PHB.\n");
281 phb->dma_window_base_cur += phb->dma_window_size;
283 /* Set the tce table size - measured in entries */
284 tbl->it_size = phb->dma_window_size >> IOMMU_PAGE_SHIFT;
287 tbl->it_blocksize = 16;
288 tbl->it_type = TCE_PCI;
292 * iommu_table_setparms_lpar
294 * Function: On pSeries LPAR systems, return TCE table info, given a pci bus.
296 static void iommu_table_setparms_lpar(struct pci_controller *phb,
297 struct device_node *dn,
298 struct iommu_table *tbl,
299 const void *dma_window)
301 unsigned long offset, size;
303 tbl->it_busno = PCI_DN(dn)->bussubno;
304 of_parse_dma_window(dn, dma_window, &tbl->it_index, &offset, &size);
307 tbl->it_blocksize = 16;
308 tbl->it_type = TCE_PCI;
309 tbl->it_offset = offset >> IOMMU_PAGE_SHIFT;
310 tbl->it_size = size >> IOMMU_PAGE_SHIFT;
313 static void pci_dma_bus_setup_pSeries(struct pci_bus *bus)
315 struct device_node *dn;
316 struct iommu_table *tbl;
317 struct device_node *isa_dn, *isa_dn_orig;
318 struct device_node *tmp;
322 dn = pci_bus_to_OF_node(bus);
324 DBG("pci_dma_bus_setup_pSeries: setting up bus %s\n", dn->full_name);
327 /* This is not a root bus, any setup will be done for the
328 * device-side of the bridge in iommu_dev_setup_pSeries().
334 /* Check if the ISA bus on the system is under
337 isa_dn = isa_dn_orig = of_find_node_by_type(NULL, "isa");
339 while (isa_dn && isa_dn != dn)
340 isa_dn = isa_dn->parent;
343 of_node_put(isa_dn_orig);
345 /* Count number of direct PCI children of the PHB. */
346 for (children = 0, tmp = dn->child; tmp; tmp = tmp->sibling)
349 DBG("Children: %d\n", children);
351 /* Calculate amount of DMA window per slot. Each window must be
352 * a power of two (due to pci_alloc_consistent requirements).
354 * Keep 256MB aside for PHBs with ISA.
358 /* No ISA/IDE - just set window size and return */
359 pci->phb->dma_window_size = 0x80000000ul; /* To be divided */
361 while (pci->phb->dma_window_size * children > 0x80000000ul)
362 pci->phb->dma_window_size >>= 1;
363 DBG("No ISA/IDE, window size is 0x%lx\n",
364 pci->phb->dma_window_size);
365 pci->phb->dma_window_base_cur = 0;
370 /* If we have ISA, then we probably have an IDE
371 * controller too. Allocate a 128MB table but
372 * skip the first 128MB to avoid stepping on ISA
375 pci->phb->dma_window_size = 0x8000000ul;
376 pci->phb->dma_window_base_cur = 0x8000000ul;
378 tbl = kmalloc_node(sizeof(struct iommu_table), GFP_KERNEL,
381 iommu_table_setparms(pci->phb, dn, tbl);
382 pci->iommu_table = iommu_init_table(tbl, pci->phb->node);
384 /* Divide the rest (1.75GB) among the children */
385 pci->phb->dma_window_size = 0x80000000ul;
386 while (pci->phb->dma_window_size * children > 0x70000000ul)
387 pci->phb->dma_window_size >>= 1;
389 DBG("ISA/IDE, window size is 0x%lx\n", pci->phb->dma_window_size);
394 static void pci_dma_bus_setup_pSeriesLP(struct pci_bus *bus)
396 struct iommu_table *tbl;
397 struct device_node *dn, *pdn;
399 const void *dma_window = NULL;
401 dn = pci_bus_to_OF_node(bus);
403 DBG("pci_dma_bus_setup_pSeriesLP: setting up bus %s\n", dn->full_name);
405 /* Find nearest ibm,dma-window, walking up the device tree */
406 for (pdn = dn; pdn != NULL; pdn = pdn->parent) {
407 dma_window = of_get_property(pdn, "ibm,dma-window", NULL);
408 if (dma_window != NULL)
412 if (dma_window == NULL) {
413 DBG(" no ibm,dma-window property !\n");
419 DBG(" parent is %s, iommu_table: 0x%p\n",
420 pdn->full_name, ppci->iommu_table);
422 if (!ppci->iommu_table) {
423 /* Bussubno hasn't been copied yet.
424 * Do it now because iommu_table_setparms_lpar needs it.
427 ppci->bussubno = bus->number;
429 tbl = kmalloc_node(sizeof(struct iommu_table), GFP_KERNEL,
432 iommu_table_setparms_lpar(ppci->phb, pdn, tbl, dma_window);
434 ppci->iommu_table = iommu_init_table(tbl, ppci->phb->node);
435 DBG(" created table: %p\n", ppci->iommu_table);
439 PCI_DN(dn)->iommu_table = ppci->iommu_table;
443 static void pci_dma_dev_setup_pSeries(struct pci_dev *dev)
445 struct device_node *dn;
446 struct iommu_table *tbl;
448 DBG("pci_dma_dev_setup_pSeries: %s\n", pci_name(dev));
450 dn = dev->dev.archdata.of_node;
452 /* If we're the direct child of a root bus, then we need to allocate
453 * an iommu table ourselves. The bus setup code should have setup
454 * the window sizes already.
456 if (!dev->bus->self) {
457 struct pci_controller *phb = PCI_DN(dn)->phb;
459 DBG(" --> first child, no bridge. Allocating iommu table.\n");
460 tbl = kmalloc_node(sizeof(struct iommu_table), GFP_KERNEL,
462 iommu_table_setparms(phb, dn, tbl);
463 PCI_DN(dn)->iommu_table = iommu_init_table(tbl, phb->node);
464 dev->dev.archdata.dma_data = PCI_DN(dn)->iommu_table;
468 /* If this device is further down the bus tree, search upwards until
469 * an already allocated iommu table is found and use that.
472 while (dn && PCI_DN(dn) && PCI_DN(dn)->iommu_table == NULL)
475 if (dn && PCI_DN(dn))
476 dev->dev.archdata.dma_data = PCI_DN(dn)->iommu_table;
478 printk(KERN_WARNING "iommu: Device %s has no iommu table\n",
482 static void pci_dma_dev_setup_pSeriesLP(struct pci_dev *dev)
484 struct device_node *pdn, *dn;
485 struct iommu_table *tbl;
486 const void *dma_window = NULL;
489 DBG("pci_dma_dev_setup_pSeriesLP: %s\n", pci_name(dev));
491 /* dev setup for LPAR is a little tricky, since the device tree might
492 * contain the dma-window properties per-device and not neccesarily
493 * for the bus. So we need to search upwards in the tree until we
494 * either hit a dma-window property, OR find a parent with a table
497 dn = pci_device_to_OF_node(dev);
498 DBG(" node is %s\n", dn->full_name);
500 for (pdn = dn; pdn && PCI_DN(pdn) && !PCI_DN(pdn)->iommu_table;
502 dma_window = of_get_property(pdn, "ibm,dma-window", NULL);
507 DBG(" parent is %s\n", pdn->full_name);
509 /* Check for parent == NULL so we don't try to setup the empty EADS
510 * slots on POWER4 machines.
512 if (dma_window == NULL || pdn->parent == NULL) {
513 DBG(" no dma window for device, linking to parent\n");
514 dev->dev.archdata.dma_data = PCI_DN(pdn)->iommu_table;
517 DBG(" found DMA window, table: %p\n", pci->iommu_table);
520 if (!pci->iommu_table) {
521 /* iommu_table_setparms_lpar needs bussubno. */
522 pci->bussubno = pci->phb->bus->number;
524 tbl = kmalloc_node(sizeof(struct iommu_table), GFP_KERNEL,
527 iommu_table_setparms_lpar(pci->phb, pdn, tbl, dma_window);
529 pci->iommu_table = iommu_init_table(tbl, pci->phb->node);
530 DBG(" created table: %p\n", pci->iommu_table);
533 dev->dev.archdata.dma_data = pci->iommu_table;
535 #else /* CONFIG_PCI */
536 #define pci_dma_bus_setup_pSeries NULL
537 #define pci_dma_dev_setup_pSeries NULL
538 #define pci_dma_bus_setup_pSeriesLP NULL
539 #define pci_dma_dev_setup_pSeriesLP NULL
540 #endif /* !CONFIG_PCI */
542 static int iommu_reconfig_notifier(struct notifier_block *nb, unsigned long action, void *node)
545 struct device_node *np = node;
546 struct pci_dn *pci = PCI_DN(np);
549 case PSERIES_RECONFIG_REMOVE:
550 if (pci && pci->iommu_table &&
551 of_get_property(np, "ibm,dma-window", NULL))
552 iommu_free_table(np);
561 static struct notifier_block iommu_reconfig_nb = {
562 .notifier_call = iommu_reconfig_notifier,
565 /* These are called very early. */
566 void iommu_init_early_pSeries(void)
568 if (of_chosen && of_get_property(of_chosen, "linux,iommu-off", NULL)) {
569 /* Direct I/O, IOMMU off */
570 ppc_md.pci_dma_dev_setup = NULL;
571 ppc_md.pci_dma_bus_setup = NULL;
572 set_pci_dma_ops(&dma_direct_ops);
576 if (firmware_has_feature(FW_FEATURE_LPAR)) {
577 if (firmware_has_feature(FW_FEATURE_MULTITCE)) {
578 ppc_md.tce_build = tce_buildmulti_pSeriesLP;
579 ppc_md.tce_free = tce_freemulti_pSeriesLP;
581 ppc_md.tce_build = tce_build_pSeriesLP;
582 ppc_md.tce_free = tce_free_pSeriesLP;
584 ppc_md.tce_get = tce_get_pSeriesLP;
585 ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_pSeriesLP;
586 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_pSeriesLP;
588 ppc_md.tce_build = tce_build_pSeries;
589 ppc_md.tce_free = tce_free_pSeries;
590 ppc_md.tce_get = tce_get_pseries;
591 ppc_md.pci_dma_bus_setup = pci_dma_bus_setup_pSeries;
592 ppc_md.pci_dma_dev_setup = pci_dma_dev_setup_pSeries;
596 pSeries_reconfig_notifier_register(&iommu_reconfig_nb);
598 set_pci_dma_ops(&dma_iommu_ops);