2 * This file contains the functions and defines necessary to modify and
3 * use the SuperH page table tree.
5 * Copyright (C) 1999 Niibe Yutaka
6 * Copyright (C) 2002 - 2005 Paul Mundt
8 * This file is subject to the terms and conditions of the GNU General
9 * Public License. See the file "COPYING" in the main directory of this
10 * archive for more details.
12 #ifndef __ASM_SH_PGTABLE_H
13 #define __ASM_SH_PGTABLE_H
15 #include <asm-generic/pgtable-nopmd.h>
19 #include <asm/addrspace.h>
20 #include <asm/fixmap.h>
23 * ZERO_PAGE is a global shared page that is always zero: used
24 * for zero-mapped memory areas etc..
26 extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
27 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
29 #endif /* !__ASSEMBLY__ */
32 * traditional two-level paging structure
36 # define PTE_MAGNITUDE 3 /* 64-bit PTEs on extended mode SH-X2 TLB */
38 # define PTE_MAGNITUDE 2 /* 32-bit PTEs */
40 #define PTE_SHIFT PAGE_SHIFT
41 #define PTE_BITS (PTE_SHIFT - PTE_MAGNITUDE)
44 #define PGDIR_SHIFT (PTE_SHIFT + PTE_BITS)
45 #define PGDIR_BITS (32 - PGDIR_SHIFT)
46 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
47 #define PGDIR_MASK (~(PGDIR_SIZE-1))
49 /* Entries per level */
50 #define PTRS_PER_PTE (PAGE_SIZE / (1 << PTE_MAGNITUDE))
51 #define PTRS_PER_PGD (PAGE_SIZE / 4)
53 #define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE)
54 #define FIRST_USER_ADDRESS 0
56 #define PTE_PHYS_MASK (0x20000000 - PAGE_SIZE)
59 * First 1MB map is used by fixed purpose.
60 * Currently only 4-entry (16kB) is used (see arch/sh/mm/cache.c)
62 #define VMALLOC_START (P3SEG+0x00100000)
63 #define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE)
66 * Linux PTEL encoding.
68 * Hardware and software bit definitions for the PTEL value (see below for
69 * notes on SH-X2 MMUs and 64-bit PTEs):
71 * - Bits 0 and 7 are reserved on SH-3 (_PAGE_WT and _PAGE_SZ1 on SH-4).
73 * - Bit 1 is the SH-bit, but is unused on SH-3 due to an MMU bug (the
74 * hardware PTEL value can't have the SH-bit set when MMUCR.IX is set,
75 * which is the default in cpu-sh3/mmu_context.h:MMU_CONTROL_INIT).
77 * In order to keep this relatively clean, do not use these for defining
78 * SH-3 specific flags until all of the other unused bits have been
81 * - Bit 9 is reserved by everyone and used by _PAGE_PROTNONE.
83 * - Bits 10 and 11 are low bits of the PPN that are reserved on >= 4K pages.
84 * Bit 10 is used for _PAGE_ACCESSED, bit 11 remains unused.
86 * - Bits 31, 30, and 29 remain unused by everyone and can be used for future
87 * software flags, although care must be taken to update _PAGE_CLEAR_FLAGS.
89 * XXX: Leave the _PAGE_FILE and _PAGE_WT overhaul for a rainy day.
91 * SH-X2 MMUs and extended PTEs
93 * SH-X2 supports an extended mode TLB with split data arrays due to the
94 * number of bits needed for PR and SZ (now EPR and ESZ) encodings. The PR and
95 * SZ bit placeholders still exist in data array 1, but are implemented as
96 * reserved bits, with the real logic existing in data array 2.
98 * The downside to this is that we can no longer fit everything in to a 32-bit
99 * PTE encoding, so a 64-bit pte_t is necessary for these parts. On the plus
100 * side, this gives us quite a few spare bits to play with for future usage.
102 /* Legacy and compat mode bits */
103 #define _PAGE_WT 0x001 /* WT-bit on SH-4, 0 on SH-3 */
104 #define _PAGE_HW_SHARED 0x002 /* SH-bit : shared among processes */
105 #define _PAGE_DIRTY 0x004 /* D-bit : page changed */
106 #define _PAGE_CACHABLE 0x008 /* C-bit : cachable */
108 # define _PAGE_SZ0 0x010 /* SZ0-bit : Size of page */
109 # define _PAGE_RW 0x020 /* PR0-bit : write access allowed */
110 # define _PAGE_USER 0x040 /* PR1-bit : user space access allowed*/
111 # define _PAGE_SZ1 0x080 /* SZ1-bit : Size of page (on SH-4) */
113 #define _PAGE_PRESENT 0x100 /* V-bit : page is valid */
114 #define _PAGE_PROTNONE 0x200 /* software: if not present */
115 #define _PAGE_ACCESSED 0x400 /* software: page referenced */
116 #define _PAGE_FILE _PAGE_WT /* software: pagecache or swap? */
118 /* Extended mode bits */
119 #define _PAGE_EXT_ESZ0 0x0010 /* ESZ0-bit: Size of page */
120 #define _PAGE_EXT_ESZ1 0x0020 /* ESZ1-bit: Size of page */
121 #define _PAGE_EXT_ESZ2 0x0040 /* ESZ2-bit: Size of page */
122 #define _PAGE_EXT_ESZ3 0x0080 /* ESZ3-bit: Size of page */
124 #define _PAGE_EXT_USER_EXEC 0x0100 /* EPR0-bit: User space executable */
125 #define _PAGE_EXT_USER_WRITE 0x0200 /* EPR1-bit: User space writable */
126 #define _PAGE_EXT_USER_READ 0x0400 /* EPR2-bit: User space readable */
128 #define _PAGE_EXT_KERN_EXEC 0x0800 /* EPR3-bit: Kernel space executable */
129 #define _PAGE_EXT_KERN_WRITE 0x1000 /* EPR4-bit: Kernel space writable */
130 #define _PAGE_EXT_KERN_READ 0x2000 /* EPR5-bit: Kernel space readable */
132 /* Wrapper for extended mode pgprot twiddling */
134 # define _PAGE_EXT(x) ((unsigned long long)(x) << 32)
136 # define _PAGE_EXT(x) (0)
139 /* software: moves to PTEA.TC (Timing Control) */
140 #define _PAGE_PCC_AREA5 0x00000000 /* use BSC registers for area5 */
141 #define _PAGE_PCC_AREA6 0x80000000 /* use BSC registers for area6 */
143 /* software: moves to PTEA.SA[2:0] (Space Attributes) */
144 #define _PAGE_PCC_IODYN 0x00000001 /* IO space, dynamically sized bus */
145 #define _PAGE_PCC_IO8 0x20000000 /* IO space, 8 bit bus */
146 #define _PAGE_PCC_IO16 0x20000001 /* IO space, 16 bit bus */
147 #define _PAGE_PCC_COM8 0x40000000 /* Common Memory space, 8 bit bus */
148 #define _PAGE_PCC_COM16 0x40000001 /* Common Memory space, 16 bit bus */
149 #define _PAGE_PCC_ATR8 0x60000000 /* Attribute Memory space, 8 bit bus */
150 #define _PAGE_PCC_ATR16 0x60000001 /* Attribute Memory space, 6 bit bus */
152 /* Mask which drops unused bits from the PTEL value */
153 #ifdef CONFIG_CPU_SH3
154 #define _PAGE_CLEAR_FLAGS (_PAGE_PROTNONE | _PAGE_ACCESSED| \
155 _PAGE_FILE | _PAGE_SZ1 | \
158 #define _PAGE_CLEAR_FLAGS (_PAGE_PROTNONE | _PAGE_ACCESSED | _PAGE_FILE)
161 #define _PAGE_FLAGS_HARDWARE_MASK (0x1fffffff & ~(_PAGE_CLEAR_FLAGS))
163 /* Hardware flags, page size encoding */
164 #if defined(CONFIG_X2TLB)
165 # if defined(CONFIG_PAGE_SIZE_4KB)
166 # define _PAGE_FLAGS_HARD _PAGE_EXT(_PAGE_EXT_ESZ0)
167 # elif defined(CONFIG_PAGE_SIZE_8KB)
168 # define _PAGE_FLAGS_HARD _PAGE_EXT(_PAGE_EXT_ESZ1)
169 # elif defined(CONFIG_PAGE_SIZE_64KB)
170 # define _PAGE_FLAGS_HARD _PAGE_EXT(_PAGE_EXT_ESZ2)
173 # if defined(CONFIG_PAGE_SIZE_4KB)
174 # define _PAGE_FLAGS_HARD _PAGE_SZ0
175 # elif defined(CONFIG_PAGE_SIZE_64KB)
176 # define _PAGE_FLAGS_HARD _PAGE_SZ1
180 #if defined(CONFIG_X2TLB)
181 # if defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
182 # define _PAGE_SZHUGE (_PAGE_EXT_ESZ2)
183 # elif defined(CONFIG_HUGETLB_PAGE_SIZE_256K)
184 # define _PAGE_SZHUGE (_PAGE_EXT_ESZ0 | _PAGE_EXT_ESZ2)
185 # elif defined(CONFIG_HUGETLB_PAGE_SIZE_1MB)
186 # define _PAGE_SZHUGE (_PAGE_EXT_ESZ0 | _PAGE_EXT_ESZ1 | _PAGE_EXT_ESZ2)
187 # elif defined(CONFIG_HUGETLB_PAGE_SIZE_4MB)
188 # define _PAGE_SZHUGE (_PAGE_EXT_ESZ3)
189 # elif defined(CONFIG_HUGETLB_PAGE_SIZE_64MB)
190 # define _PAGE_SZHUGE (_PAGE_EXT_ESZ2 | _PAGE_EXT_ESZ3)
193 # if defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
194 # define _PAGE_SZHUGE (_PAGE_SZ1)
195 # elif defined(CONFIG_HUGETLB_PAGE_SIZE_1MB)
196 # define _PAGE_SZHUGE (_PAGE_SZ0 | _PAGE_SZ1)
201 * Stub out _PAGE_SZHUGE if we don't have a good definition for it,
202 * to make pte_mkhuge() happy.
205 # define _PAGE_SZHUGE (_PAGE_FLAGS_HARD)
208 #define _PAGE_CHG_MASK \
209 (PTE_MASK | _PAGE_ACCESSED | _PAGE_CACHABLE | _PAGE_DIRTY)
213 #if defined(CONFIG_X2TLB) /* SH-X2 TLB */
214 #define PAGE_NONE __pgprot(_PAGE_PROTNONE | _PAGE_CACHABLE | \
215 _PAGE_ACCESSED | _PAGE_FLAGS_HARD)
217 #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
218 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
219 _PAGE_EXT(_PAGE_EXT_USER_READ | \
220 _PAGE_EXT_USER_WRITE))
222 #define PAGE_EXECREAD __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
223 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
224 _PAGE_EXT(_PAGE_EXT_USER_EXEC | \
225 _PAGE_EXT_USER_READ))
227 #define PAGE_COPY PAGE_EXECREAD
229 #define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
230 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
231 _PAGE_EXT(_PAGE_EXT_USER_READ))
233 #define PAGE_WRITEONLY __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
234 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
235 _PAGE_EXT(_PAGE_EXT_USER_WRITE))
237 #define PAGE_RWX __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
238 _PAGE_CACHABLE | _PAGE_FLAGS_HARD | \
239 _PAGE_EXT(_PAGE_EXT_USER_WRITE | \
240 _PAGE_EXT_USER_READ | \
241 _PAGE_EXT_USER_EXEC))
243 #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_CACHABLE | \
244 _PAGE_DIRTY | _PAGE_ACCESSED | \
245 _PAGE_HW_SHARED | _PAGE_FLAGS_HARD | \
246 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
247 _PAGE_EXT_KERN_WRITE | \
248 _PAGE_EXT_KERN_EXEC))
250 #define PAGE_KERNEL_NOCACHE \
251 __pgprot(_PAGE_PRESENT | _PAGE_DIRTY | \
252 _PAGE_ACCESSED | _PAGE_HW_SHARED | \
254 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
255 _PAGE_EXT_KERN_WRITE | \
256 _PAGE_EXT_KERN_EXEC))
258 #define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT | _PAGE_CACHABLE | \
259 _PAGE_DIRTY | _PAGE_ACCESSED | \
260 _PAGE_HW_SHARED | _PAGE_FLAGS_HARD | \
261 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
262 _PAGE_EXT_KERN_EXEC))
264 #define PAGE_KERNEL_PCC(slot, type) \
265 __pgprot(_PAGE_PRESENT | _PAGE_DIRTY | \
266 _PAGE_ACCESSED | _PAGE_FLAGS_HARD | \
267 _PAGE_EXT(_PAGE_EXT_KERN_READ | \
268 _PAGE_EXT_KERN_WRITE | \
269 _PAGE_EXT_KERN_EXEC) \
270 (slot ? _PAGE_PCC_AREA5 : _PAGE_PCC_AREA6) | \
273 #elif defined(CONFIG_MMU) /* SH-X TLB */
274 #define PAGE_NONE __pgprot(_PAGE_PROTNONE | _PAGE_CACHABLE | \
275 _PAGE_ACCESSED | _PAGE_FLAGS_HARD)
277 #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | \
278 _PAGE_CACHABLE | _PAGE_ACCESSED | \
281 #define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_CACHABLE | \
282 _PAGE_ACCESSED | _PAGE_FLAGS_HARD)
284 #define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_CACHABLE | \
285 _PAGE_ACCESSED | _PAGE_FLAGS_HARD)
287 #define PAGE_EXECREAD PAGE_READONLY
288 #define PAGE_RWX PAGE_SHARED
289 #define PAGE_WRITEONLY PAGE_SHARED
291 #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_CACHABLE | \
292 _PAGE_DIRTY | _PAGE_ACCESSED | \
293 _PAGE_HW_SHARED | _PAGE_FLAGS_HARD)
295 #define PAGE_KERNEL_NOCACHE \
296 __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | \
297 _PAGE_ACCESSED | _PAGE_HW_SHARED | \
300 #define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT | _PAGE_CACHABLE | \
301 _PAGE_DIRTY | _PAGE_ACCESSED | \
302 _PAGE_HW_SHARED | _PAGE_FLAGS_HARD)
304 #define PAGE_KERNEL_PCC(slot, type) \
305 __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | \
306 _PAGE_ACCESSED | _PAGE_FLAGS_HARD | \
307 (slot ? _PAGE_PCC_AREA5 : _PAGE_PCC_AREA6) | \
310 #define PAGE_NONE __pgprot(0)
311 #define PAGE_SHARED __pgprot(0)
312 #define PAGE_COPY __pgprot(0)
313 #define PAGE_EXECREAD __pgprot(0)
314 #define PAGE_RWX __pgprot(0)
315 #define PAGE_READONLY __pgprot(0)
316 #define PAGE_WRITEONLY __pgprot(0)
317 #define PAGE_KERNEL __pgprot(0)
318 #define PAGE_KERNEL_NOCACHE __pgprot(0)
319 #define PAGE_KERNEL_RO __pgprot(0)
320 #define PAGE_KERNEL_PCC __pgprot(0)
323 #endif /* __ASSEMBLY__ */
326 * SH-X and lower (legacy) SuperH parts (SH-3, SH-4, some SH-4A) can't do page
327 * protection for execute, and considers it the same as a read. Also, write
328 * permission implies read permission. This is the closest we can get..
330 * SH-X2 (SH7785) and later parts take this to the opposite end of the extreme,
331 * not only supporting separate execute, read, and write bits, but having
332 * completely separate permission bits for user and kernel space.
335 #define __P000 PAGE_NONE
336 #define __P001 PAGE_READONLY
337 #define __P010 PAGE_COPY
338 #define __P011 PAGE_COPY
339 #define __P100 PAGE_EXECREAD
340 #define __P101 PAGE_EXECREAD
341 #define __P110 PAGE_COPY
342 #define __P111 PAGE_COPY
344 #define __S000 PAGE_NONE
345 #define __S001 PAGE_READONLY
346 #define __S010 PAGE_WRITEONLY
347 #define __S011 PAGE_SHARED
348 #define __S100 PAGE_EXECREAD
349 #define __S101 PAGE_EXECREAD
350 #define __S110 PAGE_RWX
351 #define __S111 PAGE_RWX
356 * Certain architectures need to do special things when PTEs
357 * within a page table are directly modified. Thus, the following
358 * hook is made available.
361 static inline void set_pte(pte_t *ptep, pte_t pte)
363 ptep->pte_high = pte.pte_high;
365 ptep->pte_low = pte.pte_low;
368 #define set_pte(pteptr, pteval) (*(pteptr) = pteval)
371 #define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
374 * (pmds are folded into pgds so this doesn't get actually called,
375 * but the define is needed for a generic inline function.)
377 #define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
379 #define pte_pfn(x) ((unsigned long)(((x).pte_low >> PAGE_SHIFT)))
380 #define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
381 #define pfn_pmd(pfn, prot) __pmd(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
383 #define pte_none(x) (!pte_val(x))
384 #define pte_present(x) (pte_val(x) & (_PAGE_PRESENT | _PAGE_PROTNONE))
385 #define pte_clear(mm,addr,xp) do { set_pte_at(mm, addr, xp, __pte(0)); } while (0)
387 #define pmd_none(x) (!pmd_val(x))
388 #define pmd_present(x) (pmd_val(x))
389 #define pmd_clear(xp) do { set_pmd(xp, __pmd(0)); } while (0)
390 #define pmd_bad(x) (pmd_val(x) & ~PAGE_MASK)
392 #define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT))
393 #define pte_page(x) phys_to_page(pte_val(x)&PTE_PHYS_MASK)
396 * The following only work if pte_present() is true.
397 * Undefined behaviour if not..
399 #define pte_not_present(pte) (!(pte_val(pte) & _PAGE_PRESENT))
400 #define pte_dirty(pte) (pte_val(pte) & _PAGE_DIRTY)
401 #define pte_young(pte) (pte_val(pte) & _PAGE_ACCESSED)
402 #define pte_file(pte) (pte_val(pte) & _PAGE_FILE)
405 #define pte_write(pte) ((pte).pte_high & _PAGE_EXT_USER_WRITE)
407 #define pte_write(pte) (pte_val(pte) & _PAGE_RW)
410 #define PTE_BIT_FUNC(h,fn,op) \
411 static inline pte_t pte_##fn(pte_t pte) { pte.pte_##h op; return pte; }
415 * We cheat a bit in the SH-X2 TLB case. As the permission bits are
416 * individually toggled (and user permissions are entirely decoupled from
417 * kernel permissions), we attempt to couple them a bit more sanely here.
419 PTE_BIT_FUNC(high, wrprotect, &= ~_PAGE_EXT_USER_WRITE);
420 PTE_BIT_FUNC(high, mkwrite, |= _PAGE_EXT_USER_WRITE | _PAGE_EXT_KERN_WRITE);
421 PTE_BIT_FUNC(high, mkhuge, |= _PAGE_SZHUGE);
423 PTE_BIT_FUNC(low, wrprotect, &= ~_PAGE_RW);
424 PTE_BIT_FUNC(low, mkwrite, |= _PAGE_RW);
425 PTE_BIT_FUNC(low, mkhuge, |= _PAGE_SZHUGE);
428 PTE_BIT_FUNC(low, mkclean, &= ~_PAGE_DIRTY);
429 PTE_BIT_FUNC(low, mkdirty, |= _PAGE_DIRTY);
430 PTE_BIT_FUNC(low, mkold, &= ~_PAGE_ACCESSED);
431 PTE_BIT_FUNC(low, mkyoung, |= _PAGE_ACCESSED);
434 * Macro and implementation to make a page protection as uncachable.
436 #define pgprot_noncached pgprot_noncached
438 static inline pgprot_t pgprot_noncached(pgprot_t _prot)
440 unsigned long prot = pgprot_val(_prot);
442 prot &= ~_PAGE_CACHABLE;
443 return __pgprot(prot);
446 #define pgprot_writecombine(prot) __pgprot(pgprot_val(prot) & ~_PAGE_CACHABLE)
449 * Conversion functions: convert a page and protection to a page entry,
450 * and a page entry and page directory to the page they refer to.
452 * extern pte_t mk_pte(struct page *page, pgprot_t pgprot)
454 #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
456 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
458 set_pte(&pte, __pte((pte_val(pte) & _PAGE_CHG_MASK) |
459 pgprot_val(newprot)));
463 #define pmd_page_vaddr(pmd) pmd_val(pmd)
464 #define pmd_page(pmd) (virt_to_page(pmd_val(pmd)))
466 /* to find an entry in a page-table-directory. */
467 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
468 #define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address))
470 /* to find an entry in a kernel page-table-directory */
471 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
473 /* Find an entry in the third-level page table.. */
474 #define pte_index(address) \
475 ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
476 #define pte_offset_kernel(dir, address) \
477 ((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(address))
478 #define pte_offset_map(dir, address) pte_offset_kernel(dir, address)
479 #define pte_offset_map_nested(dir, address) pte_offset_kernel(dir, address)
480 #define pte_unmap(pte) do { } while (0)
481 #define pte_unmap_nested(pte) do { } while (0)
484 #define pte_ERROR(e) \
485 printk("%s:%d: bad pte %p(%08lx%08lx).\n", __FILE__, __LINE__, \
486 &(e), (e).pte_high, (e).pte_low)
488 #define pte_ERROR(e) \
489 printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
492 #define pgd_ERROR(e) \
493 printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
495 struct vm_area_struct;
496 extern void update_mmu_cache(struct vm_area_struct * vma,
497 unsigned long address, pte_t pte);
500 * Encode and de-code a swap entry
503 * _PAGE_FILE at bit 0
504 * _PAGE_PRESENT at bit 8
505 * _PAGE_PROTNONE at bit 9
507 * For the normal case, we encode the swap type into bits 0:7 and the
508 * swap offset into bits 10:30. For the 64-bit PTE case, we keep the
509 * preserved bits in the low 32-bits and use the upper 32 as the swap
510 * offset (along with a 5-bit type), following the same approach as x86
511 * PAE. This keeps the logic quite simple, and allows for a full 32
512 * PTE_FILE_MAX_BITS, as opposed to the 29-bits we're constrained with
513 * in the pte_low case.
515 * As is evident by the Alpha code, if we ever get a 64-bit unsigned
516 * long (swp_entry_t) to match up with the 64-bit PTEs, this all becomes
519 * NOTE: We should set ZEROs at the position of _PAGE_PRESENT
520 * and _PAGE_PROTNONE bits
523 #define __swp_type(x) ((x).val & 0x1f)
524 #define __swp_offset(x) ((x).val >> 5)
525 #define __swp_entry(type, offset) ((swp_entry_t){ (type) | (offset) << 5})
526 #define __pte_to_swp_entry(pte) ((swp_entry_t){ (pte).pte_high })
527 #define __swp_entry_to_pte(x) ((pte_t){ 0, (x).val })
530 * Encode and decode a nonlinear file mapping entry
532 #define pte_to_pgoff(pte) ((pte).pte_high)
533 #define pgoff_to_pte(off) ((pte_t) { _PAGE_FILE, (off) })
535 #define PTE_FILE_MAX_BITS 32
537 #define __swp_type(x) ((x).val & 0xff)
538 #define __swp_offset(x) ((x).val >> 10)
539 #define __swp_entry(type, offset) ((swp_entry_t){(type) | (offset) <<10})
541 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> 1 })
542 #define __swp_entry_to_pte(x) ((pte_t) { (x).val << 1 })
545 * Encode and decode a nonlinear file mapping entry
547 #define PTE_FILE_MAX_BITS 29
548 #define pte_to_pgoff(pte) (pte_val(pte) >> 1)
549 #define pgoff_to_pte(off) ((pte_t) { ((off) << 1) | _PAGE_FILE })
552 typedef pte_t *pte_addr_t;
554 #define kern_addr_valid(addr) (1)
556 #define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
557 remap_pfn_range(vma, vaddr, pfn, size, prot)
562 * No page table caches to initialise
564 #define pgtable_cache_init() do { } while (0)
567 extern unsigned int kobjsize(const void *objp);
568 #endif /* !CONFIG_MMU */
570 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
571 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
572 extern pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep);
575 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
576 extern void paging_init(void);
578 #include <asm-generic/pgtable.h>
580 #endif /* !__ASSEMBLY__ */
581 #endif /* __ASM_SH_PAGE_H */