2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
28 #include <linux/acpi.h>
29 #include <linux/pnp.h>
30 #include "linux/string.h"
31 #include "linux/bitops.h"
37 /** @file i915_gem_tiling.c
39 * Support for managing tiling state of buffer objects.
41 * The idea behind tiling is to increase cache hit rates by rearranging
42 * pixel data so that a group of pixel accesses are in the same cacheline.
43 * Performance improvement from doing this on the back/depth buffer are on
46 * Intel architectures make this somewhat more complicated, though, by
47 * adjustments made to addressing of data when the memory is in interleaved
48 * mode (matched pairs of DIMMS) to improve memory bandwidth.
49 * For interleaved memory, the CPU sends every sequential 64 bytes
50 * to an alternate memory channel so it can get the bandwidth from both.
52 * The GPU also rearranges its accesses for increased bandwidth to interleaved
53 * memory, and it matches what the CPU does for non-tiled. However, when tiled
54 * it does it a little differently, since one walks addresses not just in the
55 * X direction but also Y. So, along with alternating channels when bit
56 * 6 of the address flips, it also alternates when other bits flip -- Bits 9
57 * (every 512 bytes, an X tile scanline) and 10 (every two X tile scanlines)
58 * are common to both the 915 and 965-class hardware.
60 * The CPU also sometimes XORs in higher bits as well, to improve
61 * bandwidth doing strided access like we do so frequently in graphics. This
62 * is called "Channel XOR Randomization" in the MCH documentation. The result
63 * is that the CPU is XORing in either bit 11 or bit 17 to bit 6 of its address
66 * All of this bit 6 XORing has an effect on our memory management,
67 * as we need to make sure that the 3d driver can correctly address object
70 * If we don't have interleaved memory, all tiling is safe and no swizzling is
73 * When bit 17 is XORed in, we simply refuse to tile at all. Bit
74 * 17 is not just a page offset, so as we page an objet out and back in,
75 * individual pages in it will have different bit 17 addresses, resulting in
76 * each 64 bytes being swapped with its neighbor!
78 * Otherwise, if interleaved, we have to tell the 3d driver what the address
79 * swizzling it needs to do is, since it's writing with the CPU to the pages
80 * (bit 6 and potentially bit 11 XORed in), and the GPU is reading from the
81 * pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling
82 * required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order
83 * to match what the GPU expects.
86 #define MCHBAR_I915 0x44
87 #define MCHBAR_I965 0x48
88 #define MCHBAR_SIZE (4*4096)
90 #define DEVEN_REG 0x54
91 #define DEVEN_MCHBAR_EN (1 << 28)
93 /* Allocate space for the MCH regs if needed, return nonzero on error */
95 intel_alloc_mchbar_resource(struct drm_device *dev)
97 struct pci_dev *bridge_dev;
98 drm_i915_private_t *dev_priv = dev->dev_private;
99 int reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
100 u32 temp_lo, temp_hi = 0;
104 bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
106 DRM_DEBUG("no bridge dev?!\n");
112 pci_read_config_dword(bridge_dev, reg + 4, &temp_hi);
113 pci_read_config_dword(bridge_dev, reg, &temp_lo);
114 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
116 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
118 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) {
123 /* Get some space for it */
124 ret = pci_bus_alloc_resource(bridge_dev->bus, &dev_priv->mch_res,
125 MCHBAR_SIZE, MCHBAR_SIZE,
127 0, pcibios_align_resource,
130 DRM_DEBUG("failed bus alloc: %d\n", ret);
131 dev_priv->mch_res.start = 0;
136 pci_write_config_dword(bridge_dev, reg + 4,
137 upper_32_bits(dev_priv->mch_res.start));
139 pci_write_config_dword(bridge_dev, reg,
140 lower_32_bits(dev_priv->mch_res.start));
142 pci_dev_put(bridge_dev);
147 /* Setup MCHBAR if possible, return true if we should disable it again */
149 intel_setup_mchbar(struct drm_device *dev)
151 struct pci_dev *bridge_dev;
152 int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
154 bool need_disable = false, enabled;
156 bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
158 DRM_DEBUG("no bridge dev?!\n");
162 if (IS_I915G(dev) || IS_I915GM(dev)) {
163 pci_read_config_dword(bridge_dev, DEVEN_REG, &temp);
164 enabled = !!(temp & DEVEN_MCHBAR_EN);
166 pci_read_config_dword(bridge_dev, mchbar_reg, &temp);
170 /* If it's already enabled, don't have to do anything */
174 if (intel_alloc_mchbar_resource(dev))
179 /* Space is allocated or reserved, so enable it. */
180 if (IS_I915G(dev) || IS_I915GM(dev)) {
181 pci_write_config_dword(bridge_dev, DEVEN_REG,
182 temp | DEVEN_MCHBAR_EN);
184 pci_read_config_dword(bridge_dev, mchbar_reg, &temp);
185 pci_write_config_dword(bridge_dev, mchbar_reg, temp | 1);
188 pci_dev_put(bridge_dev);
194 intel_teardown_mchbar(struct drm_device *dev, bool disable)
196 drm_i915_private_t *dev_priv = dev->dev_private;
197 struct pci_dev *bridge_dev;
198 int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
201 bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
203 DRM_DEBUG("no bridge dev?!\n");
208 if (IS_I915G(dev) || IS_I915GM(dev)) {
209 pci_read_config_dword(bridge_dev, DEVEN_REG, &temp);
210 temp &= ~DEVEN_MCHBAR_EN;
211 pci_write_config_dword(bridge_dev, DEVEN_REG, temp);
213 pci_read_config_dword(bridge_dev, mchbar_reg, &temp);
215 pci_write_config_dword(bridge_dev, mchbar_reg, temp);
219 if (dev_priv->mch_res.start)
220 release_resource(&dev_priv->mch_res);
224 * Detects bit 6 swizzling of address lookup between IGD access and CPU
225 * access through main memory.
228 i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
230 drm_i915_private_t *dev_priv = dev->dev_private;
231 uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
232 uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
236 /* As far as we know, the 865 doesn't have these bit 6
239 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
240 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
241 } else if (IS_MOBILE(dev)) {
244 /* Try to make sure MCHBAR is enabled before poking at it */
245 need_disable = intel_setup_mchbar(dev);
247 /* On mobile 9xx chipsets, channel interleave by the CPU is
248 * determined by DCC. For single-channel, neither the CPU
249 * nor the GPU do swizzling. For dual channel interleaved,
250 * the GPU's interleave is bit 9 and 10 for X tiled, and bit
251 * 9 for Y tiled. The CPU's interleave is independent, and
252 * can be based on either bit 11 (haven't seen this yet) or
255 dcc = I915_READ(DCC);
256 switch (dcc & DCC_ADDRESSING_MODE_MASK) {
257 case DCC_ADDRESSING_MODE_SINGLE_CHANNEL:
258 case DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC:
259 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
260 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
262 case DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED:
263 if (dcc & DCC_CHANNEL_XOR_DISABLE) {
264 /* This is the base swizzling by the GPU for
267 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
268 swizzle_y = I915_BIT_6_SWIZZLE_9;
269 } else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) {
270 /* Bit 11 swizzling by the CPU in addition. */
271 swizzle_x = I915_BIT_6_SWIZZLE_9_10_11;
272 swizzle_y = I915_BIT_6_SWIZZLE_9_11;
274 /* Bit 17 swizzling by the CPU in addition. */
275 swizzle_x = I915_BIT_6_SWIZZLE_9_10_17;
276 swizzle_y = I915_BIT_6_SWIZZLE_9_17;
280 if (dcc == 0xffffffff) {
281 DRM_ERROR("Couldn't read from MCHBAR. "
282 "Disabling tiling.\n");
283 swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
284 swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
287 intel_teardown_mchbar(dev, need_disable);
289 /* The 965, G33, and newer, have a very flexible memory
290 * configuration. It will enable dual-channel mode
291 * (interleaving) on as much memory as it can, and the GPU
292 * will additionally sometimes enable different bit 6
293 * swizzling for tiled objects from the CPU.
295 * Here's what I found on the G965:
296 * slot fill memory size swizzling
297 * 0A 0B 1A 1B 1-ch 2-ch
299 * 512 0 512 0 16 1008 X
300 * 512 0 0 512 16 1008 X
301 * 0 512 0 512 16 1008 X
302 * 1024 1024 1024 0 2048 1024 O
304 * We could probably detect this based on either the DRB
305 * matching, which was the case for the swizzling required in
306 * the table above, or from the 1-ch value being less than
307 * the minimum size of a rank.
309 if (I915_READ16(C0DRB3) != I915_READ16(C1DRB3)) {
310 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
311 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
313 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
314 swizzle_y = I915_BIT_6_SWIZZLE_9;
318 /* FIXME: check with memory config on IGDNG */
320 DRM_ERROR("disable tiling on IGDNG...\n");
321 swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
322 swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
325 dev_priv->mm.bit_6_swizzle_x = swizzle_x;
326 dev_priv->mm.bit_6_swizzle_y = swizzle_y;
331 * Returns the size of the fence for a tiled object of the given size.
334 i915_get_fence_size(struct drm_device *dev, int size)
340 /* The 965 can have fences at any page boundary. */
341 return ALIGN(size, 4096);
343 /* Align the size to a power of two greater than the smallest
351 for (i = start; i < size; i <<= 1)
358 /* Check pitch constriants for all chips & tiling formats */
360 i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
364 /* Linear is always fine */
365 if (tiling_mode == I915_TILING_NONE)
369 (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))
374 /* check maximum stride & object size */
376 /* i965 stores the end address of the gtt mapping in the fence
377 * reg, so dont bother to check the size */
378 if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
380 } else if (IS_I9XX(dev)) {
381 uint32_t pitch_val = ffs(stride / tile_width) - 1;
383 /* XXX: For Y tiling, FENCE_MAX_PITCH_VAL is actually 6 (8KB)
384 * instead of 4 (2KB) on 945s.
386 if (pitch_val > I915_FENCE_MAX_PITCH_VAL ||
387 size > (I830_FENCE_MAX_SIZE_VAL << 20))
390 uint32_t pitch_val = ffs(stride / tile_width) - 1;
392 if (pitch_val > I830_FENCE_MAX_PITCH_VAL ||
393 size > (I830_FENCE_MAX_SIZE_VAL << 19))
397 /* 965+ just needs multiples of tile width */
399 if (stride & (tile_width - 1))
404 /* Pre-965 needs power of two tile widths */
405 if (stride < tile_width)
408 if (stride & (stride - 1))
411 /* We don't 0handle the aperture area covered by the fence being bigger
412 * than the object size.
414 if (i915_get_fence_size(dev, size) != size)
421 i915_gem_object_fence_offset_ok(struct drm_gem_object *obj, int tiling_mode)
423 struct drm_device *dev = obj->dev;
424 struct drm_i915_gem_object *obj_priv = obj->driver_private;
426 if (obj_priv->gtt_space == NULL)
429 if (tiling_mode == I915_TILING_NONE)
432 if (!IS_I965G(dev)) {
433 if (obj_priv->gtt_offset & (obj->size - 1))
436 if (obj_priv->gtt_offset & ~I915_FENCE_START_MASK)
439 if (obj_priv->gtt_offset & ~I830_FENCE_START_MASK)
448 * Sets the tiling mode of an object, returning the required swizzling of
449 * bit 6 of addresses in the object.
452 i915_gem_set_tiling(struct drm_device *dev, void *data,
453 struct drm_file *file_priv)
455 struct drm_i915_gem_set_tiling *args = data;
456 drm_i915_private_t *dev_priv = dev->dev_private;
457 struct drm_gem_object *obj;
458 struct drm_i915_gem_object *obj_priv;
461 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
464 obj_priv = obj->driver_private;
466 if (!i915_tiling_ok(dev, args->stride, obj->size, args->tiling_mode)) {
467 mutex_lock(&dev->struct_mutex);
468 drm_gem_object_unreference(obj);
469 mutex_unlock(&dev->struct_mutex);
473 if (args->tiling_mode == I915_TILING_NONE) {
474 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
477 if (args->tiling_mode == I915_TILING_X)
478 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
480 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
482 /* Hide bit 17 swizzling from the user. This prevents old Mesa
483 * from aborting the application on sw fallbacks to bit 17,
484 * and we use the pread/pwrite bit17 paths to swizzle for it.
485 * If there was a user that was relying on the swizzle
486 * information for drm_intel_bo_map()ed reads/writes this would
487 * break it, but we don't have any of those.
489 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
490 args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
491 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
492 args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
494 /* If we can't handle the swizzling, make it untiled. */
495 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) {
496 args->tiling_mode = I915_TILING_NONE;
497 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
502 mutex_lock(&dev->struct_mutex);
503 if (args->tiling_mode != obj_priv->tiling_mode ||
504 args->stride != obj_priv->stride) {
505 /* We need to rebind the object if its current allocation
506 * no longer meets the alignment restrictions for its new
507 * tiling mode. Otherwise we can just leave it alone, but
508 * need to ensure that any fence register is cleared.
510 if (!i915_gem_object_fence_offset_ok(obj, args->tiling_mode))
511 ret = i915_gem_object_unbind(obj);
513 ret = i915_gem_object_put_fence_reg(obj);
515 WARN(ret != -ERESTARTSYS,
516 "failed to reset object for tiling switch");
517 args->tiling_mode = obj_priv->tiling_mode;
518 args->stride = obj_priv->stride;
522 obj_priv->tiling_mode = args->tiling_mode;
523 obj_priv->stride = args->stride;
526 drm_gem_object_unreference(obj);
527 mutex_unlock(&dev->struct_mutex);
533 * Returns the current tiling mode and required bit 6 swizzling for the object.
536 i915_gem_get_tiling(struct drm_device *dev, void *data,
537 struct drm_file *file_priv)
539 struct drm_i915_gem_get_tiling *args = data;
540 drm_i915_private_t *dev_priv = dev->dev_private;
541 struct drm_gem_object *obj;
542 struct drm_i915_gem_object *obj_priv;
544 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
547 obj_priv = obj->driver_private;
549 mutex_lock(&dev->struct_mutex);
551 args->tiling_mode = obj_priv->tiling_mode;
552 switch (obj_priv->tiling_mode) {
554 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
557 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
559 case I915_TILING_NONE:
560 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
563 DRM_ERROR("unknown tiling mode\n");
566 /* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */
567 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
568 args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
569 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
570 args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
572 drm_gem_object_unreference(obj);
573 mutex_unlock(&dev->struct_mutex);
579 * Swap every 64 bytes of this page around, to account for it having a new
580 * bit 17 of its physical address and therefore being interpreted differently
584 i915_gem_swizzle_page(struct page *page)
594 for (i = 0; i < PAGE_SIZE; i += 128) {
595 memcpy(temp, &vaddr[i], 64);
596 memcpy(&vaddr[i], &vaddr[i + 64], 64);
597 memcpy(&vaddr[i + 64], temp, 64);
606 i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj)
608 struct drm_device *dev = obj->dev;
609 drm_i915_private_t *dev_priv = dev->dev_private;
610 struct drm_i915_gem_object *obj_priv = obj->driver_private;
611 int page_count = obj->size >> PAGE_SHIFT;
614 if (dev_priv->mm.bit_6_swizzle_x != I915_BIT_6_SWIZZLE_9_10_17)
617 if (obj_priv->bit_17 == NULL)
620 for (i = 0; i < page_count; i++) {
621 char new_bit_17 = page_to_phys(obj_priv->pages[i]) >> 17;
622 if ((new_bit_17 & 0x1) !=
623 (test_bit(i, obj_priv->bit_17) != 0)) {
624 int ret = i915_gem_swizzle_page(obj_priv->pages[i]);
626 DRM_ERROR("Failed to swizzle page\n");
629 set_page_dirty(obj_priv->pages[i]);
635 i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj)
637 struct drm_device *dev = obj->dev;
638 drm_i915_private_t *dev_priv = dev->dev_private;
639 struct drm_i915_gem_object *obj_priv = obj->driver_private;
640 int page_count = obj->size >> PAGE_SHIFT;
643 if (dev_priv->mm.bit_6_swizzle_x != I915_BIT_6_SWIZZLE_9_10_17)
646 if (obj_priv->bit_17 == NULL) {
647 obj_priv->bit_17 = kmalloc(BITS_TO_LONGS(page_count) *
648 sizeof(long), GFP_KERNEL);
649 if (obj_priv->bit_17 == NULL) {
650 DRM_ERROR("Failed to allocate memory for bit 17 "
656 for (i = 0; i < page_count; i++) {
657 if (page_to_phys(obj_priv->pages[i]) & (1 << 17))
658 __set_bit(i, obj_priv->bit_17);
660 __clear_bit(i, obj_priv->bit_17);