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   1 /*
   2  * $Id: synclinkmp.c,v 4.38 2005/07/15 13:29:44 paulkf Exp $
   3  *
   4  * Device driver for Microgate SyncLink Multiport
   5  * high speed multiprotocol serial adapter.
   6  *
   7  * written by Paul Fulghum for Microgate Corporation
   8  * paulkf@microgate.com
   9  *
  10  * Microgate and SyncLink are trademarks of Microgate Corporation
  11  *
  12  * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
  13  * This code is released under the GNU General Public License (GPL)
  14  *
  15  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  16  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  18  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  19  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  20  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  21  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  23  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  24  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  25  * OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
  29 #if defined(__i386__)
  30 #  define BREAKPOINT() asm("   int $3");
  31 #else
  32 #  define BREAKPOINT() { }
  33 #endif
  34
  35 #define MAX_DEVICES 12
  36
  37 #include <linux/config.h>
  38 #include <linux/module.h>
  39 #include <linux/errno.h>
  40 #include <linux/signal.h>
  41 #include <linux/sched.h>
  42 #include <linux/timer.h>
  43 #include <linux/interrupt.h>
  44 #include <linux/pci.h>
  45 #include <linux/tty.h>
  46 #include <linux/tty_flip.h>
  47 #include <linux/serial.h>
  48 #include <linux/major.h>
  49 #include <linux/string.h>
  50 #include <linux/fcntl.h>
  51 #include <linux/ptrace.h>
  52 #include <linux/ioport.h>
  53 #include <linux/mm.h>
  54 #include <linux/slab.h>
  55 #include <linux/netdevice.h>
  56 #include <linux/vmalloc.h>
  57 #include <linux/init.h>
  58 #include <linux/delay.h>
  59 #include <linux/ioctl.h>
  60
  61 #include <asm/system.h>
  62 #include <asm/io.h>
  63 #include <asm/irq.h>
  64 #include <asm/dma.h>
  65 #include <linux/bitops.h>
  66 #include <asm/types.h>
  67 #include <linux/termios.h>
  68 #include <linux/workqueue.h>
  69 #include <linux/hdlc.h>
  70
  71 #ifdef CONFIG_HDLC_MODULE
  72 #define CONFIG_HDLC 1
  73 #endif
  74
  75 #define GET_USER(error,value,addr) error = get_user(value,addr)
  76 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
  77 #define PUT_USER(error,value,addr) error = put_user(value,addr)
  78 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
  79
  80 #include <asm/uaccess.h>
  81
  82 #include "linux/synclink.h"
  83
  84 static MGSL_PARAMS default_params = {
  85         MGSL_MODE_HDLC,                 /* unsigned long mode */
  86         0,                              /* unsigned char loopback; */
  87         HDLC_FLAG_UNDERRUN_ABORT15,     /* unsigned short flags; */
  88         HDLC_ENCODING_NRZI_SPACE,       /* unsigned char encoding; */
  89         0,                              /* unsigned long clock_speed; */
  90         0xff,                           /* unsigned char addr_filter; */
  91         HDLC_CRC_16_CCITT,              /* unsigned short crc_type; */
  92         HDLC_PREAMBLE_LENGTH_8BITS,     /* unsigned char preamble_length; */
  93         HDLC_PREAMBLE_PATTERN_NONE,     /* unsigned char preamble; */
  94         9600,                           /* unsigned long data_rate; */
  95         8,                              /* unsigned char data_bits; */
  96         1,                              /* unsigned char stop_bits; */
  97         ASYNC_PARITY_NONE               /* unsigned char parity; */
  98 };
  99
 100 /* size in bytes of DMA data buffers */
 101 #define SCABUFSIZE      1024
 102 #define SCA_MEM_SIZE    0x40000
 103 #define SCA_BASE_SIZE   512
 104 #define SCA_REG_SIZE    16
 105 #define SCA_MAX_PORTS   4
 106 #define SCAMAXDESC      128
 107
 108 #define BUFFERLISTSIZE  4096
 109
 110 /* SCA-I style DMA buffer descriptor */
 111 typedef struct _SCADESC
 112 {
 113         u16     next;           /* lower l6 bits of next descriptor addr */
 114         u16     buf_ptr;        /* lower 16 bits of buffer addr */
 115         u8      buf_base;       /* upper 8 bits of buffer addr */
 116         u8      pad1;
 117         u16     length;         /* length of buffer */
 118         u8      status;         /* status of buffer */
 119         u8      pad2;
 120 } SCADESC, *PSCADESC;
 121
 122 typedef struct _SCADESC_EX
 123 {
 124         /* device driver bookkeeping section */
 125         char    *virt_addr;     /* virtual address of data buffer */
 126         u16     phys_entry;     /* lower 16-bits of physical address of this descriptor */
 127 } SCADESC_EX, *PSCADESC_EX;
 128
 129 /* The queue of BH actions to be performed */
 130
 131 #define BH_RECEIVE  1
 132 #define BH_TRANSMIT 2
 133 #define BH_STATUS   4
 134
 135 #define IO_PIN_SHUTDOWN_LIMIT 100
 136
 137 #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
 138
 139 struct  _input_signal_events {
 140         int     ri_up;
 141         int     ri_down;
 142         int     dsr_up;
 143         int     dsr_down;
 144         int     dcd_up;
 145         int     dcd_down;
 146         int     cts_up;
 147         int     cts_down;
 148 };
 149
 150 /*
 151  * Device instance data structure
 152  */
 153 typedef struct _synclinkmp_info {
 154         void *if_ptr;                           /* General purpose pointer (used by SPPP) */
 155         int                     magic;
 156         int                     flags;
 157         int                     count;          /* count of opens */
 158         int                     line;
 159         unsigned short          close_delay;
 160         unsigned short          closing_wait;   /* time to wait before closing */
 161
 162         struct mgsl_icount      icount;
 163
 164         struct tty_struct       *tty;
 165         int                     timeout;
 166         int                     x_char;         /* xon/xoff character */
 167         int                     blocked_open;   /* # of blocked opens */
 168         u16                     read_status_mask1;  /* break detection (SR1 indications) */
 169         u16                     read_status_mask2;  /* parity/framing/overun (SR2 indications) */
 170         unsigned char           ignore_status_mask1;  /* break detection (SR1 indications) */
 171         unsigned char           ignore_status_mask2;  /* parity/framing/overun (SR2 indications) */
 172         unsigned char           *tx_buf;
 173         int                     tx_put;
 174         int                     tx_get;
 175         int                     tx_count;
 176
 177         wait_queue_head_t       open_wait;
 178         wait_queue_head_t       close_wait;
 179
 180         wait_queue_head_t       status_event_wait_q;
 181         wait_queue_head_t       event_wait_q;
 182         struct timer_list       tx_timer;       /* HDLC transmit timeout timer */
 183         struct _synclinkmp_info *next_device;   /* device list link */
 184         struct timer_list       status_timer;   /* input signal status check timer */
 185
 186         spinlock_t lock;                /* spinlock for synchronizing with ISR */
 187         struct work_struct task;                        /* task structure for scheduling bh */
 188
 189         u32 max_frame_size;                     /* as set by device config */
 190
 191         u32 pending_bh;
 192
 193         int bh_running;                         /* Protection from multiple */
 194         int isr_overflow;
 195         int bh_requested;
 196
 197         int dcd_chkcount;                       /* check counts to prevent */
 198         int cts_chkcount;                       /* too many IRQs if a signal */
 199         int dsr_chkcount;                       /* is floating */
 200         int ri_chkcount;
 201
 202         char *buffer_list;                      /* virtual address of Rx & Tx buffer lists */
 203         unsigned long buffer_list_phys;
 204
 205         unsigned int rx_buf_count;              /* count of total allocated Rx buffers */
 206         SCADESC *rx_buf_list;                   /* list of receive buffer entries */
 207         SCADESC_EX rx_buf_list_ex[SCAMAXDESC]; /* list of receive buffer entries */
 208         unsigned int current_rx_buf;
 209
 210         unsigned int tx_buf_count;              /* count of total allocated Tx buffers */
 211         SCADESC *tx_buf_list;           /* list of transmit buffer entries */
 212         SCADESC_EX tx_buf_list_ex[SCAMAXDESC]; /* list of transmit buffer entries */
 213         unsigned int last_tx_buf;
 214
 215         unsigned char *tmp_rx_buf;
 216         unsigned int tmp_rx_buf_count;
 217
 218         int rx_enabled;
 219         int rx_overflow;
 220
 221         int tx_enabled;
 222         int tx_active;
 223         u32 idle_mode;
 224
 225         unsigned char ie0_value;
 226         unsigned char ie1_value;
 227         unsigned char ie2_value;
 228         unsigned char ctrlreg_value;
 229         unsigned char old_signals;
 230
 231         char device_name[25];                   /* device instance name */
 232
 233         int port_count;
 234         int adapter_num;
 235         int port_num;
 236
 237         struct _synclinkmp_info *port_array[SCA_MAX_PORTS];
 238
 239         unsigned int bus_type;                  /* expansion bus type (ISA,EISA,PCI) */
 240
 241         unsigned int irq_level;                 /* interrupt level */
 242         unsigned long irq_flags;
 243         int irq_requested;                      /* nonzero if IRQ requested */
 244
 245         MGSL_PARAMS params;                     /* communications parameters */
 246
 247         unsigned char serial_signals;           /* current serial signal states */
 248
 249         int irq_occurred;                       /* for diagnostics use */
 250         unsigned int init_error;                /* Initialization startup error */
 251
 252         u32 last_mem_alloc;
 253         unsigned char* memory_base;             /* shared memory address (PCI only) */
 254         u32 phys_memory_base;
 255         int shared_mem_requested;
 256
 257         unsigned char* sca_base;                /* HD64570 SCA Memory address */
 258         u32 phys_sca_base;
 259         u32 sca_offset;
 260         int sca_base_requested;
 261
 262         unsigned char* lcr_base;                /* local config registers (PCI only) */
 263         u32 phys_lcr_base;
 264         u32 lcr_offset;
 265         int lcr_mem_requested;
 266
 267         unsigned char* statctrl_base;           /* status/control register memory */
 268         u32 phys_statctrl_base;
 269         u32 statctrl_offset;
 270         int sca_statctrl_requested;
 271
 272         u32 misc_ctrl_value;
 273         char flag_buf[MAX_ASYNC_BUFFER_SIZE];
 274         char char_buf[MAX_ASYNC_BUFFER_SIZE];
 275         BOOLEAN drop_rts_on_tx_done;
 276
 277         struct  _input_signal_events    input_signal_events;
 278
 279         /* SPPP/Cisco HDLC device parts */
 280         int netcount;
 281         int dosyncppp;
 282         spinlock_t netlock;
 283
 284 #ifdef CONFIG_HDLC
 285         struct net_device *netdev;
 286 #endif
 287
 288 } SLMP_INFO;
 289
 290 #define MGSL_MAGIC 0x5401
 291
 292 /*
 293  * define serial signal status change macros
 294  */
 295 #define MISCSTATUS_DCD_LATCHED  (SerialSignal_DCD<<8)   /* indicates change in DCD */
 296 #define MISCSTATUS_RI_LATCHED   (SerialSignal_RI<<8)    /* indicates change in RI */
 297 #define MISCSTATUS_CTS_LATCHED  (SerialSignal_CTS<<8)   /* indicates change in CTS */
 298 #define MISCSTATUS_DSR_LATCHED  (SerialSignal_DSR<<8)   /* change in DSR */
 299
 300 /* Common Register macros */
 301 #define LPR     0x00
 302 #define PABR0   0x02
 303 #define PABR1   0x03
 304 #define WCRL    0x04
 305 #define WCRM    0x05
 306 #define WCRH    0x06
 307 #define DPCR    0x08
 308 #define DMER    0x09
 309 #define ISR0    0x10
 310 #define ISR1    0x11
 311 #define ISR2    0x12
 312 #define IER0    0x14
 313 #define IER1    0x15
 314 #define IER2    0x16
 315 #define ITCR    0x18
 316 #define INTVR   0x1a
 317 #define IMVR    0x1c
 318
 319 /* MSCI Register macros */
 320 #define TRB     0x20
 321 #define TRBL    0x20
 322 #define TRBH    0x21
 323 #define SR0     0x22
 324 #define SR1     0x23
 325 #define SR2     0x24
 326 #define SR3     0x25
 327 #define FST     0x26
 328 #define IE0     0x28
 329 #define IE1     0x29
 330 #define IE2     0x2a
 331 #define FIE     0x2b
 332 #define CMD     0x2c
 333 #define MD0     0x2e
 334 #define MD1     0x2f
 335 #define MD2     0x30
 336 #define CTL     0x31
 337 #define SA0     0x32
 338 #define SA1     0x33
 339 #define IDL     0x34
 340 #define TMC     0x35
 341 #define RXS     0x36
 342 #define TXS     0x37
 343 #define TRC0    0x38
 344 #define TRC1    0x39
 345 #define RRC     0x3a
 346 #define CST0    0x3c
 347 #define CST1    0x3d
 348
 349 /* Timer Register Macros */
 350 #define TCNT    0x60
 351 #define TCNTL   0x60
 352 #define TCNTH   0x61
 353 #define TCONR   0x62
 354 #define TCONRL  0x62
 355 #define TCONRH  0x63
 356 #define TMCS    0x64
 357 #define TEPR    0x65
 358
 359 /* DMA Controller Register macros */
 360 #define DARL    0x80
 361 #define DARH    0x81
 362 #define DARB    0x82
 363 #define BAR     0x80
 364 #define BARL    0x80
 365 #define BARH    0x81
 366 #define BARB    0x82
 367 #define SAR     0x84
 368 #define SARL    0x84
 369 #define SARH    0x85
 370 #define SARB    0x86
 371 #define CPB     0x86
 372 #define CDA     0x88
 373 #define CDAL    0x88
 374 #define CDAH    0x89
 375 #define EDA     0x8a
 376 #define EDAL    0x8a
 377 #define EDAH    0x8b
 378 #define BFL     0x8c
 379 #define BFLL    0x8c
 380 #define BFLH    0x8d
 381 #define BCR     0x8e
 382 #define BCRL    0x8e
 383 #define BCRH    0x8f
 384 #define DSR     0x90
 385 #define DMR     0x91
 386 #define FCT     0x93
 387 #define DIR     0x94
 388 #define DCMD    0x95
 389
 390 /* combine with timer or DMA register address */
 391 #define TIMER0  0x00
 392 #define TIMER1  0x08
 393 #define TIMER2  0x10
 394 #define TIMER3  0x18
 395 #define RXDMA   0x00
 396 #define TXDMA   0x20
 397
 398 /* SCA Command Codes */
 399 #define NOOP            0x00
 400 #define TXRESET         0x01
 401 #define TXENABLE        0x02
 402 #define TXDISABLE       0x03
 403 #define TXCRCINIT       0x04
 404 #define TXCRCEXCL       0x05
 405 #define TXEOM           0x06
 406 #define TXABORT         0x07
 407 #define MPON            0x08
 408 #define TXBUFCLR        0x09
 409 #define RXRESET         0x11
 410 #define RXENABLE        0x12
 411 #define RXDISABLE       0x13
 412 #define RXCRCINIT       0x14
 413 #define RXREJECT        0x15
 414 #define SEARCHMP        0x16
 415 #define RXCRCEXCL       0x17
 416 #define RXCRCCALC       0x18
 417 #define CHRESET         0x21
 418 #define HUNT            0x31
 419
 420 /* DMA command codes */
 421 #define SWABORT         0x01
 422 #define FEICLEAR        0x02
 423
 424 /* IE0 */
 425 #define TXINTE          BIT7
 426 #define RXINTE          BIT6
 427 #define TXRDYE          BIT1
 428 #define RXRDYE          BIT0
 429
 430 /* IE1 & SR1 */
 431 #define UDRN    BIT7
 432 #define IDLE    BIT6
 433 #define SYNCD   BIT4
 434 #define FLGD    BIT4
 435 #define CCTS    BIT3
 436 #define CDCD    BIT2
 437 #define BRKD    BIT1
 438 #define ABTD    BIT1
 439 #define GAPD    BIT1
 440 #define BRKE    BIT0
 441 #define IDLD    BIT0
 442
 443 /* IE2 & SR2 */
 444 #define EOM     BIT7
 445 #define PMP     BIT6
 446 #define SHRT    BIT6
 447 #define PE      BIT5
 448 #define ABT     BIT5
 449 #define FRME    BIT4
 450 #define RBIT    BIT4
 451 #define OVRN    BIT3
 452 #define CRCE    BIT2
 453
 454
 455 /*
 456  * Global linked list of SyncLink devices
 457  */
 458 static SLMP_INFO *synclinkmp_device_list = NULL;
 459 static int synclinkmp_adapter_count = -1;
 460 static int synclinkmp_device_count = 0;
 461
 462 /*
 463  * Set this param to non-zero to load eax with the
 464  * .text section address and breakpoint on module load.
 465  * This is useful for use with gdb and add-symbol-file command.
 466  */
 467 static int break_on_load=0;
 468
 469 /*
 470  * Driver major number, defaults to zero to get auto
 471  * assigned major number. May be forced as module parameter.
 472  */
 473 static int ttymajor=0;
 474
 475 /*
 476  * Array of user specified options for ISA adapters.
 477  */
 478 static int debug_level = 0;
 479 static int maxframe[MAX_DEVICES] = {0,};
 480 static int dosyncppp[MAX_DEVICES] = {0,};
 481
 482 module_param(break_on_load, bool, 0);
 483 module_param(ttymajor, int, 0);
 484 module_param(debug_level, int, 0);
 485 module_param_array(maxframe, int, NULL, 0);
 486 module_param_array(dosyncppp, int, NULL, 0);
 487
 488 static char *driver_name = "SyncLink MultiPort driver";
 489 static char *driver_version = "$Revision: 4.38 $";
 490
 491 static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent);
 492 static void synclinkmp_remove_one(struct pci_dev *dev);
 493
 494 static struct pci_device_id synclinkmp_pci_tbl[] = {
 495         { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, },
 496         { 0, }, /* terminate list */
 497 };
 498 MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl);
 499
 500 MODULE_LICENSE("GPL");
 501
 502 static struct pci_driver synclinkmp_pci_driver = {
 503         .name           = "synclinkmp",
 504         .id_table       = synclinkmp_pci_tbl,
 505         .probe          = synclinkmp_init_one,
 506         .remove         = __devexit_p(synclinkmp_remove_one),
 507 };
 508
 509
 510 static struct tty_driver *serial_driver;
 511
 512 /* number of characters left in xmit buffer before we ask for more */
 513 #define WAKEUP_CHARS 256
 514
 515
 516 /* tty callbacks */
 517
 518 static int  open(struct tty_struct *tty, struct file * filp);
 519 static void close(struct tty_struct *tty, struct file * filp);
 520 static void hangup(struct tty_struct *tty);
 521 static void set_termios(struct tty_struct *tty, struct termios *old_termios);
 522
 523 static int  write(struct tty_struct *tty, const unsigned char *buf, int count);
 524 static void put_char(struct tty_struct *tty, unsigned char ch);
 525 static void send_xchar(struct tty_struct *tty, char ch);
 526 static void wait_until_sent(struct tty_struct *tty, int timeout);
 527 static int  write_room(struct tty_struct *tty);
 528 static void flush_chars(struct tty_struct *tty);
 529 static void flush_buffer(struct tty_struct *tty);
 530 static void tx_hold(struct tty_struct *tty);
 531 static void tx_release(struct tty_struct *tty);
 532
 533 static int  ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
 534 static int  read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
 535 static int  chars_in_buffer(struct tty_struct *tty);
 536 static void throttle(struct tty_struct * tty);
 537 static void unthrottle(struct tty_struct * tty);
 538 static void set_break(struct tty_struct *tty, int break_state);
 539
 540 #ifdef CONFIG_HDLC
 541 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
 542 static void hdlcdev_tx_done(SLMP_INFO *info);
 543 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size);
 544 static int  hdlcdev_init(SLMP_INFO *info);
 545 static void hdlcdev_exit(SLMP_INFO *info);
 546 #endif
 547
 548 /* ioctl handlers */
 549
 550 static int  get_stats(SLMP_INFO *info, struct mgsl_icount __user *user_icount);
 551 static int  get_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
 552 static int  set_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
 553 static int  get_txidle(SLMP_INFO *info, int __user *idle_mode);
 554 static int  set_txidle(SLMP_INFO *info, int idle_mode);
 555 static int  tx_enable(SLMP_INFO *info, int enable);
 556 static int  tx_abort(SLMP_INFO *info);
 557 static int  rx_enable(SLMP_INFO *info, int enable);
 558 static int  modem_input_wait(SLMP_INFO *info,int arg);
 559 static int  wait_mgsl_event(SLMP_INFO *info, int __user *mask_ptr);
 560 static int  tiocmget(struct tty_struct *tty, struct file *file);
 561 static int  tiocmset(struct tty_struct *tty, struct file *file,
 562                      unsigned int set, unsigned int clear);
 563 static void set_break(struct tty_struct *tty, int break_state);
 564
 565 static void add_device(SLMP_INFO *info);
 566 static void device_init(int adapter_num, struct pci_dev *pdev);
 567 static int  claim_resources(SLMP_INFO *info);
 568 static void release_resources(SLMP_INFO *info);
 569
 570 static int  startup(SLMP_INFO *info);
 571 static int  block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info);
 572 static void shutdown(SLMP_INFO *info);
 573 static void program_hw(SLMP_INFO *info);
 574 static void change_params(SLMP_INFO *info);
 575
 576 static int  init_adapter(SLMP_INFO *info);
 577 static int  register_test(SLMP_INFO *info);
 578 static int  irq_test(SLMP_INFO *info);
 579 static int  loopback_test(SLMP_INFO *info);
 580 static int  adapter_test(SLMP_INFO *info);
 581 static int  memory_test(SLMP_INFO *info);
 582
 583 static void reset_adapter(SLMP_INFO *info);
 584 static void reset_port(SLMP_INFO *info);
 585 static void async_mode(SLMP_INFO *info);
 586 static void hdlc_mode(SLMP_INFO *info);
 587
 588 static void rx_stop(SLMP_INFO *info);
 589 static void rx_start(SLMP_INFO *info);
 590 static void rx_reset_buffers(SLMP_INFO *info);
 591 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last);
 592 static int  rx_get_frame(SLMP_INFO *info);
 593
 594 static void tx_start(SLMP_INFO *info);
 595 static void tx_stop(SLMP_INFO *info);
 596 static void tx_load_fifo(SLMP_INFO *info);
 597 static void tx_set_idle(SLMP_INFO *info);
 598 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count);
 599
 600 static void get_signals(SLMP_INFO *info);
 601 static void set_signals(SLMP_INFO *info);
 602 static void enable_loopback(SLMP_INFO *info, int enable);
 603 static void set_rate(SLMP_INFO *info, u32 data_rate);
 604
 605 static int  bh_action(SLMP_INFO *info);
 606 static void bh_handler(void* Context);
 607 static void bh_receive(SLMP_INFO *info);
 608 static void bh_transmit(SLMP_INFO *info);
 609 static void bh_status(SLMP_INFO *info);
 610 static void isr_timer(SLMP_INFO *info);
 611 static void isr_rxint(SLMP_INFO *info);
 612 static void isr_rxrdy(SLMP_INFO *info);
 613 static void isr_txint(SLMP_INFO *info);
 614 static void isr_txrdy(SLMP_INFO *info);
 615 static void isr_rxdmaok(SLMP_INFO *info);
 616 static void isr_rxdmaerror(SLMP_INFO *info);
 617 static void isr_txdmaok(SLMP_INFO *info);
 618 static void isr_txdmaerror(SLMP_INFO *info);
 619 static void isr_io_pin(SLMP_INFO *info, u16 status);
 620
 621 static int  alloc_dma_bufs(SLMP_INFO *info);
 622 static void free_dma_bufs(SLMP_INFO *info);
 623 static int  alloc_buf_list(SLMP_INFO *info);
 624 static int  alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count);
 625 static int  alloc_tmp_rx_buf(SLMP_INFO *info);
 626 static void free_tmp_rx_buf(SLMP_INFO *info);
 627
 628 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count);
 629 static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit);
 630 static void tx_timeout(unsigned long context);
 631 static void status_timeout(unsigned long context);
 632
 633 static unsigned char read_reg(SLMP_INFO *info, unsigned char addr);
 634 static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
 635 static u16 read_reg16(SLMP_INFO *info, unsigned char addr);
 636 static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val);
 637 static unsigned char read_status_reg(SLMP_INFO * info);
 638 static void write_control_reg(SLMP_INFO * info);
 639
 640
 641 static unsigned char rx_active_fifo_level = 16; // rx request FIFO activation level in bytes
 642 static unsigned char tx_active_fifo_level = 16; // tx request FIFO activation level in bytes
 643 static unsigned char tx_negate_fifo_level = 32; // tx request FIFO negation level in bytes
 644
 645 static u32 misc_ctrl_value = 0x007e4040;
 646 static u32 lcr1_brdr_value = 0x00800028;
 647
 648 static u32 read_ahead_count = 8;
 649
 650 /* DPCR, DMA Priority Control
 651  *
 652  * 07..05  Not used, must be 0
 653  * 04      BRC, bus release condition: 0=all transfers complete
 654  *              1=release after 1 xfer on all channels
 655  * 03      CCC, channel change condition: 0=every cycle
 656  *              1=after each channel completes all xfers
 657  * 02..00  PR<2..0>, priority 100=round robin
 658  *
 659  * 00000100 = 0x00
 660  */
 661 static unsigned char dma_priority = 0x04;
 662
 663 // Number of bytes that can be written to shared RAM
 664 // in a single write operation
 665 static u32 sca_pci_load_interval = 64;
 666
 667 /*
 668  * 1st function defined in .text section. Calling this function in
 669  * init_module() followed by a breakpoint allows a remote debugger
 670  * (gdb) to get the .text address for the add-symbol-file command.
 671  * This allows remote debugging of dynamically loadable modules.
 672  */
 673 static void* synclinkmp_get_text_ptr(void);
 674 static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr;}
 675
 676 static inline int sanity_check(SLMP_INFO *info,
 677                                char *name, const char *routine)
 678 {
 679 #ifdef SANITY_CHECK
 680         static const char *badmagic =
 681                 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
 682         static const char *badinfo =
 683                 "Warning: null synclinkmp_struct for (%s) in %s\n";
 684
 685         if (!info) {
 686                 printk(badinfo, name, routine);
 687                 return 1;
 688         }
 689         if (info->magic != MGSL_MAGIC) {
 690                 printk(badmagic, name, routine);
 691                 return 1;
 692         }
 693 #else
 694         if (!info)
 695                 return 1;
 696 #endif
 697         return 0;
 698 }
 699
 700 /**
 701  * line discipline callback wrappers
 702  *
 703  * The wrappers maintain line discipline references
 704  * while calling into the line discipline.
 705  *
 706  * ldisc_receive_buf  - pass receive data to line discipline
 707  */
 708
 709 static void ldisc_receive_buf(struct tty_struct *tty,
 710                               const __u8 *data, char *flags, int count)
 711 {
 712         struct tty_ldisc *ld;
 713         if (!tty)
 714                 return;
 715         ld = tty_ldisc_ref(tty);
 716         if (ld) {
 717                 if (ld->receive_buf)
 718                         ld->receive_buf(tty, data, flags, count);
 719                 tty_ldisc_deref(ld);
 720         }
 721 }
 722
 723 /* tty callbacks */
 724
 725 /* Called when a port is opened.  Init and enable port.
 726  */
 727 static int open(struct tty_struct *tty, struct file *filp)
 728 {
 729         SLMP_INFO *info;
 730         int retval, line;
 731         unsigned long flags;
 732
 733         line = tty->index;
 734         if ((line < 0) || (line >= synclinkmp_device_count)) {
 735                 printk("%s(%d): open with invalid line #%d.\n",
 736                         __FILE__,__LINE__,line);
 737                 return -ENODEV;
 738         }
 739
 740         info = synclinkmp_device_list;
 741         while(info && info->line != line)
 742                 info = info->next_device;
 743         if (sanity_check(info, tty->name, "open"))
 744                 return -ENODEV;
 745         if ( info->init_error ) {
 746                 printk("%s(%d):%s device is not allocated, init error=%d\n",
 747                         __FILE__,__LINE__,info->device_name,info->init_error);
 748                 return -ENODEV;
 749         }
 750
 751         tty->driver_data = info;
 752         info->tty = tty;
 753
 754         if (debug_level >= DEBUG_LEVEL_INFO)
 755                 printk("%s(%d):%s open(), old ref count = %d\n",
 756                          __FILE__,__LINE__,tty->driver->name, info->count);
 757
 758         /* If port is closing, signal caller to try again */
 759         if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){
 760                 if (info->flags & ASYNC_CLOSING)
 761                         interruptible_sleep_on(&info->close_wait);
 762                 retval = ((info->flags & ASYNC_HUP_NOTIFY) ?
 763                         -EAGAIN : -ERESTARTSYS);
 764                 goto cleanup;
 765         }
 766
 767         info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
 768
 769         spin_lock_irqsave(&info->netlock, flags);
 770         if (info->netcount) {
 771                 retval = -EBUSY;
 772                 spin_unlock_irqrestore(&info->netlock, flags);
 773                 goto cleanup;
 774         }
 775         info->count++;
 776         spin_unlock_irqrestore(&info->netlock, flags);
 777
 778         if (info->count == 1) {
 779                 /* 1st open on this device, init hardware */
 780                 retval = startup(info);
 781                 if (retval < 0)
 782                         goto cleanup;
 783         }
 784
 785         retval = block_til_ready(tty, filp, info);
 786         if (retval) {
 787                 if (debug_level >= DEBUG_LEVEL_INFO)
 788                         printk("%s(%d):%s block_til_ready() returned %d\n",
 789                                  __FILE__,__LINE__, info->device_name, retval);
 790                 goto cleanup;
 791         }
 792
 793         if (debug_level >= DEBUG_LEVEL_INFO)
 794                 printk("%s(%d):%s open() success\n",
 795                          __FILE__,__LINE__, info->device_name);
 796         retval = 0;
 797
 798 cleanup:
 799         if (retval) {
 800                 if (tty->count == 1)
 801                         info->tty = NULL; /* tty layer will release tty struct */
 802                 if(info->count)
 803                         info->count--;
 804         }
 805
 806         return retval;
 807 }
 808
 809 /* Called when port is closed. Wait for remaining data to be
 810  * sent. Disable port and free resources.
 811  */
 812 static void close(struct tty_struct *tty, struct file *filp)
 813 {
 814         SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
 815
 816         if (sanity_check(info, tty->name, "close"))
 817                 return;
 818
 819         if (debug_level >= DEBUG_LEVEL_INFO)
 820                 printk("%s(%d):%s close() entry, count=%d\n",
 821                          __FILE__,__LINE__, info->device_name, info->count);
 822
 823         if (!info->count)
 824                 return;
 825
 826         if (tty_hung_up_p(filp))
 827                 goto cleanup;
 828
 829         if ((tty->count == 1) && (info->count != 1)) {
 830                 /*
 831                  * tty->count is 1 and the tty structure will be freed.
 832                  * info->count should be one in this case.
 833                  * if it's not, correct it so that the port is shutdown.
 834                  */
 835                 printk("%s(%d):%s close: bad refcount; tty->count is 1, "
 836                        "info->count is %d\n",
 837                          __FILE__,__LINE__, info->device_name, info->count);
 838                 info->count = 1;
 839         }
 840
 841         info->count--;
 842
 843         /* if at least one open remaining, leave hardware active */
 844         if (info->count)
 845                 goto cleanup;
 846
 847         info->flags |= ASYNC_CLOSING;
 848
 849         /* set tty->closing to notify line discipline to
 850          * only process XON/XOFF characters. Only the N_TTY
 851          * discipline appears to use this (ppp does not).
 852          */
 853         tty->closing = 1;
 854
 855         /* wait for transmit data to clear all layers */
 856
 857         if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) {
 858                 if (debug_level >= DEBUG_LEVEL_INFO)
 859                         printk("%s(%d):%s close() calling tty_wait_until_sent\n",
 860                                  __FILE__,__LINE__, info->device_name );
 861                 tty_wait_until_sent(tty, info->closing_wait);
 862         }
 863
 864         if (info->flags & ASYNC_INITIALIZED)
 865                 wait_until_sent(tty, info->timeout);
 866
 867         if (tty->driver->flush_buffer)
 868                 tty->driver->flush_buffer(tty);
 869
 870         tty_ldisc_flush(tty);
 871
 872         shutdown(info);
 873
 874         tty->closing = 0;
 875         info->tty = NULL;
 876
 877         if (info->blocked_open) {
 878                 if (info->close_delay) {
 879                         msleep_interruptible(jiffies_to_msecs(info->close_delay));
 880                 }
 881                 wake_up_interruptible(&info->open_wait);
 882         }
 883
 884         info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
 885
 886         wake_up_interruptible(&info->close_wait);
 887
 888 cleanup:
 889         if (debug_level >= DEBUG_LEVEL_INFO)
 890                 printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__,
 891                         tty->driver->name, info->count);
 892 }
 893
 894 /* Called by tty_hangup() when a hangup is signaled.
 895  * This is the same as closing all open descriptors for the port.
 896  */
 897 static void hangup(struct tty_struct *tty)
 898 {
 899         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
 900
 901         if (debug_level >= DEBUG_LEVEL_INFO)
 902                 printk("%s(%d):%s hangup()\n",
 903                          __FILE__,__LINE__, info->device_name );
 904
 905         if (sanity_check(info, tty->name, "hangup"))
 906                 return;
 907
 908         flush_buffer(tty);
 909         shutdown(info);
 910
 911         info->count = 0;
 912         info->flags &= ~ASYNC_NORMAL_ACTIVE;
 913         info->tty = NULL;
 914
 915         wake_up_interruptible(&info->open_wait);
 916 }
 917
 918 /* Set new termios settings
 919  */
 920 static void set_termios(struct tty_struct *tty, struct termios *old_termios)
 921 {
 922         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
 923         unsigned long flags;
 924
 925         if (debug_level >= DEBUG_LEVEL_INFO)
 926                 printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__,
 927                         tty->driver->name );
 928
 929         /* just return if nothing has changed */
 930         if ((tty->termios->c_cflag == old_termios->c_cflag)
 931             && (RELEVANT_IFLAG(tty->termios->c_iflag)
 932                 == RELEVANT_IFLAG(old_termios->c_iflag)))
 933           return;
 934
 935         change_params(info);
 936
 937         /* Handle transition to B0 status */
 938         if (old_termios->c_cflag & CBAUD &&
 939             !(tty->termios->c_cflag & CBAUD)) {
 940                 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
 941                 spin_lock_irqsave(&info->lock,flags);
 942                 set_signals(info);
 943                 spin_unlock_irqrestore(&info->lock,flags);
 944         }
 945
 946         /* Handle transition away from B0 status */
 947         if (!(old_termios->c_cflag & CBAUD) &&
 948             tty->termios->c_cflag & CBAUD) {
 949                 info->serial_signals |= SerialSignal_DTR;
 950                 if (!(tty->termios->c_cflag & CRTSCTS) ||
 951                     !test_bit(TTY_THROTTLED, &tty->flags)) {
 952                         info->serial_signals |= SerialSignal_RTS;
 953                 }
 954                 spin_lock_irqsave(&info->lock,flags);
 955                 set_signals(info);
 956                 spin_unlock_irqrestore(&info->lock,flags);
 957         }
 958
 959         /* Handle turning off CRTSCTS */
 960         if (old_termios->c_cflag & CRTSCTS &&
 961             !(tty->termios->c_cflag & CRTSCTS)) {
 962                 tty->hw_stopped = 0;
 963                 tx_release(tty);
 964         }
 965 }
 966
 967 /* Send a block of data
 968  *
 969  * Arguments:
 970  *
 971  *      tty             pointer to tty information structure
 972  *      buf             pointer to buffer containing send data
 973  *      count           size of send data in bytes
 974  *
 975  * Return Value:        number of characters written
 976  */
 977 static int write(struct tty_struct *tty,
 978                  const unsigned char *buf, int count)
 979 {
 980         int     c, ret = 0;
 981         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
 982         unsigned long flags;
 983
 984         if (debug_level >= DEBUG_LEVEL_INFO)
 985                 printk("%s(%d):%s write() count=%d\n",
 986                        __FILE__,__LINE__,info->device_name,count);
 987
 988         if (sanity_check(info, tty->name, "write"))
 989                 goto cleanup;
 990
 991         if (!tty || !info->tx_buf)
 992                 goto cleanup;
 993
 994         if (info->params.mode == MGSL_MODE_HDLC) {
 995                 if (count > info->max_frame_size) {
 996                         ret = -EIO;
 997                         goto cleanup;
 998                 }
 999                 if (info->tx_active)
1000                         goto cleanup;
1001                 if (info->tx_count) {
1002                         /* send accumulated data from send_char() calls */
1003                         /* as frame and wait before accepting more data. */
1004                         tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
1005                         goto start;
1006                 }
1007                 ret = info->tx_count = count;
1008                 tx_load_dma_buffer(info, buf, count);
1009                 goto start;
1010         }
1011
1012         for (;;) {
1013                 c = min_t(int, count,
1014                         min(info->max_frame_size - info->tx_count - 1,
1015                             info->max_frame_size - info->tx_put));
1016                 if (c <= 0)
1017                         break;
1018
1019                 memcpy(info->tx_buf + info->tx_put, buf, c);
1020
1021                 spin_lock_irqsave(&info->lock,flags);
1022                 info->tx_put += c;
1023                 if (info->tx_put >= info->max_frame_size)
1024                         info->tx_put -= info->max_frame_size;
1025                 info->tx_count += c;
1026                 spin_unlock_irqrestore(&info->lock,flags);
1027
1028                 buf += c;
1029                 count -= c;
1030                 ret += c;
1031         }
1032
1033         if (info->params.mode == MGSL_MODE_HDLC) {
1034                 if (count) {
1035                         ret = info->tx_count = 0;
1036                         goto cleanup;
1037                 }
1038                 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
1039         }
1040 start:
1041         if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
1042                 spin_lock_irqsave(&info->lock,flags);
1043                 if (!info->tx_active)
1044                         tx_start(info);
1045                 spin_unlock_irqrestore(&info->lock,flags);
1046         }
1047
1048 cleanup:
1049         if (debug_level >= DEBUG_LEVEL_INFO)
1050                 printk( "%s(%d):%s write() returning=%d\n",
1051                         __FILE__,__LINE__,info->device_name,ret);
1052         return ret;
1053 }
1054
1055 /* Add a character to the transmit buffer.
1056  */
1057 static void put_char(struct tty_struct *tty, unsigned char ch)
1058 {
1059         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1060         unsigned long flags;
1061
1062         if ( debug_level >= DEBUG_LEVEL_INFO ) {
1063                 printk( "%s(%d):%s put_char(%d)\n",
1064                         __FILE__,__LINE__,info->device_name,ch);
1065         }
1066
1067         if (sanity_check(info, tty->name, "put_char"))
1068                 return;
1069
1070         if (!tty || !info->tx_buf)
1071                 return;
1072
1073         spin_lock_irqsave(&info->lock,flags);
1074
1075         if ( (info->params.mode != MGSL_MODE_HDLC) ||
1076              !info->tx_active ) {
1077
1078                 if (info->tx_count < info->max_frame_size - 1) {
1079                         info->tx_buf[info->tx_put++] = ch;
1080                         if (info->tx_put >= info->max_frame_size)
1081                                 info->tx_put -= info->max_frame_size;
1082                         info->tx_count++;
1083                 }
1084         }
1085
1086         spin_unlock_irqrestore(&info->lock,flags);
1087 }
1088
1089 /* Send a high-priority XON/XOFF character
1090  */
1091 static void send_xchar(struct tty_struct *tty, char ch)
1092 {
1093         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1094         unsigned long flags;
1095
1096         if (debug_level >= DEBUG_LEVEL_INFO)
1097                 printk("%s(%d):%s send_xchar(%d)\n",
1098                          __FILE__,__LINE__, info->device_name, ch );
1099
1100         if (sanity_check(info, tty->name, "send_xchar"))
1101                 return;
1102
1103         info->x_char = ch;
1104         if (ch) {
1105                 /* Make sure transmit interrupts are on */
1106                 spin_lock_irqsave(&info->lock,flags);
1107                 if (!info->tx_enabled)
1108                         tx_start(info);
1109                 spin_unlock_irqrestore(&info->lock,flags);
1110         }
1111 }
1112
1113 /* Wait until the transmitter is empty.
1114  */
1115 static void wait_until_sent(struct tty_struct *tty, int timeout)
1116 {
1117         SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
1118         unsigned long orig_jiffies, char_time;
1119
1120         if (!info )
1121                 return;
1122
1123         if (debug_level >= DEBUG_LEVEL_INFO)
1124                 printk("%s(%d):%s wait_until_sent() entry\n",
1125                          __FILE__,__LINE__, info->device_name );
1126
1127         if (sanity_check(info, tty->name, "wait_until_sent"))
1128                 return;
1129
1130         if (!(info->flags & ASYNC_INITIALIZED))
1131                 goto exit;
1132
1133         orig_jiffies = jiffies;
1134
1135         /* Set check interval to 1/5 of estimated time to
1136          * send a character, and make it at least 1. The check
1137          * interval should also be less than the timeout.
1138          * Note: use tight timings here to satisfy the NIST-PCTS.
1139          */
1140
1141         if ( info->params.data_rate ) {
1142                 char_time = info->timeout/(32 * 5);
1143                 if (!char_time)
1144                         char_time++;
1145         } else
1146                 char_time = 1;
1147
1148         if (timeout)
1149                 char_time = min_t(unsigned long, char_time, timeout);
1150
1151         if ( info->params.mode == MGSL_MODE_HDLC ) {
1152                 while (info->tx_active) {
1153                         msleep_interruptible(jiffies_to_msecs(char_time));
1154                         if (signal_pending(current))
1155                                 break;
1156                         if (timeout && time_after(jiffies, orig_jiffies + timeout))
1157                                 break;
1158                 }
1159         } else {
1160                 //TODO: determine if there is something similar to USC16C32
1161                 //      TXSTATUS_ALL_SENT status
1162                 while ( info->tx_active && info->tx_enabled) {
1163                         msleep_interruptible(jiffies_to_msecs(char_time));
1164                         if (signal_pending(current))
1165                                 break;
1166                         if (timeout && time_after(jiffies, orig_jiffies + timeout))
1167                                 break;
1168                 }
1169         }
1170
1171 exit:
1172         if (debug_level >= DEBUG_LEVEL_INFO)
1173                 printk("%s(%d):%s wait_until_sent() exit\n",
1174                          __FILE__,__LINE__, info->device_name );
1175 }
1176
1177 /* Return the count of free bytes in transmit buffer
1178  */
1179 static int write_room(struct tty_struct *tty)
1180 {
1181         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1182         int ret;
1183
1184         if (sanity_check(info, tty->name, "write_room"))
1185                 return 0;
1186
1187         if (info->params.mode == MGSL_MODE_HDLC) {
1188                 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1189         } else {
1190                 ret = info->max_frame_size - info->tx_count - 1;
1191                 if (ret < 0)
1192                         ret = 0;
1193         }
1194
1195         if (debug_level >= DEBUG_LEVEL_INFO)
1196                 printk("%s(%d):%s write_room()=%d\n",
1197                        __FILE__, __LINE__, info->device_name, ret);
1198
1199         return ret;
1200 }
1201
1202 /* enable transmitter and send remaining buffered characters
1203  */
1204 static void flush_chars(struct tty_struct *tty)
1205 {
1206         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1207         unsigned long flags;
1208
1209         if ( debug_level >= DEBUG_LEVEL_INFO )
1210                 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1211                         __FILE__,__LINE__,info->device_name,info->tx_count);
1212
1213         if (sanity_check(info, tty->name, "flush_chars"))
1214                 return;
1215
1216         if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped ||
1217             !info->tx_buf)
1218                 return;
1219
1220         if ( debug_level >= DEBUG_LEVEL_INFO )
1221                 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1222                         __FILE__,__LINE__,info->device_name );
1223
1224         spin_lock_irqsave(&info->lock,flags);
1225
1226         if (!info->tx_active) {
1227                 if ( (info->params.mode == MGSL_MODE_HDLC) &&
1228                         info->tx_count ) {
1229                         /* operating in synchronous (frame oriented) mode */
1230                         /* copy data from circular tx_buf to */
1231                         /* transmit DMA buffer. */
1232                         tx_load_dma_buffer(info,
1233                                  info->tx_buf,info->tx_count);
1234                 }
1235                 tx_start(info);
1236         }
1237
1238         spin_unlock_irqrestore(&info->lock,flags);
1239 }
1240
1241 /* Discard all data in the send buffer
1242  */
1243 static void flush_buffer(struct tty_struct *tty)
1244 {
1245         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1246         unsigned long flags;
1247
1248         if (debug_level >= DEBUG_LEVEL_INFO)
1249                 printk("%s(%d):%s flush_buffer() entry\n",
1250                          __FILE__,__LINE__, info->device_name );
1251
1252         if (sanity_check(info, tty->name, "flush_buffer"))
1253                 return;
1254
1255         spin_lock_irqsave(&info->lock,flags);
1256         info->tx_count = info->tx_put = info->tx_get = 0;
1257         del_timer(&info->tx_timer);
1258         spin_unlock_irqrestore(&info->lock,flags);
1259
1260         wake_up_interruptible(&tty->write_wait);
1261         tty_wakeup(tty);
1262 }
1263
1264 /* throttle (stop) transmitter
1265  */
1266 static void tx_hold(struct tty_struct *tty)
1267 {
1268         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1269         unsigned long flags;
1270
1271         if (sanity_check(info, tty->name, "tx_hold"))
1272                 return;
1273
1274         if ( debug_level >= DEBUG_LEVEL_INFO )
1275                 printk("%s(%d):%s tx_hold()\n",
1276                         __FILE__,__LINE__,info->device_name);
1277
1278         spin_lock_irqsave(&info->lock,flags);
1279         if (info->tx_enabled)
1280                 tx_stop(info);
1281         spin_unlock_irqrestore(&info->lock,flags);
1282 }
1283
1284 /* release (start) transmitter
1285  */
1286 static void tx_release(struct tty_struct *tty)
1287 {
1288         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1289         unsigned long flags;
1290
1291         if (sanity_check(info, tty->name, "tx_release"))
1292                 return;
1293
1294         if ( debug_level >= DEBUG_LEVEL_INFO )
1295                 printk("%s(%d):%s tx_release()\n",
1296                         __FILE__,__LINE__,info->device_name);
1297
1298         spin_lock_irqsave(&info->lock,flags);
1299         if (!info->tx_enabled)
1300                 tx_start(info);
1301         spin_unlock_irqrestore(&info->lock,flags);
1302 }
1303
1304 /* Service an IOCTL request
1305  *
1306  * Arguments:
1307  *
1308  *      tty     pointer to tty instance data
1309  *      file    pointer to associated file object for device
1310  *      cmd     IOCTL command code
1311  *      arg     command argument/context
1312  *
1313  * Return Value:        0 if success, otherwise error code
1314  */
1315 static int ioctl(struct tty_struct *tty, struct file *file,
1316                  unsigned int cmd, unsigned long arg)
1317 {
1318         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1319         int error;
1320         struct mgsl_icount cnow;        /* kernel counter temps */
1321         struct serial_icounter_struct __user *p_cuser;  /* user space */
1322         unsigned long flags;
1323         void __user *argp = (void __user *)arg;
1324
1325         if (debug_level >= DEBUG_LEVEL_INFO)
1326                 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__,
1327                         info->device_name, cmd );
1328
1329         if (sanity_check(info, tty->name, "ioctl"))
1330                 return -ENODEV;
1331
1332         if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1333             (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1334                 if (tty->flags & (1 << TTY_IO_ERROR))
1335                     return -EIO;
1336         }
1337
1338         switch (cmd) {
1339         case MGSL_IOCGPARAMS:
1340                 return get_params(info, argp);
1341         case MGSL_IOCSPARAMS:
1342                 return set_params(info, argp);
1343         case MGSL_IOCGTXIDLE:
1344                 return get_txidle(info, argp);
1345         case MGSL_IOCSTXIDLE:
1346                 return set_txidle(info, (int)arg);
1347         case MGSL_IOCTXENABLE:
1348                 return tx_enable(info, (int)arg);
1349         case MGSL_IOCRXENABLE:
1350                 return rx_enable(info, (int)arg);
1351         case MGSL_IOCTXABORT:
1352                 return tx_abort(info);
1353         case MGSL_IOCGSTATS:
1354                 return get_stats(info, argp);
1355         case MGSL_IOCWAITEVENT:
1356                 return wait_mgsl_event(info, argp);
1357         case MGSL_IOCLOOPTXDONE:
1358                 return 0; // TODO: Not supported, need to document
1359                 /* Wait for modem input (DCD,RI,DSR,CTS) change
1360                  * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1361                  */
1362         case TIOCMIWAIT:
1363                 return modem_input_wait(info,(int)arg);
1364
1365                 /*
1366                  * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1367                  * Return: write counters to the user passed counter struct
1368                  * NB: both 1->0 and 0->1 transitions are counted except for
1369                  *     RI where only 0->1 is counted.
1370                  */
1371         case TIOCGICOUNT:
1372                 spin_lock_irqsave(&info->lock,flags);
1373                 cnow = info->icount;
1374                 spin_unlock_irqrestore(&info->lock,flags);
1375                 p_cuser = argp;
1376                 PUT_USER(error,cnow.cts, &p_cuser->cts);
1377                 if (error) return error;
1378                 PUT_USER(error,cnow.dsr, &p_cuser->dsr);
1379                 if (error) return error;
1380                 PUT_USER(error,cnow.rng, &p_cuser->rng);
1381                 if (error) return error;
1382                 PUT_USER(error,cnow.dcd, &p_cuser->dcd);
1383                 if (error) return error;
1384                 PUT_USER(error,cnow.rx, &p_cuser->rx);
1385                 if (error) return error;
1386                 PUT_USER(error,cnow.tx, &p_cuser->tx);
1387                 if (error) return error;
1388                 PUT_USER(error,cnow.frame, &p_cuser->frame);
1389                 if (error) return error;
1390                 PUT_USER(error,cnow.overrun, &p_cuser->overrun);
1391                 if (error) return error;
1392                 PUT_USER(error,cnow.parity, &p_cuser->parity);
1393                 if (error) return error;
1394                 PUT_USER(error,cnow.brk, &p_cuser->brk);
1395                 if (error) return error;
1396                 PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
1397                 if (error) return error;
1398                 return 0;
1399         default:
1400                 return -ENOIOCTLCMD;
1401         }
1402         return 0;
1403 }
1404
1405 /*
1406  * /proc fs routines....
1407  */
1408
1409 static inline int line_info(char *buf, SLMP_INFO *info)
1410 {
1411         char    stat_buf[30];
1412         int     ret;
1413         unsigned long flags;
1414
1415         ret = sprintf(buf, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1416                        "\tIRQ=%d MaxFrameSize=%u\n",
1417                 info->device_name,
1418                 info->phys_sca_base,
1419                 info->phys_memory_base,
1420                 info->phys_statctrl_base,
1421                 info->phys_lcr_base,
1422                 info->irq_level,
1423                 info->max_frame_size );
1424
1425         /* output current serial signal states */
1426         spin_lock_irqsave(&info->lock,flags);
1427         get_signals(info);
1428         spin_unlock_irqrestore(&info->lock,flags);
1429
1430         stat_buf[0] = 0;
1431         stat_buf[1] = 0;
1432         if (info->serial_signals & SerialSignal_RTS)
1433                 strcat(stat_buf, "|RTS");
1434         if (info->serial_signals & SerialSignal_CTS)
1435                 strcat(stat_buf, "|CTS");
1436         if (info->serial_signals & SerialSignal_DTR)
1437                 strcat(stat_buf, "|DTR");
1438         if (info->serial_signals & SerialSignal_DSR)
1439                 strcat(stat_buf, "|DSR");
1440         if (info->serial_signals & SerialSignal_DCD)
1441                 strcat(stat_buf, "|CD");
1442         if (info->serial_signals & SerialSignal_RI)
1443                 strcat(stat_buf, "|RI");
1444
1445         if (info->params.mode == MGSL_MODE_HDLC) {
1446                 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1447                               info->icount.txok, info->icount.rxok);
1448                 if (info->icount.txunder)
1449                         ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1450                 if (info->icount.txabort)
1451                         ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1452                 if (info->icount.rxshort)
1453                         ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1454                 if (info->icount.rxlong)
1455                         ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1456                 if (info->icount.rxover)
1457                         ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1458                 if (info->icount.rxcrc)
1459                         ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxcrc);
1460         } else {
1461                 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1462                               info->icount.tx, info->icount.rx);
1463                 if (info->icount.frame)
1464                         ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1465                 if (info->icount.parity)
1466                         ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1467                 if (info->icount.brk)
1468                         ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1469                 if (info->icount.overrun)
1470                         ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1471         }
1472
1473         /* Append serial signal status to end */
1474         ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1475
1476         ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1477          info->tx_active,info->bh_requested,info->bh_running,
1478          info->pending_bh);
1479
1480         return ret;
1481 }
1482
1483 /* Called to print information about devices
1484  */
1485 int read_proc(char *page, char **start, off_t off, int count,
1486               int *eof, void *data)
1487 {
1488         int len = 0, l;
1489         off_t   begin = 0;
1490         SLMP_INFO *info;
1491
1492         len += sprintf(page, "synclinkmp driver:%s\n", driver_version);
1493
1494         info = synclinkmp_device_list;
1495         while( info ) {
1496                 l = line_info(page + len, info);
1497                 len += l;
1498                 if (len+begin > off+count)
1499                         goto done;
1500                 if (len+begin < off) {
1501                         begin += len;
1502                         len = 0;
1503                 }
1504                 info = info->next_device;
1505         }
1506
1507         *eof = 1;
1508 done:
1509         if (off >= len+begin)
1510                 return 0;
1511         *start = page + (off-begin);
1512         return ((count < begin+len-off) ? count : begin+len-off);
1513 }
1514
1515 /* Return the count of bytes in transmit buffer
1516  */
1517 static int chars_in_buffer(struct tty_struct *tty)
1518 {
1519         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1520
1521         if (sanity_check(info, tty->name, "chars_in_buffer"))
1522                 return 0;
1523
1524         if (debug_level >= DEBUG_LEVEL_INFO)
1525                 printk("%s(%d):%s chars_in_buffer()=%d\n",
1526                        __FILE__, __LINE__, info->device_name, info->tx_count);
1527
1528         return info->tx_count;
1529 }
1530
1531 /* Signal remote device to throttle send data (our receive data)
1532  */
1533 static void throttle(struct tty_struct * tty)
1534 {
1535         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1536         unsigned long flags;
1537
1538         if (debug_level >= DEBUG_LEVEL_INFO)
1539                 printk("%s(%d):%s throttle() entry\n",
1540                          __FILE__,__LINE__, info->device_name );
1541
1542         if (sanity_check(info, tty->name, "throttle"))
1543                 return;
1544
1545         if (I_IXOFF(tty))
1546                 send_xchar(tty, STOP_CHAR(tty));
1547
1548         if (tty->termios->c_cflag & CRTSCTS) {
1549                 spin_lock_irqsave(&info->lock,flags);
1550                 info->serial_signals &= ~SerialSignal_RTS;
1551                 set_signals(info);
1552                 spin_unlock_irqrestore(&info->lock,flags);
1553         }
1554 }
1555
1556 /* Signal remote device to stop throttling send data (our receive data)
1557  */
1558 static void unthrottle(struct tty_struct * tty)
1559 {
1560         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1561         unsigned long flags;
1562
1563         if (debug_level >= DEBUG_LEVEL_INFO)
1564                 printk("%s(%d):%s unthrottle() entry\n",
1565                          __FILE__,__LINE__, info->device_name );
1566
1567         if (sanity_check(info, tty->name, "unthrottle"))
1568                 return;
1569
1570         if (I_IXOFF(tty)) {
1571                 if (info->x_char)
1572                         info->x_char = 0;
1573                 else
1574                         send_xchar(tty, START_CHAR(tty));
1575         }
1576
1577         if (tty->termios->c_cflag & CRTSCTS) {
1578                 spin_lock_irqsave(&info->lock,flags);
1579                 info->serial_signals |= SerialSignal_RTS;
1580                 set_signals(info);
1581                 spin_unlock_irqrestore(&info->lock,flags);
1582         }
1583 }
1584
1585 /* set or clear transmit break condition
1586  * break_state  -1=set break condition, 0=clear
1587  */
1588 static void set_break(struct tty_struct *tty, int break_state)
1589 {
1590         unsigned char RegValue;
1591         SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
1592         unsigned long flags;
1593
1594         if (debug_level >= DEBUG_LEVEL_INFO)
1595                 printk("%s(%d):%s set_break(%d)\n",
1596                          __FILE__,__LINE__, info->device_name, break_state);
1597
1598         if (sanity_check(info, tty->name, "set_break"))
1599                 return;
1600
1601         spin_lock_irqsave(&info->lock,flags);
1602         RegValue = read_reg(info, CTL);
1603         if (break_state == -1)
1604                 RegValue |= BIT3;
1605         else
1606                 RegValue &= ~BIT3;
1607         write_reg(info, CTL, RegValue);
1608         spin_unlock_irqrestore(&info->lock,flags);
1609 }
1610
1611 #ifdef CONFIG_HDLC
1612
1613 /**
1614  * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1615  * set encoding and frame check sequence (FCS) options
1616  *
1617  * dev       pointer to network device structure
1618  * encoding  serial encoding setting
1619  * parity    FCS setting
1620  *
1621  * returns 0 if success, otherwise error code
1622  */
1623 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1624                           unsigned short parity)
1625 {
1626         SLMP_INFO *info = dev_to_port(dev);
1627         unsigned char  new_encoding;
1628         unsigned short new_crctype;
1629
1630         /* return error if TTY interface open */
1631         if (info->count)
1632                 return -EBUSY;
1633
1634         switch (encoding)
1635         {
1636         case ENCODING_NRZ:        new_encoding = HDLC_ENCODING_NRZ; break;
1637         case ENCODING_NRZI:       new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1638         case ENCODING_FM_MARK:    new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1639         case ENCODING_FM_SPACE:   new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1640         case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1641         default: return -EINVAL;
1642         }
1643
1644         switch (parity)
1645         {
1646         case PARITY_NONE:            new_crctype = HDLC_CRC_NONE; break;
1647         case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1648         case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1649         default: return -EINVAL;
1650         }
1651
1652         info->params.encoding = new_encoding;
1653         info->params.crc_type = new_crctype;;
1654
1655         /* if network interface up, reprogram hardware */
1656         if (info->netcount)
1657                 program_hw(info);
1658
1659         return 0;
1660 }
1661
1662 /**
1663  * called by generic HDLC layer to send frame
1664  *
1665  * skb  socket buffer containing HDLC frame
1666  * dev  pointer to network device structure
1667  *
1668  * returns 0 if success, otherwise error code
1669  */
1670 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1671 {
1672         SLMP_INFO *info = dev_to_port(dev);
1673         struct net_device_stats *stats = hdlc_stats(dev);
1674         unsigned long flags;
1675
1676         if (debug_level >= DEBUG_LEVEL_INFO)
1677                 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
1678
1679         /* stop sending until this frame completes */
1680         netif_stop_queue(dev);
1681
1682         /* copy data to device buffers */
1683         info->tx_count = skb->len;
1684         tx_load_dma_buffer(info, skb->data, skb->len);
1685
1686         /* update network statistics */
1687         stats->tx_packets++;
1688         stats->tx_bytes += skb->len;
1689
1690         /* done with socket buffer, so free it */
1691         dev_kfree_skb(skb);
1692
1693         /* save start time for transmit timeout detection */
1694         dev->trans_start = jiffies;
1695
1696         /* start hardware transmitter if necessary */
1697         spin_lock_irqsave(&info->lock,flags);
1698         if (!info->tx_active)
1699                 tx_start(info);
1700         spin_unlock_irqrestore(&info->lock,flags);
1701
1702         return 0;
1703 }
1704
1705 /**
1706  * called by network layer when interface enabled
1707  * claim resources and initialize hardware
1708  *
1709  * dev  pointer to network device structure
1710  *
1711  * returns 0 if success, otherwise error code
1712  */
1713 static int hdlcdev_open(struct net_device *dev)
1714 {
1715         SLMP_INFO *info = dev_to_port(dev);
1716         int rc;
1717         unsigned long flags;
1718
1719         if (debug_level >= DEBUG_LEVEL_INFO)
1720                 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
1721
1722         /* generic HDLC layer open processing */
1723         if ((rc = hdlc_open(dev)))
1724                 return rc;
1725
1726         /* arbitrate between network and tty opens */
1727         spin_lock_irqsave(&info->netlock, flags);
1728         if (info->count != 0 || info->netcount != 0) {
1729                 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
1730                 spin_unlock_irqrestore(&info->netlock, flags);
1731                 return -EBUSY;
1732         }
1733         info->netcount=1;
1734         spin_unlock_irqrestore(&info->netlock, flags);
1735
1736         /* claim resources and init adapter */
1737         if ((rc = startup(info)) != 0) {
1738                 spin_lock_irqsave(&info->netlock, flags);
1739                 info->netcount=0;
1740                 spin_unlock_irqrestore(&info->netlock, flags);
1741                 return rc;
1742         }
1743
1744         /* assert DTR and RTS, apply hardware settings */
1745         info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1746         program_hw(info);
1747
1748         /* enable network layer transmit */
1749         dev->trans_start = jiffies;
1750         netif_start_queue(dev);
1751
1752         /* inform generic HDLC layer of current DCD status */
1753         spin_lock_irqsave(&info->lock, flags);
1754         get_signals(info);
1755         spin_unlock_irqrestore(&info->lock, flags);
1756         hdlc_set_carrier(info->serial_signals & SerialSignal_DCD, dev);
1757
1758         return 0;
1759 }
1760
1761 /**
1762  * called by network layer when interface is disabled
1763  * shutdown hardware and release resources
1764  *
1765  * dev  pointer to network device structure
1766  *
1767  * returns 0 if success, otherwise error code
1768  */
1769 static int hdlcdev_close(struct net_device *dev)
1770 {
1771         SLMP_INFO *info = dev_to_port(dev);
1772         unsigned long flags;
1773
1774         if (debug_level >= DEBUG_LEVEL_INFO)
1775                 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
1776
1777         netif_stop_queue(dev);
1778
1779         /* shutdown adapter and release resources */
1780         shutdown(info);
1781
1782         hdlc_close(dev);
1783
1784         spin_lock_irqsave(&info->netlock, flags);
1785         info->netcount=0;
1786         spin_unlock_irqrestore(&info->netlock, flags);
1787
1788         return 0;
1789 }
1790
1791 /**
1792  * called by network layer to process IOCTL call to network device
1793  *
1794  * dev  pointer to network device structure
1795  * ifr  pointer to network interface request structure
1796  * cmd  IOCTL command code
1797  *
1798  * returns 0 if success, otherwise error code
1799  */
1800 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1801 {
1802         const size_t size = sizeof(sync_serial_settings);
1803         sync_serial_settings new_line;
1804         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1805         SLMP_INFO *info = dev_to_port(dev);
1806         unsigned int flags;
1807
1808         if (debug_level >= DEBUG_LEVEL_INFO)
1809                 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
1810
1811         /* return error if TTY interface open */
1812         if (info->count)
1813                 return -EBUSY;
1814
1815         if (cmd != SIOCWANDEV)
1816                 return hdlc_ioctl(dev, ifr, cmd);
1817
1818         switch(ifr->ifr_settings.type) {
1819         case IF_GET_IFACE: /* return current sync_serial_settings */
1820
1821                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1822                 if (ifr->ifr_settings.size < size) {
1823                         ifr->ifr_settings.size = size; /* data size wanted */
1824                         return -ENOBUFS;
1825                 }
1826
1827                 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1828                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1829                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1830                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1831
1832                 switch (flags){
1833                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1834                 case (HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_INT; break;
1835                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG):    new_line.clock_type = CLOCK_TXINT; break;
1836                 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1837                 default: new_line.clock_type = CLOCK_DEFAULT;
1838                 }
1839
1840                 new_line.clock_rate = info->params.clock_speed;
1841                 new_line.loopback   = info->params.loopback ? 1:0;
1842
1843                 if (copy_to_user(line, &new_line, size))
1844                         return -EFAULT;
1845                 return 0;
1846
1847         case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1848
1849                 if(!capable(CAP_NET_ADMIN))
1850                         return -EPERM;
1851                 if (copy_from_user(&new_line, line, size))
1852                         return -EFAULT;
1853
1854                 switch (new_line.clock_type)
1855                 {
1856                 case CLOCK_EXT:      flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1857                 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1858                 case CLOCK_INT:      flags = HDLC_FLAG_RXC_BRG    | HDLC_FLAG_TXC_BRG;    break;
1859                 case CLOCK_TXINT:    flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG;    break;
1860                 case CLOCK_DEFAULT:  flags = info->params.flags &
1861                                              (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1862                                               HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1863                                               HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1864                                               HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN); break;
1865                 default: return -EINVAL;
1866                 }
1867
1868                 if (new_line.loopback != 0 && new_line.loopback != 1)
1869                         return -EINVAL;
1870
1871                 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1872                                         HDLC_FLAG_RXC_BRG    | HDLC_FLAG_RXC_TXCPIN |
1873                                         HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1874                                         HDLC_FLAG_TXC_BRG    | HDLC_FLAG_TXC_RXCPIN);
1875                 info->params.flags |= flags;
1876
1877                 info->params.loopback = new_line.loopback;
1878
1879                 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1880                         info->params.clock_speed = new_line.clock_rate;
1881                 else
1882                         info->params.clock_speed = 0;
1883
1884                 /* if network interface up, reprogram hardware */
1885                 if (info->netcount)
1886                         program_hw(info);
1887                 return 0;
1888
1889         default:
1890                 return hdlc_ioctl(dev, ifr, cmd);
1891         }
1892 }
1893
1894 /**
1895  * called by network layer when transmit timeout is detected
1896  *
1897  * dev  pointer to network device structure
1898  */
1899 static void hdlcdev_tx_timeout(struct net_device *dev)
1900 {
1901         SLMP_INFO *info = dev_to_port(dev);
1902         struct net_device_stats *stats = hdlc_stats(dev);
1903         unsigned long flags;
1904
1905         if (debug_level >= DEBUG_LEVEL_INFO)
1906                 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
1907
1908         stats->tx_errors++;
1909         stats->tx_aborted_errors++;
1910
1911         spin_lock_irqsave(&info->lock,flags);
1912         tx_stop(info);
1913         spin_unlock_irqrestore(&info->lock,flags);
1914
1915         netif_wake_queue(dev);
1916 }
1917
1918 /**
1919  * called by device driver when transmit completes
1920  * reenable network layer transmit if stopped
1921  *
1922  * info  pointer to device instance information
1923  */
1924 static void hdlcdev_tx_done(SLMP_INFO *info)
1925 {
1926         if (netif_queue_stopped(info->netdev))
1927                 netif_wake_queue(info->netdev);
1928 }
1929
1930 /**
1931  * called by device driver when frame received
1932  * pass frame to network layer
1933  *
1934  * info  pointer to device instance information
1935  * buf   pointer to buffer contianing frame data
1936  * size  count of data bytes in buf
1937  */
1938 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size)
1939 {
1940         struct sk_buff *skb = dev_alloc_skb(size);
1941         struct net_device *dev = info->netdev;
1942         struct net_device_stats *stats = hdlc_stats(dev);
1943
1944         if (debug_level >= DEBUG_LEVEL_INFO)
1945                 printk("hdlcdev_rx(%s)\n",dev->name);
1946
1947         if (skb == NULL) {
1948                 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n", dev->name);
1949                 stats->rx_dropped++;
1950                 return;
1951         }
1952
1953         memcpy(skb_put(skb, size),buf,size);
1954
1955         skb->protocol = hdlc_type_trans(skb, info->netdev);
1956
1957         stats->rx_packets++;
1958         stats->rx_bytes += size;
1959
1960         netif_rx(skb);
1961
1962         info->netdev->last_rx = jiffies;
1963 }
1964
1965 /**
1966  * called by device driver when adding device instance
1967  * do generic HDLC initialization
1968  *
1969  * info  pointer to device instance information
1970  *
1971  * returns 0 if success, otherwise error code
1972  */
1973 static int hdlcdev_init(SLMP_INFO *info)
1974 {
1975         int rc;
1976         struct net_device *dev;
1977         hdlc_device *hdlc;
1978
1979         /* allocate and initialize network and HDLC layer objects */
1980
1981         if (!(dev = alloc_hdlcdev(info))) {
1982                 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
1983                 return -ENOMEM;
1984         }
1985
1986         /* for network layer reporting purposes only */
1987         dev->mem_start = info->phys_sca_base;
1988         dev->mem_end   = info->phys_sca_base + SCA_BASE_SIZE - 1;
1989         dev->irq       = info->irq_level;
1990
1991         /* network layer callbacks and settings */
1992         dev->do_ioctl       = hdlcdev_ioctl;
1993         dev->open           = hdlcdev_open;
1994         dev->stop           = hdlcdev_close;
1995         dev->tx_timeout     = hdlcdev_tx_timeout;
1996         dev->watchdog_timeo = 10*HZ;
1997         dev->tx_queue_len   = 50;
1998
1999         /* generic HDLC layer callbacks and settings */
2000         hdlc         = dev_to_hdlc(dev);
2001         hdlc->attach = hdlcdev_attach;
2002         hdlc->xmit   = hdlcdev_xmit;
2003
2004         /* register objects with HDLC layer */
2005         if ((rc = register_hdlc_device(dev))) {
2006                 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
2007                 free_netdev(dev);
2008                 return rc;
2009         }
2010
2011         info->netdev = dev;
2012         return 0;
2013 }
2014
2015 /**
2016  * called by device driver when removing device instance
2017  * do generic HDLC cleanup
2018  *
2019  * info  pointer to device instance information
2020  */
2021 static void hdlcdev_exit(SLMP_INFO *info)
2022 {
2023         unregister_hdlc_device(info->netdev);
2024         free_netdev(info->netdev);
2025         info->netdev = NULL;
2026 }
2027
2028 #endif /* CONFIG_HDLC */
2029
2030
2031 /* Return next bottom half action to perform.
2032  * Return Value:        BH action code or 0 if nothing to do.
2033  */
2034 int bh_action(SLMP_INFO *info)
2035 {
2036         unsigned long flags;
2037         int rc = 0;
2038
2039         spin_lock_irqsave(&info->lock,flags);
2040
2041         if (info->pending_bh & BH_RECEIVE) {
2042                 info->pending_bh &= ~BH_RECEIVE;
2043                 rc = BH_RECEIVE;
2044         } else if (info->pending_bh & BH_TRANSMIT) {
2045                 info->pending_bh &= ~BH_TRANSMIT;
2046                 rc = BH_TRANSMIT;
2047         } else if (info->pending_bh & BH_STATUS) {
2048                 info->pending_bh &= ~BH_STATUS;
2049                 rc = BH_STATUS;
2050         }
2051
2052         if (!rc) {
2053                 /* Mark BH routine as complete */
2054                 info->bh_running   = 0;
2055                 info->bh_requested = 0;
2056         }
2057
2058         spin_unlock_irqrestore(&info->lock,flags);
2059
2060         return rc;
2061 }
2062
2063 /* Perform bottom half processing of work items queued by ISR.
2064  */
2065 void bh_handler(void* Context)
2066 {
2067         SLMP_INFO *info = (SLMP_INFO*)Context;
2068         int action;
2069
2070         if (!info)
2071                 return;
2072
2073         if ( debug_level >= DEBUG_LEVEL_BH )
2074                 printk( "%s(%d):%s bh_handler() entry\n",
2075                         __FILE__,__LINE__,info->device_name);
2076
2077         info->bh_running = 1;
2078
2079         while((action = bh_action(info)) != 0) {
2080
2081                 /* Process work item */
2082                 if ( debug_level >= DEBUG_LEVEL_BH )
2083                         printk( "%s(%d):%s bh_handler() work item action=%d\n",
2084                                 __FILE__,__LINE__,info->device_name, action);
2085
2086                 switch (action) {
2087
2088                 case BH_RECEIVE:
2089                         bh_receive(info);
2090                         break;
2091                 case BH_TRANSMIT:
2092                         bh_transmit(info);
2093                         break;
2094                 case BH_STATUS:
2095                         bh_status(info);
2096                         break;
2097                 default:
2098                         /* unknown work item ID */
2099                         printk("%s(%d):%s Unknown work item ID=%08X!\n",
2100                                 __FILE__,__LINE__,info->device_name,action);
2101                         break;
2102                 }
2103         }
2104
2105         if ( debug_level >= DEBUG_LEVEL_BH )
2106                 printk( "%s(%d):%s bh_handler() exit\n",
2107                         __FILE__,__LINE__,info->device_name);
2108 }
2109
2110 void bh_receive(SLMP_INFO *info)
2111 {
2112         if ( debug_level >= DEBUG_LEVEL_BH )
2113                 printk( "%s(%d):%s bh_receive()\n",
2114                         __FILE__,__LINE__,info->device_name);
2115
2116         while( rx_get_frame(info) );
2117 }
2118
2119 void bh_transmit(SLMP_INFO *info)
2120 {
2121         struct tty_struct *tty = info->tty;
2122
2123         if ( debug_level >= DEBUG_LEVEL_BH )
2124                 printk( "%s(%d):%s bh_transmit() entry\n",
2125                         __FILE__,__LINE__,info->device_name);
2126
2127         if (tty) {
2128                 tty_wakeup(tty);
2129                 wake_up_interruptible(&tty->write_wait);
2130         }
2131 }
2132
2133 void bh_status(SLMP_INFO *info)
2134 {
2135         if ( debug_level >= DEBUG_LEVEL_BH )
2136                 printk( "%s(%d):%s bh_status() entry\n",
2137                         __FILE__,__LINE__,info->device_name);
2138
2139         info->ri_chkcount = 0;
2140         info->dsr_chkcount = 0;
2141         info->dcd_chkcount = 0;
2142         info->cts_chkcount = 0;
2143 }
2144
2145 void isr_timer(SLMP_INFO * info)
2146 {
2147         unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
2148
2149         /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
2150         write_reg(info, IER2, 0);
2151
2152         /* TMCS, Timer Control/Status Register
2153          *
2154          * 07      CMF, Compare match flag (read only) 1=match
2155          * 06      ECMI, CMF Interrupt Enable: 0=disabled
2156          * 05      Reserved, must be 0
2157          * 04      TME, Timer Enable
2158          * 03..00  Reserved, must be 0
2159          *
2160          * 0000 0000
2161          */
2162         write_reg(info, (unsigned char)(timer + TMCS), 0);
2163
2164         info->irq_occurred = TRUE;
2165
2166         if ( debug_level >= DEBUG_LEVEL_ISR )
2167                 printk("%s(%d):%s isr_timer()\n",
2168                         __FILE__,__LINE__,info->device_name);
2169 }
2170
2171 void isr_rxint(SLMP_INFO * info)
2172 {
2173         struct tty_struct *tty = info->tty;
2174         struct  mgsl_icount *icount = &info->icount;
2175         unsigned char status = read_reg(info, SR1) & info->ie1_value & (FLGD + IDLD + CDCD + BRKD);
2176         unsigned char status2 = read_reg(info, SR2) & info->ie2_value & OVRN;
2177
2178         /* clear status bits */
2179         if (status)
2180                 write_reg(info, SR1, status);
2181
2182         if (status2)
2183                 write_reg(info, SR2, status2);
2184
2185         if ( debug_level >= DEBUG_LEVEL_ISR )
2186                 printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2187                         __FILE__,__LINE__,info->device_name,status,status2);
2188
2189         if (info->params.mode == MGSL_MODE_ASYNC) {
2190                 if (status & BRKD) {
2191                         icount->brk++;
2192
2193                         /* process break detection if tty control
2194                          * is not set to ignore it
2195                          */
2196                         if ( tty ) {
2197                                 if (!(status & info->ignore_status_mask1)) {
2198                                         if (info->read_status_mask1 & BRKD) {
2199                                                 tty_insert_flip_char(tty, 0, TTY_BREAK);
2200                                                 if (info->flags & ASYNC_SAK)
2201                                                         do_SAK(tty);
2202                                         }
2203                                 }
2204                         }
2205                 }
2206         }
2207         else {
2208                 if (status & (FLGD|IDLD)) {
2209                         if (status & FLGD)
2210                                 info->icount.exithunt++;
2211                         else if (status & IDLD)
2212                                 info->icount.rxidle++;
2213                         wake_up_interruptible(&info->event_wait_q);
2214                 }
2215         }
2216
2217         if (status & CDCD) {
2218                 /* simulate a common modem status change interrupt
2219                  * for our handler
2220                  */
2221                 get_signals( info );
2222                 isr_io_pin(info,
2223                         MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD));
2224         }
2225 }
2226
2227 /*
2228  * handle async rx data interrupts
2229  */
2230 void isr_rxrdy(SLMP_INFO * info)
2231 {
2232         u16 status;
2233         unsigned char DataByte;
2234         struct tty_struct *tty = info->tty;
2235         struct  mgsl_icount *icount = &info->icount;
2236
2237         if ( debug_level >= DEBUG_LEVEL_ISR )
2238                 printk("%s(%d):%s isr_rxrdy\n",
2239                         __FILE__,__LINE__,info->device_name);
2240
2241         while((status = read_reg(info,CST0)) & BIT0)
2242         {
2243                 int flag = 0;
2244                 int over = 0;
2245                 DataByte = read_reg(info,TRB);
2246
2247                 icount->rx++;
2248
2249                 if ( status & (PE + FRME + OVRN) ) {
2250                         printk("%s(%d):%s rxerr=%04X\n",
2251                                 __FILE__,__LINE__,info->device_name,status);
2252
2253                         /* update error statistics */
2254                         if (status & PE)
2255                                 icount->parity++;
2256                         else if (status & FRME)
2257                                 icount->frame++;
2258                         else if (status & OVRN)
2259                                 icount->overrun++;
2260
2261                         /* discard char if tty control flags say so */
2262                         if (status & info->ignore_status_mask2)
2263                                 continue;
2264
2265                         status &= info->read_status_mask2;
2266
2267                         if ( tty ) {
2268                                 if (status & PE)
2269                                         flag = TTY_PARITY;
2270                                 else if (status & FRME)
2271                                         flag = TTY_FRAME;
2272                                 if (status & OVRN) {
2273                                         /* Overrun is special, since it's
2274                                          * reported immediately, and doesn't
2275                                          * affect the current character
2276                                          */
2277                                         over = 1;
2278                                 }
2279                         }
2280                 }       /* end of if (error) */
2281
2282                 if ( tty ) {
2283                         tty_insert_flip_char(tty, DataByte, flag);
2284                         if (over)
2285                                 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
2286                 }
2287         }
2288
2289         if ( debug_level >= DEBUG_LEVEL_ISR ) {
2290                 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2291                         __FILE__,__LINE__,info->device_name,
2292                         icount->rx,icount->brk,icount->parity,
2293                         icount->frame,icount->overrun);
2294         }
2295
2296         if ( tty )
2297                 tty_flip_buffer_push(tty);
2298 }
2299
2300 static void isr_txeom(SLMP_INFO * info, unsigned char status)
2301 {
2302         if ( debug_level >= DEBUG_LEVEL_ISR )
2303                 printk("%s(%d):%s isr_txeom status=%02x\n",
2304                         __FILE__,__LINE__,info->device_name,status);
2305
2306         write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2307         write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2308         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2309
2310         if (status & UDRN) {
2311                 write_reg(info, CMD, TXRESET);
2312                 write_reg(info, CMD, TXENABLE);
2313         } else
2314                 write_reg(info, CMD, TXBUFCLR);
2315
2316         /* disable and clear tx interrupts */
2317         info->ie0_value &= ~TXRDYE;
2318         info->ie1_value &= ~(IDLE + UDRN);
2319         write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2320         write_reg(info, SR1, (unsigned char)(UDRN + IDLE));
2321
2322         if ( info->tx_active ) {
2323                 if (info->params.mode != MGSL_MODE_ASYNC) {
2324                         if (status & UDRN)
2325                                 info->icount.txunder++;
2326                         else if (status & IDLE)
2327                                 info->icount.txok++;
2328                 }
2329
2330                 info->tx_active = 0;
2331                 info->tx_count = info->tx_put = info->tx_get = 0;
2332
2333                 del_timer(&info->tx_timer);
2334
2335                 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) {
2336                         info->serial_signals &= ~SerialSignal_RTS;
2337                         info->drop_rts_on_tx_done = 0;
2338                         set_signals(info);
2339                 }
2340
2341 #ifdef CONFIG_HDLC
2342                 if (info->netcount)
2343                         hdlcdev_tx_done(info);
2344                 else
2345 #endif
2346                 {
2347                         if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2348                                 tx_stop(info);
2349                                 return;
2350                         }
2351                         info->pending_bh |= BH_TRANSMIT;
2352                 }
2353         }
2354 }
2355
2356
2357 /*
2358  * handle tx status interrupts
2359  */
2360 void isr_txint(SLMP_INFO * info)
2361 {
2362         unsigned char status = read_reg(info, SR1) & info->ie1_value & (UDRN + IDLE + CCTS);
2363
2364         /* clear status bits */
2365         write_reg(info, SR1, status);
2366
2367         if ( debug_level >= DEBUG_LEVEL_ISR )
2368                 printk("%s(%d):%s isr_txint status=%02x\n",
2369                         __FILE__,__LINE__,info->device_name,status);
2370
2371         if (status & (UDRN + IDLE))
2372                 isr_txeom(info, status);
2373
2374         if (status & CCTS) {
2375                 /* simulate a common modem status change interrupt
2376                  * for our handler
2377                  */
2378                 get_signals( info );
2379                 isr_io_pin(info,
2380                         MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS));
2381
2382         }
2383 }
2384
2385 /*
2386  * handle async tx data interrupts
2387  */
2388 void isr_txrdy(SLMP_INFO * info)
2389 {
2390         if ( debug_level >= DEBUG_LEVEL_ISR )
2391                 printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2392                         __FILE__,__LINE__,info->device_name,info->tx_count);
2393
2394         if (info->params.mode != MGSL_MODE_ASYNC) {
2395                 /* disable TXRDY IRQ, enable IDLE IRQ */
2396                 info->ie0_value &= ~TXRDYE;
2397                 info->ie1_value |= IDLE;
2398                 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2399                 return;
2400         }
2401
2402         if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2403                 tx_stop(info);
2404                 return;
2405         }
2406
2407         if ( info->tx_count )
2408                 tx_load_fifo( info );
2409         else {
2410                 info->tx_active = 0;
2411                 info->ie0_value &= ~TXRDYE;
2412                 write_reg(info, IE0, info->ie0_value);
2413         }
2414
2415         if (info->tx_count < WAKEUP_CHARS)
2416                 info->pending_bh |= BH_TRANSMIT;
2417 }
2418
2419 void isr_rxdmaok(SLMP_INFO * info)
2420 {
2421         /* BIT7 = EOT (end of transfer)
2422          * BIT6 = EOM (end of message/frame)
2423          */
2424         unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0;
2425
2426         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2427         write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2428
2429         if ( debug_level >= DEBUG_LEVEL_ISR )
2430                 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2431                         __FILE__,__LINE__,info->device_name,status);
2432
2433         info->pending_bh |= BH_RECEIVE;
2434 }
2435
2436 void isr_rxdmaerror(SLMP_INFO * info)
2437 {
2438         /* BIT5 = BOF (buffer overflow)
2439          * BIT4 = COF (counter overflow)
2440          */
2441         unsigned char status = read_reg(info,RXDMA + DSR) & 0x30;
2442
2443         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2444         write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2445
2446         if ( debug_level >= DEBUG_LEVEL_ISR )
2447                 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2448                         __FILE__,__LINE__,info->device_name,status);
2449
2450         info->rx_overflow = TRUE;
2451         info->pending_bh |= BH_RECEIVE;
2452 }
2453
2454 void isr_txdmaok(SLMP_INFO * info)
2455 {
2456         unsigned char status_reg1 = read_reg(info, SR1);
2457
2458         write_reg(info, TXDMA + DIR, 0x00);     /* disable Tx DMA IRQs */
2459         write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2460         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2461
2462         if ( debug_level >= DEBUG_LEVEL_ISR )
2463                 printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2464                         __FILE__,__LINE__,info->device_name,status_reg1);
2465
2466         /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */
2467         write_reg16(info, TRC0, 0);
2468         info->ie0_value |= TXRDYE;
2469         write_reg(info, IE0, info->ie0_value);
2470 }
2471
2472 void isr_txdmaerror(SLMP_INFO * info)
2473 {
2474         /* BIT5 = BOF (buffer overflow)
2475          * BIT4 = COF (counter overflow)
2476          */
2477         unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
2478
2479         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2480         write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
2481
2482         if ( debug_level >= DEBUG_LEVEL_ISR )
2483                 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2484                         __FILE__,__LINE__,info->device_name,status);
2485 }
2486
2487 /* handle input serial signal changes
2488  */
2489 void isr_io_pin( SLMP_INFO *info, u16 status )
2490 {
2491         struct  mgsl_icount *icount;
2492
2493         if ( debug_level >= DEBUG_LEVEL_ISR )
2494                 printk("%s(%d):isr_io_pin status=%04X\n",
2495                         __FILE__,__LINE__,status);
2496
2497         if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
2498                       MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
2499                 icount = &info->icount;
2500                 /* update input line counters */
2501                 if (status & MISCSTATUS_RI_LATCHED) {
2502                         icount->rng++;
2503                         if ( status & SerialSignal_RI )
2504                                 info->input_signal_events.ri_up++;
2505                         else
2506                                 info->input_signal_events.ri_down++;
2507                 }
2508                 if (status & MISCSTATUS_DSR_LATCHED) {
2509                         icount->dsr++;
2510                         if ( status & SerialSignal_DSR )
2511                                 info->input_signal_events.dsr_up++;
2512                         else
2513                                 info->input_signal_events.dsr_down++;
2514                 }
2515                 if (status & MISCSTATUS_DCD_LATCHED) {
2516                         if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2517                                 info->ie1_value &= ~CDCD;
2518                                 write_reg(info, IE1, info->ie1_value);
2519                         }
2520                         icount->dcd++;
2521                         if (status & SerialSignal_DCD) {
2522                                 info->input_signal_events.dcd_up++;
2523                         } else
2524                                 info->input_signal_events.dcd_down++;
2525 #ifdef CONFIG_HDLC
2526                         if (info->netcount)
2527                                 hdlc_set_carrier(status & SerialSignal_DCD, info->netdev);
2528 #endif
2529                 }
2530                 if (status & MISCSTATUS_CTS_LATCHED)
2531                 {
2532                         if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2533                                 info->ie1_value &= ~CCTS;
2534                                 write_reg(info, IE1, info->ie1_value);
2535                         }
2536                         icount->cts++;
2537                         if ( status & SerialSignal_CTS )
2538                                 info->input_signal_events.cts_up++;
2539                         else
2540                                 info->input_signal_events.cts_down++;
2541                 }
2542                 wake_up_interruptible(&info->status_event_wait_q);
2543                 wake_up_interruptible(&info->event_wait_q);
2544
2545                 if ( (info->flags & ASYNC_CHECK_CD) &&
2546                      (status & MISCSTATUS_DCD_LATCHED) ) {
2547                         if ( debug_level >= DEBUG_LEVEL_ISR )
2548                                 printk("%s CD now %s...", info->device_name,
2549                                        (status & SerialSignal_DCD) ? "on" : "off");
2550                         if (status & SerialSignal_DCD)
2551                                 wake_up_interruptible(&info->open_wait);
2552                         else {
2553                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2554                                         printk("doing serial hangup...");
2555                                 if (info->tty)
2556                                         tty_hangup(info->tty);
2557                         }
2558                 }
2559
2560                 if ( (info->flags & ASYNC_CTS_FLOW) &&
2561                      (status & MISCSTATUS_CTS_LATCHED) ) {
2562                         if ( info->tty ) {
2563                                 if (info->tty->hw_stopped) {
2564                                         if (status & SerialSignal_CTS) {
2565                                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2566                                                         printk("CTS tx start...");
2567                                                 info->tty->hw_stopped = 0;
2568                                                 tx_start(info);
2569                                                 info->pending_bh |= BH_TRANSMIT;
2570                                                 return;
2571                                         }
2572                                 } else {
2573                                         if (!(status & SerialSignal_CTS)) {
2574                                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2575                                                         printk("CTS tx stop...");
2576                                                 info->tty->hw_stopped = 1;
2577                                                 tx_stop(info);
2578                                         }
2579                                 }
2580                         }
2581                 }
2582         }
2583
2584         info->pending_bh |= BH_STATUS;
2585 }
2586
2587 /* Interrupt service routine entry point.
2588  *
2589  * Arguments:
2590  *      irq             interrupt number that caused interrupt
2591  *      dev_id          device ID supplied during interrupt registration
2592  *      regs            interrupted processor context
2593  */
2594 static irqreturn_t synclinkmp_interrupt(int irq, void *dev_id,
2595                                         struct pt_regs *regs)
2596 {
2597         SLMP_INFO * info;
2598         unsigned char status, status0, status1=0;
2599         unsigned char dmastatus, dmastatus0, dmastatus1=0;
2600         unsigned char timerstatus0, timerstatus1=0;
2601         unsigned char shift;
2602         unsigned int i;
2603         unsigned short tmp;
2604
2605         if ( debug_level >= DEBUG_LEVEL_ISR )
2606                 printk("%s(%d): synclinkmp_interrupt(%d)entry.\n",
2607                         __FILE__,__LINE__,irq);
2608
2609         info = (SLMP_INFO *)dev_id;
2610         if (!info)
2611                 return IRQ_NONE;
2612
2613         spin_lock(&info->lock);
2614
2615         for(;;) {
2616
2617                 /* get status for SCA0 (ports 0-1) */
2618                 tmp = read_reg16(info, ISR0);   /* get ISR0 and ISR1 in one read */
2619                 status0 = (unsigned char)tmp;
2620                 dmastatus0 = (unsigned char)(tmp>>8);
2621                 timerstatus0 = read_reg(info, ISR2);
2622
2623                 if ( debug_level >= DEBUG_LEVEL_ISR )
2624                         printk("%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2625                                 __FILE__,__LINE__,info->device_name,
2626                                 status0,dmastatus0,timerstatus0);
2627
2628                 if (info->port_count == 4) {
2629                         /* get status for SCA1 (ports 2-3) */
2630                         tmp = read_reg16(info->port_array[2], ISR0);
2631                         status1 = (unsigned char)tmp;
2632                         dmastatus1 = (unsigned char)(tmp>>8);
2633                         timerstatus1 = read_reg(info->port_array[2], ISR2);
2634
2635                         if ( debug_level >= DEBUG_LEVEL_ISR )
2636                                 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2637                                         __FILE__,__LINE__,info->device_name,
2638                                         status1,dmastatus1,timerstatus1);
2639                 }
2640
2641                 if (!status0 && !dmastatus0 && !timerstatus0 &&
2642                          !status1 && !dmastatus1 && !timerstatus1)
2643                         break;
2644
2645                 for(i=0; i < info->port_count ; i++) {
2646                         if (info->port_array[i] == NULL)
2647                                 continue;
2648                         if (i < 2) {
2649                                 status = status0;
2650                                 dmastatus = dmastatus0;
2651                         } else {
2652                                 status = status1;
2653                                 dmastatus = dmastatus1;
2654                         }
2655
2656                         shift = i & 1 ? 4 :0;
2657
2658                         if (status & BIT0 << shift)
2659                                 isr_rxrdy(info->port_array[i]);
2660                         if (status & BIT1 << shift)
2661                                 isr_txrdy(info->port_array[i]);
2662                         if (status & BIT2 << shift)
2663                                 isr_rxint(info->port_array[i]);
2664                         if (status & BIT3 << shift)
2665                                 isr_txint(info->port_array[i]);
2666
2667                         if (dmastatus & BIT0 << shift)
2668                                 isr_rxdmaerror(info->port_array[i]);
2669                         if (dmastatus & BIT1 << shift)
2670                                 isr_rxdmaok(info->port_array[i]);
2671                         if (dmastatus & BIT2 << shift)
2672                                 isr_txdmaerror(info->port_array[i]);
2673                         if (dmastatus & BIT3 << shift)
2674                                 isr_txdmaok(info->port_array[i]);
2675                 }
2676
2677                 if (timerstatus0 & (BIT5 | BIT4))
2678                         isr_timer(info->port_array[0]);
2679                 if (timerstatus0 & (BIT7 | BIT6))
2680                         isr_timer(info->port_array[1]);
2681                 if (timerstatus1 & (BIT5 | BIT4))
2682                         isr_timer(info->port_array[2]);
2683                 if (timerstatus1 & (BIT7 | BIT6))
2684                         isr_timer(info->port_array[3]);
2685         }
2686
2687         for(i=0; i < info->port_count ; i++) {
2688                 SLMP_INFO * port = info->port_array[i];
2689
2690                 /* Request bottom half processing if there's something
2691                  * for it to do and the bh is not already running.
2692                  *
2693                  * Note: startup adapter diags require interrupts.
2694                  * do not request bottom half processing if the
2695                  * device is not open in a normal mode.
2696                  */
2697                 if ( port && (port->count || port->netcount) &&
2698                      port->pending_bh && !port->bh_running &&
2699                      !port->bh_requested ) {
2700                         if ( debug_level >= DEBUG_LEVEL_ISR )
2701                                 printk("%s(%d):%s queueing bh task.\n",
2702                                         __FILE__,__LINE__,port->device_name);
2703                         schedule_work(&port->task);
2704                         port->bh_requested = 1;
2705                 }
2706         }
2707
2708         spin_unlock(&info->lock);
2709
2710         if ( debug_level >= DEBUG_LEVEL_ISR )
2711                 printk("%s(%d):synclinkmp_interrupt(%d)exit.\n",
2712                         __FILE__,__LINE__,irq);
2713         return IRQ_HANDLED;
2714 }
2715
2716 /* Initialize and start device.
2717  */
2718 static int startup(SLMP_INFO * info)
2719 {
2720         if ( debug_level >= DEBUG_LEVEL_INFO )
2721                 printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name);
2722
2723         if (info->flags & ASYNC_INITIALIZED)
2724                 return 0;
2725
2726         if (!info->tx_buf) {
2727                 info->tx_buf = (unsigned char *)kmalloc(info->max_frame_size, GFP_KERNEL);
2728                 if (!info->tx_buf) {
2729                         printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
2730                                 __FILE__,__LINE__,info->device_name);
2731                         return -ENOMEM;
2732                 }
2733         }
2734
2735         info->pending_bh = 0;
2736
2737         memset(&info->icount, 0, sizeof(info->icount));
2738
2739         /* program hardware for current parameters */
2740         reset_port(info);
2741
2742         change_params(info);
2743
2744         info->status_timer.expires = jiffies + msecs_to_jiffies(10);
2745         add_timer(&info->status_timer);
2746
2747         if (info->tty)
2748                 clear_bit(TTY_IO_ERROR, &info->tty->flags);
2749
2750         info->flags |= ASYNC_INITIALIZED;
2751
2752         return 0;
2753 }
2754
2755 /* Called by close() and hangup() to shutdown hardware
2756  */
2757 static void shutdown(SLMP_INFO * info)
2758 {
2759         unsigned long flags;
2760
2761         if (!(info->flags & ASYNC_INITIALIZED))
2762                 return;
2763
2764         if (debug_level >= DEBUG_LEVEL_INFO)
2765                 printk("%s(%d):%s synclinkmp_shutdown()\n",
2766                          __FILE__,__LINE__, info->device_name );
2767
2768         /* clear status wait queue because status changes */
2769         /* can't happen after shutting down the hardware */
2770         wake_up_interruptible(&info->status_event_wait_q);
2771         wake_up_interruptible(&info->event_wait_q);
2772
2773         del_timer(&info->tx_timer);
2774         del_timer(&info->status_timer);
2775
2776         kfree(info->tx_buf);
2777         info->tx_buf = NULL;
2778
2779         spin_lock_irqsave(&info->lock,flags);
2780
2781         reset_port(info);
2782
2783         if (!info->tty || info->tty->termios->c_cflag & HUPCL) {
2784                 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2785                 set_signals(info);
2786         }
2787
2788         spin_unlock_irqrestore(&info->lock,flags);
2789
2790         if (info->tty)
2791                 set_bit(TTY_IO_ERROR, &info->tty->flags);
2792
2793         info->flags &= ~ASYNC_INITIALIZED;
2794 }
2795
2796 static void program_hw(SLMP_INFO *info)
2797 {
2798         unsigned long flags;
2799
2800         spin_lock_irqsave(&info->lock,flags);
2801
2802         rx_stop(info);
2803         tx_stop(info);
2804
2805         info->tx_count = info->tx_put = info->tx_get = 0;
2806
2807         if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
2808                 hdlc_mode(info);
2809         else
2810                 async_mode(info);
2811
2812         set_signals(info);
2813
2814         info->dcd_chkcount = 0;
2815         info->cts_chkcount = 0;
2816         info->ri_chkcount = 0;
2817         info->dsr_chkcount = 0;
2818
2819         info->ie1_value |= (CDCD|CCTS);
2820         write_reg(info, IE1, info->ie1_value);
2821
2822         get_signals(info);
2823
2824         if (info->netcount || (info->tty && info->tty->termios->c_cflag & CREAD) )
2825                 rx_start(info);
2826
2827         spin_unlock_irqrestore(&info->lock,flags);
2828 }
2829
2830 /* Reconfigure adapter based on new parameters
2831  */
2832 static void change_params(SLMP_INFO *info)
2833 {
2834         unsigned cflag;
2835         int bits_per_char;
2836
2837         if (!info->tty || !info->tty->termios)
2838                 return;
2839
2840         if (debug_level >= DEBUG_LEVEL_INFO)
2841                 printk("%s(%d):%s change_params()\n",
2842                          __FILE__,__LINE__, info->device_name );
2843
2844         cflag = info->tty->termios->c_cflag;
2845
2846         /* if B0 rate (hangup) specified then negate DTR and RTS */
2847         /* otherwise assert DTR and RTS */
2848         if (cflag & CBAUD)
2849                 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
2850         else
2851                 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2852
2853         /* byte size and parity */
2854
2855         switch (cflag & CSIZE) {
2856               case CS5: info->params.data_bits = 5; break;
2857               case CS6: info->params.data_bits = 6; break;
2858               case CS7: info->params.data_bits = 7; break;
2859               case CS8: info->params.data_bits = 8; break;
2860               /* Never happens, but GCC is too dumb to figure it out */
2861               default:  info->params.data_bits = 7; break;
2862               }
2863
2864         if (cflag & CSTOPB)
2865                 info->params.stop_bits = 2;
2866         else
2867                 info->params.stop_bits = 1;
2868
2869         info->params.parity = ASYNC_PARITY_NONE;
2870         if (cflag & PARENB) {
2871                 if (cflag & PARODD)
2872                         info->params.parity = ASYNC_PARITY_ODD;
2873                 else
2874                         info->params.parity = ASYNC_PARITY_EVEN;
2875 #ifdef CMSPAR
2876                 if (cflag & CMSPAR)
2877                         info->params.parity = ASYNC_PARITY_SPACE;
2878 #endif
2879         }
2880
2881         /* calculate number of jiffies to transmit a full
2882          * FIFO (32 bytes) at specified data rate
2883          */
2884         bits_per_char = info->params.data_bits +
2885                         info->params.stop_bits + 1;
2886
2887         /* if port data rate is set to 460800 or less then
2888          * allow tty settings to override, otherwise keep the
2889          * current data rate.
2890          */
2891         if (info->params.data_rate <= 460800) {
2892                 info->params.data_rate = tty_get_baud_rate(info->tty);
2893         }
2894
2895         if ( info->params.data_rate ) {
2896                 info->timeout = (32*HZ*bits_per_char) /
2897                                 info->params.data_rate;
2898         }
2899         info->timeout += HZ/50;         /* Add .02 seconds of slop */
2900
2901         if (cflag & CRTSCTS)
2902                 info->flags |= ASYNC_CTS_FLOW;
2903         else
2904                 info->flags &= ~ASYNC_CTS_FLOW;
2905
2906         if (cflag & CLOCAL)
2907                 info->flags &= ~ASYNC_CHECK_CD;
2908         else
2909                 info->flags |= ASYNC_CHECK_CD;
2910
2911         /* process tty input control flags */
2912
2913         info->read_status_mask2 = OVRN;
2914         if (I_INPCK(info->tty))
2915                 info->read_status_mask2 |= PE | FRME;
2916         if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
2917                 info->read_status_mask1 |= BRKD;
2918         if (I_IGNPAR(info->tty))
2919                 info->ignore_status_mask2 |= PE | FRME;
2920         if (I_IGNBRK(info->tty)) {
2921                 info->ignore_status_mask1 |= BRKD;
2922                 /* If ignoring parity and break indicators, ignore
2923                  * overruns too.  (For real raw support).
2924                  */
2925                 if (I_IGNPAR(info->tty))
2926                         info->ignore_status_mask2 |= OVRN;
2927         }
2928
2929         program_hw(info);
2930 }
2931
2932 static int get_stats(SLMP_INFO * info, struct mgsl_icount __user *user_icount)
2933 {
2934         int err;
2935
2936         if (debug_level >= DEBUG_LEVEL_INFO)
2937                 printk("%s(%d):%s get_params()\n",
2938                          __FILE__,__LINE__, info->device_name);
2939
2940         if (!user_icount) {
2941                 memset(&info->icount, 0, sizeof(info->icount));
2942         } else {
2943                 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2944                 if (err)
2945                         return -EFAULT;
2946         }
2947
2948         return 0;
2949 }
2950
2951 static int get_params(SLMP_INFO * info, MGSL_PARAMS __user *user_params)
2952 {
2953         int err;
2954         if (debug_level >= DEBUG_LEVEL_INFO)
2955                 printk("%s(%d):%s get_params()\n",
2956                          __FILE__,__LINE__, info->device_name);
2957
2958         COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2959         if (err) {
2960                 if ( debug_level >= DEBUG_LEVEL_INFO )
2961                         printk( "%s(%d):%s get_params() user buffer copy failed\n",
2962                                 __FILE__,__LINE__,info->device_name);
2963                 return -EFAULT;
2964         }
2965
2966         return 0;
2967 }
2968
2969 static int set_params(SLMP_INFO * info, MGSL_PARAMS __user *new_params)
2970 {
2971         unsigned long flags;
2972         MGSL_PARAMS tmp_params;
2973         int err;
2974
2975         if (debug_level >= DEBUG_LEVEL_INFO)
2976                 printk("%s(%d):%s set_params\n",
2977                         __FILE__,__LINE__,info->device_name );
2978         COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2979         if (err) {
2980                 if ( debug_level >= DEBUG_LEVEL_INFO )
2981                         printk( "%s(%d):%s set_params() user buffer copy failed\n",
2982                                 __FILE__,__LINE__,info->device_name);
2983                 return -EFAULT;
2984         }
2985
2986         spin_lock_irqsave(&info->lock,flags);
2987         memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2988         spin_unlock_irqrestore(&info->lock,flags);
2989
2990         change_params(info);
2991
2992         return 0;
2993 }
2994
2995 static int get_txidle(SLMP_INFO * info, int __user *idle_mode)
2996 {
2997         int err;
2998
2999         if (debug_level >= DEBUG_LEVEL_INFO)
3000                 printk("%s(%d):%s get_txidle()=%d\n",
3001                          __FILE__,__LINE__, info->device_name, info->idle_mode);
3002
3003         COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
3004         if (err) {
3005                 if ( debug_level >= DEBUG_LEVEL_INFO )
3006                         printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
3007                                 __FILE__,__LINE__,info->device_name);
3008                 return -EFAULT;
3009         }
3010
3011         return 0;
3012 }
3013
3014 static int set_txidle(SLMP_INFO * info, int idle_mode)
3015 {
3016         unsigned long flags;
3017
3018         if (debug_level >= DEBUG_LEVEL_INFO)
3019                 printk("%s(%d):%s set_txidle(%d)\n",
3020                         __FILE__,__LINE__,info->device_name, idle_mode );
3021
3022         spin_lock_irqsave(&info->lock,flags);
3023         info->idle_mode = idle_mode;
3024         tx_set_idle( info );
3025         spin_unlock_irqrestore(&info->lock,flags);
3026         return 0;
3027 }
3028
3029 static int tx_enable(SLMP_INFO * info, int enable)
3030 {
3031         unsigned long flags;
3032
3033         if (debug_level >= DEBUG_LEVEL_INFO)
3034                 printk("%s(%d):%s tx_enable(%d)\n",
3035                         __FILE__,__LINE__,info->device_name, enable);
3036
3037         spin_lock_irqsave(&info->lock,flags);
3038         if ( enable ) {
3039                 if ( !info->tx_enabled ) {
3040                         tx_start(info);
3041                 }
3042         } else {
3043                 if ( info->tx_enabled )
3044                         tx_stop(info);
3045         }
3046         spin_unlock_irqrestore(&info->lock,flags);
3047         return 0;
3048 }
3049
3050 /* abort send HDLC frame
3051  */
3052 static int tx_abort(SLMP_INFO * info)
3053 {
3054         unsigned long flags;
3055
3056         if (debug_level >= DEBUG_LEVEL_INFO)
3057                 printk("%s(%d):%s tx_abort()\n",
3058                         __FILE__,__LINE__,info->device_name);
3059
3060         spin_lock_irqsave(&info->lock,flags);
3061         if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) {
3062                 info->ie1_value &= ~UDRN;
3063                 info->ie1_value |= IDLE;
3064                 write_reg(info, IE1, info->ie1_value);  /* disable tx status interrupts */
3065                 write_reg(info, SR1, (unsigned char)(IDLE + UDRN));     /* clear pending */
3066
3067                 write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
3068                 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
3069
3070                 write_reg(info, CMD, TXABORT);
3071         }
3072         spin_unlock_irqrestore(&info->lock,flags);
3073         return 0;
3074 }
3075
3076 static int rx_enable(SLMP_INFO * info, int enable)
3077 {
3078         unsigned long flags;
3079
3080         if (debug_level >= DEBUG_LEVEL_INFO)
3081                 printk("%s(%d):%s rx_enable(%d)\n",
3082                         __FILE__,__LINE__,info->device_name,enable);
3083
3084         spin_lock_irqsave(&info->lock,flags);
3085         if ( enable ) {
3086                 if ( !info->rx_enabled )
3087                         rx_start(info);
3088         } else {
3089                 if ( info->rx_enabled )
3090                         rx_stop(info);
3091         }
3092         spin_unlock_irqrestore(&info->lock,flags);
3093         return 0;
3094 }
3095
3096 /* wait for specified event to occur
3097  */
3098 static int wait_mgsl_event(SLMP_INFO * info, int __user *mask_ptr)
3099 {
3100         unsigned long flags;
3101         int s;
3102         int rc=0;
3103         struct mgsl_icount cprev, cnow;
3104         int events;
3105         int mask;
3106         struct  _input_signal_events oldsigs, newsigs;
3107         DECLARE_WAITQUEUE(wait, current);
3108
3109         COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
3110         if (rc) {
3111                 return  -EFAULT;
3112         }
3113
3114         if (debug_level >= DEBUG_LEVEL_INFO)
3115                 printk("%s(%d):%s wait_mgsl_event(%d)\n",
3116                         __FILE__,__LINE__,info->device_name,mask);
3117
3118         spin_lock_irqsave(&info->lock,flags);
3119
3120         /* return immediately if state matches requested events */
3121         get_signals(info);
3122         s = info->serial_signals;
3123
3124         events = mask &
3125                 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
3126                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
3127                   ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
3128                   ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
3129         if (events) {
3130                 spin_unlock_irqrestore(&info->lock,flags);
3131                 goto exit;
3132         }
3133
3134         /* save current irq counts */
3135         cprev = info->icount;
3136         oldsigs = info->input_signal_events;
3137
3138         /* enable hunt and idle irqs if needed */
3139         if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
3140                 unsigned char oldval = info->ie1_value;
3141                 unsigned char newval = oldval +
3142                          (mask & MgslEvent_ExitHuntMode ? FLGD:0) +
3143                          (mask & MgslEvent_IdleReceived ? IDLD:0);
3144                 if ( oldval != newval ) {
3145                         info->ie1_value = newval;
3146                         write_reg(info, IE1, info->ie1_value);
3147                 }
3148         }
3149
3150         set_current_state(TASK_INTERRUPTIBLE);
3151         add_wait_queue(&info->event_wait_q, &wait);
3152
3153         spin_unlock_irqrestore(&info->lock,flags);
3154
3155         for(;;) {
3156                 schedule();
3157                 if (signal_pending(current)) {
3158                         rc = -ERESTARTSYS;
3159                         break;
3160                 }
3161
3162                 /* get current irq counts */
3163                 spin_lock_irqsave(&info->lock,flags);
3164                 cnow = info->icount;
3165                 newsigs = info->input_signal_events;
3166                 set_current_state(TASK_INTERRUPTIBLE);
3167                 spin_unlock_irqrestore(&info->lock,flags);
3168
3169                 /* if no change, wait aborted for some reason */
3170                 if (newsigs.dsr_up   == oldsigs.dsr_up   &&
3171                     newsigs.dsr_down == oldsigs.dsr_down &&
3172                     newsigs.dcd_up   == oldsigs.dcd_up   &&
3173                     newsigs.dcd_down == oldsigs.dcd_down &&
3174                     newsigs.cts_up   == oldsigs.cts_up   &&
3175                     newsigs.cts_down == oldsigs.cts_down &&
3176                     newsigs.ri_up    == oldsigs.ri_up    &&
3177                     newsigs.ri_down  == oldsigs.ri_down  &&
3178                     cnow.exithunt    == cprev.exithunt   &&
3179                     cnow.rxidle      == cprev.rxidle) {
3180                         rc = -EIO;
3181                         break;
3182                 }
3183
3184                 events = mask &
3185                         ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
3186                           (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
3187                           (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
3188                           (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
3189                           (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
3190                           (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
3191                           (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
3192                           (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
3193                           (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
3194                           (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
3195                 if (events)
3196                         break;
3197
3198                 cprev = cnow;
3199                 oldsigs = newsigs;
3200         }
3201
3202         remove_wait_queue(&info->event_wait_q, &wait);
3203         set_current_state(TASK_RUNNING);
3204
3205
3206         if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
3207                 spin_lock_irqsave(&info->lock,flags);
3208                 if (!waitqueue_active(&info->event_wait_q)) {
3209                         /* disable enable exit hunt mode/idle rcvd IRQs */
3210                         info->ie1_value &= ~(FLGD|IDLD);
3211                         write_reg(info, IE1, info->ie1_value);
3212                 }
3213                 spin_unlock_irqrestore(&info->lock,flags);
3214         }
3215 exit:
3216         if ( rc == 0 )
3217                 PUT_USER(rc, events, mask_ptr);
3218
3219         return rc;
3220 }
3221
3222 static int modem_input_wait(SLMP_INFO *info,int arg)
3223 {
3224         unsigned long flags;
3225         int rc;
3226         struct mgsl_icount cprev, cnow;
3227         DECLARE_WAITQUEUE(wait, current);
3228
3229         /* save current irq counts */
3230         spin_lock_irqsave(&info->lock,flags);
3231         cprev = info->icount;
3232         add_wait_queue(&info->status_event_wait_q, &wait);
3233         set_current_state(TASK_INTERRUPTIBLE);
3234         spin_unlock_irqrestore(&info->lock,flags);
3235
3236         for(;;) {
3237                 schedule();
3238                 if (signal_pending(current)) {
3239                         rc = -ERESTARTSYS;
3240                         break;
3241                 }
3242
3243                 /* get new irq counts */
3244                 spin_lock_irqsave(&info->lock,flags);
3245                 cnow = info->icount;
3246                 set_current_state(TASK_INTERRUPTIBLE);
3247                 spin_unlock_irqrestore(&info->lock,flags);
3248
3249                 /* if no change, wait aborted for some reason */
3250                 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3251                     cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3252                         rc = -EIO;
3253                         break;
3254                 }
3255
3256                 /* check for change in caller specified modem input */
3257                 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3258                     (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3259                     (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
3260                     (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3261                         rc = 0;
3262                         break;
3263                 }
3264
3265                 cprev = cnow;
3266         }
3267         remove_wait_queue(&info->status_event_wait_q, &wait);
3268         set_current_state(TASK_RUNNING);
3269         return rc;
3270 }
3271
3272 /* return the state of the serial control and status signals
3273  */
3274 static int tiocmget(struct tty_struct *tty, struct file *file)
3275 {
3276         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
3277         unsigned int result;
3278         unsigned long flags;
3279
3280         spin_lock_irqsave(&info->lock,flags);
3281         get_signals(info);
3282         spin_unlock_irqrestore(&info->lock,flags);
3283
3284         result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3285                 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3286                 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3287                 ((info->serial_signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
3288                 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3289                 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3290
3291         if (debug_level >= DEBUG_LEVEL_INFO)
3292                 printk("%s(%d):%s tiocmget() value=%08X\n",
3293                          __FILE__,__LINE__, info->device_name, result );
3294         return result;
3295 }
3296
3297 /* set modem control signals (DTR/RTS)
3298  */
3299 static int tiocmset(struct tty_struct *tty, struct file *file,
3300                     unsigned int set, unsigned int clear)
3301 {
3302         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
3303         unsigned long flags;
3304
3305         if (debug_level >= DEBUG_LEVEL_INFO)
3306                 printk("%s(%d):%s tiocmset(%x,%x)\n",
3307                         __FILE__,__LINE__,info->device_name, set, clear);
3308
3309         if (set & TIOCM_RTS)
3310                 info->serial_signals |= SerialSignal_RTS;
3311         if (set & TIOCM_DTR)
3312                 info->serial_signals |= SerialSignal_DTR;
3313         if (clear & TIOCM_RTS)
3314                 info->serial_signals &= ~SerialSignal_RTS;
3315         if (clear & TIOCM_DTR)
3316                 info->serial_signals &= ~SerialSignal_DTR;
3317
3318         spin_lock_irqsave(&info->lock,flags);
3319         set_signals(info);
3320         spin_unlock_irqrestore(&info->lock,flags);
3321
3322         return 0;
3323 }
3324
3325
3326
3327 /* Block the current process until the specified port is ready to open.
3328  */
3329 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3330                            SLMP_INFO *info)
3331 {
3332         DECLARE_WAITQUEUE(wait, current);
3333         int             retval;
3334         int             do_clocal = 0, extra_count = 0;
3335         unsigned long   flags;
3336
3337         if (debug_level >= DEBUG_LEVEL_INFO)
3338                 printk("%s(%d):%s block_til_ready()\n",
3339                          __FILE__,__LINE__, tty->driver->name );
3340
3341         if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3342                 /* nonblock mode is set or port is not enabled */
3343                 /* just verify that callout device is not active */
3344                 info->flags |= ASYNC_NORMAL_ACTIVE;
3345                 return 0;
3346         }
3347
3348         if (tty->termios->c_cflag & CLOCAL)
3349                 do_clocal = 1;
3350
3351         /* Wait for carrier detect and the line to become
3352          * free (i.e., not in use by the callout).  While we are in
3353          * this loop, info->count is dropped by one, so that
3354          * close() knows when to free things.  We restore it upon
3355          * exit, either normal or abnormal.
3356          */
3357
3358         retval = 0;
3359         add_wait_queue(&info->open_wait, &wait);
3360
3361         if (debug_level >= DEBUG_LEVEL_INFO)
3362                 printk("%s(%d):%s block_til_ready() before block, count=%d\n",
3363                          __FILE__,__LINE__, tty->driver->name, info->count );
3364
3365         spin_lock_irqsave(&info->lock, flags);
3366         if (!tty_hung_up_p(filp)) {
3367                 extra_count = 1;
3368                 info->count--;
3369         }
3370         spin_unlock_irqrestore(&info->lock, flags);
3371         info->blocked_open++;
3372
3373         while (1) {
3374                 if ((tty->termios->c_cflag & CBAUD)) {
3375                         spin_lock_irqsave(&info->lock,flags);
3376                         info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3377                         set_signals(info);
3378                         spin_unlock_irqrestore(&info->lock,flags);
3379                 }
3380
3381                 set_current_state(TASK_INTERRUPTIBLE);
3382
3383                 if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){
3384                         retval = (info->flags & ASYNC_HUP_NOTIFY) ?
3385                                         -EAGAIN : -ERESTARTSYS;
3386                         break;
3387                 }
3388
3389                 spin_lock_irqsave(&info->lock,flags);
3390                 get_signals(info);
3391                 spin_unlock_irqrestore(&info->lock,flags);
3392
3393                 if (!(info->flags & ASYNC_CLOSING) &&
3394                     (do_clocal || (info->serial_signals & SerialSignal_DCD)) ) {
3395                         break;
3396                 }
3397
3398                 if (signal_pending(current)) {
3399                         retval = -ERESTARTSYS;
3400                         break;
3401                 }
3402
3403                 if (debug_level >= DEBUG_LEVEL_INFO)
3404                         printk("%s(%d):%s block_til_ready() count=%d\n",
3405                                  __FILE__,__LINE__, tty->driver->name, info->count );
3406
3407                 schedule();
3408         }
3409
3410         set_current_state(TASK_RUNNING);
3411         remove_wait_queue(&info->open_wait, &wait);
3412
3413         if (extra_count)
3414                 info->count++;
3415         info->blocked_open--;
3416
3417         if (debug_level >= DEBUG_LEVEL_INFO)
3418                 printk("%s(%d):%s block_til_ready() after, count=%d\n",
3419                          __FILE__,__LINE__, tty->driver->name, info->count );
3420
3421         if (!retval)
3422                 info->flags |= ASYNC_NORMAL_ACTIVE;
3423
3424         return retval;
3425 }
3426
3427 int alloc_dma_bufs(SLMP_INFO *info)
3428 {
3429         unsigned short BuffersPerFrame;
3430         unsigned short BufferCount;
3431
3432         // Force allocation to start at 64K boundary for each port.
3433         // This is necessary because *all* buffer descriptors for a port
3434         // *must* be in the same 64K block. All descriptors on a port
3435         // share a common 'base' address (upper 8 bits of 24 bits) programmed
3436         // into the CBP register.
3437         info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num;
3438
3439         /* Calculate the number of DMA buffers necessary to hold the */
3440         /* largest allowable frame size. Note: If the max frame size is */
3441         /* not an even multiple of the DMA buffer size then we need to */
3442         /* round the buffer count per frame up one. */
3443
3444         BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE);
3445         if ( info->max_frame_size % SCABUFSIZE )
3446                 BuffersPerFrame++;
3447
3448         /* calculate total number of data buffers (SCABUFSIZE) possible
3449          * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
3450          * for the descriptor list (BUFFERLISTSIZE).
3451          */
3452         BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE;
3453
3454         /* limit number of buffers to maximum amount of descriptors */
3455         if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC))
3456                 BufferCount = BUFFERLISTSIZE/sizeof(SCADESC);
3457
3458         /* use enough buffers to transmit one max size frame */
3459         info->tx_buf_count = BuffersPerFrame + 1;
3460
3461         /* never use more than half the available buffers for transmit */
3462         if (info->tx_buf_count > (BufferCount/2))
3463                 info->tx_buf_count = BufferCount/2;
3464
3465         if (info->tx_buf_count > SCAMAXDESC)
3466                 info->tx_buf_count = SCAMAXDESC;
3467
3468         /* use remaining buffers for receive */
3469         info->rx_buf_count = BufferCount - info->tx_buf_count;
3470
3471         if (info->rx_buf_count > SCAMAXDESC)
3472                 info->rx_buf_count = SCAMAXDESC;
3473
3474         if ( debug_level >= DEBUG_LEVEL_INFO )
3475                 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3476                         __FILE__,__LINE__, info->device_name,
3477                         info->tx_buf_count,info->rx_buf_count);
3478
3479         if ( alloc_buf_list( info ) < 0 ||
3480                 alloc_frame_bufs(info,
3481                                         info->rx_buf_list,
3482                                         info->rx_buf_list_ex,
3483                                         info->rx_buf_count) < 0 ||
3484                 alloc_frame_bufs(info,
3485                                         info->tx_buf_list,
3486                                         info->tx_buf_list_ex,
3487                                         info->tx_buf_count) < 0 ||
3488                 alloc_tmp_rx_buf(info) < 0 ) {
3489                 printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3490                         __FILE__,__LINE__, info->device_name);
3491                 return -ENOMEM;
3492         }
3493
3494         rx_reset_buffers( info );
3495
3496         return 0;
3497 }
3498
3499 /* Allocate DMA buffers for the transmit and receive descriptor lists.
3500  */
3501 int alloc_buf_list(SLMP_INFO *info)
3502 {
3503         unsigned int i;
3504
3505         /* build list in adapter shared memory */
3506         info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc;
3507         info->buffer_list_phys = info->port_array[0]->last_mem_alloc;
3508         info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE;
3509
3510         memset(info->buffer_list, 0, BUFFERLISTSIZE);
3511
3512         /* Save virtual address pointers to the receive and */
3513         /* transmit buffer lists. (Receive 1st). These pointers will */
3514         /* be used by the processor to access the lists. */
3515         info->rx_buf_list = (SCADESC *)info->buffer_list;
3516
3517         info->tx_buf_list = (SCADESC *)info->buffer_list;
3518         info->tx_buf_list += info->rx_buf_count;
3519
3520         /* Build links for circular buffer entry lists (tx and rx)
3521          *
3522          * Note: links are physical addresses read by the SCA device
3523          * to determine the next buffer entry to use.
3524          */
3525
3526         for ( i = 0; i < info->rx_buf_count; i++ ) {
3527                 /* calculate and store physical address of this buffer entry */
3528                 info->rx_buf_list_ex[i].phys_entry =
3529                         info->buffer_list_phys + (i * sizeof(SCABUFSIZE));
3530
3531                 /* calculate and store physical address of */
3532                 /* next entry in cirular list of entries */
3533                 info->rx_buf_list[i].next = info->buffer_list_phys;
3534                 if ( i < info->rx_buf_count - 1 )
3535                         info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3536
3537                 info->rx_buf_list[i].length = SCABUFSIZE;
3538         }
3539
3540         for ( i = 0; i < info->tx_buf_count; i++ ) {
3541                 /* calculate and store physical address of this buffer entry */
3542                 info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys +
3543                         ((info->rx_buf_count + i) * sizeof(SCADESC));
3544
3545                 /* calculate and store physical address of */
3546                 /* next entry in cirular list of entries */
3547
3548                 info->tx_buf_list[i].next = info->buffer_list_phys +
3549                         info->rx_buf_count * sizeof(SCADESC);
3550
3551                 if ( i < info->tx_buf_count - 1 )
3552                         info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3553         }
3554
3555         return 0;
3556 }
3557
3558 /* Allocate the frame DMA buffers used by the specified buffer list.
3559  */
3560 int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count)
3561 {
3562         int i;
3563         unsigned long phys_addr;
3564
3565         for ( i = 0; i < count; i++ ) {
3566                 buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc;
3567                 phys_addr = info->port_array[0]->last_mem_alloc;
3568                 info->port_array[0]->last_mem_alloc += SCABUFSIZE;
3569
3570                 buf_list[i].buf_ptr  = (unsigned short)phys_addr;
3571                 buf_list[i].buf_base = (unsigned char)(phys_addr >> 16);
3572         }
3573
3574         return 0;
3575 }
3576
3577 void free_dma_bufs(SLMP_INFO *info)
3578 {
3579         info->buffer_list = NULL;
3580         info->rx_buf_list = NULL;
3581         info->tx_buf_list = NULL;
3582 }
3583
3584 /* allocate buffer large enough to hold max_frame_size.
3585  * This buffer is used to pass an assembled frame to the line discipline.
3586  */
3587 int alloc_tmp_rx_buf(SLMP_INFO *info)
3588 {
3589         info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
3590         if (info->tmp_rx_buf == NULL)
3591                 return -ENOMEM;
3592         return 0;
3593 }
3594
3595 void free_tmp_rx_buf(SLMP_INFO *info)
3596 {
3597         kfree(info->tmp_rx_buf);
3598         info->tmp_rx_buf = NULL;
3599 }
3600
3601 int claim_resources(SLMP_INFO *info)
3602 {
3603         if (request_mem_region(info->phys_memory_base,SCA_MEM_SIZE,"synclinkmp") == NULL) {
3604                 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3605                         __FILE__,__LINE__,info->device_name, info->phys_memory_base);
3606                 info->init_error = DiagStatus_AddressConflict;
3607                 goto errout;
3608         }
3609         else
3610                 info->shared_mem_requested = 1;
3611
3612         if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) {
3613                 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3614                         __FILE__,__LINE__,info->device_name, info->phys_lcr_base);
3615                 info->init_error = DiagStatus_AddressConflict;
3616                 goto errout;
3617         }
3618         else
3619                 info->lcr_mem_requested = 1;
3620
3621         if (request_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE,"synclinkmp") == NULL) {
3622                 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3623                         __FILE__,__LINE__,info->device_name, info->phys_sca_base);
3624                 info->init_error = DiagStatus_AddressConflict;
3625                 goto errout;
3626         }
3627         else
3628                 info->sca_base_requested = 1;
3629
3630         if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE,"synclinkmp") == NULL) {
3631                 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3632                         __FILE__,__LINE__,info->device_name, info->phys_statctrl_base);
3633                 info->init_error = DiagStatus_AddressConflict;
3634                 goto errout;
3635         }
3636         else
3637                 info->sca_statctrl_requested = 1;
3638
3639         info->memory_base = ioremap(info->phys_memory_base,SCA_MEM_SIZE);
3640         if (!info->memory_base) {
3641                 printk( "%s(%d):%s Cant map shared memory, MemAddr=%08X\n",
3642                         __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3643                 info->init_error = DiagStatus_CantAssignPciResources;
3644                 goto errout;
3645         }
3646
3647         info->lcr_base = ioremap(info->phys_lcr_base,PAGE_SIZE);
3648         if (!info->lcr_base) {
3649                 printk( "%s(%d):%s Cant map LCR memory, MemAddr=%08X\n",
3650                         __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
3651                 info->init_error = DiagStatus_CantAssignPciResources;
3652                 goto errout;
3653         }
3654         info->lcr_base += info->lcr_offset;
3655
3656         info->sca_base = ioremap(info->phys_sca_base,PAGE_SIZE);
3657         if (!info->sca_base) {
3658                 printk( "%s(%d):%s Cant map SCA memory, MemAddr=%08X\n",
3659                         __FILE__,__LINE__,info->device_name, info->phys_sca_base );
3660                 info->init_error = DiagStatus_CantAssignPciResources;
3661                 goto errout;
3662         }
3663         info->sca_base += info->sca_offset;
3664
3665         info->statctrl_base = ioremap(info->phys_statctrl_base,PAGE_SIZE);
3666         if (!info->statctrl_base) {
3667                 printk( "%s(%d):%s Cant map SCA Status/Control memory, MemAddr=%08X\n",
3668                         __FILE__,__LINE__,info->device_name, info->phys_statctrl_base );
3669                 info->init_error = DiagStatus_CantAssignPciResources;
3670                 goto errout;
3671         }
3672         info->statctrl_base += info->statctrl_offset;
3673
3674         if ( !memory_test(info) ) {
3675                 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3676                         __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3677                 info->init_error = DiagStatus_MemoryError;
3678                 goto errout;
3679         }
3680
3681         return 0;
3682
3683 errout:
3684         release_resources( info );
3685         return -ENODEV;
3686 }
3687
3688 void release_resources(SLMP_INFO *info)
3689 {
3690         if ( debug_level >= DEBUG_LEVEL_INFO )
3691                 printk( "%s(%d):%s release_resources() entry\n",
3692                         __FILE__,__LINE__,info->device_name );
3693
3694         if ( info->irq_requested ) {
3695                 free_irq(info->irq_level, info);
3696                 info->irq_requested = 0;
3697         }
3698
3699         if ( info->shared_mem_requested ) {
3700                 release_mem_region(info->phys_memory_base,SCA_MEM_SIZE);
3701                 info->shared_mem_requested = 0;
3702         }
3703         if ( info->lcr_mem_requested ) {
3704                 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
3705                 info->lcr_mem_requested = 0;
3706         }
3707         if ( info->sca_base_requested ) {
3708                 release_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE);
3709                 info->sca_base_requested = 0;
3710         }
3711         if ( info->sca_statctrl_requested ) {
3712                 release_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE);
3713                 info->sca_statctrl_requested = 0;
3714         }
3715
3716         if (info->memory_base){
3717                 iounmap(info->memory_base);
3718                 info->memory_base = NULL;
3719         }
3720
3721         if (info->sca_base) {
3722                 iounmap(info->sca_base - info->sca_offset);
3723                 info->sca_base=NULL;
3724         }
3725
3726         if (info->statctrl_base) {
3727                 iounmap(info->statctrl_base - info->statctrl_offset);
3728                 info->statctrl_base=NULL;
3729         }
3730
3731         if (info->lcr_base){
3732                 iounmap(info->lcr_base - info->lcr_offset);
3733                 info->lcr_base = NULL;
3734         }
3735
3736         if ( debug_level >= DEBUG_LEVEL_INFO )
3737                 printk( "%s(%d):%s release_resources() exit\n",
3738                         __FILE__,__LINE__,info->device_name );
3739 }
3740
3741 /* Add the specified device instance data structure to the
3742  * global linked list of devices and increment the device count.
3743  */
3744 void add_device(SLMP_INFO *info)
3745 {
3746         info->next_device = NULL;
3747         info->line = synclinkmp_device_count;
3748         sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num);
3749
3750         if (info->line < MAX_DEVICES) {
3751                 if (maxframe[info->line])
3752                         info->max_frame_size = maxframe[info->line];
3753                 info->dosyncppp = dosyncppp[info->line];
3754         }
3755
3756         synclinkmp_device_count++;
3757
3758         if ( !synclinkmp_device_list )
3759                 synclinkmp_device_list = info;
3760         else {
3761                 SLMP_INFO *current_dev = synclinkmp_device_list;
3762                 while( current_dev->next_device )
3763                         current_dev = current_dev->next_device;
3764                 current_dev->next_device = info;
3765         }
3766
3767         if ( info->max_frame_size < 4096 )
3768                 info->max_frame_size = 4096;
3769         else if ( info->max_frame_size > 65535 )
3770                 info->max_frame_size = 65535;
3771
3772         printk( "SyncLink MultiPort %s: "
3773                 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3774                 info->device_name,
3775                 info->phys_sca_base,
3776                 info->phys_memory_base,
3777                 info->phys_statctrl_base,
3778                 info->phys_lcr_base,
3779                 info->irq_level,
3780                 info->max_frame_size );
3781
3782 #ifdef CONFIG_HDLC
3783         hdlcdev_init(info);
3784 #endif
3785 }
3786
3787 /* Allocate and initialize a device instance structure
3788  *
3789  * Return Value:        pointer to SLMP_INFO if success, otherwise NULL
3790  */
3791 static SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3792 {
3793         SLMP_INFO *info;
3794
3795         info = (SLMP_INFO *)kmalloc(sizeof(SLMP_INFO),
3796                  GFP_KERNEL);
3797
3798         if (!info) {
3799                 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3800                         __FILE__,__LINE__, adapter_num, port_num);
3801         } else {
3802                 memset(info, 0, sizeof(SLMP_INFO));
3803                 info->magic = MGSL_MAGIC;
3804                 INIT_WORK(&info->task, bh_handler, info);
3805                 info->max_frame_size = 4096;
3806                 info->close_delay = 5*HZ/10;
3807                 info->closing_wait = 30*HZ;
3808                 init_waitqueue_head(&info->open_wait);
3809                 init_waitqueue_head(&info->close_wait);
3810                 init_waitqueue_head(&info->status_event_wait_q);
3811                 init_waitqueue_head(&info->event_wait_q);
3812                 spin_lock_init(&info->netlock);
3813                 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3814                 info->idle_mode = HDLC_TXIDLE_FLAGS;
3815                 info->adapter_num = adapter_num;
3816                 info->port_num = port_num;
3817
3818                 /* Copy configuration info to device instance data */
3819                 info->irq_level = pdev->irq;
3820                 info->phys_lcr_base = pci_resource_start(pdev,0);
3821                 info->phys_sca_base = pci_resource_start(pdev,2);
3822                 info->phys_memory_base = pci_resource_start(pdev,3);
3823                 info->phys_statctrl_base = pci_resource_start(pdev,4);
3824
3825                 /* Because veremap only works on page boundaries we must map
3826                  * a larger area than is actually implemented for the LCR
3827                  * memory range. We map a full page starting at the page boundary.
3828                  */
3829                 info->lcr_offset    = info->phys_lcr_base & (PAGE_SIZE-1);
3830                 info->phys_lcr_base &= ~(PAGE_SIZE-1);
3831
3832                 info->sca_offset    = info->phys_sca_base & (PAGE_SIZE-1);
3833                 info->phys_sca_base &= ~(PAGE_SIZE-1);
3834
3835                 info->statctrl_offset    = info->phys_statctrl_base & (PAGE_SIZE-1);
3836                 info->phys_statctrl_base &= ~(PAGE_SIZE-1);
3837
3838                 info->bus_type = MGSL_BUS_TYPE_PCI;
3839                 info->irq_flags = SA_SHIRQ;
3840
3841                 init_timer(&info->tx_timer);
3842                 info->tx_timer.data = (unsigned long)info;
3843                 info->tx_timer.function = tx_timeout;
3844
3845                 init_timer(&info->status_timer);
3846                 info->status_timer.data = (unsigned long)info;
3847                 info->status_timer.function = status_timeout;
3848
3849                 /* Store the PCI9050 misc control register value because a flaw
3850                  * in the PCI9050 prevents LCR registers from being read if
3851                  * BIOS assigns an LCR base address with bit 7 set.
3852                  *
3853                  * Only the misc control register is accessed for which only
3854                  * write access is needed, so set an initial value and change
3855                  * bits to the device instance data as we write the value
3856                  * to the actual misc control register.
3857                  */
3858                 info->misc_ctrl_value = 0x087e4546;
3859
3860                 /* initial port state is unknown - if startup errors
3861                  * occur, init_error will be set to indicate the
3862                  * problem. Once the port is fully initialized,
3863                  * this value will be set to 0 to indicate the
3864                  * port is available.
3865                  */
3866                 info->init_error = -1;
3867         }
3868
3869         return info;
3870 }
3871
3872 void device_init(int adapter_num, struct pci_dev *pdev)
3873 {
3874         SLMP_INFO *port_array[SCA_MAX_PORTS];
3875         int port;
3876
3877         /* allocate device instances for up to SCA_MAX_PORTS devices */
3878         for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3879                 port_array[port] = alloc_dev(adapter_num,port,pdev);
3880                 if( port_array[port] == NULL ) {
3881                         for ( --port; port >= 0; --port )
3882                                 kfree(port_array[port]);
3883                         return;
3884                 }
3885         }
3886
3887         /* give copy of port_array to all ports and add to device list  */
3888         for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3889                 memcpy(port_array[port]->port_array,port_array,sizeof(port_array));
3890                 add_device( port_array[port] );
3891                 spin_lock_init(&port_array[port]->lock);
3892         }
3893
3894         /* Allocate and claim adapter resources */
3895         if ( !claim_resources(port_array[0]) ) {
3896
3897                 alloc_dma_bufs(port_array[0]);
3898
3899                 /* copy resource information from first port to others */
3900                 for ( port = 1; port < SCA_MAX_PORTS; ++port ) {
3901                         port_array[port]->lock  = port_array[0]->lock;
3902                         port_array[port]->irq_level     = port_array[0]->irq_level;
3903                         port_array[port]->memory_base   = port_array[0]->memory_base;
3904                         port_array[port]->sca_base      = port_array[0]->sca_base;
3905                         port_array[port]->statctrl_base = port_array[0]->statctrl_base;
3906                         port_array[port]->lcr_base      = port_array[0]->lcr_base;
3907                         alloc_dma_bufs(port_array[port]);
3908                 }
3909
3910                 if ( request_irq(port_array[0]->irq_level,
3911                                         synclinkmp_interrupt,
3912                                         port_array[0]->irq_flags,
3913                                         port_array[0]->device_name,
3914                                         port_array[0]) < 0 ) {
3915                         printk( "%s(%d):%s Cant request interrupt, IRQ=%d\n",
3916                                 __FILE__,__LINE__,
3917                                 port_array[0]->device_name,
3918                                 port_array[0]->irq_level );
3919                 }
3920                 else {
3921                         port_array[0]->irq_requested = 1;
3922                         adapter_test(port_array[0]);
3923                 }
3924         }
3925 }
3926
3927 static struct tty_operations ops = {
3928         .open = open,
3929         .close = close,
3930         .write = write,
3931         .put_char = put_char,
3932         .flush_chars = flush_chars,
3933         .write_room = write_room,
3934         .chars_in_buffer = chars_in_buffer,
3935         .flush_buffer = flush_buffer,
3936         .ioctl = ioctl,
3937         .throttle = throttle,
3938         .unthrottle = unthrottle,
3939         .send_xchar = send_xchar,
3940         .break_ctl = set_break,
3941         .wait_until_sent = wait_until_sent,
3942         .read_proc = read_proc,
3943         .set_termios = set_termios,
3944         .stop = tx_hold,
3945         .start = tx_release,
3946         .hangup = hangup,
3947         .tiocmget = tiocmget,
3948         .tiocmset = tiocmset,
3949 };
3950
3951 static void synclinkmp_cleanup(void)
3952 {
3953         int rc;
3954         SLMP_INFO *info;
3955         SLMP_INFO *tmp;
3956
3957         printk("Unloading %s %s\n", driver_name, driver_version);
3958
3959         if (serial_driver) {
3960                 if ((rc = tty_unregister_driver(serial_driver)))
3961                         printk("%s(%d) failed to unregister tty driver err=%d\n",
3962                                __FILE__,__LINE__,rc);
3963                 put_tty_driver(serial_driver);
3964         }
3965
3966         /* reset devices */
3967         info = synclinkmp_device_list;
3968         while(info) {
3969                 reset_port(info);
3970                 info = info->next_device;
3971         }
3972
3973         /* release devices */
3974         info = synclinkmp_device_list;
3975         while(info) {
3976 #ifdef CONFIG_HDLC
3977                 hdlcdev_exit(info);
3978 #endif
3979                 free_dma_bufs(info);
3980                 free_tmp_rx_buf(info);
3981                 if ( info->port_num == 0 ) {
3982                         if (info->sca_base)
3983                                 write_reg(info, LPR, 1); /* set low power mode */
3984                         release_resources(info);
3985                 }
3986                 tmp = info;
3987                 info = info->next_device;
3988                 kfree(tmp);
3989         }
3990
3991         pci_unregister_driver(&synclinkmp_pci_driver);
3992 }
3993
3994 /* Driver initialization entry point.
3995  */
3996
3997 static int __init synclinkmp_init(void)
3998 {
3999         int rc;
4000
4001         if (break_on_load) {
4002                 synclinkmp_get_text_ptr();
4003                 BREAKPOINT();
4004         }
4005
4006         printk("%s %s\n", driver_name, driver_version);
4007
4008         if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) {
4009                 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
4010                 return rc;
4011         }
4012
4013         serial_driver = alloc_tty_driver(128);
4014         if (!serial_driver) {
4015                 rc = -ENOMEM;
4016                 goto error;
4017         }
4018
4019         /* Initialize the tty_driver structure */
4020
4021         serial_driver->owner = THIS_MODULE;
4022         serial_driver->driver_name = "synclinkmp";
4023         serial_driver->name = "ttySLM";
4024         serial_driver->major = ttymajor;
4025         serial_driver->minor_start = 64;
4026         serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
4027         serial_driver->subtype = SERIAL_TYPE_NORMAL;
4028         serial_driver->init_termios = tty_std_termios;
4029         serial_driver->init_termios.c_cflag =
4030                 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
4031         serial_driver->flags = TTY_DRIVER_REAL_RAW;
4032         tty_set_operations(serial_driver, &ops);
4033         if ((rc = tty_register_driver(serial_driver)) < 0) {
4034                 printk("%s(%d):Couldn't register serial driver\n",
4035                         __FILE__,__LINE__);
4036                 put_tty_driver(serial_driver);
4037                 serial_driver = NULL;
4038                 goto error;
4039         }
4040
4041         printk("%s %s, tty major#%d\n",
4042                 driver_name, driver_version,
4043                 serial_driver->major);
4044
4045         return 0;
4046
4047 error:
4048         synclinkmp_cleanup();
4049         return rc;
4050 }
4051
4052 static void __exit synclinkmp_exit(void)
4053 {
4054         synclinkmp_cleanup();
4055 }
4056
4057 module_init(synclinkmp_init);
4058 module_exit(synclinkmp_exit);
4059
4060 /* Set the port for internal loopback mode.
4061  * The TxCLK and RxCLK signals are generated from the BRG and
4062  * the TxD is looped back to the RxD internally.
4063  */
4064 void enable_loopback(SLMP_INFO *info, int enable)
4065 {
4066         if (enable) {
4067                 /* MD2 (Mode Register 2)
4068                  * 01..00  CNCT<1..0> Channel Connection 11=Local Loopback
4069                  */
4070                 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
4071
4072                 /* degate external TxC clock source */
4073                 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4074                 write_control_reg(info);
4075
4076                 /* RXS/TXS (Rx/Tx clock source)
4077                  * 07      Reserved, must be 0
4078                  * 06..04  Clock Source, 100=BRG
4079                  * 03..00  Clock Divisor, 0000=1
4080                  */
4081                 write_reg(info, RXS, 0x40);
4082                 write_reg(info, TXS, 0x40);
4083
4084         } else {
4085                 /* MD2 (Mode Register 2)
4086                  * 01..00  CNCT<1..0> Channel connection, 0=normal
4087                  */
4088                 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0)));
4089
4090                 /* RXS/TXS (Rx/Tx clock source)
4091                  * 07      Reserved, must be 0
4092                  * 06..04  Clock Source, 000=RxC/TxC Pin
4093                  * 03..00  Clock Divisor, 0000=1
4094                  */
4095                 write_reg(info, RXS, 0x00);
4096                 write_reg(info, TXS, 0x00);
4097         }
4098
4099         /* set LinkSpeed if available, otherwise default to 2Mbps */
4100         if (info->params.clock_speed)
4101                 set_rate(info, info->params.clock_speed);
4102         else
4103                 set_rate(info, 3686400);
4104 }
4105
4106 /* Set the baud rate register to the desired speed
4107  *
4108  *      data_rate       data rate of clock in bits per second
4109  *                      A data rate of 0 disables the AUX clock.
4110  */
4111 void set_rate( SLMP_INFO *info, u32 data_rate )
4112 {
4113         u32 TMCValue;
4114         unsigned char BRValue;
4115         u32 Divisor=0;
4116
4117         /* fBRG = fCLK/(TMC * 2^BR)
4118          */
4119         if (data_rate != 0) {
4120                 Divisor = 14745600/data_rate;
4121                 if (!Divisor)
4122                         Divisor = 1;
4123
4124                 TMCValue = Divisor;
4125
4126                 BRValue = 0;
4127                 if (TMCValue != 1 && TMCValue != 2) {
4128                         /* BRValue of 0 provides 50/50 duty cycle *only* when
4129                          * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
4130                          * 50/50 duty cycle.
4131                          */
4132                         BRValue = 1;
4133                         TMCValue >>= 1;
4134                 }
4135
4136                 /* while TMCValue is too big for TMC register, divide
4137                  * by 2 and increment BR exponent.
4138                  */
4139                 for(; TMCValue > 256 && BRValue < 10; BRValue++)
4140                         TMCValue >>= 1;
4141
4142                 write_reg(info, TXS,
4143                         (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue));
4144                 write_reg(info, RXS,
4145                         (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue));
4146                 write_reg(info, TMC, (unsigned char)TMCValue);
4147         }
4148         else {
4149                 write_reg(info, TXS,0);
4150                 write_reg(info, RXS,0);
4151                 write_reg(info, TMC, 0);
4152         }
4153 }
4154
4155 /* Disable receiver
4156  */
4157 void rx_stop(SLMP_INFO *info)
4158 {
4159         if (debug_level >= DEBUG_LEVEL_ISR)
4160                 printk("%s(%d):%s rx_stop()\n",
4161                          __FILE__,__LINE__, info->device_name );
4162
4163         write_reg(info, CMD, RXRESET);
4164
4165         info->ie0_value &= ~RXRDYE;
4166         write_reg(info, IE0, info->ie0_value);  /* disable Rx data interrupts */
4167
4168         write_reg(info, RXDMA + DSR, 0);        /* disable Rx DMA */
4169         write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4170         write_reg(info, RXDMA + DIR, 0);        /* disable Rx DMA interrupts */
4171
4172         info->rx_enabled = 0;
4173         info->rx_overflow = 0;
4174 }
4175
4176 /* enable the receiver
4177  */
4178 void rx_start(SLMP_INFO *info)
4179 {
4180         int i;
4181
4182         if (debug_level >= DEBUG_LEVEL_ISR)
4183                 printk("%s(%d):%s rx_start()\n",
4184                          __FILE__,__LINE__, info->device_name );
4185
4186         write_reg(info, CMD, RXRESET);
4187
4188         if ( info->params.mode == MGSL_MODE_HDLC ) {
4189                 /* HDLC, disabe IRQ on rxdata */
4190                 info->ie0_value &= ~RXRDYE;
4191                 write_reg(info, IE0, info->ie0_value);
4192
4193                 /* Reset all Rx DMA buffers and program rx dma */
4194                 write_reg(info, RXDMA + DSR, 0);                /* disable Rx DMA */
4195                 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4196
4197                 for (i = 0; i < info->rx_buf_count; i++) {
4198                         info->rx_buf_list[i].status = 0xff;
4199
4200                         // throttle to 4 shared memory writes at a time to prevent
4201                         // hogging local bus (keep latency time for DMA requests low).
4202                         if (!(i % 4))
4203                                 read_status_reg(info);
4204                 }
4205                 info->current_rx_buf = 0;
4206
4207                 /* set current/1st descriptor address */
4208                 write_reg16(info, RXDMA + CDA,
4209                         info->rx_buf_list_ex[0].phys_entry);
4210
4211                 /* set new last rx descriptor address */
4212                 write_reg16(info, RXDMA + EDA,
4213                         info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry);
4214
4215                 /* set buffer length (shared by all rx dma data buffers) */
4216                 write_reg16(info, RXDMA + BFL, SCABUFSIZE);
4217
4218                 write_reg(info, RXDMA + DIR, 0x60);     /* enable Rx DMA interrupts (EOM/BOF) */
4219                 write_reg(info, RXDMA + DSR, 0xf2);     /* clear Rx DMA IRQs, enable Rx DMA */
4220         } else {
4221                 /* async, enable IRQ on rxdata */
4222                 info->ie0_value |= RXRDYE;
4223                 write_reg(info, IE0, info->ie0_value);
4224         }
4225
4226         write_reg(info, CMD, RXENABLE);
4227
4228         info->rx_overflow = FALSE;
4229         info->rx_enabled = 1;
4230 }
4231
4232 /* Enable the transmitter and send a transmit frame if
4233  * one is loaded in the DMA buffers.
4234  */
4235 void tx_start(SLMP_INFO *info)
4236 {
4237         if (debug_level >= DEBUG_LEVEL_ISR)
4238                 printk("%s(%d):%s tx_start() tx_count=%d\n",
4239                          __FILE__,__LINE__, info->device_name,info->tx_count );
4240
4241         if (!info->tx_enabled ) {
4242                 write_reg(info, CMD, TXRESET);
4243                 write_reg(info, CMD, TXENABLE);
4244                 info->tx_enabled = TRUE;
4245         }
4246
4247         if ( info->tx_count ) {
4248
4249                 /* If auto RTS enabled and RTS is inactive, then assert */
4250                 /* RTS and set a flag indicating that the driver should */
4251                 /* negate RTS when the transmission completes. */
4252
4253                 info->drop_rts_on_tx_done = 0;
4254
4255                 if (info->params.mode != MGSL_MODE_ASYNC) {
4256
4257                         if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
4258                                 get_signals( info );
4259                                 if ( !(info->serial_signals & SerialSignal_RTS) ) {
4260                                         info->serial_signals |= SerialSignal_RTS;
4261                                         set_signals( info );
4262                                         info->drop_rts_on_tx_done = 1;
4263                                 }
4264                         }
4265
4266                         write_reg16(info, TRC0,
4267                                 (unsigned short)(((tx_negate_fifo_level-1)<<8) + tx_active_fifo_level));
4268
4269                         write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
4270                         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4271
4272                         /* set TX CDA (current descriptor address) */
4273                         write_reg16(info, TXDMA + CDA,
4274                                 info->tx_buf_list_ex[0].phys_entry);
4275
4276                         /* set TX EDA (last descriptor address) */
4277                         write_reg16(info, TXDMA + EDA,
4278                                 info->tx_buf_list_ex[info->last_tx_buf].phys_entry);
4279
4280                         /* enable underrun IRQ */
4281                         info->ie1_value &= ~IDLE;
4282                         info->ie1_value |= UDRN;
4283                         write_reg(info, IE1, info->ie1_value);
4284                         write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
4285
4286                         write_reg(info, TXDMA + DIR, 0x40);             /* enable Tx DMA interrupts (EOM) */
4287                         write_reg(info, TXDMA + DSR, 0xf2);             /* clear Tx DMA IRQs, enable Tx DMA */
4288
4289                         info->tx_timer.expires = jiffies + msecs_to_jiffies(5000);
4290                         add_timer(&info->tx_timer);
4291                 }
4292                 else {
4293                         tx_load_fifo(info);
4294                         /* async, enable IRQ on txdata */
4295                         info->ie0_value |= TXRDYE;
4296                         write_reg(info, IE0, info->ie0_value);
4297                 }
4298
4299                 info->tx_active = 1;
4300         }
4301 }
4302
4303 /* stop the transmitter and DMA
4304  */
4305 void tx_stop( SLMP_INFO *info )
4306 {
4307         if (debug_level >= DEBUG_LEVEL_ISR)
4308                 printk("%s(%d):%s tx_stop()\n",
4309                          __FILE__,__LINE__, info->device_name );
4310
4311         del_timer(&info->tx_timer);
4312
4313         write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
4314         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4315
4316         write_reg(info, CMD, TXRESET);
4317
4318         info->ie1_value &= ~(UDRN + IDLE);
4319         write_reg(info, IE1, info->ie1_value);  /* disable tx status interrupts */
4320         write_reg(info, SR1, (unsigned char)(IDLE + UDRN));     /* clear pending */
4321
4322         info->ie0_value &= ~TXRDYE;
4323         write_reg(info, IE0, info->ie0_value);  /* disable tx data interrupts */
4324
4325         info->tx_enabled = 0;
4326         info->tx_active  = 0;
4327 }
4328
4329 /* Fill the transmit FIFO until the FIFO is full or
4330  * there is no more data to load.
4331  */
4332 void tx_load_fifo(SLMP_INFO *info)
4333 {
4334         u8 TwoBytes[2];
4335
4336         /* do nothing is now tx data available and no XON/XOFF pending */
4337
4338         if ( !info->tx_count && !info->x_char )
4339                 return;
4340
4341         /* load the Transmit FIFO until FIFOs full or all data sent */
4342
4343         while( info->tx_count && (read_reg(info,SR0) & BIT1) ) {
4344
4345                 /* there is more space in the transmit FIFO and */
4346                 /* there is more data in transmit buffer */
4347
4348                 if ( (info->tx_count > 1) && !info->x_char ) {
4349                         /* write 16-bits */
4350                         TwoBytes[0] = info->tx_buf[info->tx_get++];
4351                         if (info->tx_get >= info->max_frame_size)
4352                                 info->tx_get -= info->max_frame_size;
4353                         TwoBytes[1] = info->tx_buf[info->tx_get++];
4354                         if (info->tx_get >= info->max_frame_size)
4355                                 info->tx_get -= info->max_frame_size;
4356
4357                         write_reg16(info, TRB, *((u16 *)TwoBytes));
4358
4359                         info->tx_count -= 2;
4360                         info->icount.tx += 2;
4361                 } else {
4362                         /* only 1 byte left to transmit or 1 FIFO slot left */
4363
4364                         if (info->x_char) {
4365                                 /* transmit pending high priority char */
4366                                 write_reg(info, TRB, info->x_char);
4367                                 info->x_char = 0;
4368                         } else {
4369                                 write_reg(info, TRB, info->tx_buf[info->tx_get++]);
4370                                 if (info->tx_get >= info->max_frame_size)
4371                                         info->tx_get -= info->max_frame_size;
4372                                 info->tx_count--;
4373                         }
4374                         info->icount.tx++;
4375                 }
4376         }
4377 }
4378
4379 /* Reset a port to a known state
4380  */
4381 void reset_port(SLMP_INFO *info)
4382 {
4383         if (info->sca_base) {
4384
4385                 tx_stop(info);
4386                 rx_stop(info);
4387
4388                 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
4389                 set_signals(info);
4390
4391                 /* disable all port interrupts */
4392                 info->ie0_value = 0;
4393                 info->ie1_value = 0;
4394                 info->ie2_value = 0;
4395                 write_reg(info, IE0, info->ie0_value);
4396                 write_reg(info, IE1, info->ie1_value);
4397                 write_reg(info, IE2, info->ie2_value);
4398
4399                 write_reg(info, CMD, CHRESET);
4400         }
4401 }
4402
4403 /* Reset all the ports to a known state.
4404  */
4405 void reset_adapter(SLMP_INFO *info)
4406 {
4407         int i;
4408
4409         for ( i=0; i < SCA_MAX_PORTS; ++i) {
4410                 if (info->port_array[i])
4411                         reset_port(info->port_array[i]);
4412         }
4413 }
4414
4415 /* Program port for asynchronous communications.
4416  */
4417 void async_mode(SLMP_INFO *info)
4418 {
4419
4420         unsigned char RegValue;
4421
4422         tx_stop(info);
4423         rx_stop(info);
4424
4425         /* MD0, Mode Register 0
4426          *
4427          * 07..05  PRCTL<2..0>, Protocol Mode, 000=async
4428          * 04      AUTO, Auto-enable (RTS/CTS/DCD)
4429          * 03      Reserved, must be 0
4430          * 02      CRCCC, CRC Calculation, 0=disabled
4431          * 01..00  STOP<1..0> Stop bits (00=1,10=2)
4432          *
4433          * 0000 0000
4434          */
4435         RegValue = 0x00;
4436         if (info->params.stop_bits != 1)
4437                 RegValue |= BIT1;
4438         write_reg(info, MD0, RegValue);
4439
4440         /* MD1, Mode Register 1
4441          *
4442          * 07..06  BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
4443          * 05..04  TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
4444          * 03..02  RXCHR<1..0>, rx char size
4445          * 01..00  PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
4446          *
4447          * 0100 0000
4448          */
4449         RegValue = 0x40;
4450         switch (info->params.data_bits) {
4451         case 7: RegValue |= BIT4 + BIT2; break;
4452         case 6: RegValue |= BIT5 + BIT3; break;
4453         case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;
4454         }
4455         if (info->params.parity != ASYNC_PARITY_NONE) {
4456                 RegValue |= BIT1;
4457                 if (info->params.parity == ASYNC_PARITY_ODD)
4458                         RegValue |= BIT0;
4459         }
4460         write_reg(info, MD1, RegValue);
4461
4462         /* MD2, Mode Register 2
4463          *
4464          * 07..02  Reserved, must be 0
4465          * 01..00  CNCT<1..0> Channel connection, 00=normal 11=local loopback
4466          *
4467          * 0000 0000
4468          */
4469         RegValue = 0x00;
4470         if (info->params.loopback)
4471                 RegValue |= (BIT1 + BIT0);
4472         write_reg(info, MD2, RegValue);
4473
4474         /* RXS, Receive clock source
4475          *
4476          * 07      Reserved, must be 0
4477          * 06..04  RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4478          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4479          */
4480         RegValue=BIT6;
4481         write_reg(info, RXS, RegValue);
4482
4483         /* TXS, Transmit clock source
4484          *
4485          * 07      Reserved, must be 0
4486          * 06..04  RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4487          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4488          */
4489         RegValue=BIT6;
4490         write_reg(info, TXS, RegValue);
4491
4492         /* Control Register
4493          *
4494          * 6,4,2,0  CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4495          */
4496         info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4497         write_control_reg(info);
4498
4499         tx_set_idle(info);
4500
4501         /* RRC Receive Ready Control 0
4502          *
4503          * 07..05  Reserved, must be 0
4504          * 04..00  RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
4505          */
4506         write_reg(info, RRC, 0x00);
4507
4508         /* TRC0 Transmit Ready Control 0
4509          *
4510          * 07..05  Reserved, must be 0
4511          * 04..00  TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
4512          */
4513         write_reg(info, TRC0, 0x10);
4514
4515         /* TRC1 Transmit Ready Control 1
4516          *
4517          * 07..05  Reserved, must be 0
4518          * 04..00  TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
4519          */
4520         write_reg(info, TRC1, 0x1e);
4521
4522         /* CTL, MSCI control register
4523          *
4524          * 07..06  Reserved, set to 0
4525          * 05      UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4526          * 04      IDLC, idle control, 0=mark 1=idle register
4527          * 03      BRK, break, 0=off 1 =on (async)
4528          * 02      SYNCLD, sync char load enable (BSC) 1=enabled
4529          * 01      GOP, go active on poll (LOOP mode) 1=enabled
4530          * 00      RTS, RTS output control, 0=active 1=inactive
4531          *
4532          * 0001 0001
4533          */
4534         RegValue = 0x10;
4535         if (!(info->serial_signals & SerialSignal_RTS))
4536                 RegValue |= 0x01;
4537         write_reg(info, CTL, RegValue);
4538
4539         /* enable status interrupts */
4540         info->ie0_value |= TXINTE + RXINTE;
4541         write_reg(info, IE0, info->ie0_value);
4542
4543         /* enable break detect interrupt */
4544         info->ie1_value = BRKD;
4545         write_reg(info, IE1, info->ie1_value);
4546
4547         /* enable rx overrun interrupt */
4548         info->ie2_value = OVRN;
4549         write_reg(info, IE2, info->ie2_value);
4550
4551         set_rate( info, info->params.data_rate * 16 );
4552 }
4553
4554 /* Program the SCA for HDLC communications.
4555  */
4556 void hdlc_mode(SLMP_INFO *info)
4557 {
4558         unsigned char RegValue;
4559         u32 DpllDivisor;
4560
4561         // Can't use DPLL because SCA outputs recovered clock on RxC when
4562         // DPLL mode selected. This causes output contention with RxC receiver.
4563         // Use of DPLL would require external hardware to disable RxC receiver
4564         // when DPLL mode selected.
4565         info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL);
4566
4567         /* disable DMA interrupts */
4568         write_reg(info, TXDMA + DIR, 0);
4569         write_reg(info, RXDMA + DIR, 0);
4570
4571         /* MD0, Mode Register 0
4572          *
4573          * 07..05  PRCTL<2..0>, Protocol Mode, 100=HDLC
4574          * 04      AUTO, Auto-enable (RTS/CTS/DCD)
4575          * 03      Reserved, must be 0
4576          * 02      CRCCC, CRC Calculation, 1=enabled
4577          * 01      CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
4578          * 00      CRC0, CRC initial value, 1 = all 1s
4579          *
4580          * 1000 0001
4581          */
4582         RegValue = 0x81;
4583         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4584                 RegValue |= BIT4;
4585         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4586                 RegValue |= BIT4;
4587         if (info->params.crc_type == HDLC_CRC_16_CCITT)
4588                 RegValue |= BIT2 + BIT1;
4589         write_reg(info, MD0, RegValue);
4590
4591         /* MD1, Mode Register 1
4592          *
4593          * 07..06  ADDRS<1..0>, Address detect, 00=no addr check
4594          * 05..04  TXCHR<1..0>, tx char size, 00=8 bits
4595          * 03..02  RXCHR<1..0>, rx char size, 00=8 bits
4596          * 01..00  PMPM<1..0>, Parity mode, 00=no parity
4597          *
4598          * 0000 0000
4599          */
4600         RegValue = 0x00;
4601         write_reg(info, MD1, RegValue);
4602
4603         /* MD2, Mode Register 2
4604          *
4605          * 07      NRZFM, 0=NRZ, 1=FM
4606          * 06..05  CODE<1..0> Encoding, 00=NRZ
4607          * 04..03  DRATE<1..0> DPLL Divisor, 00=8
4608          * 02      Reserved, must be 0
4609          * 01..00  CNCT<1..0> Channel connection, 0=normal
4610          *
4611          * 0000 0000
4612          */
4613         RegValue = 0x00;
4614         switch(info->params.encoding) {
4615         case HDLC_ENCODING_NRZI:          RegValue |= BIT5; break;
4616         case HDLC_ENCODING_BIPHASE_MARK:  RegValue |= BIT7 + BIT5; break; /* aka FM1 */
4617         case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */
4618         case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break;      /* aka Manchester */
4619 #if 0
4620         case HDLC_ENCODING_NRZB:                                        /* not supported */
4621         case HDLC_ENCODING_NRZI_MARK:                                   /* not supported */
4622         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:                          /* not supported */
4623 #endif
4624         }
4625         if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4626                 DpllDivisor = 16;
4627                 RegValue |= BIT3;
4628         } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4629                 DpllDivisor = 8;
4630         } else {
4631                 DpllDivisor = 32;
4632                 RegValue |= BIT4;
4633         }
4634         write_reg(info, MD2, RegValue);
4635
4636
4637         /* RXS, Receive clock source
4638          *
4639          * 07      Reserved, must be 0
4640          * 06..04  RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4641          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4642          */
4643         RegValue=0;
4644         if (info->params.flags & HDLC_FLAG_RXC_BRG)
4645                 RegValue |= BIT6;
4646         if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4647                 RegValue |= BIT6 + BIT5;
4648         write_reg(info, RXS, RegValue);
4649
4650         /* TXS, Transmit clock source
4651          *
4652          * 07      Reserved, must be 0
4653          * 06..04  RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4654          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4655          */
4656         RegValue=0;
4657         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4658                 RegValue |= BIT6;
4659         if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4660                 RegValue |= BIT6 + BIT5;
4661         write_reg(info, TXS, RegValue);
4662
4663         if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4664                 set_rate(info, info->params.clock_speed * DpllDivisor);
4665         else
4666                 set_rate(info, info->params.clock_speed);
4667
4668         /* GPDATA (General Purpose I/O Data Register)
4669          *
4670          * 6,4,2,0  CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4671          */
4672         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4673                 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4674         else
4675                 info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2));
4676         write_control_reg(info);
4677
4678         /* RRC Receive Ready Control 0
4679          *
4680          * 07..05  Reserved, must be 0
4681          * 04..00  RRC<4..0> Rx FIFO trigger active
4682          */
4683         write_reg(info, RRC, rx_active_fifo_level);
4684
4685         /* TRC0 Transmit Ready Control 0
4686          *
4687          * 07..05  Reserved, must be 0
4688          * 04..00  TRC<4..0> Tx FIFO trigger active
4689          */
4690         write_reg(info, TRC0, tx_active_fifo_level);
4691
4692         /* TRC1 Transmit Ready Control 1
4693          *
4694          * 07..05  Reserved, must be 0
4695          * 04..00  TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
4696          */
4697         write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1));
4698
4699         /* DMR, DMA Mode Register
4700          *
4701          * 07..05  Reserved, must be 0
4702          * 04      TMOD, Transfer Mode: 1=chained-block
4703          * 03      Reserved, must be 0
4704          * 02      NF, Number of Frames: 1=multi-frame
4705          * 01      CNTE, Frame End IRQ Counter enable: 0=disabled
4706          * 00      Reserved, must be 0
4707          *
4708          * 0001 0100
4709          */
4710         write_reg(info, TXDMA + DMR, 0x14);
4711         write_reg(info, RXDMA + DMR, 0x14);
4712
4713         /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4714         write_reg(info, RXDMA + CPB,
4715                 (unsigned char)(info->buffer_list_phys >> 16));
4716
4717         /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4718         write_reg(info, TXDMA + CPB,
4719                 (unsigned char)(info->buffer_list_phys >> 16));
4720
4721         /* enable status interrupts. other code enables/disables
4722          * the individual sources for these two interrupt classes.
4723          */
4724         info->ie0_value |= TXINTE + RXINTE;
4725         write_reg(info, IE0, info->ie0_value);
4726
4727         /* CTL, MSCI control register
4728          *
4729          * 07..06  Reserved, set to 0
4730          * 05      UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4731          * 04      IDLC, idle control, 0=mark 1=idle register
4732          * 03      BRK, break, 0=off 1 =on (async)
4733          * 02      SYNCLD, sync char load enable (BSC) 1=enabled
4734          * 01      GOP, go active on poll (LOOP mode) 1=enabled
4735          * 00      RTS, RTS output control, 0=active 1=inactive
4736          *
4737          * 0001 0001
4738          */
4739         RegValue = 0x10;
4740         if (!(info->serial_signals & SerialSignal_RTS))
4741                 RegValue |= 0x01;
4742         write_reg(info, CTL, RegValue);
4743
4744         /* preamble not supported ! */
4745
4746         tx_set_idle(info);
4747         tx_stop(info);
4748         rx_stop(info);
4749
4750         set_rate(info, info->params.clock_speed);
4751
4752         if (info->params.loopback)
4753                 enable_loopback(info,1);
4754 }
4755
4756 /* Set the transmit HDLC idle mode
4757  */
4758 void tx_set_idle(SLMP_INFO *info)
4759 {
4760         unsigned char RegValue = 0xff;
4761
4762         /* Map API idle mode to SCA register bits */
4763         switch(info->idle_mode) {
4764         case HDLC_TXIDLE_FLAGS:                 RegValue = 0x7e; break;
4765         case HDLC_TXIDLE_ALT_ZEROS_ONES:        RegValue = 0xaa; break;
4766         case HDLC_TXIDLE_ZEROS:                 RegValue = 0x00; break;
4767         case HDLC_TXIDLE_ONES:                  RegValue = 0xff; break;
4768         case HDLC_TXIDLE_ALT_MARK_SPACE:        RegValue = 0xaa; break;
4769         case HDLC_TXIDLE_SPACE:                 RegValue = 0x00; break;
4770         case HDLC_TXIDLE_MARK:                  RegValue = 0xff; break;
4771         }
4772
4773         write_reg(info, IDL, RegValue);
4774 }
4775
4776 /* Query the adapter for the state of the V24 status (input) signals.
4777  */
4778 void get_signals(SLMP_INFO *info)
4779 {
4780         u16 status = read_reg(info, SR3);
4781         u16 gpstatus = read_status_reg(info);
4782         u16 testbit;
4783
4784         /* clear all serial signals except DTR and RTS */
4785         info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
4786
4787         /* set serial signal bits to reflect MISR */
4788
4789         if (!(status & BIT3))
4790                 info->serial_signals |= SerialSignal_CTS;
4791
4792         if ( !(status & BIT2))
4793                 info->serial_signals |= SerialSignal_DCD;
4794
4795         testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7>
4796         if (!(gpstatus & testbit))
4797                 info->serial_signals |= SerialSignal_RI;
4798
4799         testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4800         if (!(gpstatus & testbit))
4801                 info->serial_signals |= SerialSignal_DSR;
4802 }
4803
4804 /* Set the state of DTR and RTS based on contents of
4805  * serial_signals member of device context.
4806  */
4807 void set_signals(SLMP_INFO *info)
4808 {
4809         unsigned char RegValue;
4810         u16 EnableBit;
4811
4812         RegValue = read_reg(info, CTL);
4813         if (info->serial_signals & SerialSignal_RTS)
4814                 RegValue &= ~BIT0;
4815         else
4816                 RegValue |= BIT0;
4817         write_reg(info, CTL, RegValue);
4818
4819         // Port 0..3 DTR is ctrl reg <1,3,5,7>
4820         EnableBit = BIT1 << (info->port_num*2);
4821         if (info->serial_signals & SerialSignal_DTR)
4822                 info->port_array[0]->ctrlreg_value &= ~EnableBit;
4823         else
4824                 info->port_array[0]->ctrlreg_value |= EnableBit;
4825         write_control_reg(info);
4826 }
4827
4828 /*******************/
4829 /* DMA Buffer Code */
4830 /*******************/
4831
4832 /* Set the count for all receive buffers to SCABUFSIZE
4833  * and set the current buffer to the first buffer. This effectively
4834  * makes all buffers free and discards any data in buffers.
4835  */
4836 void rx_reset_buffers(SLMP_INFO *info)
4837 {
4838         rx_free_frame_buffers(info, 0, info->rx_buf_count - 1);
4839 }
4840
4841 /* Free the buffers used by a received frame
4842  *
4843  * info   pointer to device instance data
4844  * first  index of 1st receive buffer of frame
4845  * last   index of last receive buffer of frame
4846  */
4847 void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last)
4848 {
4849         int done = 0;
4850
4851         while(!done) {
4852                 /* reset current buffer for reuse */
4853                 info->rx_buf_list[first].status = 0xff;
4854
4855                 if (first == last) {
4856                         done = 1;
4857                         /* set new last rx descriptor address */
4858                         write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry);
4859                 }
4860
4861                 first++;
4862                 if (first == info->rx_buf_count)
4863                         first = 0;
4864         }
4865
4866         /* set current buffer to next buffer after last buffer of frame */
4867         info->current_rx_buf = first;
4868 }
4869
4870 /* Return a received frame from the receive DMA buffers.
4871  * Only frames received without errors are returned.
4872  *
4873  * Return Value:        1 if frame returned, otherwise 0
4874  */
4875 int rx_get_frame(SLMP_INFO *info)
4876 {
4877         unsigned int StartIndex, EndIndex;      /* index of 1st and last buffers of Rx frame */
4878         unsigned short status;
4879         unsigned int framesize = 0;
4880         int ReturnCode = 0;
4881         unsigned long flags;
4882         struct tty_struct *tty = info->tty;
4883         unsigned char addr_field = 0xff;
4884         SCADESC *desc;
4885         SCADESC_EX *desc_ex;
4886
4887 CheckAgain:
4888         /* assume no frame returned, set zero length */
4889         framesize = 0;
4890         addr_field = 0xff;
4891
4892         /*
4893          * current_rx_buf points to the 1st buffer of the next available
4894          * receive frame. To find the last buffer of the frame look for
4895          * a non-zero status field in the buffer entries. (The status
4896          * field is set by the 16C32 after completing a receive frame.
4897          */
4898         StartIndex = EndIndex = info->current_rx_buf;
4899
4900         for ( ;; ) {
4901                 desc = &info->rx_buf_list[EndIndex];
4902                 desc_ex = &info->rx_buf_list_ex[EndIndex];
4903
4904                 if (desc->status == 0xff)
4905                         goto Cleanup;   /* current desc still in use, no frames available */
4906
4907                 if (framesize == 0 && info->params.addr_filter != 0xff)
4908                         addr_field = desc_ex->virt_addr[0];
4909
4910                 framesize += desc->length;
4911
4912                 /* Status != 0 means last buffer of frame */
4913                 if (desc->status)
4914                         break;
4915
4916                 EndIndex++;
4917                 if (EndIndex == info->rx_buf_count)
4918                         EndIndex = 0;
4919
4920                 if (EndIndex == info->current_rx_buf) {
4921                         /* all buffers have been 'used' but none mark      */
4922                         /* the end of a frame. Reset buffers and receiver. */
4923                         if ( info->rx_enabled ){
4924                                 spin_lock_irqsave(&info->lock,flags);
4925                                 rx_start(info);
4926                                 spin_unlock_irqrestore(&info->lock,flags);
4927                         }
4928                         goto Cleanup;
4929                 }
4930
4931         }
4932
4933         /* check status of receive frame */
4934
4935         /* frame status is byte stored after frame data
4936          *
4937          * 7 EOM (end of msg), 1 = last buffer of frame
4938          * 6 Short Frame, 1 = short frame
4939          * 5 Abort, 1 = frame aborted
4940          * 4 Residue, 1 = last byte is partial
4941          * 3 Overrun, 1 = overrun occurred during frame reception
4942          * 2 CRC,     1 = CRC error detected
4943          *
4944          */
4945         status = desc->status;
4946
4947         /* ignore CRC bit if not using CRC (bit is undefined) */
4948         /* Note:CRC is not save to data buffer */
4949         if (info->params.crc_type == HDLC_CRC_NONE)
4950                 status &= ~BIT2;
4951
4952         if (framesize == 0 ||
4953                  (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4954                 /* discard 0 byte frames, this seems to occur sometime
4955                  * when remote is idling flags.
4956                  */
4957                 rx_free_frame_buffers(info, StartIndex, EndIndex);
4958                 goto CheckAgain;
4959         }
4960
4961         if (framesize < 2)
4962                 status |= BIT6;
4963
4964         if (status & (BIT6+BIT5+BIT3+BIT2)) {
4965                 /* received frame has errors,
4966                  * update counts and mark frame size as 0
4967                  */
4968                 if (status & BIT6)
4969                         info->icount.rxshort++;
4970                 else if (status & BIT5)
4971                         info->icount.rxabort++;
4972                 else if (status & BIT3)
4973                         info->icount.rxover++;
4974                 else
4975                         info->icount.rxcrc++;
4976
4977                 framesize = 0;
4978 #ifdef CONFIG_HDLC
4979                 {
4980                         struct net_device_stats *stats = hdlc_stats(info->netdev);
4981                         stats->rx_errors++;
4982                         stats->rx_frame_errors++;
4983                 }
4984 #endif
4985         }
4986
4987         if ( debug_level >= DEBUG_LEVEL_BH )
4988                 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
4989                         __FILE__,__LINE__,info->device_name,status,framesize);
4990
4991         if ( debug_level >= DEBUG_LEVEL_DATA )
4992                 trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr,
4993                         min_t(int, framesize,SCABUFSIZE),0);
4994
4995         if (framesize) {
4996                 if (framesize > info->max_frame_size)
4997                         info->icount.rxlong++;
4998                 else {
4999                         /* copy dma buffer(s) to contiguous intermediate buffer */
5000                         int copy_count = framesize;
5001                         int index = StartIndex;
5002                         unsigned char *ptmp = info->tmp_rx_buf;
5003                         info->tmp_rx_buf_count = framesize;
5004
5005                         info->icount.rxok++;
5006
5007                         while(copy_count) {
5008                                 int partial_count = min(copy_count,SCABUFSIZE);
5009                                 memcpy( ptmp,
5010                                         info->rx_buf_list_ex[index].virt_addr,
5011                                         partial_count );
5012                                 ptmp += partial_count;
5013                                 copy_count -= partial_count;
5014
5015                                 if ( ++index == info->rx_buf_count )
5016                                         index = 0;
5017                         }
5018
5019 #ifdef CONFIG_HDLC
5020                         if (info->netcount)
5021                                 hdlcdev_rx(info,info->tmp_rx_buf,framesize);
5022                         else
5023 #endif
5024                                 ldisc_receive_buf(tty,info->tmp_rx_buf,
5025                                                   info->flag_buf, framesize);
5026                 }
5027         }
5028         /* Free the buffers used by this frame. */
5029         rx_free_frame_buffers( info, StartIndex, EndIndex );
5030
5031         ReturnCode = 1;
5032
5033 Cleanup:
5034         if ( info->rx_enabled && info->rx_overflow ) {
5035                 /* Receiver is enabled, but needs to restarted due to
5036                  * rx buffer overflow. If buffers are empty, restart receiver.
5037                  */
5038                 if (info->rx_buf_list[EndIndex].status == 0xff) {
5039                         spin_lock_irqsave(&info->lock,flags);
5040                         rx_start(info);
5041                         spin_unlock_irqrestore(&info->lock,flags);
5042                 }
5043         }
5044
5045         return ReturnCode;
5046 }
5047
5048 /* load the transmit DMA buffer with data
5049  */
5050 void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count)
5051 {
5052         unsigned short copy_count;
5053         unsigned int i = 0;
5054         SCADESC *desc;
5055         SCADESC_EX *desc_ex;
5056
5057         if ( debug_level >= DEBUG_LEVEL_DATA )
5058                 trace_block(info,buf, min_t(int, count,SCABUFSIZE), 1);
5059
5060         /* Copy source buffer to one or more DMA buffers, starting with
5061          * the first transmit dma buffer.
5062          */
5063         for(i=0;;)
5064         {
5065                 copy_count = min_t(unsigned short,count,SCABUFSIZE);
5066
5067                 desc = &info->tx_buf_list[i];
5068                 desc_ex = &info->tx_buf_list_ex[i];
5069
5070                 load_pci_memory(info, desc_ex->virt_addr,buf,copy_count);
5071
5072                 desc->length = copy_count;
5073                 desc->status = 0;
5074
5075                 buf += copy_count;
5076                 count -= copy_count;
5077
5078                 if (!count)
5079                         break;
5080
5081                 i++;
5082                 if (i >= info->tx_buf_count)
5083                         i = 0;
5084         }
5085
5086         info->tx_buf_list[i].status = 0x81;     /* set EOM and EOT status */
5087         info->last_tx_buf = ++i;
5088 }
5089
5090 int register_test(SLMP_INFO *info)
5091 {
5092         static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
5093         static unsigned int count = ARRAY_SIZE(testval);
5094         unsigned int i;
5095         int rc = TRUE;
5096         unsigned long flags;
5097
5098         spin_lock_irqsave(&info->lock,flags);
5099         reset_port(info);
5100
5101         /* assume failure */
5102         info->init_error = DiagStatus_AddressFailure;
5103
5104         /* Write bit patterns to various registers but do it out of */
5105         /* sync, then read back and verify values. */
5106
5107         for (i = 0 ; i < count ; i++) {
5108                 write_reg(info, TMC, testval[i]);
5109                 write_reg(info, IDL, testval[(i+1)%count]);
5110                 write_reg(info, SA0, testval[(i+2)%count]);
5111                 write_reg(info, SA1, testval[(i+3)%count]);
5112
5113                 if ( (read_reg(info, TMC) != testval[i]) ||
5114                           (read_reg(info, IDL) != testval[(i+1)%count]) ||
5115                           (read_reg(info, SA0) != testval[(i+2)%count]) ||
5116                           (read_reg(info, SA1) != testval[(i+3)%count]) )
5117                 {
5118                         rc = FALSE;
5119                         break;
5120                 }
5121         }
5122
5123         reset_port(info);
5124         spin_unlock_irqrestore(&info->lock,flags);
5125
5126         return rc;
5127 }
5128
5129 int irq_test(SLMP_INFO *info)
5130 {
5131         unsigned long timeout;
5132         unsigned long flags;
5133
5134         unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
5135
5136         spin_lock_irqsave(&info->lock,flags);
5137         reset_port(info);
5138
5139         /* assume failure */
5140         info->init_error = DiagStatus_IrqFailure;
5141         info->irq_occurred = FALSE;
5142
5143         /* setup timer0 on SCA0 to interrupt */
5144
5145         /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
5146         write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4));
5147
5148         write_reg(info, (unsigned char)(timer + TEPR), 0);      /* timer expand prescale */
5149         write_reg16(info, (unsigned char)(timer + TCONR), 1);   /* timer constant */
5150
5151
5152         /* TMCS, Timer Control/Status Register
5153          *
5154          * 07      CMF, Compare match flag (read only) 1=match
5155          * 06      ECMI, CMF Interrupt Enable: 1=enabled
5156          * 05      Reserved, must be 0
5157          * 04      TME, Timer Enable
5158          * 03..00  Reserved, must be 0
5159          *
5160          * 0101 0000
5161          */
5162         write_reg(info, (unsigned char)(timer + TMCS), 0x50);
5163
5164         spin_unlock_irqrestore(&info->lock,flags);
5165
5166         timeout=100;
5167         while( timeout-- && !info->irq_occurred ) {
5168                 msleep_interruptible(10);
5169         }
5170
5171         spin_lock_irqsave(&info->lock,flags);
5172         reset_port(info);
5173         spin_unlock_irqrestore(&info->lock,flags);
5174
5175         return info->irq_occurred;
5176 }
5177
5178 /* initialize individual SCA device (2 ports)
5179  */
5180 static int sca_init(SLMP_INFO *info)
5181 {
5182         /* set wait controller to single mem partition (low), no wait states */
5183         write_reg(info, PABR0, 0);      /* wait controller addr boundary 0 */
5184         write_reg(info, PABR1, 0);      /* wait controller addr boundary 1 */
5185         write_reg(info, WCRL, 0);       /* wait controller low range */
5186         write_reg(info, WCRM, 0);       /* wait controller mid range */
5187         write_reg(info, WCRH, 0);       /* wait controller high range */
5188
5189         /* DPCR, DMA Priority Control
5190          *
5191          * 07..05  Not used, must be 0
5192          * 04      BRC, bus release condition: 0=all transfers complete
5193          * 03      CCC, channel change condition: 0=every cycle
5194          * 02..00  PR<2..0>, priority 100=round robin
5195          *
5196          * 00000100 = 0x04
5197          */
5198         write_reg(info, DPCR, dma_priority);
5199
5200         /* DMA Master Enable, BIT7: 1=enable all channels */
5201         write_reg(info, DMER, 0x80);
5202
5203         /* enable all interrupt classes */
5204         write_reg(info, IER0, 0xff);    /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
5205         write_reg(info, IER1, 0xff);    /* DMIB,DMIA (channels 0-3) */
5206         write_reg(info, IER2, 0xf0);    /* TIRQ (timers 0-3) */
5207
5208         /* ITCR, interrupt control register
5209          * 07      IPC, interrupt priority, 0=MSCI->DMA
5210          * 06..05  IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
5211          * 04      VOS, Vector Output, 0=unmodified vector
5212          * 03..00  Reserved, must be 0
5213          */
5214         write_reg(info, ITCR, 0);
5215
5216         return TRUE;
5217 }
5218
5219 /* initialize adapter hardware
5220  */
5221 int init_adapter(SLMP_INFO *info)
5222 {
5223         int i;
5224
5225         /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
5226         volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5227         u32 readval;
5228
5229         info->misc_ctrl_value |= BIT30;
5230         *MiscCtrl = info->misc_ctrl_value;
5231
5232         /*
5233          * Force at least 170ns delay before clearing
5234          * reset bit. Each read from LCR takes at least
5235          * 30ns so 10 times for 300ns to be safe.
5236          */
5237         for(i=0;i<10;i++)
5238                 readval = *MiscCtrl;
5239
5240         info->misc_ctrl_value &= ~BIT30;
5241         *MiscCtrl = info->misc_ctrl_value;
5242
5243         /* init control reg (all DTRs off, all clksel=input) */
5244         info->ctrlreg_value = 0xaa;
5245         write_control_reg(info);
5246
5247         {
5248                 volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c);
5249                 lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3);
5250
5251                 switch(read_ahead_count)
5252                 {
5253                 case 16:
5254                         lcr1_brdr_value |= BIT5 + BIT4 + BIT3;
5255                         break;
5256                 case 8:
5257                         lcr1_brdr_value |= BIT5 + BIT4;
5258                         break;
5259                 case 4:
5260                         lcr1_brdr_value |= BIT5 + BIT3;
5261                         break;
5262                 case 0:
5263                         lcr1_brdr_value |= BIT5;
5264                         break;
5265                 }
5266
5267                 *LCR1BRDR = lcr1_brdr_value;
5268                 *MiscCtrl = misc_ctrl_value;
5269         }
5270
5271         sca_init(info->port_array[0]);
5272         sca_init(info->port_array[2]);
5273
5274         return TRUE;
5275 }
5276
5277 /* Loopback an HDLC frame to test the hardware
5278  * interrupt and DMA functions.
5279  */
5280 int loopback_test(SLMP_INFO *info)
5281 {
5282 #define TESTFRAMESIZE 20
5283
5284         unsigned long timeout;
5285         u16 count = TESTFRAMESIZE;
5286         unsigned char buf[TESTFRAMESIZE];
5287         int rc = FALSE;
5288         unsigned long flags;
5289
5290         struct tty_struct *oldtty = info->tty;
5291         u32 speed = info->params.clock_speed;
5292
5293         info->params.clock_speed = 3686400;
5294         info->tty = NULL;
5295
5296         /* assume failure */
5297         info->init_error = DiagStatus_DmaFailure;
5298
5299         /* build and send transmit frame */
5300         for (count = 0; count < TESTFRAMESIZE;++count)
5301                 buf[count] = (unsigned char)count;
5302
5303         memset(info->tmp_rx_buf,0,TESTFRAMESIZE);
5304
5305         /* program hardware for HDLC and enabled receiver */
5306         spin_lock_irqsave(&info->lock,flags);
5307         hdlc_mode(info);
5308         enable_loopback(info,1);
5309         rx_start(info);
5310         info->tx_count = count;
5311         tx_load_dma_buffer(info,buf,count);
5312         tx_start(info);
5313         spin_unlock_irqrestore(&info->lock,flags);
5314
5315         /* wait for receive complete */
5316         /* Set a timeout for waiting for interrupt. */
5317         for ( timeout = 100; timeout; --timeout ) {
5318                 msleep_interruptible(10);
5319
5320                 if (rx_get_frame(info)) {
5321                         rc = TRUE;
5322                         break;
5323                 }
5324         }
5325
5326         /* verify received frame length and contents */
5327         if (rc == TRUE &&
5328                 ( info->tmp_rx_buf_count != count ||
5329                   memcmp(buf, info->tmp_rx_buf,count))) {
5330                 rc = FALSE;
5331         }
5332
5333         spin_lock_irqsave(&info->lock,flags);
5334         reset_adapter(info);
5335         spin_unlock_irqrestore(&info->lock,flags);
5336
5337         info->params.clock_speed = speed;
5338         info->tty = oldtty;
5339
5340         return rc;
5341 }
5342
5343 /* Perform diagnostics on hardware
5344  */
5345 int adapter_test( SLMP_INFO *info )
5346 {
5347         unsigned long flags;
5348         if ( debug_level >= DEBUG_LEVEL_INFO )
5349                 printk( "%s(%d):Testing device %s\n",
5350                         __FILE__,__LINE__,info->device_name );
5351
5352         spin_lock_irqsave(&info->lock,flags);
5353         init_adapter(info);
5354         spin_unlock_irqrestore(&info->lock,flags);
5355
5356         info->port_array[0]->port_count = 0;
5357
5358         if ( register_test(info->port_array[0]) &&
5359                 register_test(info->port_array[1])) {
5360
5361                 info->port_array[0]->port_count = 2;
5362
5363                 if ( register_test(info->port_array[2]) &&
5364                         register_test(info->port_array[3]) )
5365                         info->port_array[0]->port_count += 2;
5366         }
5367         else {
5368                 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5369                         __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base));
5370                 return -ENODEV;
5371         }
5372
5373         if ( !irq_test(info->port_array[0]) ||
5374                 !irq_test(info->port_array[1]) ||
5375                  (info->port_count == 4 && !irq_test(info->port_array[2])) ||
5376                  (info->port_count == 4 && !irq_test(info->port_array[3]))) {
5377                 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5378                         __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
5379                 return -ENODEV;
5380         }
5381
5382         if (!loopback_test(info->port_array[0]) ||
5383                 !loopback_test(info->port_array[1]) ||
5384                  (info->port_count == 4 && !loopback_test(info->port_array[2])) ||
5385                  (info->port_count == 4 && !loopback_test(info->port_array[3]))) {
5386                 printk( "%s(%d):DMA test failure for device %s\n",
5387                         __FILE__,__LINE__,info->device_name);
5388                 return -ENODEV;
5389         }
5390
5391         if ( debug_level >= DEBUG_LEVEL_INFO )
5392                 printk( "%s(%d):device %s passed diagnostics\n",
5393                         __FILE__,__LINE__,info->device_name );
5394
5395         info->port_array[0]->init_error = 0;
5396         info->port_array[1]->init_error = 0;
5397         if ( info->port_count > 2 ) {
5398                 info->port_array[2]->init_error = 0;
5399                 info->port_array[3]->init_error = 0;
5400         }
5401
5402         return 0;
5403 }
5404
5405 /* Test the shared memory on a PCI adapter.
5406  */
5407 int memory_test(SLMP_INFO *info)
5408 {
5409         static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5410                 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
5411         unsigned long count = ARRAY_SIZE(testval);
5412         unsigned long i;
5413         unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long);
5414         unsigned long * addr = (unsigned long *)info->memory_base;
5415
5416         /* Test data lines with test pattern at one location. */
5417
5418         for ( i = 0 ; i < count ; i++ ) {
5419                 *addr = testval[i];
5420                 if ( *addr != testval[i] )
5421                         return FALSE;
5422         }
5423
5424         /* Test address lines with incrementing pattern over */
5425         /* entire address range. */
5426
5427         for ( i = 0 ; i < limit ; i++ ) {
5428                 *addr = i * 4;
5429                 addr++;
5430         }
5431
5432         addr = (unsigned long *)info->memory_base;
5433
5434         for ( i = 0 ; i < limit ; i++ ) {
5435                 if ( *addr != i * 4 )
5436                         return FALSE;
5437                 addr++;
5438         }
5439
5440         memset( info->memory_base, 0, SCA_MEM_SIZE );
5441         return TRUE;
5442 }
5443
5444 /* Load data into PCI adapter shared memory.
5445  *
5446  * The PCI9050 releases control of the local bus
5447  * after completing the current read or write operation.
5448  *
5449  * While the PCI9050 write FIFO not empty, the
5450  * PCI9050 treats all of the writes as a single transaction
5451  * and does not release the bus. This causes DMA latency problems
5452  * at high speeds when copying large data blocks to the shared memory.
5453  *
5454  * This function breaks a write into multiple transations by
5455  * interleaving a read which flushes the write FIFO and 'completes'
5456  * the write transation. This allows any pending DMA request to gain control
5457  * of the local bus in a timely fasion.
5458  */
5459 void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count)
5460 {
5461         /* A load interval of 16 allows for 4 32-bit writes at */
5462         /* 136ns each for a maximum latency of 542ns on the local bus.*/
5463
5464         unsigned short interval = count / sca_pci_load_interval;
5465         unsigned short i;
5466
5467         for ( i = 0 ; i < interval ; i++ )
5468         {
5469                 memcpy(dest, src, sca_pci_load_interval);
5470                 read_status_reg(info);
5471                 dest += sca_pci_load_interval;
5472                 src += sca_pci_load_interval;
5473         }
5474
5475         memcpy(dest, src, count % sca_pci_load_interval);
5476 }
5477
5478 void trace_block(SLMP_INFO *info,const char* data, int count, int xmit)
5479 {
5480         int i;
5481         int linecount;
5482         if (xmit)
5483                 printk("%s tx data:\n",info->device_name);
5484         else
5485                 printk("%s rx data:\n",info->device_name);
5486
5487         while(count) {
5488                 if (count > 16)
5489                         linecount = 16;
5490                 else
5491                         linecount = count;
5492
5493                 for(i=0;i<linecount;i++)
5494                         printk("%02X ",(unsigned char)data[i]);
5495                 for(;i<17;i++)
5496                         printk("   ");
5497                 for(i=0;i<linecount;i++) {
5498                         if (data[i]>=040 && data[i]<=0176)
5499                                 printk("%c",data[i]);
5500                         else
5501                                 printk(".");
5502                 }
5503                 printk("\n");
5504
5505                 data  += linecount;
5506                 count -= linecount;
5507         }
5508 }       /* end of trace_block() */
5509
5510 /* called when HDLC frame times out
5511  * update stats and do tx completion processing
5512  */
5513 void tx_timeout(unsigned long context)
5514 {
5515         SLMP_INFO *info = (SLMP_INFO*)context;
5516         unsigned long flags;
5517
5518         if ( debug_level >= DEBUG_LEVEL_INFO )
5519                 printk( "%s(%d):%s tx_timeout()\n",
5520                         __FILE__,__LINE__,info->device_name);
5521         if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5522                 info->icount.txtimeout++;
5523         }
5524         spin_lock_irqsave(&info->lock,flags);
5525         info->tx_active = 0;
5526         info->tx_count = info->tx_put = info->tx_get = 0;
5527
5528         spin_unlock_irqrestore(&info->lock,flags);
5529
5530 #ifdef CONFIG_HDLC
5531         if (info->netcount)
5532                 hdlcdev_tx_done(info);
5533         else
5534 #endif
5535                 bh_transmit(info);
5536 }
5537
5538 /* called to periodically check the DSR/RI modem signal input status
5539  */
5540 void status_timeout(unsigned long context)
5541 {
5542         u16 status = 0;
5543         SLMP_INFO *info = (SLMP_INFO*)context;
5544         unsigned long flags;
5545         unsigned char delta;
5546
5547
5548         spin_lock_irqsave(&info->lock,flags);
5549         get_signals(info);
5550         spin_unlock_irqrestore(&info->lock,flags);
5551
5552         /* check for DSR/RI state change */
5553
5554         delta = info->old_signals ^ info->serial_signals;
5555         info->old_signals = info->serial_signals;
5556
5557         if (delta & SerialSignal_DSR)
5558                 status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR);
5559
5560         if (delta & SerialSignal_RI)
5561                 status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI);
5562
5563         if (delta & SerialSignal_DCD)
5564                 status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD);
5565
5566         if (delta & SerialSignal_CTS)
5567                 status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS);
5568
5569         if (status)
5570                 isr_io_pin(info,status);
5571
5572         info->status_timer.data = (unsigned long)info;
5573         info->status_timer.function = status_timeout;
5574         info->status_timer.expires = jiffies + msecs_to_jiffies(10);
5575         add_timer(&info->status_timer);
5576 }
5577
5578
5579 /* Register Access Routines -
5580  * All registers are memory mapped
5581  */
5582 #define CALC_REGADDR() \
5583         unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5584         if (info->port_num > 1) \
5585                 RegAddr += 256;                 /* port 0-1 SCA0, 2-3 SCA1 */ \
5586         if ( info->port_num & 1) { \
5587                 if (Addr > 0x7f) \
5588                         RegAddr += 0x40;        /* DMA access */ \
5589                 else if (Addr > 0x1f && Addr < 0x60) \
5590                         RegAddr += 0x20;        /* MSCI access */ \
5591         }
5592
5593
5594 unsigned char read_reg(SLMP_INFO * info, unsigned char Addr)
5595 {
5596         CALC_REGADDR();
5597         return *RegAddr;
5598 }
5599 void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value)
5600 {
5601         CALC_REGADDR();
5602         *RegAddr = Value;
5603 }
5604
5605 u16 read_reg16(SLMP_INFO * info, unsigned char Addr)
5606 {
5607         CALC_REGADDR();
5608         return *((u16 *)RegAddr);
5609 }
5610
5611 void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value)
5612 {
5613         CALC_REGADDR();
5614         *((u16 *)RegAddr) = Value;
5615 }
5616
5617 unsigned char read_status_reg(SLMP_INFO * info)
5618 {
5619         unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5620         return *RegAddr;
5621 }
5622
5623 void write_control_reg(SLMP_INFO * info)
5624 {
5625         unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5626         *RegAddr = info->port_array[0]->ctrlreg_value;
5627 }
5628
5629
5630 static int __devinit synclinkmp_init_one (struct pci_dev *dev,
5631                                           const struct pci_device_id *ent)
5632 {
5633         if (pci_enable_device(dev)) {
5634                 printk("error enabling pci device %p\n", dev);
5635                 return -EIO;
5636         }
5637         device_init( ++synclinkmp_adapter_count, dev );
5638         return 0;
5639 }
5640
5641 static void __devexit synclinkmp_remove_one (struct pci_dev *dev)
5642 {
5643 }