Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound-2.6
[linux-2.6] / arch / powerpc / boot / dts / mpc832x_mds.dts
1 /*
2  * MPC8323E EMDS Device Tree Source
3  *
4  * Copyright 2006 Freescale Semiconductor Inc.
5  *
6  * This program is free software; you can redistribute  it and/or modify it
7  * under  the terms of  the GNU General  Public License as published by the
8  * Free Software Foundation;  either version 2 of the  License, or (at your
9  * option) any later version.
10
11  * To enable external serial I/O on a Freescale MPC 8323 SYS/MDS board, do
12  * this:
13  *
14  * 1) On chip U61, lift (disconnect) pins 21 (TXD) and 22 (RXD) from the board.
15  * 2) Solder a wire from U61-21 to P19A-23.  P19 is a grid of pins on the board
16  *    next to the serial ports.
17  * 3) Solder a wire from U61-22 to P19K-22.
18  *
19  * Note that there's a typo in the schematic.  The board labels the last column
20  * of pins "P19K", but in the schematic, that column is called "P19J".  So if
21  * you're going by the schematic, the pin is called "P19J-K22".
22  */
23
24 /dts-v1/;
25
26 / {
27         model = "MPC8323EMDS";
28         compatible = "MPC8323EMDS", "MPC832xMDS", "MPC83xxMDS";
29         #address-cells = <1>;
30         #size-cells = <1>;
31
32         aliases {
33                 ethernet0 = &enet0;
34                 ethernet1 = &enet1;
35                 serial0 = &serial0;
36                 serial1 = &serial1;
37                 pci0 = &pci0;
38         };
39
40         cpus {
41                 #address-cells = <1>;
42                 #size-cells = <0>;
43
44                 PowerPC,8323@0 {
45                         device_type = "cpu";
46                         reg = <0x0>;
47                         d-cache-line-size = <32>;       // 32 bytes
48                         i-cache-line-size = <32>;       // 32 bytes
49                         d-cache-size = <16384>;         // L1, 16K
50                         i-cache-size = <16384>;         // L1, 16K
51                         timebase-frequency = <0>;
52                         bus-frequency = <0>;
53                         clock-frequency = <0>;
54                 };
55         };
56
57         memory {
58                 device_type = "memory";
59                 reg = <0x00000000 0x08000000>;
60         };
61
62         bcsr@f8000000 {
63                 device_type = "board-control";
64                 reg = <0xf8000000 0x8000>;
65         };
66
67         soc8323@e0000000 {
68                 #address-cells = <1>;
69                 #size-cells = <1>;
70                 device_type = "soc";
71                 compatible = "simple-bus";
72                 ranges = <0x0 0xe0000000 0x00100000>;
73                 reg = <0xe0000000 0x00000200>;
74                 bus-frequency = <132000000>;
75
76                 wdt@200 {
77                         device_type = "watchdog";
78                         compatible = "mpc83xx_wdt";
79                         reg = <0x200 0x100>;
80                 };
81
82                 i2c@3000 {
83                         #address-cells = <1>;
84                         #size-cells = <0>;
85                         cell-index = <0>;
86                         compatible = "fsl-i2c";
87                         reg = <0x3000 0x100>;
88                         interrupts = <14 0x8>;
89                         interrupt-parent = <&ipic>;
90                         dfsrr;
91
92                         rtc@68 {
93                                 compatible = "dallas,ds1374";
94                                 reg = <0x68>;
95                         };
96                 };
97
98                 serial0: serial@4500 {
99                         cell-index = <0>;
100                         device_type = "serial";
101                         compatible = "ns16550";
102                         reg = <0x4500 0x100>;
103                         clock-frequency = <0>;
104                         interrupts = <9 0x8>;
105                         interrupt-parent = <&ipic>;
106                 };
107
108                 serial1: serial@4600 {
109                         cell-index = <1>;
110                         device_type = "serial";
111                         compatible = "ns16550";
112                         reg = <0x4600 0x100>;
113                         clock-frequency = <0>;
114                         interrupts = <10 0x8>;
115                         interrupt-parent = <&ipic>;
116                 };
117
118                 dma@82a8 {
119                         #address-cells = <1>;
120                         #size-cells = <1>;
121                         compatible = "fsl,mpc8323-dma", "fsl,elo-dma";
122                         reg = <0x82a8 4>;
123                         ranges = <0 0x8100 0x1a8>;
124                         interrupt-parent = <&ipic>;
125                         interrupts = <71 8>;
126                         cell-index = <0>;
127                         dma-channel@0 {
128                                 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
129                                 reg = <0 0x80>;
130                                 interrupt-parent = <&ipic>;
131                                 interrupts = <71 8>;
132                         };
133                         dma-channel@80 {
134                                 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
135                                 reg = <0x80 0x80>;
136                                 interrupt-parent = <&ipic>;
137                                 interrupts = <71 8>;
138                         };
139                         dma-channel@100 {
140                                 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
141                                 reg = <0x100 0x80>;
142                                 interrupt-parent = <&ipic>;
143                                 interrupts = <71 8>;
144                         };
145                         dma-channel@180 {
146                                 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
147                                 reg = <0x180 0x28>;
148                                 interrupt-parent = <&ipic>;
149                                 interrupts = <71 8>;
150                         };
151                 };
152
153                 crypto@30000 {
154                         compatible = "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
155                         reg = <0x30000 0x10000>;
156                         interrupts = <11 0x8>;
157                         interrupt-parent = <&ipic>;
158                         fsl,num-channels = <1>;
159                         fsl,channel-fifo-len = <24>;
160                         fsl,exec-units-mask = <0x4c>;
161                         fsl,descriptor-types-mask = <0x0122003f>;
162                 };
163
164                 ipic: pic@700 {
165                         interrupt-controller;
166                         #address-cells = <0>;
167                         #interrupt-cells = <2>;
168                         reg = <0x700 0x100>;
169                         device_type = "ipic";
170                 };
171
172                 par_io@1400 {
173                         reg = <0x1400 0x100>;
174                         device_type = "par_io";
175                         num-ports = <7>;
176
177                         pio3: ucc_pin@03 {
178                                 pio-map = <
179                         /* port  pin  dir  open_drain  assignment  has_irq */
180                                         3  4  3  0  2  0  /* MDIO */
181                                         3  5  1  0  2  0  /* MDC */
182                                         0 13  2  0  1  0        /* RX_CLK (CLK9) */
183                                         3 24  2  0  1  0        /* TX_CLK (CLK10) */
184                                         1  0  1  0  1  0        /* TxD0 */
185                                         1  1  1  0  1  0        /* TxD1 */
186                                         1  2  1  0  1  0        /* TxD2 */
187                                         1  3  1  0  1  0        /* TxD3 */
188                                         1  4  2  0  1  0        /* RxD0 */
189                                         1  5  2  0  1  0        /* RxD1 */
190                                         1  6  2  0  1  0        /* RxD2 */
191                                         1  7  2  0  1  0        /* RxD3 */
192                                         1  8  2  0  1  0        /* RX_ER */
193                                         1  9  1  0  1  0        /* TX_ER */
194                                         1 10  2  0  1  0        /* RX_DV */
195                                         1 11  2  0  1  0        /* COL */
196                                         1 12  1  0  1  0        /* TX_EN */
197                                         1 13  2  0  1  0>;      /* CRS */
198                         };
199                         pio4: ucc_pin@04 {
200                                 pio-map = <
201                         /* port  pin  dir  open_drain  assignment  has_irq */
202                                         3 31  2  0  1  0        /* RX_CLK (CLK7) */
203                                         3  6  2  0  1  0        /* TX_CLK (CLK8) */
204                                         1 18  1  0  1  0        /* TxD0 */
205                                         1 19  1  0  1  0        /* TxD1 */
206                                         1 20  1  0  1  0        /* TxD2 */
207                                         1 21  1  0  1  0        /* TxD3 */
208                                         1 22  2  0  1  0        /* RxD0 */
209                                         1 23  2  0  1  0        /* RxD1 */
210                                         1 24  2  0  1  0        /* RxD2 */
211                                         1 25  2  0  1  0        /* RxD3 */
212                                         1 26  2  0  1  0        /* RX_ER */
213                                         1 27  1  0  1  0        /* TX_ER */
214                                         1 28  2  0  1  0        /* RX_DV */
215                                         1 29  2  0  1  0        /* COL */
216                                         1 30  1  0  1  0        /* TX_EN */
217                                         1 31  2  0  1  0>;      /* CRS */
218                         };
219                         pio5: ucc_pin@05 {
220                                 pio-map = <
221                                 /*
222                                  *                    open       has
223                                  *   port  pin  dir  drain  sel  irq
224                                  */
225                                         2    0    1      0    2    0  /* TxD5 */
226                                         2    8    2      0    2    0  /* RxD5 */
227
228                                         2   29    2      0    0    0  /* CTS5 */
229                                         2   31    1      0    2    0  /* RTS5 */
230
231                                         2   24    2      0    0    0  /* CD */
232
233                                 >;
234                         };
235
236                 };
237         };
238
239         qe@e0100000 {
240                 #address-cells = <1>;
241                 #size-cells = <1>;
242                 device_type = "qe";
243                 compatible = "fsl,qe";
244                 ranges = <0x0 0xe0100000 0x00100000>;
245                 reg = <0xe0100000 0x480>;
246                 brg-frequency = <0>;
247                 bus-frequency = <198000000>;
248
249                 muram@10000 {
250                         #address-cells = <1>;
251                         #size-cells = <1>;
252                         compatible = "fsl,qe-muram", "fsl,cpm-muram";
253                         ranges = <0x0 0x00010000 0x00004000>;
254
255                         data-only@0 {
256                                 compatible = "fsl,qe-muram-data",
257                                              "fsl,cpm-muram-data";
258                                 reg = <0x0 0x4000>;
259                         };
260                 };
261
262                 spi@4c0 {
263                         cell-index = <0>;
264                         compatible = "fsl,spi";
265                         reg = <0x4c0 0x40>;
266                         interrupts = <2>;
267                         interrupt-parent = <&qeic>;
268                         mode = "cpu";
269                 };
270
271                 spi@500 {
272                         cell-index = <1>;
273                         compatible = "fsl,spi";
274                         reg = <0x500 0x40>;
275                         interrupts = <1>;
276                         interrupt-parent = <&qeic>;
277                         mode = "cpu";
278                 };
279
280                 usb@6c0 {
281                         compatible = "qe_udc";
282                         reg = <0x6c0 0x40 0x8b00 0x100>;
283                         interrupts = <11>;
284                         interrupt-parent = <&qeic>;
285                         mode = "slave";
286                 };
287
288                 enet0: ucc@2200 {
289                         device_type = "network";
290                         compatible = "ucc_geth";
291                         cell-index = <3>;
292                         reg = <0x2200 0x200>;
293                         interrupts = <34>;
294                         interrupt-parent = <&qeic>;
295                         local-mac-address = [ 00 00 00 00 00 00 ];
296                         rx-clock-name = "clk9";
297                         tx-clock-name = "clk10";
298                         phy-handle = <&phy3>;
299                         pio-handle = <&pio3>;
300                 };
301
302                 enet1: ucc@3200 {
303                         device_type = "network";
304                         compatible = "ucc_geth";
305                         cell-index = <4>;
306                         reg = <0x3200 0x200>;
307                         interrupts = <35>;
308                         interrupt-parent = <&qeic>;
309                         local-mac-address = [ 00 00 00 00 00 00 ];
310                         rx-clock-name = "clk7";
311                         tx-clock-name = "clk8";
312                         phy-handle = <&phy4>;
313                         pio-handle = <&pio4>;
314                 };
315
316                 ucc@2400 {
317                         device_type = "serial";
318                         compatible = "ucc_uart";
319                         cell-index = <5>;       /* The UCC number, 1-7*/
320                         port-number = <0>;      /* Which ttyQEx device */
321                         soft-uart;              /* We need Soft-UART */
322                         reg = <0x2400 0x200>;
323                         interrupts = <40>;      /* From Table 18-12 */
324                         interrupt-parent = < &qeic >;
325                         /*
326                          * For Soft-UART, we need to set TX to 1X, which
327                          * means specifying separate clock sources.
328                          */
329                         rx-clock-name = "brg5";
330                         tx-clock-name = "brg6";
331                         pio-handle = < &pio5 >;
332                 };
333
334
335                 mdio@2320 {
336                         #address-cells = <1>;
337                         #size-cells = <0>;
338                         reg = <0x2320 0x18>;
339                         compatible = "fsl,ucc-mdio";
340
341                         phy3: ethernet-phy@03 {
342                                 interrupt-parent = <&ipic>;
343                                 interrupts = <17 0x8>;
344                                 reg = <0x3>;
345                                 device_type = "ethernet-phy";
346                         };
347                         phy4: ethernet-phy@04 {
348                                 interrupt-parent = <&ipic>;
349                                 interrupts = <18 0x8>;
350                                 reg = <0x4>;
351                                 device_type = "ethernet-phy";
352                         };
353                 };
354
355                 qeic: interrupt-controller@80 {
356                         interrupt-controller;
357                         compatible = "fsl,qe-ic";
358                         #address-cells = <0>;
359                         #interrupt-cells = <1>;
360                         reg = <0x80 0x80>;
361                         big-endian;
362                         interrupts = <32 0x8 33 0x8>; //high:32 low:33
363                         interrupt-parent = <&ipic>;
364                 };
365         };
366
367         pci0: pci@e0008500 {
368                 cell-index = <1>;
369                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
370                 interrupt-map = <
371                                 /* IDSEL 0x11 AD17 */
372                                  0x8800 0x0 0x0 0x1 &ipic 20 0x8
373                                  0x8800 0x0 0x0 0x2 &ipic 21 0x8
374                                  0x8800 0x0 0x0 0x3 &ipic 22 0x8
375                                  0x8800 0x0 0x0 0x4 &ipic 23 0x8
376
377                                 /* IDSEL 0x12 AD18 */
378                                  0x9000 0x0 0x0 0x1 &ipic 22 0x8
379                                  0x9000 0x0 0x0 0x2 &ipic 23 0x8
380                                  0x9000 0x0 0x0 0x3 &ipic 20 0x8
381                                  0x9000 0x0 0x0 0x4 &ipic 21 0x8
382
383                                 /* IDSEL 0x13 AD19 */
384                                  0x9800 0x0 0x0 0x1 &ipic 23 0x8
385                                  0x9800 0x0 0x0 0x2 &ipic 20 0x8
386                                  0x9800 0x0 0x0 0x3 &ipic 21 0x8
387                                  0x9800 0x0 0x0 0x4 &ipic 22 0x8
388
389                                 /* IDSEL 0x15 AD21*/
390                                  0xa800 0x0 0x0 0x1 &ipic 20 0x8
391                                  0xa800 0x0 0x0 0x2 &ipic 21 0x8
392                                  0xa800 0x0 0x0 0x3 &ipic 22 0x8
393                                  0xa800 0x0 0x0 0x4 &ipic 23 0x8
394
395                                 /* IDSEL 0x16 AD22*/
396                                  0xb000 0x0 0x0 0x1 &ipic 23 0x8
397                                  0xb000 0x0 0x0 0x2 &ipic 20 0x8
398                                  0xb000 0x0 0x0 0x3 &ipic 21 0x8
399                                  0xb000 0x0 0x0 0x4 &ipic 22 0x8
400
401                                 /* IDSEL 0x17 AD23*/
402                                  0xb800 0x0 0x0 0x1 &ipic 22 0x8
403                                  0xb800 0x0 0x0 0x2 &ipic 23 0x8
404                                  0xb800 0x0 0x0 0x3 &ipic 20 0x8
405                                  0xb800 0x0 0x0 0x4 &ipic 21 0x8
406
407                                 /* IDSEL 0x18 AD24*/
408                                  0xc000 0x0 0x0 0x1 &ipic 21 0x8
409                                  0xc000 0x0 0x0 0x2 &ipic 22 0x8
410                                  0xc000 0x0 0x0 0x3 &ipic 23 0x8
411                                  0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
412                 interrupt-parent = <&ipic>;
413                 interrupts = <66 0x8>;
414                 bus-range = <0x0 0x0>;
415                 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
416                           0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
417                           0x01000000 0x0 0x00000000 0xd0000000 0x0 0x00100000>;
418                 clock-frequency = <0>;
419                 #interrupt-cells = <1>;
420                 #size-cells = <2>;
421                 #address-cells = <3>;
422                 reg = <0xe0008500 0x100>;
423                 compatible = "fsl,mpc8349-pci";
424                 device_type = "pci";
425         };
426 };