git.oblomov.eu Git - linux-2.6/blob - arch/powerpc/boot/dts/mpc8641_hpcn.dts

   1 /*
   2  * MPC8641 HPCN Device Tree Source
   3  *
   4  * Copyright 2006 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12
  13 / {
  14         model = "MPC8641HPCN";
  15         compatible = "mpc86xx";
  16         #address-cells = <1>;
  17         #size-cells = <1>;
  18
  19         cpus {
  20                 #address-cells = <1>;
  21                 #size-cells = <0>;
  22
  23                 PowerPC,8641@0 {
  24                         device_type = "cpu";
  25                         reg = <0>;
  26                         d-cache-line-size = <20>;       // 32 bytes
  27                         i-cache-line-size = <20>;       // 32 bytes
  28                         d-cache-size = <8000>;          // L1, 32K
  29                         i-cache-size = <8000>;          // L1, 32K
  30                         timebase-frequency = <0>;       // 33 MHz, from uboot
  31                         bus-frequency = <0>;            // From uboot
  32                         clock-frequency = <0>;          // From uboot
  33                         32-bit;
  34                 };
  35                 PowerPC,8641@1 {
  36                         device_type = "cpu";
  37                         reg = <1>;
  38                         d-cache-line-size = <20>;       // 32 bytes
  39                         i-cache-line-size = <20>;       // 32 bytes
  40                         d-cache-size = <8000>;          // L1, 32K
  41                         i-cache-size = <8000>;          // L1, 32K
  42                         timebase-frequency = <0>;       // 33 MHz, from uboot
  43                         bus-frequency = <0>;            // From uboot
  44                         clock-frequency = <0>;          // From uboot
  45                         32-bit;
  46                 };
  47         };
  48
  49         memory {
  50                 device_type = "memory";
  51                 reg = <00000000 40000000>;      // 1G at 0x0
  52         };
  53
  54         soc8641@f8000000 {
  55                 #address-cells = <1>;
  56                 #size-cells = <1>;
  57                 #interrupt-cells = <2>;
  58                 device_type = "soc";
  59                 ranges = <00001000 f8001000 000ff000
  60                           80000000 80000000 20000000
  61                           e2000000 e2000000 00100000
  62                           a0000000 a0000000 20000000
  63                           e3000000 e3000000 00100000>;
  64                 reg = <f8000000 00001000>;      // CCSRBAR
  65                 bus-frequency = <0>;
  66
  67                 i2c@3000 {
  68                         device_type = "i2c";
  69                         compatible = "fsl-i2c";
  70                         reg = <3000 100>;
  71                         interrupts = <2b 2>;
  72                         interrupt-parent = <&mpic>;
  73                         dfsrr;
  74                 };
  75
  76                 i2c@3100 {
  77                         device_type = "i2c";
  78                         compatible = "fsl-i2c";
  79                         reg = <3100 100>;
  80                         interrupts = <2b 2>;
  81                         interrupt-parent = <&mpic>;
  82                         dfsrr;
  83                 };
  84
  85                 mdio@24520 {
  86                         #address-cells = <1>;
  87                         #size-cells = <0>;
  88                         device_type = "mdio";
  89                         compatible = "gianfar";
  90                         reg = <24520 20>;
  91                         phy0: ethernet-phy@0 {
  92                                 interrupt-parent = <&mpic>;
  93                                 interrupts = <4a 1>;
  94                                 reg = <0>;
  95                                 device_type = "ethernet-phy";
  96                         };
  97                         phy1: ethernet-phy@1 {
  98                                 interrupt-parent = <&mpic>;
  99                                 interrupts = <4a 1>;
 100                                 reg = <1>;
 101                                 device_type = "ethernet-phy";
 102                         };
 103                         phy2: ethernet-phy@2 {
 104                                 interrupt-parent = <&mpic>;
 105                                 interrupts = <4a 1>;
 106                                 reg = <2>;
 107                                 device_type = "ethernet-phy";
 108                         };
 109                         phy3: ethernet-phy@3 {
 110                                 interrupt-parent = <&mpic>;
 111                                 interrupts = <4a 1>;
 112                                 reg = <3>;
 113                                 device_type = "ethernet-phy";
 114                         };
 115                 };
 116
 117                 ethernet@24000 {
 118                         #address-cells = <1>;
 119                         #size-cells = <0>;
 120                         device_type = "network";
 121                         model = "TSEC";
 122                         compatible = "gianfar";
 123                         reg = <24000 1000>;
 124                         mac-address = [ 00 E0 0C 00 73 00 ];
 125                         interrupts = <1d 2 1e 2 22 2>;
 126                         interrupt-parent = <&mpic>;
 127                         phy-handle = <&phy0>;
 128                 };
 129
 130                 ethernet@25000 {
 131                         #address-cells = <1>;
 132                         #size-cells = <0>;
 133                         device_type = "network";
 134                         model = "TSEC";
 135                         compatible = "gianfar";
 136                         reg = <25000 1000>;
 137                         mac-address = [ 00 E0 0C 00 73 01 ];
 138                         interrupts = <23 2 24 2 28 2>;
 139                         interrupt-parent = <&mpic>;
 140                         phy-handle = <&phy1>;
 141                 };
 142
 143                 ethernet@26000 {
 144                         #address-cells = <1>;
 145                         #size-cells = <0>;
 146                         device_type = "network";
 147                         model = "TSEC";
 148                         compatible = "gianfar";
 149                         reg = <26000 1000>;
 150                         mac-address = [ 00 E0 0C 00 02 FD ];
 151                         interrupts = <1F 2 20 2 21 2>;
 152                         interrupt-parent = <&mpic>;
 153                         phy-handle = <&phy2>;
 154                 };
 155
 156                 ethernet@27000 {
 157                         #address-cells = <1>;
 158                         #size-cells = <0>;
 159                         device_type = "network";
 160                         model = "TSEC";
 161                         compatible = "gianfar";
 162                         reg = <27000 1000>;
 163                         mac-address = [ 00 E0 0C 00 03 FD ];
 164                         interrupts = <25 2 26 2 27 2>;
 165                         interrupt-parent = <&mpic>;
 166                         phy-handle = <&phy3>;
 167                 };
 168                 serial@4500 {
 169                         device_type = "serial";
 170                         compatible = "ns16550";
 171                         reg = <4500 100>;
 172                         clock-frequency = <0>;
 173                         interrupts = <2a 2>;
 174                         interrupt-parent = <&mpic>;
 175                 };
 176
 177                 serial@4600 {
 178                         device_type = "serial";
 179                         compatible = "ns16550";
 180                         reg = <4600 100>;
 181                         clock-frequency = <0>;
 182                         interrupts = <1c 2>;
 183                         interrupt-parent = <&mpic>;
 184                 };
 185
 186                 pci@8000 {
 187                         compatible = "86xx";
 188                         device_type = "pci";
 189                         #interrupt-cells = <1>;
 190                         #size-cells = <2>;
 191                         #address-cells = <3>;
 192                         reg = <8000 1000>;
 193                         bus-range = <0 ff>;
 194                         ranges = <02000000 0 80000000 80000000 0 20000000
 195                                   01000000 0 00000000 e2000000 0 00100000>;
 196                         clock-frequency = <1fca055>;
 197                         interrupt-parent = <&mpic>;
 198                         interrupts = <18 2>;
 199                         interrupt-map-mask = <f800 0 0 7>;
 200                         interrupt-map = <
 201                                 /* IDSEL 0x11 */
 202                                 8800 0 0 1 &i8259 3 2
 203                                 8800 0 0 2 &i8259 4 2
 204                                 8800 0 0 3 &i8259 5 2
 205                                 8800 0 0 4 &i8259 6 2
 206
 207                                 /* IDSEL 0x12 */
 208                                 9000 0 0 1 &i8259 4 2
 209                                 9000 0 0 2 &i8259 5 2
 210                                 9000 0 0 3 &i8259 6 2
 211                                 9000 0 0 4 &i8259 3 2
 212
 213                                 /* IDSEL 0x13 */
 214                                 9800 0 0 1 &i8259 0 0
 215                                 9800 0 0 2 &i8259 0 0
 216                                 9800 0 0 3 &i8259 0 0
 217                                 9800 0 0 4 &i8259 0 0
 218
 219                                 /* IDSEL 0x14 */
 220                                 a000 0 0 1 &i8259 0 0
 221                                 a000 0 0 2 &i8259 0 0
 222                                 a000 0 0 3 &i8259 0 0
 223                                 a000 0 0 4 &i8259 0 0
 224
 225                                 /* IDSEL 0x15 */
 226                                 a800 0 0 1 &i8259 0 0
 227                                 a800 0 0 2 &i8259 0 0
 228                                 a800 0 0 3 &i8259 0 0
 229                                 a800 0 0 4 &i8259 0 0
 230
 231                                 /* IDSEL 0x16 */
 232                                 b000 0 0 1 &i8259 0 0
 233                                 b000 0 0 2 &i8259 0 0
 234                                 b000 0 0 3 &i8259 0 0
 235                                 b000 0 0 4 &i8259 0 0
 236
 237                                 /* IDSEL 0x17 */
 238                                 b800 0 0 1 &i8259 0 0
 239                                 b800 0 0 2 &i8259 0 0
 240                                 b800 0 0 3 &i8259 0 0
 241                                 b800 0 0 4 &i8259 0 0
 242
 243                                 /* IDSEL 0x18 */
 244                                 c000 0 0 1 &i8259 0 0
 245                                 c000 0 0 2 &i8259 0 0
 246                                 c000 0 0 3 &i8259 0 0
 247                                 c000 0 0 4 &i8259 0 0
 248
 249                                 /* IDSEL 0x19 */
 250                                 c800 0 0 1 &i8259 0 0
 251                                 c800 0 0 2 &i8259 0 0
 252                                 c800 0 0 3 &i8259 0 0
 253                                 c800 0 0 4 &i8259 0 0
 254
 255                                 /* IDSEL 0x1a */
 256                                 d000 0 0 1 &i8259 6 2
 257                                 d000 0 0 2 &i8259 3 2
 258                                 d000 0 0 3 &i8259 4 2
 259                                 d000 0 0 4 &i8259 5 2
 260
 261
 262                                 /* IDSEL 0x1b */
 263                                 d800 0 0 1 &i8259 5 2
 264                                 d800 0 0 2 &i8259 0 0
 265                                 d800 0 0 3 &i8259 0 0
 266                                 d800 0 0 4 &i8259 0 0
 267
 268                                 /* IDSEL 0x1c */
 269                                 e000 0 0 1 &i8259 9 2
 270                                 e000 0 0 2 &i8259 a 2
 271                                 e000 0 0 3 &i8259 c 2
 272                                 e000 0 0 4 &i8259 7 2
 273
 274                                 /* IDSEL 0x1d */
 275                                 e800 0 0 1 &i8259 9 2
 276                                 e800 0 0 2 &i8259 a 2
 277                                 e800 0 0 3 &i8259 b 2
 278                                 e800 0 0 4 &i8259 0 0
 279
 280                                 /* IDSEL 0x1e */
 281                                 f000 0 0 1 &i8259 c 2
 282                                 f000 0 0 2 &i8259 0 0
 283                                 f000 0 0 3 &i8259 0 0
 284                                 f000 0 0 4 &i8259 0 0
 285
 286                                 /* IDSEL 0x1f */
 287                                 f800 0 0 1 &i8259 6 2
 288                                 f800 0 0 2 &i8259 0 0
 289                                 f800 0 0 3 &i8259 0 0
 290                                 f800 0 0 4 &i8259 0 0
 291                                 >;
 292                         uli1575@0 {
 293                                 reg = <0 0 0 0 0>;
 294                                 #size-cells = <2>;
 295                                 #address-cells = <3>;
 296                                 ranges = <02000000 0 80000000
 297                                           02000000 0 80000000
 298                                           0 20000000
 299                                           01000000 0 00000000
 300                                           01000000 0 00000000
 301                                           0 00100000>;
 302
 303                                 pci_bridge@0 {
 304                                         reg = <0 0 0 0 0>;
 305                                         #size-cells = <2>;
 306                                         #address-cells = <3>;
 307                                         ranges = <02000000 0 80000000
 308                                                   02000000 0 80000000
 309                                                   0 20000000
 310                                                   01000000 0 00000000
 311                                                   01000000 0 00000000
 312                                                   0 00100000>;
 313
 314                                         isa@1e {
 315                                                 device_type = "isa";
 316                                                 #interrupt-cells = <2>;
 317                                                 #size-cells = <1>;
 318                                                 #address-cells = <2>;
 319                                                 reg = <f000 0 0 0 0>;
 320                                                 ranges = <1 0 01000000 0 0
 321                                                           00001000>;
 322                                                 interrupt-parent = <&i8259>;
 323
 324                                                 i8259: interrupt-controller@20 {
 325                                                         reg = <1 20 2
 326                                                                1 a0 2
 327                                                                1 4d0 2>;
 328                                                         clock-frequency = <0>;
 329                                                         interrupt-controller;
 330                                                         device_type = "interrupt-controller";
 331                                                         #address-cells = <0>;
 332                                                         #interrupt-cells = <2>;
 333                                                         built-in;
 334                                                         compatible = "chrp,iic";
 335                                                         interrupts = <49 2>;
 336                                                         interrupt-parent =
 337                                                                 <&mpic>;
 338                                                 };
 339
 340                                                 i8042@60 {
 341                                                         #size-cells = <0>;
 342                                                         #address-cells = <1>;
 343                                                         reg = <1 60 1 1 64 1>;
 344                                                         interrupts = <1 3 c 3>;
 345                                                         interrupt-parent =
 346                                                                 <&i8259>;
 347
 348                                                         keyboard@0 {
 349                                                                 reg = <0>;
 350                                                                 compatible = "pnpPNP,303";
 351                                                         };
 352
 353                                                         mouse@1 {
 354                                                                 reg = <1>;
 355                                                                 compatible = "pnpPNP,f03";
 356                                                         };
 357                                                 };
 358
 359                                                 rtc@70 {
 360                                                         compatible =
 361                                                                 "pnpPNP,b00";
 362                                                         reg = <1 70 2>;
 363                                                 };
 364
 365                                                 gpio@400 {
 366                                                         reg = <1 400 80>;
 367                                                 };
 368                                         };
 369                                 };
 370                         };
 371
 372                 };
 373
 374                 pci@9000 {
 375                         compatible = "86xx";
 376                         device_type = "pci";
 377                         #interrupt-cells = <1>;
 378                         #size-cells = <2>;
 379                         #address-cells = <3>;
 380                         reg = <9000 1000>;
 381                         bus-range = <0 ff>;
 382                         ranges = <02000000 0 a0000000 a0000000 0 20000000
 383                                   01000000 0 00000000 e3000000 0 00100000>;
 384                         clock-frequency = <1fca055>;
 385                         interrupt-parent = <&mpic>;
 386                         interrupts = <19 2>;
 387                         interrupt-map-mask = <f800 0 0 7>;
 388                         interrupt-map = <
 389                                 /* IDSEL 0x0 */
 390                                 0000 0 0 1 &mpic 44 1
 391                                 0000 0 0 2 &mpic 45 1
 392                                 0000 0 0 3 &mpic 46 1
 393                                 0000 0 0 4 &mpic 47 1
 394                                 >;
 395                 };
 396
 397                 mpic: pic@40000 {
 398                         clock-frequency = <0>;
 399                         interrupt-controller;
 400                         #address-cells = <0>;
 401                         #interrupt-cells = <2>;
 402                         reg = <40000 40000>;
 403                         built-in;
 404                         compatible = "chrp,open-pic";
 405                         device_type = "open-pic";
 406                         big-endian;
 407                 };
 408         };
 409 };