git.oblomov.eu Git - linux-2.6/blob - drivers/video/aty/atyfb_base.c

   1 /*
   2  *  ATI Frame Buffer Device Driver Core
   3  *
   4  *      Copyright (C) 2004  Alex Kern <alex.kern@gmx.de>
   5  *      Copyright (C) 1997-2001  Geert Uytterhoeven
   6  *      Copyright (C) 1998  Bernd Harries
   7  *      Copyright (C) 1998  Eddie C. Dost  (ecd@skynet.be)
   8  *
   9  *  This driver supports the following ATI graphics chips:
  10  *    - ATI Mach64
  11  *
  12  *  To do: add support for
  13  *    - ATI Rage128 (from aty128fb.c)
  14  *    - ATI Radeon (from radeonfb.c)
  15  *
  16  *  This driver is partly based on the PowerMac console driver:
  17  *
  18  *      Copyright (C) 1996 Paul Mackerras
  19  *
  20  *  and on the PowerMac ATI/mach64 display driver:
  21  *
  22  *      Copyright (C) 1997 Michael AK Tesch
  23  *
  24  *            with work by Jon Howell
  25  *                         Harry AC Eaton
  26  *                         Anthony Tong <atong@uiuc.edu>
  27  *
  28  *  Generic LCD support written by Daniel Mantione, ported from 2.4.20 by Alex Kern
  29  *  Many Thanks to Ville Syrjälä for patches and fixing nasting 16 bit color bug.
  30  *
  31  *  This file is subject to the terms and conditions of the GNU General Public
  32  *  License. See the file COPYING in the main directory of this archive for
  33  *  more details.
  34  *
  35  *  Many thanks to Nitya from ATI devrel for support and patience !
  36  */
  37
  38 /******************************************************************************
  39
  40   TODO:
  41
  42     - cursor support on all cards and all ramdacs.
  43     - cursor parameters controlable via ioctl()s.
  44     - guess PLL and MCLK based on the original PLL register values initialized
  45       by Open Firmware (if they are initialized). BIOS is done
  46
  47     (Anyone with Mac to help with this?)
  48
  49 ******************************************************************************/
  50
  51
  52 #include <linux/module.h>
  53 #include <linux/moduleparam.h>
  54 #include <linux/kernel.h>
  55 #include <linux/errno.h>
  56 #include <linux/string.h>
  57 #include <linux/mm.h>
  58 #include <linux/slab.h>
  59 #include <linux/vmalloc.h>
  60 #include <linux/delay.h>
  61 #include <linux/console.h>
  62 #include <linux/fb.h>
  63 #include <linux/init.h>
  64 #include <linux/pci.h>
  65 #include <linux/interrupt.h>
  66 #include <linux/spinlock.h>
  67 #include <linux/wait.h>
  68 #include <linux/backlight.h>
  69
  70 #include <asm/io.h>
  71 #include <asm/uaccess.h>
  72
  73 #include <video/mach64.h>
  74 #include "atyfb.h"
  75 #include "ati_ids.h"
  76
  77 #ifdef __powerpc__
  78 #include <asm/machdep.h>
  79 #include <asm/prom.h>
  80 #include "../macmodes.h"
  81 #endif
  82 #ifdef __sparc__
  83 #include <asm/pbm.h>
  84 #include <asm/fbio.h>
  85 #endif
  86
  87 #ifdef CONFIG_ADB_PMU
  88 #include <linux/adb.h>
  89 #include <linux/pmu.h>
  90 #endif
  91 #ifdef CONFIG_BOOTX_TEXT
  92 #include <asm/btext.h>
  93 #endif
  94 #ifdef CONFIG_PMAC_BACKLIGHT
  95 #include <asm/backlight.h>
  96 #endif
  97 #ifdef CONFIG_MTRR
  98 #include <asm/mtrr.h>
  99 #endif
 100
 101 /*
 102  * Debug flags.
 103  */
 104 #undef DEBUG
 105 /*#define DEBUG*/
 106
 107 /* Make sure n * PAGE_SIZE is protected at end of Aperture for GUI-regs */
 108 /*  - must be large enough to catch all GUI-Regs   */
 109 /*  - must be aligned to a PAGE boundary           */
 110 #define GUI_RESERVE     (1 * PAGE_SIZE)
 111
 112 /* FIXME: remove the FAIL definition */
 113 #define FAIL(msg) do { \
 114         if (!(var->activate & FB_ACTIVATE_TEST)) \
 115                 printk(KERN_CRIT "atyfb: " msg "\n"); \
 116         return -EINVAL; \
 117 } while (0)
 118 #define FAIL_MAX(msg, x, _max_) do { \
 119         if (x > _max_) { \
 120                 if (!(var->activate & FB_ACTIVATE_TEST)) \
 121                         printk(KERN_CRIT "atyfb: " msg " %x(%x)\n", x, _max_); \
 122                 return -EINVAL; \
 123         } \
 124 } while (0)
 125 #ifdef DEBUG
 126 #define DPRINTK(fmt, args...)   printk(KERN_DEBUG "atyfb: " fmt, ## args)
 127 #else
 128 #define DPRINTK(fmt, args...)
 129 #endif
 130
 131 #define PRINTKI(fmt, args...)   printk(KERN_INFO "atyfb: " fmt, ## args)
 132 #define PRINTKE(fmt, args...)    printk(KERN_ERR "atyfb: " fmt, ## args)
 133
 134 #if defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD)
 135 static const u32 lt_lcd_regs[] = {
 136         CONFIG_PANEL_LG,
 137         LCD_GEN_CNTL_LG,
 138         DSTN_CONTROL_LG,
 139         HFB_PITCH_ADDR_LG,
 140         HORZ_STRETCHING_LG,
 141         VERT_STRETCHING_LG,
 142         0, /* EXT_VERT_STRETCH */
 143         LT_GIO_LG,
 144         POWER_MANAGEMENT_LG
 145 };
 146
 147 void aty_st_lcd(int index, u32 val, const struct atyfb_par *par)
 148 {
 149         if (M64_HAS(LT_LCD_REGS)) {
 150                 aty_st_le32(lt_lcd_regs[index], val, par);
 151         } else {
 152                 unsigned long temp;
 153
 154                 /* write addr byte */
 155                 temp = aty_ld_le32(LCD_INDEX, par);
 156                 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
 157                 /* write the register value */
 158                 aty_st_le32(LCD_DATA, val, par);
 159         }
 160 }
 161
 162 u32 aty_ld_lcd(int index, const struct atyfb_par *par)
 163 {
 164         if (M64_HAS(LT_LCD_REGS)) {
 165                 return aty_ld_le32(lt_lcd_regs[index], par);
 166         } else {
 167                 unsigned long temp;
 168
 169                 /* write addr byte */
 170                 temp = aty_ld_le32(LCD_INDEX, par);
 171                 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
 172                 /* read the register value */
 173                 return aty_ld_le32(LCD_DATA, par);
 174         }
 175 }
 176 #endif /* defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD) */
 177
 178 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 179 /*
 180  * ATIReduceRatio --
 181  *
 182  * Reduce a fraction by factoring out the largest common divider of the
 183  * fraction's numerator and denominator.
 184  */
 185 static void ATIReduceRatio(int *Numerator, int *Denominator)
 186 {
 187     int Multiplier, Divider, Remainder;
 188
 189     Multiplier = *Numerator;
 190     Divider = *Denominator;
 191
 192     while ((Remainder = Multiplier % Divider))
 193     {
 194         Multiplier = Divider;
 195         Divider = Remainder;
 196     }
 197
 198     *Numerator /= Divider;
 199     *Denominator /= Divider;
 200 }
 201 #endif
 202     /*
 203      *  The Hardware parameters for each card
 204      */
 205
 206 struct pci_mmap_map {
 207         unsigned long voff;
 208         unsigned long poff;
 209         unsigned long size;
 210         unsigned long prot_flag;
 211         unsigned long prot_mask;
 212 };
 213
 214 static struct fb_fix_screeninfo atyfb_fix __devinitdata = {
 215         .id             = "ATY Mach64",
 216         .type           = FB_TYPE_PACKED_PIXELS,
 217         .visual         = FB_VISUAL_PSEUDOCOLOR,
 218         .xpanstep       = 8,
 219         .ypanstep       = 1,
 220 };
 221
 222     /*
 223      *  Frame buffer device API
 224      */
 225
 226 static int atyfb_open(struct fb_info *info, int user);
 227 static int atyfb_release(struct fb_info *info, int user);
 228 static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info);
 229 static int atyfb_set_par(struct fb_info *info);
 230 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
 231         u_int transp, struct fb_info *info);
 232 static int atyfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info);
 233 static int atyfb_blank(int blank, struct fb_info *info);
 234 static int atyfb_ioctl(struct fb_info *info, u_int cmd, u_long arg);
 235 #ifdef __sparc__
 236 static int atyfb_mmap(struct fb_info *info, struct vm_area_struct *vma);
 237 #endif
 238 static int atyfb_sync(struct fb_info *info);
 239
 240     /*
 241      *  Internal routines
 242      */
 243
 244 static int aty_init(struct fb_info *info);
 245 static void aty_resume_chip(struct fb_info *info);
 246 #ifdef CONFIG_ATARI
 247 static int store_video_par(char *videopar, unsigned char m64_num);
 248 #endif
 249
 250 static struct crtc saved_crtc;
 251 static union aty_pll saved_pll;
 252 static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc);
 253
 254 static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc);
 255 static int aty_var_to_crtc(const struct fb_info *info, const struct fb_var_screeninfo *var, struct crtc *crtc);
 256 static int aty_crtc_to_var(const struct crtc *crtc, struct fb_var_screeninfo *var);
 257 static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info);
 258 #ifdef CONFIG_PPC
 259 static int read_aty_sense(const struct atyfb_par *par);
 260 #endif
 261
 262
 263     /*
 264      *  Interface used by the world
 265      */
 266
 267 static struct fb_var_screeninfo default_var = {
 268         /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
 269         640, 480, 640, 480, 0, 0, 8, 0,
 270         {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
 271         0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
 272         0, FB_VMODE_NONINTERLACED
 273 };
 274
 275 static struct fb_videomode defmode = {
 276         /* 640x480 @ 60 Hz, 31.5 kHz hsync */
 277         NULL, 60, 640, 480, 39721, 40, 24, 32, 11, 96, 2,
 278         0, FB_VMODE_NONINTERLACED
 279 };
 280
 281 static struct fb_ops atyfb_ops = {
 282         .owner          = THIS_MODULE,
 283         .fb_open        = atyfb_open,
 284         .fb_release     = atyfb_release,
 285         .fb_check_var   = atyfb_check_var,
 286         .fb_set_par     = atyfb_set_par,
 287         .fb_setcolreg   = atyfb_setcolreg,
 288         .fb_pan_display = atyfb_pan_display,
 289         .fb_blank       = atyfb_blank,
 290         .fb_ioctl       = atyfb_ioctl,
 291         .fb_fillrect    = atyfb_fillrect,
 292         .fb_copyarea    = atyfb_copyarea,
 293         .fb_imageblit   = atyfb_imageblit,
 294 #ifdef __sparc__
 295         .fb_mmap        = atyfb_mmap,
 296 #endif
 297         .fb_sync        = atyfb_sync,
 298 };
 299
 300 static int noaccel;
 301 #ifdef CONFIG_MTRR
 302 static int nomtrr;
 303 #endif
 304 static int vram;
 305 static int pll;
 306 static int mclk;
 307 static int xclk;
 308 static int comp_sync __devinitdata = -1;
 309 static char *mode;
 310
 311 #ifdef CONFIG_PPC
 312 static int default_vmode __devinitdata = VMODE_CHOOSE;
 313 static int default_cmode __devinitdata = CMODE_CHOOSE;
 314
 315 module_param_named(vmode, default_vmode, int, 0);
 316 MODULE_PARM_DESC(vmode, "int: video mode for mac");
 317 module_param_named(cmode, default_cmode, int, 0);
 318 MODULE_PARM_DESC(cmode, "int: color mode for mac");
 319 #endif
 320
 321 #ifdef CONFIG_ATARI
 322 static unsigned int mach64_count __devinitdata = 0;
 323 static unsigned long phys_vmembase[FB_MAX] __devinitdata = { 0, };
 324 static unsigned long phys_size[FB_MAX] __devinitdata = { 0, };
 325 static unsigned long phys_guiregbase[FB_MAX] __devinitdata = { 0, };
 326 #endif
 327
 328 /* top -> down is an evolution of mach64 chipset, any corrections? */
 329 #define ATI_CHIP_88800GX   (M64F_GX)
 330 #define ATI_CHIP_88800CX   (M64F_GX)
 331
 332 #define ATI_CHIP_264CT     (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
 333 #define ATI_CHIP_264ET     (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
 334
 335 #define ATI_CHIP_264VT     (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_MAGIC_FIFO)
 336 #define ATI_CHIP_264GT     (M64F_GT | M64F_INTEGRATED               | M64F_MAGIC_FIFO | M64F_EXTRA_BRIGHT)
 337
 338 #define ATI_CHIP_264VTB    (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP)
 339 #define ATI_CHIP_264VT3    (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL)
 340 #define ATI_CHIP_264VT4    (M64F_VT | M64F_INTEGRATED               | M64F_GTB_DSP)
 341
 342 /* FIXME what is this chip? */
 343 #define ATI_CHIP_264LT     (M64F_GT | M64F_INTEGRATED               | M64F_GTB_DSP)
 344
 345 /* make sets shorter */
 346 #define ATI_MODERN_SET     (M64F_GT | M64F_INTEGRATED               | M64F_GTB_DSP | M64F_EXTRA_BRIGHT)
 347
 348 #define ATI_CHIP_264GTB    (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
 349 /*#define ATI_CHIP_264GTDVD  ?*/
 350 #define ATI_CHIP_264LTG    (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
 351
 352 #define ATI_CHIP_264GT2C   (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE)
 353 #define ATI_CHIP_264GTPRO  (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
 354 #define ATI_CHIP_264LTPRO  (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
 355
 356 #define ATI_CHIP_264XL     (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4)
 357 #define ATI_CHIP_MOBILITY  (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4 | M64F_MOBIL_BUS)
 358
 359 static struct {
 360         u16 pci_id;
 361         const char *name;
 362         int pll, mclk, xclk, ecp_max;
 363         u32 features;
 364 } aty_chips[] __devinitdata = {
 365 #ifdef CONFIG_FB_ATY_GX
 366         /* Mach64 GX */
 367         { PCI_CHIP_MACH64GX, "ATI888GX00 (Mach64 GX)", 135, 50, 50, 0, ATI_CHIP_88800GX },
 368         { PCI_CHIP_MACH64CX, "ATI888CX00 (Mach64 CX)", 135, 50, 50, 0, ATI_CHIP_88800CX },
 369 #endif /* CONFIG_FB_ATY_GX */
 370
 371 #ifdef CONFIG_FB_ATY_CT
 372         { PCI_CHIP_MACH64CT, "ATI264CT (Mach64 CT)", 135, 60, 60, 0, ATI_CHIP_264CT },
 373         { PCI_CHIP_MACH64ET, "ATI264ET (Mach64 ET)", 135, 60, 60, 0, ATI_CHIP_264ET },
 374
 375         /* FIXME what is this chip? */
 376         { PCI_CHIP_MACH64LT, "ATI264LT (Mach64 LT)", 135, 63, 63, 0, ATI_CHIP_264LT },
 377
 378         { PCI_CHIP_MACH64VT, "ATI264VT (Mach64 VT)", 170, 67, 67, 80, ATI_CHIP_264VT },
 379         { PCI_CHIP_MACH64GT, "3D RAGE (Mach64 GT)", 135, 63, 63, 80, ATI_CHIP_264GT },
 380
 381         { PCI_CHIP_MACH64VU, "ATI264VT3 (Mach64 VU)", 200, 67, 67, 80, ATI_CHIP_264VT3 },
 382         { PCI_CHIP_MACH64GU, "3D RAGE II+ (Mach64 GU)", 200, 67, 67, 100, ATI_CHIP_264GTB },
 383
 384         { PCI_CHIP_MACH64LG, "3D RAGE LT (Mach64 LG)", 230, 63, 63, 100, ATI_CHIP_264LTG | M64F_LT_LCD_REGS | M64F_G3_PB_1024x768 },
 385
 386         { PCI_CHIP_MACH64VV, "ATI264VT4 (Mach64 VV)", 230, 83, 83, 100, ATI_CHIP_264VT4 },
 387
 388         { PCI_CHIP_MACH64GV, "3D RAGE IIC (Mach64 GV, PCI)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
 389         { PCI_CHIP_MACH64GW, "3D RAGE IIC (Mach64 GW, AGP)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
 390         { PCI_CHIP_MACH64GY, "3D RAGE IIC (Mach64 GY, PCI)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
 391         { PCI_CHIP_MACH64GZ, "3D RAGE IIC (Mach64 GZ, AGP)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
 392
 393         { PCI_CHIP_MACH64GB, "3D RAGE PRO (Mach64 GB, BGA, AGP)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
 394         { PCI_CHIP_MACH64GD, "3D RAGE PRO (Mach64 GD, BGA, AGP 1x)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
 395         { PCI_CHIP_MACH64GI, "3D RAGE PRO (Mach64 GI, BGA, PCI)", 230, 100, 100, 125, ATI_CHIP_264GTPRO | M64F_MAGIC_VRAM_SIZE },
 396         { PCI_CHIP_MACH64GP, "3D RAGE PRO (Mach64 GP, PQFP, PCI)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
 397         { PCI_CHIP_MACH64GQ, "3D RAGE PRO (Mach64 GQ, PQFP, PCI, limited 3D)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
 398
 399         { PCI_CHIP_MACH64LB, "3D RAGE LT PRO (Mach64 LB, AGP)", 236, 75, 100, 135, ATI_CHIP_264LTPRO },
 400         { PCI_CHIP_MACH64LD, "3D RAGE LT PRO (Mach64 LD, AGP)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
 401         { PCI_CHIP_MACH64LI, "3D RAGE LT PRO (Mach64 LI, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO | M64F_G3_PB_1_1 | M64F_G3_PB_1024x768 },
 402         { PCI_CHIP_MACH64LP, "3D RAGE LT PRO (Mach64 LP, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO | M64F_G3_PB_1024x768 },
 403         { PCI_CHIP_MACH64LQ, "3D RAGE LT PRO (Mach64 LQ, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
 404
 405         { PCI_CHIP_MACH64GM, "3D RAGE XL (Mach64 GM, AGP 2x)", 230, 83, 63, 135, ATI_CHIP_264XL },
 406         { PCI_CHIP_MACH64GN, "3D RAGE XC (Mach64 GN, AGP 2x)", 230, 83, 63, 135, ATI_CHIP_264XL },
 407         { PCI_CHIP_MACH64GO, "3D RAGE XL (Mach64 GO, PCI-66)", 230, 83, 63, 135, ATI_CHIP_264XL },
 408         { PCI_CHIP_MACH64GL, "3D RAGE XC (Mach64 GL, PCI-66)", 230, 83, 63, 135, ATI_CHIP_264XL },
 409         { PCI_CHIP_MACH64GR, "3D RAGE XL (Mach64 GR, PCI-33)", 230, 83, 63, 135, ATI_CHIP_264XL | M64F_SDRAM_MAGIC_PLL },
 410         { PCI_CHIP_MACH64GS, "3D RAGE XC (Mach64 GS, PCI-33)", 230, 83, 63, 135, ATI_CHIP_264XL },
 411
 412         { PCI_CHIP_MACH64LM, "3D RAGE Mobility P/M (Mach64 LM, AGP 2x)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
 413         { PCI_CHIP_MACH64LN, "3D RAGE Mobility L (Mach64 LN, AGP 2x)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
 414         { PCI_CHIP_MACH64LR, "3D RAGE Mobility P/M (Mach64 LR, PCI)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
 415         { PCI_CHIP_MACH64LS, "3D RAGE Mobility L (Mach64 LS, PCI)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
 416 #endif /* CONFIG_FB_ATY_CT */
 417 };
 418
 419 /* can not fail */
 420 static int __devinit correct_chipset(struct atyfb_par *par)
 421 {
 422         u8 rev;
 423         u16 type;
 424         u32 chip_id;
 425         const char *name;
 426         int i;
 427
 428         for (i = ARRAY_SIZE(aty_chips) - 1; i >= 0; i--)
 429                 if (par->pci_id == aty_chips[i].pci_id)
 430                         break;
 431
 432         name = aty_chips[i].name;
 433         par->pll_limits.pll_max = aty_chips[i].pll;
 434         par->pll_limits.mclk = aty_chips[i].mclk;
 435         par->pll_limits.xclk = aty_chips[i].xclk;
 436         par->pll_limits.ecp_max = aty_chips[i].ecp_max;
 437         par->features = aty_chips[i].features;
 438
 439         chip_id = aty_ld_le32(CONFIG_CHIP_ID, par);
 440         type = chip_id & CFG_CHIP_TYPE;
 441         rev = (chip_id & CFG_CHIP_REV) >> 24;
 442
 443         switch(par->pci_id) {
 444 #ifdef CONFIG_FB_ATY_GX
 445         case PCI_CHIP_MACH64GX:
 446                 if(type != 0x00d7)
 447                         return -ENODEV;
 448                 break;
 449         case PCI_CHIP_MACH64CX:
 450                 if(type != 0x0057)
 451                         return -ENODEV;
 452                 break;
 453 #endif
 454 #ifdef CONFIG_FB_ATY_CT
 455         case PCI_CHIP_MACH64VT:
 456                 switch (rev & 0x07) {
 457                 case 0x00:
 458                         switch (rev & 0xc0) {
 459                         case 0x00:
 460                                 name = "ATI264VT (A3) (Mach64 VT)";
 461                                 par->pll_limits.pll_max = 170;
 462                                 par->pll_limits.mclk = 67;
 463                                 par->pll_limits.xclk = 67;
 464                                 par->pll_limits.ecp_max = 80;
 465                                 par->features = ATI_CHIP_264VT;
 466                                 break;
 467                         case 0x40:
 468                                 name = "ATI264VT2 (A4) (Mach64 VT)";
 469                                 par->pll_limits.pll_max = 200;
 470                                 par->pll_limits.mclk = 67;
 471                                 par->pll_limits.xclk = 67;
 472                                 par->pll_limits.ecp_max = 80;
 473                                 par->features = ATI_CHIP_264VT | M64F_MAGIC_POSTDIV;
 474                                 break;
 475                         }
 476                         break;
 477                 case 0x01:
 478                         name = "ATI264VT3 (B1) (Mach64 VT)";
 479                         par->pll_limits.pll_max = 200;
 480                         par->pll_limits.mclk = 67;
 481                         par->pll_limits.xclk = 67;
 482                         par->pll_limits.ecp_max = 80;
 483                         par->features = ATI_CHIP_264VTB;
 484                         break;
 485                 case 0x02:
 486                         name = "ATI264VT3 (B2) (Mach64 VT)";
 487                         par->pll_limits.pll_max = 200;
 488                         par->pll_limits.mclk = 67;
 489                         par->pll_limits.xclk = 67;
 490                         par->pll_limits.ecp_max = 80;
 491                         par->features = ATI_CHIP_264VT3;
 492                         break;
 493                 }
 494                 break;
 495         case PCI_CHIP_MACH64GT:
 496                 switch (rev & 0x07) {
 497                 case 0x01:
 498                         name = "3D RAGE II (Mach64 GT)";
 499                         par->pll_limits.pll_max = 170;
 500                         par->pll_limits.mclk = 67;
 501                         par->pll_limits.xclk = 67;
 502                         par->pll_limits.ecp_max = 80;
 503                         par->features = ATI_CHIP_264GTB;
 504                         break;
 505                 case 0x02:
 506                         name = "3D RAGE II+ (Mach64 GT)";
 507                         par->pll_limits.pll_max = 200;
 508                         par->pll_limits.mclk = 67;
 509                         par->pll_limits.xclk = 67;
 510                         par->pll_limits.ecp_max = 100;
 511                         par->features = ATI_CHIP_264GTB;
 512                         break;
 513                 }
 514                 break;
 515 #endif
 516         }
 517
 518         PRINTKI("%s [0x%04x rev 0x%02x]\n", name, type, rev);
 519         return 0;
 520 }
 521
 522 static char ram_dram[] __devinitdata = "DRAM";
 523 static char ram_resv[] __devinitdata = "RESV";
 524 #ifdef CONFIG_FB_ATY_GX
 525 static char ram_vram[] __devinitdata = "VRAM";
 526 #endif /* CONFIG_FB_ATY_GX */
 527 #ifdef CONFIG_FB_ATY_CT
 528 static char ram_edo[] __devinitdata = "EDO";
 529 static char ram_sdram[] __devinitdata = "SDRAM (1:1)";
 530 static char ram_sgram[] __devinitdata = "SGRAM (1:1)";
 531 static char ram_sdram32[] __devinitdata = "SDRAM (2:1) (32-bit)";
 532 static char ram_off[] __devinitdata = "OFF";
 533 #endif /* CONFIG_FB_ATY_CT */
 534
 535
 536 static u32 pseudo_palette[17];
 537
 538 #ifdef CONFIG_FB_ATY_GX
 539 static char *aty_gx_ram[8] __devinitdata = {
 540         ram_dram, ram_vram, ram_vram, ram_dram,
 541         ram_dram, ram_vram, ram_vram, ram_resv
 542 };
 543 #endif /* CONFIG_FB_ATY_GX */
 544
 545 #ifdef CONFIG_FB_ATY_CT
 546 static char *aty_ct_ram[8] __devinitdata = {
 547         ram_off, ram_dram, ram_edo, ram_edo,
 548         ram_sdram, ram_sgram, ram_sdram32, ram_resv
 549 };
 550 #endif /* CONFIG_FB_ATY_CT */
 551
 552 static u32 atyfb_get_pixclock(struct fb_var_screeninfo *var, struct atyfb_par *par)
 553 {
 554         u32 pixclock = var->pixclock;
 555 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 556         u32 lcd_on_off;
 557         par->pll.ct.xres = 0;
 558         if (par->lcd_table != 0) {
 559                 lcd_on_off = aty_ld_lcd(LCD_GEN_CNTL, par);
 560                 if(lcd_on_off & LCD_ON) {
 561                         par->pll.ct.xres = var->xres;
 562                         pixclock = par->lcd_pixclock;
 563                 }
 564         }
 565 #endif
 566         return pixclock;
 567 }
 568
 569 #if defined(CONFIG_PPC)
 570
 571 /*
 572  *  Apple monitor sense
 573  */
 574
 575 static int __devinit read_aty_sense(const struct atyfb_par *par)
 576 {
 577         int sense, i;
 578
 579         aty_st_le32(GP_IO, 0x31003100, par); /* drive outputs high */
 580         __delay(200);
 581         aty_st_le32(GP_IO, 0, par); /* turn off outputs */
 582         __delay(2000);
 583         i = aty_ld_le32(GP_IO, par); /* get primary sense value */
 584         sense = ((i & 0x3000) >> 3) | (i & 0x100);
 585
 586         /* drive each sense line low in turn and collect the other 2 */
 587         aty_st_le32(GP_IO, 0x20000000, par); /* drive A low */
 588         __delay(2000);
 589         i = aty_ld_le32(GP_IO, par);
 590         sense |= ((i & 0x1000) >> 7) | ((i & 0x100) >> 4);
 591         aty_st_le32(GP_IO, 0x20002000, par); /* drive A high again */
 592         __delay(200);
 593
 594         aty_st_le32(GP_IO, 0x10000000, par); /* drive B low */
 595         __delay(2000);
 596         i = aty_ld_le32(GP_IO, par);
 597         sense |= ((i & 0x2000) >> 10) | ((i & 0x100) >> 6);
 598         aty_st_le32(GP_IO, 0x10001000, par); /* drive B high again */
 599         __delay(200);
 600
 601         aty_st_le32(GP_IO, 0x01000000, par); /* drive C low */
 602         __delay(2000);
 603         sense |= (aty_ld_le32(GP_IO, par) & 0x3000) >> 12;
 604         aty_st_le32(GP_IO, 0, par); /* turn off outputs */
 605         return sense;
 606 }
 607
 608 #endif /* defined(CONFIG_PPC) */
 609
 610 /* ------------------------------------------------------------------------- */
 611
 612 /*
 613  *  CRTC programming
 614  */
 615
 616 static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc)
 617 {
 618 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 619         if (par->lcd_table != 0) {
 620                 if(!M64_HAS(LT_LCD_REGS)) {
 621                     crtc->lcd_index = aty_ld_le32(LCD_INDEX, par);
 622                     aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
 623                 }
 624                 crtc->lcd_config_panel = aty_ld_lcd(CONFIG_PANEL, par);
 625                 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par);
 626
 627
 628                 /* switch to non shadow registers */
 629                 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
 630                     ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
 631
 632                 /* save stretching */
 633                 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
 634                 crtc->vert_stretching = aty_ld_lcd(VERT_STRETCHING, par);
 635                 if (!M64_HAS(LT_LCD_REGS))
 636                         crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par);
 637         }
 638 #endif
 639         crtc->h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
 640         crtc->h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
 641         crtc->v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
 642         crtc->v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
 643         crtc->vline_crnt_vline = aty_ld_le32(CRTC_VLINE_CRNT_VLINE, par);
 644         crtc->off_pitch = aty_ld_le32(CRTC_OFF_PITCH, par);
 645         crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
 646
 647 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 648         if (par->lcd_table != 0) {
 649                 /* switch to shadow registers */
 650                 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
 651                         SHADOW_EN | SHADOW_RW_EN, par);
 652
 653                 crtc->shadow_h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
 654                 crtc->shadow_h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
 655                 crtc->shadow_v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
 656                 crtc->shadow_v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
 657
 658                 aty_st_le32(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
 659         }
 660 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
 661 }
 662
 663 static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc)
 664 {
 665 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 666         if (par->lcd_table != 0) {
 667                 /* stop CRTC */
 668                 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~(CRTC_EXT_DISP_EN | CRTC_EN), par);
 669
 670                 /* update non-shadow registers first */
 671                 aty_st_lcd(CONFIG_PANEL, crtc->lcd_config_panel, par);
 672                 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
 673                         ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
 674
 675                 /* temporarily disable stretching */
 676                 aty_st_lcd(HORZ_STRETCHING,
 677                         crtc->horz_stretching &
 678                         ~(HORZ_STRETCH_MODE | HORZ_STRETCH_EN), par);
 679                 aty_st_lcd(VERT_STRETCHING,
 680                         crtc->vert_stretching &
 681                         ~(VERT_STRETCH_RATIO1 | VERT_STRETCH_RATIO2 |
 682                         VERT_STRETCH_USE0 | VERT_STRETCH_EN), par);
 683         }
 684 #endif
 685         /* turn off CRT */
 686         aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~CRTC_EN, par);
 687
 688         DPRINTK("setting up CRTC\n");
 689         DPRINTK("set primary CRT to %ix%i %c%c composite %c\n",
 690             ((((crtc->h_tot_disp>>16) & 0xff) + 1)<<3), (((crtc->v_tot_disp>>16) & 0x7ff) + 1),
 691             (crtc->h_sync_strt_wid & 0x200000)?'N':'P', (crtc->v_sync_strt_wid & 0x200000)?'N':'P',
 692             (crtc->gen_cntl & CRTC_CSYNC_EN)?'P':'N');
 693
 694         DPRINTK("CRTC_H_TOTAL_DISP: %x\n",crtc->h_tot_disp);
 695         DPRINTK("CRTC_H_SYNC_STRT_WID: %x\n",crtc->h_sync_strt_wid);
 696         DPRINTK("CRTC_V_TOTAL_DISP: %x\n",crtc->v_tot_disp);
 697         DPRINTK("CRTC_V_SYNC_STRT_WID: %x\n",crtc->v_sync_strt_wid);
 698         DPRINTK("CRTC_OFF_PITCH: %x\n", crtc->off_pitch);
 699         DPRINTK("CRTC_VLINE_CRNT_VLINE: %x\n", crtc->vline_crnt_vline);
 700         DPRINTK("CRTC_GEN_CNTL: %x\n",crtc->gen_cntl);
 701
 702         aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_tot_disp, par);
 703         aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid, par);
 704         aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_tot_disp, par);
 705         aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid, par);
 706         aty_st_le32(CRTC_OFF_PITCH, crtc->off_pitch, par);
 707         aty_st_le32(CRTC_VLINE_CRNT_VLINE, crtc->vline_crnt_vline, par);
 708
 709         aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl, par);
 710 #if 0
 711         FIXME
 712         if (par->accel_flags & FB_ACCELF_TEXT)
 713                 aty_init_engine(par, info);
 714 #endif
 715 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 716         /* after setting the CRTC registers we should set the LCD registers. */
 717         if (par->lcd_table != 0) {
 718                 /* switch to shadow registers */
 719                 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
 720                         (SHADOW_EN | SHADOW_RW_EN), par);
 721
 722                 DPRINTK("set shadow CRT to %ix%i %c%c\n",
 723                     ((((crtc->shadow_h_tot_disp>>16) & 0xff) + 1)<<3), (((crtc->shadow_v_tot_disp>>16) & 0x7ff) + 1),
 724                     (crtc->shadow_h_sync_strt_wid & 0x200000)?'N':'P', (crtc->shadow_v_sync_strt_wid & 0x200000)?'N':'P');
 725
 726                 DPRINTK("SHADOW CRTC_H_TOTAL_DISP: %x\n", crtc->shadow_h_tot_disp);
 727                 DPRINTK("SHADOW CRTC_H_SYNC_STRT_WID: %x\n", crtc->shadow_h_sync_strt_wid);
 728                 DPRINTK("SHADOW CRTC_V_TOTAL_DISP: %x\n", crtc->shadow_v_tot_disp);
 729                 DPRINTK("SHADOW CRTC_V_SYNC_STRT_WID: %x\n", crtc->shadow_v_sync_strt_wid);
 730
 731                 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->shadow_h_tot_disp, par);
 732                 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->shadow_h_sync_strt_wid, par);
 733                 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->shadow_v_tot_disp, par);
 734                 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->shadow_v_sync_strt_wid, par);
 735
 736                 /* restore CRTC selection & shadow state and enable stretching */
 737                 DPRINTK("LCD_GEN_CNTL: %x\n", crtc->lcd_gen_cntl);
 738                 DPRINTK("HORZ_STRETCHING: %x\n", crtc->horz_stretching);
 739                 DPRINTK("VERT_STRETCHING: %x\n", crtc->vert_stretching);
 740                 if(!M64_HAS(LT_LCD_REGS))
 741                     DPRINTK("EXT_VERT_STRETCH: %x\n", crtc->ext_vert_stretch);
 742
 743                 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
 744                 aty_st_lcd(HORZ_STRETCHING, crtc->horz_stretching, par);
 745                 aty_st_lcd(VERT_STRETCHING, crtc->vert_stretching, par);
 746                 if(!M64_HAS(LT_LCD_REGS)) {
 747                     aty_st_lcd(EXT_VERT_STRETCH, crtc->ext_vert_stretch, par);
 748                     aty_ld_le32(LCD_INDEX, par);
 749                     aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
 750                 }
 751         }
 752 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
 753 }
 754
 755 static int aty_var_to_crtc(const struct fb_info *info,
 756         const struct fb_var_screeninfo *var, struct crtc *crtc)
 757 {
 758         struct atyfb_par *par = (struct atyfb_par *) info->par;
 759         u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp;
 760         u32 sync, vmode, vdisplay;
 761         u32 h_total, h_disp, h_sync_strt, h_sync_end, h_sync_dly, h_sync_wid, h_sync_pol;
 762         u32 v_total, v_disp, v_sync_strt, v_sync_end, v_sync_wid, v_sync_pol, c_sync;
 763         u32 pix_width, dp_pix_width, dp_chain_mask;
 764
 765         /* input */
 766         xres = var->xres;
 767         yres = var->yres;
 768         vxres = var->xres_virtual;
 769         vyres = var->yres_virtual;
 770         xoffset = var->xoffset;
 771         yoffset = var->yoffset;
 772         bpp = var->bits_per_pixel;
 773         if (bpp == 16)
 774                 bpp = (var->green.length == 5) ? 15 : 16;
 775         sync = var->sync;
 776         vmode = var->vmode;
 777
 778         /* convert (and round up) and validate */
 779         if (vxres < xres + xoffset)
 780                 vxres = xres + xoffset;
 781         h_disp = xres;
 782
 783         if (vyres < yres + yoffset)
 784                 vyres = yres + yoffset;
 785         v_disp = yres;
 786
 787         if (bpp <= 8) {
 788                 bpp = 8;
 789                 pix_width = CRTC_PIX_WIDTH_8BPP;
 790                 dp_pix_width =
 791                     HOST_8BPP | SRC_8BPP | DST_8BPP |
 792                     BYTE_ORDER_LSB_TO_MSB;
 793                 dp_chain_mask = DP_CHAIN_8BPP;
 794         } else if (bpp <= 15) {
 795                 bpp = 16;
 796                 pix_width = CRTC_PIX_WIDTH_15BPP;
 797                 dp_pix_width = HOST_15BPP | SRC_15BPP | DST_15BPP |
 798                     BYTE_ORDER_LSB_TO_MSB;
 799                 dp_chain_mask = DP_CHAIN_15BPP;
 800         } else if (bpp <= 16) {
 801                 bpp = 16;
 802                 pix_width = CRTC_PIX_WIDTH_16BPP;
 803                 dp_pix_width = HOST_16BPP | SRC_16BPP | DST_16BPP |
 804                     BYTE_ORDER_LSB_TO_MSB;
 805                 dp_chain_mask = DP_CHAIN_16BPP;
 806         } else if (bpp <= 24 && M64_HAS(INTEGRATED)) {
 807                 bpp = 24;
 808                 pix_width = CRTC_PIX_WIDTH_24BPP;
 809                 dp_pix_width =
 810                     HOST_8BPP | SRC_8BPP | DST_8BPP |
 811                     BYTE_ORDER_LSB_TO_MSB;
 812                 dp_chain_mask = DP_CHAIN_24BPP;
 813         } else if (bpp <= 32) {
 814                 bpp = 32;
 815                 pix_width = CRTC_PIX_WIDTH_32BPP;
 816                 dp_pix_width = HOST_32BPP | SRC_32BPP | DST_32BPP |
 817                     BYTE_ORDER_LSB_TO_MSB;
 818                 dp_chain_mask = DP_CHAIN_32BPP;
 819         } else
 820                 FAIL("invalid bpp");
 821
 822         if (vxres * vyres * bpp / 8 > info->fix.smem_len)
 823                 FAIL("not enough video RAM");
 824
 825         h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
 826         v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
 827
 828         if((xres > 1600) || (yres > 1200)) {
 829                 FAIL("MACH64 chips are designed for max 1600x1200\n"
 830                 "select anoter resolution.");
 831         }
 832         h_sync_strt = h_disp + var->right_margin;
 833         h_sync_end = h_sync_strt + var->hsync_len;
 834         h_sync_dly  = var->right_margin & 7;
 835         h_total = h_sync_end + h_sync_dly + var->left_margin;
 836
 837         v_sync_strt = v_disp + var->lower_margin;
 838         v_sync_end = v_sync_strt + var->vsync_len;
 839         v_total = v_sync_end + var->upper_margin;
 840
 841 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 842         if (par->lcd_table != 0) {
 843                 if(!M64_HAS(LT_LCD_REGS)) {
 844                     u32 lcd_index = aty_ld_le32(LCD_INDEX, par);
 845                     crtc->lcd_index = lcd_index &
 846                         ~(LCD_INDEX_MASK | LCD_DISPLAY_DIS | LCD_SRC_SEL | CRTC2_DISPLAY_DIS);
 847                     aty_st_le32(LCD_INDEX, lcd_index, par);
 848                 }
 849
 850                 if (!M64_HAS(MOBIL_BUS))
 851                         crtc->lcd_index |= CRTC2_DISPLAY_DIS;
 852
 853                 crtc->lcd_config_panel = aty_ld_lcd(CONFIG_PANEL, par) | 0x4000;
 854                 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par) & ~CRTC_RW_SELECT;
 855
 856                 crtc->lcd_gen_cntl &=
 857                         ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 | TVCLK_PM_EN |
 858                         /*VCLK_DAC_PM_EN | USE_SHADOWED_VEND |*/
 859                         USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN);
 860                 crtc->lcd_gen_cntl |= DONT_SHADOW_VPAR | LOCK_8DOT;
 861
 862                 if((crtc->lcd_gen_cntl & LCD_ON) &&
 863                         ((xres > par->lcd_width) || (yres > par->lcd_height))) {
 864                         /* We cannot display the mode on the LCD. If the CRT is enabled
 865                            we can turn off the LCD.
 866                            If the CRT is off, it isn't a good idea to switch it on; we don't
 867                            know if one is connected. So it's better to fail then.
 868                          */
 869                         if (crtc->lcd_gen_cntl & CRT_ON) {
 870                                 if (!(var->activate & FB_ACTIVATE_TEST))
 871                                         PRINTKI("Disable LCD panel, because video mode does not fit.\n");
 872                                 crtc->lcd_gen_cntl &= ~LCD_ON;
 873                                 /*aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);*/
 874                         } else {
 875                                 if (!(var->activate & FB_ACTIVATE_TEST))
 876                                         PRINTKE("Video mode exceeds size of LCD panel.\nConnect this computer to a conventional monitor if you really need this mode.\n");
 877                                 return -EINVAL;
 878                         }
 879                 }
 880         }
 881
 882         if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON)) {
 883                 int VScan = 1;
 884                 /* bpp -> bytespp, 1,4 -> 0; 8 -> 2; 15,16 -> 1; 24 -> 6; 32 -> 5
 885                 const u8 DFP_h_sync_dly_LT[] = { 0, 2, 1, 6, 5 };
 886                 const u8 ADD_to_strt_wid_and_dly_LT_DAC[] = { 0, 5, 6, 9, 9, 12, 12 };  */
 887
 888                 vmode &= ~(FB_VMODE_DOUBLE | FB_VMODE_INTERLACED);
 889
 890                 /* This is horror! When we simulate, say 640x480 on an 800x600
 891                    LCD monitor, the CRTC should be programmed 800x600 values for
 892                    the non visible part, but 640x480 for the visible part.
 893                    This code has been tested on a laptop with it's 1400x1050 LCD
 894                    monitor and a conventional monitor both switched on.
 895                    Tested modes: 1280x1024, 1152x864, 1024x768, 800x600,
 896                     works with little glitches also with DOUBLESCAN modes
 897                  */
 898                 if (yres < par->lcd_height) {
 899                         VScan = par->lcd_height / yres;
 900                         if(VScan > 1) {
 901                                 VScan = 2;
 902                                 vmode |= FB_VMODE_DOUBLE;
 903                         }
 904                 }
 905
 906                 h_sync_strt = h_disp + par->lcd_right_margin;
 907                 h_sync_end = h_sync_strt + par->lcd_hsync_len;
 908                 h_sync_dly = /*DFP_h_sync_dly[ ( bpp + 1 ) / 3 ]; */par->lcd_hsync_dly;
 909                 h_total = h_disp + par->lcd_hblank_len;
 910
 911                 v_sync_strt = v_disp + par->lcd_lower_margin / VScan;
 912                 v_sync_end = v_sync_strt + par->lcd_vsync_len / VScan;
 913                 v_total = v_disp + par->lcd_vblank_len / VScan;
 914         }
 915 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
 916
 917         h_disp = (h_disp >> 3) - 1;
 918         h_sync_strt = (h_sync_strt >> 3) - 1;
 919         h_sync_end = (h_sync_end >> 3) - 1;
 920         h_total = (h_total >> 3) - 1;
 921         h_sync_wid = h_sync_end - h_sync_strt;
 922
 923         FAIL_MAX("h_disp too large", h_disp, 0xff);
 924         FAIL_MAX("h_sync_strt too large", h_sync_strt, 0x1ff);
 925         /*FAIL_MAX("h_sync_wid too large", h_sync_wid, 0x1f);*/
 926         if(h_sync_wid > 0x1f)
 927                 h_sync_wid = 0x1f;
 928         FAIL_MAX("h_total too large", h_total, 0x1ff);
 929
 930         if (vmode & FB_VMODE_DOUBLE) {
 931                 v_disp <<= 1;
 932                 v_sync_strt <<= 1;
 933                 v_sync_end <<= 1;
 934                 v_total <<= 1;
 935         }
 936
 937         vdisplay = yres;
 938 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 939         if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON))
 940                 vdisplay  = par->lcd_height;
 941 #endif
 942
 943         v_disp--;
 944         v_sync_strt--;
 945         v_sync_end--;
 946         v_total--;
 947         v_sync_wid = v_sync_end - v_sync_strt;
 948
 949         FAIL_MAX("v_disp too large", v_disp, 0x7ff);
 950         FAIL_MAX("v_sync_stsrt too large", v_sync_strt, 0x7ff);
 951         /*FAIL_MAX("v_sync_wid too large", v_sync_wid, 0x1f);*/
 952         if(v_sync_wid > 0x1f)
 953                 v_sync_wid = 0x1f;
 954         FAIL_MAX("v_total too large", v_total, 0x7ff);
 955
 956         c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? CRTC_CSYNC_EN : 0;
 957
 958         /* output */
 959         crtc->vxres = vxres;
 960         crtc->vyres = vyres;
 961         crtc->xoffset = xoffset;
 962         crtc->yoffset = yoffset;
 963         crtc->bpp = bpp;
 964         crtc->off_pitch = ((yoffset*vxres+xoffset)*bpp/64) | (vxres<<19);
 965         crtc->vline_crnt_vline = 0;
 966
 967         crtc->h_tot_disp = h_total | (h_disp<<16);
 968         crtc->h_sync_strt_wid = (h_sync_strt & 0xff) | (h_sync_dly<<8) |
 969                 ((h_sync_strt & 0x100)<<4) | (h_sync_wid<<16) | (h_sync_pol<<21);
 970         crtc->v_tot_disp = v_total | (v_disp<<16);
 971         crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid<<16) | (v_sync_pol<<21);
 972
 973         /* crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_PRESERVED_MASK; */
 974         crtc->gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN | pix_width | c_sync;
 975         crtc->gen_cntl |= CRTC_VGA_LINEAR;
 976
 977         /* Enable doublescan mode if requested */
 978         if (vmode & FB_VMODE_DOUBLE)
 979                 crtc->gen_cntl |= CRTC_DBL_SCAN_EN;
 980         /* Enable interlaced mode if requested */
 981         if (vmode & FB_VMODE_INTERLACED)
 982                 crtc->gen_cntl |= CRTC_INTERLACE_EN;
 983 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 984         if (par->lcd_table != 0) {
 985                 vdisplay = yres;
 986                 if(vmode & FB_VMODE_DOUBLE)
 987                         vdisplay <<= 1;
 988                 crtc->gen_cntl &= ~(CRTC2_EN | CRTC2_PIX_WIDTH);
 989                 crtc->lcd_gen_cntl &= ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 |
 990                         /*TVCLK_PM_EN | VCLK_DAC_PM_EN |*/
 991                         USE_SHADOWED_VEND | USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN);
 992                 crtc->lcd_gen_cntl |= (DONT_SHADOW_VPAR/* | LOCK_8DOT*/);
 993
 994                 /* MOBILITY M1 tested, FIXME: LT */
 995                 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
 996                 if (!M64_HAS(LT_LCD_REGS))
 997                         crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par) &
 998                                 ~(AUTO_VERT_RATIO | VERT_STRETCH_MODE | VERT_STRETCH_RATIO3);
 999
1000                 crtc->horz_stretching &=
1001                         ~(HORZ_STRETCH_RATIO | HORZ_STRETCH_LOOP | AUTO_HORZ_RATIO |
1002                         HORZ_STRETCH_MODE | HORZ_STRETCH_EN);
1003                 if (xres < par->lcd_width && crtc->lcd_gen_cntl & LCD_ON) {
1004                         do {
1005                                 /*
1006                                 * The horizontal blender misbehaves when HDisplay is less than a
1007                                 * a certain threshold (440 for a 1024-wide panel).  It doesn't
1008                                 * stretch such modes enough.  Use pixel replication instead of
1009                                 * blending to stretch modes that can be made to exactly fit the
1010                                 * panel width.  The undocumented "NoLCDBlend" option allows the
1011                                 * pixel-replicated mode to be slightly wider or narrower than the
1012                                 * panel width.  It also causes a mode that is exactly half as wide
1013                                 * as the panel to be pixel-replicated, rather than blended.
1014                                 */
1015                                 int HDisplay  = xres & ~7;
1016                                 int nStretch  = par->lcd_width / HDisplay;
1017                                 int Remainder = par->lcd_width % HDisplay;
1018
1019                                 if ((!Remainder && ((nStretch > 2))) ||
1020                                         (((HDisplay * 16) / par->lcd_width) < 7)) {
1021                                         static const char StretchLoops[] = {10, 12, 13, 15, 16};
1022                                         int horz_stretch_loop = -1, BestRemainder;
1023                                         int Numerator = HDisplay, Denominator = par->lcd_width;
1024                                         int Index = 5;
1025                                         ATIReduceRatio(&Numerator, &Denominator);
1026
1027                                         BestRemainder = (Numerator * 16) / Denominator;
1028                                         while (--Index >= 0) {
1029                                                 Remainder = ((Denominator - Numerator) * StretchLoops[Index]) %
1030                                                         Denominator;
1031                                                 if (Remainder < BestRemainder) {
1032                                                         horz_stretch_loop = Index;
1033                                                         if (!(BestRemainder = Remainder))
1034                                                                 break;
1035                                                 }
1036                                         }
1037
1038                                         if ((horz_stretch_loop >= 0) && !BestRemainder) {
1039                                                 int horz_stretch_ratio = 0, Accumulator = 0;
1040                                                 int reuse_previous = 1;
1041
1042                                                 Index = StretchLoops[horz_stretch_loop];
1043
1044                                                 while (--Index >= 0) {
1045                                                         if (Accumulator > 0)
1046                                                                 horz_stretch_ratio |= reuse_previous;
1047                                                         else
1048                                                                 Accumulator += Denominator;
1049                                                         Accumulator -= Numerator;
1050                                                         reuse_previous <<= 1;
1051                                                 }
1052
1053                                                 crtc->horz_stretching |= (HORZ_STRETCH_EN |
1054                                                         ((horz_stretch_loop & HORZ_STRETCH_LOOP) << 16) |
1055                                                         (horz_stretch_ratio & HORZ_STRETCH_RATIO));
1056                                                 break;      /* Out of the do { ... } while (0) */
1057                                         }
1058                                 }
1059
1060                                 crtc->horz_stretching |= (HORZ_STRETCH_MODE | HORZ_STRETCH_EN |
1061                                         (((HDisplay * (HORZ_STRETCH_BLEND + 1)) / par->lcd_width) & HORZ_STRETCH_BLEND));
1062                         } while (0);
1063                 }
1064
1065                 if (vdisplay < par->lcd_height && crtc->lcd_gen_cntl & LCD_ON) {
1066                         crtc->vert_stretching = (VERT_STRETCH_USE0 | VERT_STRETCH_EN |
1067                                 (((vdisplay * (VERT_STRETCH_RATIO0 + 1)) / par->lcd_height) & VERT_STRETCH_RATIO0));
1068
1069                         if (!M64_HAS(LT_LCD_REGS) &&
1070                             xres <= (M64_HAS(MOBIL_BUS)?1024:800))
1071                                 crtc->ext_vert_stretch |= VERT_STRETCH_MODE;
1072                 } else {
1073                         /*
1074                          * Don't use vertical blending if the mode is too wide or not
1075                          * vertically stretched.
1076                          */
1077                         crtc->vert_stretching = 0;
1078                 }
1079                 /* copy to shadow crtc */
1080                 crtc->shadow_h_tot_disp = crtc->h_tot_disp;
1081                 crtc->shadow_h_sync_strt_wid = crtc->h_sync_strt_wid;
1082                 crtc->shadow_v_tot_disp = crtc->v_tot_disp;
1083                 crtc->shadow_v_sync_strt_wid = crtc->v_sync_strt_wid;
1084         }
1085 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
1086
1087         if (M64_HAS(MAGIC_FIFO)) {
1088                 /* FIXME: display FIFO low watermark values */
1089                 crtc->gen_cntl |= (aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_FIFO_LWM);
1090         }
1091         crtc->dp_pix_width = dp_pix_width;
1092         crtc->dp_chain_mask = dp_chain_mask;
1093
1094         return 0;
1095 }
1096
1097 static int aty_crtc_to_var(const struct crtc *crtc, struct fb_var_screeninfo *var)
1098 {
1099         u32 xres, yres, bpp, left, right, upper, lower, hslen, vslen, sync;
1100         u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid,
1101             h_sync_pol;
1102         u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1103         u32 pix_width;
1104         u32 double_scan, interlace;
1105
1106         /* input */
1107         h_total = crtc->h_tot_disp & 0x1ff;
1108         h_disp = (crtc->h_tot_disp >> 16) & 0xff;
1109         h_sync_strt = (crtc->h_sync_strt_wid & 0xff) | ((crtc->h_sync_strt_wid >> 4) & 0x100);
1110         h_sync_dly = (crtc->h_sync_strt_wid >> 8) & 0x7;
1111         h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x1f;
1112         h_sync_pol = (crtc->h_sync_strt_wid >> 21) & 0x1;
1113         v_total = crtc->v_tot_disp & 0x7ff;
1114         v_disp = (crtc->v_tot_disp >> 16) & 0x7ff;
1115         v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
1116         v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f;
1117         v_sync_pol = (crtc->v_sync_strt_wid >> 21) & 0x1;
1118         c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
1119         pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
1120         double_scan = crtc->gen_cntl & CRTC_DBL_SCAN_EN;
1121         interlace = crtc->gen_cntl & CRTC_INTERLACE_EN;
1122
1123         /* convert */
1124         xres = (h_disp + 1) * 8;
1125         yres = v_disp + 1;
1126         left = (h_total - h_sync_strt - h_sync_wid) * 8 - h_sync_dly;
1127         right = (h_sync_strt - h_disp) * 8 + h_sync_dly;
1128         hslen = h_sync_wid * 8;
1129         upper = v_total - v_sync_strt - v_sync_wid;
1130         lower = v_sync_strt - v_disp;
1131         vslen = v_sync_wid;
1132         sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
1133             (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
1134             (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
1135
1136         switch (pix_width) {
1137 #if 0
1138         case CRTC_PIX_WIDTH_4BPP:
1139                 bpp = 4;
1140                 var->red.offset = 0;
1141                 var->red.length = 8;
1142                 var->green.offset = 0;
1143                 var->green.length = 8;
1144                 var->blue.offset = 0;
1145                 var->blue.length = 8;
1146                 var->transp.offset = 0;
1147                 var->transp.length = 0;
1148                 break;
1149 #endif
1150         case CRTC_PIX_WIDTH_8BPP:
1151                 bpp = 8;
1152                 var->red.offset = 0;
1153                 var->red.length = 8;
1154                 var->green.offset = 0;
1155                 var->green.length = 8;
1156                 var->blue.offset = 0;
1157                 var->blue.length = 8;
1158                 var->transp.offset = 0;
1159                 var->transp.length = 0;
1160                 break;
1161         case CRTC_PIX_WIDTH_15BPP:      /* RGB 555 */
1162                 bpp = 16;
1163                 var->red.offset = 10;
1164                 var->red.length = 5;
1165                 var->green.offset = 5;
1166                 var->green.length = 5;
1167                 var->blue.offset = 0;
1168                 var->blue.length = 5;
1169                 var->transp.offset = 0;
1170                 var->transp.length = 0;
1171                 break;
1172         case CRTC_PIX_WIDTH_16BPP:      /* RGB 565 */
1173                 bpp = 16;
1174                 var->red.offset = 11;
1175                 var->red.length = 5;
1176                 var->green.offset = 5;
1177                 var->green.length = 6;
1178                 var->blue.offset = 0;
1179                 var->blue.length = 5;
1180                 var->transp.offset = 0;
1181                 var->transp.length = 0;
1182                 break;
1183         case CRTC_PIX_WIDTH_24BPP:      /* RGB 888 */
1184                 bpp = 24;
1185                 var->red.offset = 16;
1186                 var->red.length = 8;
1187                 var->green.offset = 8;
1188                 var->green.length = 8;
1189                 var->blue.offset = 0;
1190                 var->blue.length = 8;
1191                 var->transp.offset = 0;
1192                 var->transp.length = 0;
1193                 break;
1194         case CRTC_PIX_WIDTH_32BPP:      /* ARGB 8888 */
1195                 bpp = 32;
1196                 var->red.offset = 16;
1197                 var->red.length = 8;
1198                 var->green.offset = 8;
1199                 var->green.length = 8;
1200                 var->blue.offset = 0;
1201                 var->blue.length = 8;
1202                 var->transp.offset = 24;
1203                 var->transp.length = 8;
1204                 break;
1205         default:
1206                 PRINTKE("Invalid pixel width\n");
1207                 return -EINVAL;
1208         }
1209
1210         /* output */
1211         var->xres = xres;
1212         var->yres = yres;
1213         var->xres_virtual = crtc->vxres;
1214         var->yres_virtual = crtc->vyres;
1215         var->bits_per_pixel = bpp;
1216         var->left_margin = left;
1217         var->right_margin = right;
1218         var->upper_margin = upper;
1219         var->lower_margin = lower;
1220         var->hsync_len = hslen;
1221         var->vsync_len = vslen;
1222         var->sync = sync;
1223         var->vmode = FB_VMODE_NONINTERLACED;
1224         /* In double scan mode, the vertical parameters are doubled, so we need to
1225            half them to get the right values.
1226            In interlaced mode the values are already correct, so no correction is
1227            necessary.
1228          */
1229         if (interlace)
1230                 var->vmode = FB_VMODE_INTERLACED;
1231
1232         if (double_scan) {
1233                 var->vmode = FB_VMODE_DOUBLE;
1234                 var->yres>>=1;
1235                 var->upper_margin>>=1;
1236                 var->lower_margin>>=1;
1237                 var->vsync_len>>=1;
1238         }
1239
1240         return 0;
1241 }
1242
1243 /* ------------------------------------------------------------------------- */
1244
1245 static int atyfb_set_par(struct fb_info *info)
1246 {
1247         struct atyfb_par *par = (struct atyfb_par *) info->par;
1248         struct fb_var_screeninfo *var = &info->var;
1249         u32 tmp, pixclock;
1250         int err;
1251 #ifdef DEBUG
1252         struct fb_var_screeninfo debug;
1253         u32 pixclock_in_ps;
1254 #endif
1255         if (par->asleep)
1256                 return 0;
1257
1258         if ((err = aty_var_to_crtc(info, var, &par->crtc)))
1259                 return err;
1260
1261         pixclock = atyfb_get_pixclock(var, par);
1262
1263         if (pixclock == 0) {
1264                 PRINTKE("Invalid pixclock\n");
1265                 return -EINVAL;
1266         } else {
1267                 if((err = par->pll_ops->var_to_pll(info, pixclock, var->bits_per_pixel, &par->pll)))
1268                         return err;
1269         }
1270
1271         par->accel_flags = var->accel_flags; /* hack */
1272
1273         if (var->accel_flags) {
1274                 info->fbops->fb_sync = atyfb_sync;
1275                 info->flags &= ~FBINFO_HWACCEL_DISABLED;
1276         } else {
1277                 info->fbops->fb_sync = NULL;
1278                 info->flags |= FBINFO_HWACCEL_DISABLED;
1279         }
1280
1281         if (par->blitter_may_be_busy)
1282                 wait_for_idle(par);
1283
1284         aty_set_crtc(par, &par->crtc);
1285         par->dac_ops->set_dac(info, &par->pll, var->bits_per_pixel, par->accel_flags);
1286         par->pll_ops->set_pll(info, &par->pll);
1287
1288 #ifdef DEBUG
1289         if(par->pll_ops && par->pll_ops->pll_to_var)
1290                 pixclock_in_ps = par->pll_ops->pll_to_var(info, &(par->pll));
1291         else
1292                 pixclock_in_ps = 0;
1293
1294         if(0 == pixclock_in_ps) {
1295                 PRINTKE("ALERT ops->pll_to_var get 0\n");
1296                 pixclock_in_ps = pixclock;
1297         }
1298
1299         memset(&debug, 0, sizeof(debug));
1300         if(!aty_crtc_to_var(&(par->crtc), &debug)) {
1301                 u32 hSync, vRefresh;
1302                 u32 h_disp, h_sync_strt, h_sync_end, h_total;
1303                 u32 v_disp, v_sync_strt, v_sync_end, v_total;
1304
1305                 h_disp = debug.xres;
1306                 h_sync_strt = h_disp + debug.right_margin;
1307                 h_sync_end = h_sync_strt + debug.hsync_len;
1308                 h_total = h_sync_end + debug.left_margin;
1309                 v_disp = debug.yres;
1310                 v_sync_strt = v_disp + debug.lower_margin;
1311                 v_sync_end = v_sync_strt + debug.vsync_len;
1312                 v_total = v_sync_end + debug.upper_margin;
1313
1314                 hSync = 1000000000 / (pixclock_in_ps * h_total);
1315                 vRefresh = (hSync * 1000) / v_total;
1316                 if (par->crtc.gen_cntl & CRTC_INTERLACE_EN)
1317                 vRefresh *= 2;
1318                 if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1319                 vRefresh /= 2;
1320
1321                 DPRINTK("atyfb_set_par\n");
1322                 DPRINTK(" Set Visible Mode to %ix%i-%i\n", var->xres, var->yres, var->bits_per_pixel);
1323                 DPRINTK(" Virtual resolution %ix%i, pixclock_in_ps %i (calculated %i)\n",
1324                         var->xres_virtual, var->yres_virtual, pixclock, pixclock_in_ps);
1325                 DPRINTK(" Dot clock:           %i MHz\n", 1000000 / pixclock_in_ps);
1326                 DPRINTK(" Horizontal sync:     %i kHz\n", hSync);
1327                 DPRINTK(" Vertical refresh:    %i Hz\n", vRefresh);
1328                 DPRINTK(" x  style: %i.%03i %i %i %i %i   %i %i %i %i\n",
1329                         1000000 / pixclock_in_ps, 1000000 % pixclock_in_ps,
1330                         h_disp, h_sync_strt, h_sync_end, h_total,
1331                         v_disp, v_sync_strt, v_sync_end, v_total);
1332                 DPRINTK(" fb style: %i  %i %i %i %i %i %i %i %i\n",
1333                         pixclock_in_ps,
1334                         debug.left_margin, h_disp, debug.right_margin, debug.hsync_len,
1335                         debug.upper_margin, v_disp, debug.lower_margin, debug.vsync_len);
1336         }
1337 #endif /* DEBUG */
1338
1339         if (!M64_HAS(INTEGRATED)) {
1340                 /* Don't forget MEM_CNTL */
1341                 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf0ffffff;
1342                 switch (var->bits_per_pixel) {
1343                 case 8:
1344                         tmp |= 0x02000000;
1345                         break;
1346                 case 16:
1347                         tmp |= 0x03000000;
1348                         break;
1349                 case 32:
1350                         tmp |= 0x06000000;
1351                         break;
1352                 }
1353                 aty_st_le32(MEM_CNTL, tmp, par);
1354         } else {
1355                 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf00fffff;
1356                 if (!M64_HAS(MAGIC_POSTDIV))
1357                         tmp |= par->mem_refresh_rate << 20;
1358                 switch (var->bits_per_pixel) {
1359                 case 8:
1360                 case 24:
1361                         tmp |= 0x00000000;
1362                         break;
1363                 case 16:
1364                         tmp |= 0x04000000;
1365                         break;
1366                 case 32:
1367                         tmp |= 0x08000000;
1368                         break;
1369                 }
1370                 if (M64_HAS(CT_BUS)) {
1371                         aty_st_le32(DAC_CNTL, 0x87010184, par);
1372                         aty_st_le32(BUS_CNTL, 0x680000f9, par);
1373                 } else if (M64_HAS(VT_BUS)) {
1374                         aty_st_le32(DAC_CNTL, 0x87010184, par);
1375                         aty_st_le32(BUS_CNTL, 0x680000f9, par);
1376                 } else if (M64_HAS(MOBIL_BUS)) {
1377                         aty_st_le32(DAC_CNTL, 0x80010102, par);
1378                         aty_st_le32(BUS_CNTL, 0x7b33a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1379                 } else {
1380                         /* GT */
1381                         aty_st_le32(DAC_CNTL, 0x86010102, par);
1382                         aty_st_le32(BUS_CNTL, 0x7b23a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1383                         aty_st_le32(EXT_MEM_CNTL, aty_ld_le32(EXT_MEM_CNTL, par) | 0x5000001, par);
1384                 }
1385                 aty_st_le32(MEM_CNTL, tmp, par);
1386         }
1387         aty_st_8(DAC_MASK, 0xff, par);
1388
1389         info->fix.line_length = var->xres_virtual * var->bits_per_pixel/8;
1390         info->fix.visual = var->bits_per_pixel <= 8 ?
1391                 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1392
1393         /* Initialize the graphics engine */
1394         if (par->accel_flags & FB_ACCELF_TEXT)
1395                 aty_init_engine(par, info);
1396
1397 #ifdef CONFIG_BOOTX_TEXT
1398         btext_update_display(info->fix.smem_start,
1399                 (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8,
1400                 ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1,
1401                 var->bits_per_pixel,
1402                 par->crtc.vxres * var->bits_per_pixel / 8);
1403 #endif /* CONFIG_BOOTX_TEXT */
1404 #if 0
1405         /* switch to accelerator mode */
1406         if (!(par->crtc.gen_cntl & CRTC_EXT_DISP_EN))
1407                 aty_st_le32(CRTC_GEN_CNTL, par->crtc.gen_cntl | CRTC_EXT_DISP_EN, par);
1408 #endif
1409 #ifdef DEBUG
1410 {
1411         /* dump non shadow CRTC, pll, LCD registers */
1412         int i; u32 base;
1413
1414         /* CRTC registers */
1415         base = 0x2000;
1416         printk("debug atyfb: Mach64 non-shadow register values:");
1417         for (i = 0; i < 256; i = i+4) {
1418                 if(i%16 == 0) printk("\ndebug atyfb: 0x%04X: ", base + i);
1419                 printk(" %08X", aty_ld_le32(i, par));
1420         }
1421         printk("\n\n");
1422
1423 #ifdef CONFIG_FB_ATY_CT
1424         /* PLL registers */
1425         base = 0x00;
1426         printk("debug atyfb: Mach64 PLL register values:");
1427         for (i = 0; i < 64; i++) {
1428                 if(i%16 == 0) printk("\ndebug atyfb: 0x%02X: ", base + i);
1429                 if(i%4 == 0)  printk(" ");
1430                 printk("%02X", aty_ld_pll_ct(i, par));
1431         }
1432         printk("\n\n");
1433 #endif  /* CONFIG_FB_ATY_CT */
1434
1435 #ifdef CONFIG_FB_ATY_GENERIC_LCD
1436         if (par->lcd_table != 0) {
1437                 /* LCD registers */
1438                 base = 0x00;
1439                 printk("debug atyfb: LCD register values:");
1440                 if(M64_HAS(LT_LCD_REGS)) {
1441                     for(i = 0; i <= POWER_MANAGEMENT; i++) {
1442                         if(i == EXT_VERT_STRETCH)
1443                             continue;
1444                         printk("\ndebug atyfb: 0x%04X: ", lt_lcd_regs[i]);
1445                         printk(" %08X", aty_ld_lcd(i, par));
1446                     }
1447
1448                 } else {
1449                     for (i = 0; i < 64; i++) {
1450                         if(i%4 == 0) printk("\ndebug atyfb: 0x%02X: ", base + i);
1451                         printk(" %08X", aty_ld_lcd(i, par));
1452                     }
1453                 }
1454                 printk("\n\n");
1455         }
1456 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
1457 }
1458 #endif /* DEBUG */
1459         return 0;
1460 }
1461
1462 static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1463 {
1464         struct atyfb_par *par = (struct atyfb_par *) info->par;
1465         int err;
1466         struct crtc crtc;
1467         union aty_pll pll;
1468         u32 pixclock;
1469
1470         memcpy(&pll, &(par->pll), sizeof(pll));
1471
1472         if((err = aty_var_to_crtc(info, var, &crtc)))
1473                 return err;
1474
1475         pixclock = atyfb_get_pixclock(var, par);
1476
1477         if (pixclock == 0) {
1478                 if (!(var->activate & FB_ACTIVATE_TEST))
1479                         PRINTKE("Invalid pixclock\n");
1480                 return -EINVAL;
1481         } else {
1482                 if((err = par->pll_ops->var_to_pll(info, pixclock, var->bits_per_pixel, &pll)))
1483                         return err;
1484         }
1485
1486         if (var->accel_flags & FB_ACCELF_TEXT)
1487                 info->var.accel_flags = FB_ACCELF_TEXT;
1488         else
1489                 info->var.accel_flags = 0;
1490
1491         aty_crtc_to_var(&crtc, var);
1492         var->pixclock = par->pll_ops->pll_to_var(info, &pll);
1493         return 0;
1494 }
1495
1496 static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info)
1497 {
1498         u32 xoffset = info->var.xoffset;
1499         u32 yoffset = info->var.yoffset;
1500         u32 vxres = par->crtc.vxres;
1501         u32 bpp = info->var.bits_per_pixel;
1502
1503         par->crtc.off_pitch = ((yoffset * vxres + xoffset) * bpp / 64) | (vxres << 19);
1504 }
1505
1506
1507     /*
1508      *  Open/Release the frame buffer device
1509      */
1510
1511 static int atyfb_open(struct fb_info *info, int user)
1512 {
1513         struct atyfb_par *par = (struct atyfb_par *) info->par;
1514
1515         if (user) {
1516                 par->open++;
1517 #ifdef __sparc__
1518                 par->mmaped = 0;
1519 #endif
1520         }
1521         return (0);
1522 }
1523
1524 static irqreturn_t aty_irq(int irq, void *dev_id)
1525 {
1526         struct atyfb_par *par = dev_id;
1527         int handled = 0;
1528         u32 int_cntl;
1529
1530         spin_lock(&par->int_lock);
1531
1532         int_cntl = aty_ld_le32(CRTC_INT_CNTL, par);
1533
1534         if (int_cntl & CRTC_VBLANK_INT) {
1535                 /* clear interrupt */
1536                 aty_st_le32(CRTC_INT_CNTL, (int_cntl & CRTC_INT_EN_MASK) | CRTC_VBLANK_INT_AK, par);
1537                 par->vblank.count++;
1538                 if (par->vblank.pan_display) {
1539                         par->vblank.pan_display = 0;
1540                         aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1541                 }
1542                 wake_up_interruptible(&par->vblank.wait);
1543                 handled = 1;
1544         }
1545
1546         spin_unlock(&par->int_lock);
1547
1548         return IRQ_RETVAL(handled);
1549 }
1550
1551 static int aty_enable_irq(struct atyfb_par *par, int reenable)
1552 {
1553         u32 int_cntl;
1554
1555         if (!test_and_set_bit(0, &par->irq_flags)) {
1556                 if (request_irq(par->irq, aty_irq, IRQF_SHARED, "atyfb", par)) {
1557                         clear_bit(0, &par->irq_flags);
1558                         return -EINVAL;
1559                 }
1560                 spin_lock_irq(&par->int_lock);
1561                 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1562                 /* clear interrupt */
1563                 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_AK, par);
1564                 /* enable interrupt */
1565                 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par);
1566                 spin_unlock_irq(&par->int_lock);
1567         } else if (reenable) {
1568                 spin_lock_irq(&par->int_lock);
1569                 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1570                 if (!(int_cntl & CRTC_VBLANK_INT_EN)) {
1571                         printk("atyfb: someone disabled IRQ [%08x]\n", int_cntl);
1572                         /* re-enable interrupt */
1573                         aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par );
1574                 }
1575                 spin_unlock_irq(&par->int_lock);
1576         }
1577
1578         return 0;
1579 }
1580
1581 static int aty_disable_irq(struct atyfb_par *par)
1582 {
1583         u32 int_cntl;
1584
1585         if (test_and_clear_bit(0, &par->irq_flags)) {
1586                 if (par->vblank.pan_display) {
1587                         par->vblank.pan_display = 0;
1588                         aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1589                 }
1590                 spin_lock_irq(&par->int_lock);
1591                 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1592                 /* disable interrupt */
1593                 aty_st_le32(CRTC_INT_CNTL, int_cntl & ~CRTC_VBLANK_INT_EN, par );
1594                 spin_unlock_irq(&par->int_lock);
1595                 free_irq(par->irq, par);
1596         }
1597
1598         return 0;
1599 }
1600
1601 static int atyfb_release(struct fb_info *info, int user)
1602 {
1603         struct atyfb_par *par = (struct atyfb_par *) info->par;
1604         if (user) {
1605                 par->open--;
1606                 mdelay(1);
1607                 wait_for_idle(par);
1608                 if (!par->open) {
1609 #ifdef __sparc__
1610                         int was_mmaped = par->mmaped;
1611
1612                         par->mmaped = 0;
1613
1614                         if (was_mmaped) {
1615                                 struct fb_var_screeninfo var;
1616
1617                                 /* Now reset the default display config, we have no
1618                                  * idea what the program(s) which mmap'd the chip did
1619                                  * to the configuration, nor whether it restored it
1620                                  * correctly.
1621                                  */
1622                                 var = default_var;
1623                                 if (noaccel)
1624                                         var.accel_flags &= ~FB_ACCELF_TEXT;
1625                                 else
1626                                         var.accel_flags |= FB_ACCELF_TEXT;
1627                                 if (var.yres == var.yres_virtual) {
1628                                         u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
1629                                         var.yres_virtual = ((videoram * 8) / var.bits_per_pixel) / var.xres_virtual;
1630                                         if (var.yres_virtual < var.yres)
1631                                                 var.yres_virtual = var.yres;
1632                                 }
1633                         }
1634 #endif
1635                         aty_disable_irq(par);
1636                 }
1637         }
1638         return (0);
1639 }
1640
1641     /*
1642      *  Pan or Wrap the Display
1643      *
1644      *  This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1645      */
1646
1647 static int atyfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
1648 {
1649         struct atyfb_par *par = (struct atyfb_par *) info->par;
1650         u32 xres, yres, xoffset, yoffset;
1651
1652         xres = (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8;
1653         yres = ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1;
1654         if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1655                 yres >>= 1;
1656         xoffset = (var->xoffset + 7) & ~7;
1657         yoffset = var->yoffset;
1658         if (xoffset + xres > par->crtc.vxres || yoffset + yres > par->crtc.vyres)
1659                 return -EINVAL;
1660         info->var.xoffset = xoffset;
1661         info->var.yoffset = yoffset;
1662         if (par->asleep)
1663                 return 0;
1664
1665         set_off_pitch(par, info);
1666         if ((var->activate & FB_ACTIVATE_VBL) && !aty_enable_irq(par, 0)) {
1667                 par->vblank.pan_display = 1;
1668         } else {
1669                 par->vblank.pan_display = 0;
1670                 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1671         }
1672
1673         return 0;
1674 }
1675
1676 static int aty_waitforvblank(struct atyfb_par *par, u32 crtc)
1677 {
1678         struct aty_interrupt *vbl;
1679         unsigned int count;
1680         int ret;
1681
1682         switch (crtc) {
1683         case 0:
1684                 vbl = &par->vblank;
1685                 break;
1686         default:
1687                 return -ENODEV;
1688         }
1689
1690         ret = aty_enable_irq(par, 0);
1691         if (ret)
1692                 return ret;
1693
1694         count = vbl->count;
1695         ret = wait_event_interruptible_timeout(vbl->wait, count != vbl->count, HZ/10);
1696         if (ret < 0) {
1697                 return ret;
1698         }
1699         if (ret == 0) {
1700                 aty_enable_irq(par, 1);
1701                 return -ETIMEDOUT;
1702         }
1703
1704         return 0;
1705 }
1706
1707
1708 #ifdef DEBUG
1709 #define ATYIO_CLKR              0x41545900      /* ATY\00 */
1710 #define ATYIO_CLKW              0x41545901      /* ATY\01 */
1711
1712 struct atyclk {
1713         u32 ref_clk_per;
1714         u8 pll_ref_div;
1715         u8 mclk_fb_div;
1716         u8 mclk_post_div;       /* 1,2,3,4,8 */
1717         u8 mclk_fb_mult;        /* 2 or 4 */
1718         u8 xclk_post_div;       /* 1,2,3,4,8 */
1719         u8 vclk_fb_div;
1720         u8 vclk_post_div;       /* 1,2,3,4,6,8,12 */
1721         u32 dsp_xclks_per_row;  /* 0-16383 */
1722         u32 dsp_loop_latency;   /* 0-15 */
1723         u32 dsp_precision;      /* 0-7 */
1724         u32 dsp_on;             /* 0-2047 */
1725         u32 dsp_off;            /* 0-2047 */
1726 };
1727
1728 #define ATYIO_FEATR             0x41545902      /* ATY\02 */
1729 #define ATYIO_FEATW             0x41545903      /* ATY\03 */
1730 #endif
1731
1732 #ifndef FBIO_WAITFORVSYNC
1733 #define FBIO_WAITFORVSYNC _IOW('F', 0x20, __u32)
1734 #endif
1735
1736 static int atyfb_ioctl(struct fb_info *info, u_int cmd, u_long arg)
1737 {
1738         struct atyfb_par *par = (struct atyfb_par *) info->par;
1739 #ifdef __sparc__
1740         struct fbtype fbtyp;
1741 #endif
1742
1743         switch (cmd) {
1744 #ifdef __sparc__
1745         case FBIOGTYPE:
1746                 fbtyp.fb_type = FBTYPE_PCI_GENERIC;
1747                 fbtyp.fb_width = par->crtc.vxres;
1748                 fbtyp.fb_height = par->crtc.vyres;
1749                 fbtyp.fb_depth = info->var.bits_per_pixel;
1750                 fbtyp.fb_cmsize = info->cmap.len;
1751                 fbtyp.fb_size = info->fix.smem_len;
1752                 if (copy_to_user((struct fbtype __user *) arg, &fbtyp, sizeof(fbtyp)))
1753                         return -EFAULT;
1754                 break;
1755 #endif /* __sparc__ */
1756
1757         case FBIO_WAITFORVSYNC:
1758                 {
1759                         u32 crtc;
1760
1761                         if (get_user(crtc, (__u32 __user *) arg))
1762                                 return -EFAULT;
1763
1764                         return aty_waitforvblank(par, crtc);
1765                 }
1766                 break;
1767
1768 #if defined(DEBUG) && defined(CONFIG_FB_ATY_CT)
1769         case ATYIO_CLKR:
1770                 if (M64_HAS(INTEGRATED)) {
1771                         struct atyclk clk;
1772                         union aty_pll *pll = &(par->pll);
1773                         u32 dsp_config = pll->ct.dsp_config;
1774                         u32 dsp_on_off = pll->ct.dsp_on_off;
1775                         clk.ref_clk_per = par->ref_clk_per;
1776                         clk.pll_ref_div = pll->ct.pll_ref_div;
1777                         clk.mclk_fb_div = pll->ct.mclk_fb_div;
1778                         clk.mclk_post_div = pll->ct.mclk_post_div_real;
1779                         clk.mclk_fb_mult = pll->ct.mclk_fb_mult;
1780                         clk.xclk_post_div = pll->ct.xclk_post_div_real;
1781                         clk.vclk_fb_div = pll->ct.vclk_fb_div;
1782                         clk.vclk_post_div = pll->ct.vclk_post_div_real;
1783                         clk.dsp_xclks_per_row = dsp_config & 0x3fff;
1784                         clk.dsp_loop_latency = (dsp_config >> 16) & 0xf;
1785                         clk.dsp_precision = (dsp_config >> 20) & 7;
1786                         clk.dsp_off = dsp_on_off & 0x7ff;
1787                         clk.dsp_on = (dsp_on_off >> 16) & 0x7ff;
1788                         if (copy_to_user((struct atyclk __user *) arg, &clk,
1789                                          sizeof(clk)))
1790                                 return -EFAULT;
1791                 } else
1792                         return -EINVAL;
1793                 break;
1794         case ATYIO_CLKW:
1795                 if (M64_HAS(INTEGRATED)) {
1796                         struct atyclk clk;
1797                         union aty_pll *pll = &(par->pll);
1798                         if (copy_from_user(&clk, (struct atyclk __user *) arg, sizeof(clk)))
1799                                 return -EFAULT;
1800                         par->ref_clk_per = clk.ref_clk_per;
1801                         pll->ct.pll_ref_div = clk.pll_ref_div;
1802                         pll->ct.mclk_fb_div = clk.mclk_fb_div;
1803                         pll->ct.mclk_post_div_real = clk.mclk_post_div;
1804                         pll->ct.mclk_fb_mult = clk.mclk_fb_mult;
1805                         pll->ct.xclk_post_div_real = clk.xclk_post_div;
1806                         pll->ct.vclk_fb_div = clk.vclk_fb_div;
1807                         pll->ct.vclk_post_div_real = clk.vclk_post_div;
1808                         pll->ct.dsp_config = (clk.dsp_xclks_per_row & 0x3fff) |
1809                                 ((clk.dsp_loop_latency & 0xf)<<16)| ((clk.dsp_precision & 7)<<20);
1810                         pll->ct.dsp_on_off = (clk.dsp_off & 0x7ff) | ((clk.dsp_on & 0x7ff)<<16);
1811                         /*aty_calc_pll_ct(info, &pll->ct);*/
1812                         aty_set_pll_ct(info, pll);
1813                 } else
1814                         return -EINVAL;
1815                 break;
1816         case ATYIO_FEATR:
1817                 if (get_user(par->features, (u32 __user *) arg))
1818                         return -EFAULT;
1819                 break;
1820         case ATYIO_FEATW:
1821                 if (put_user(par->features, (u32 __user *) arg))
1822                         return -EFAULT;
1823                 break;
1824 #endif /* DEBUG && CONFIG_FB_ATY_CT */
1825         default:
1826                 return -EINVAL;
1827         }
1828         return 0;
1829 }
1830
1831 static int atyfb_sync(struct fb_info *info)
1832 {
1833         struct atyfb_par *par = (struct atyfb_par *) info->par;
1834
1835         if (par->blitter_may_be_busy)
1836                 wait_for_idle(par);
1837         return 0;
1838 }
1839
1840 #ifdef __sparc__
1841 static int atyfb_mmap(struct fb_info *info, struct vm_area_struct *vma)
1842 {
1843         struct atyfb_par *par = (struct atyfb_par *) info->par;
1844         unsigned int size, page, map_size = 0;
1845         unsigned long map_offset = 0;
1846         unsigned long off;
1847         int i;
1848
1849         if (!par->mmap_map)
1850                 return -ENXIO;
1851
1852         if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
1853                 return -EINVAL;
1854
1855         off = vma->vm_pgoff << PAGE_SHIFT;
1856         size = vma->vm_end - vma->vm_start;
1857
1858         /* To stop the swapper from even considering these pages. */
1859         vma->vm_flags |= (VM_IO | VM_RESERVED);
1860
1861         if (((vma->vm_pgoff == 0) && (size == info->fix.smem_len)) ||
1862             ((off == info->fix.smem_len) && (size == PAGE_SIZE)))
1863                 off += 0x8000000000000000UL;
1864
1865         vma->vm_pgoff = off >> PAGE_SHIFT;      /* propagate off changes */
1866
1867         /* Each page, see which map applies */
1868         for (page = 0; page < size;) {
1869                 map_size = 0;
1870                 for (i = 0; par->mmap_map[i].size; i++) {
1871                         unsigned long start = par->mmap_map[i].voff;
1872                         unsigned long end = start + par->mmap_map[i].size;
1873                         unsigned long offset = off + page;
1874
1875                         if (start > offset)
1876                                 continue;
1877                         if (offset >= end)
1878                                 continue;
1879
1880                         map_size = par->mmap_map[i].size - (offset - start);
1881                         map_offset =
1882                             par->mmap_map[i].poff + (offset - start);
1883                         break;
1884                 }
1885                 if (!map_size) {
1886                         page += PAGE_SIZE;
1887                         continue;
1888                 }
1889                 if (page + map_size > size)
1890                         map_size = size - page;
1891
1892                 pgprot_val(vma->vm_page_prot) &=
1893                     ~(par->mmap_map[i].prot_mask);
1894                 pgprot_val(vma->vm_page_prot) |= par->mmap_map[i].prot_flag;
1895
1896                 if (remap_pfn_range(vma, vma->vm_start + page,
1897                         map_offset >> PAGE_SHIFT, map_size, vma->vm_page_prot))
1898                         return -EAGAIN;
1899
1900                 page += map_size;
1901         }
1902
1903         if (!map_size)
1904                 return -EINVAL;
1905
1906         if (!par->mmaped)
1907                 par->mmaped = 1;
1908         return 0;
1909 }
1910
1911 static struct {
1912         u32 yoffset;
1913         u8 r[2][256];
1914         u8 g[2][256];
1915         u8 b[2][256];
1916 } atyfb_save;
1917
1918 static void atyfb_save_palette(struct atyfb_par *par, int enter)
1919 {
1920         int i, tmp;
1921
1922         for (i = 0; i < 256; i++) {
1923                 tmp = aty_ld_8(DAC_CNTL, par) & 0xfc;
1924                 if (M64_HAS(EXTRA_BRIGHT))
1925                         tmp |= 0x2;
1926                 aty_st_8(DAC_CNTL, tmp, par);
1927                 aty_st_8(DAC_MASK, 0xff, par);
1928
1929                 aty_st_8(DAC_R_INDEX, i, par);
1930                 atyfb_save.r[enter][i] = aty_ld_8(DAC_DATA, par);
1931                 atyfb_save.g[enter][i] = aty_ld_8(DAC_DATA, par);
1932                 atyfb_save.b[enter][i] = aty_ld_8(DAC_DATA, par);
1933                 aty_st_8(DAC_W_INDEX, i, par);
1934                 aty_st_8(DAC_DATA, atyfb_save.r[1 - enter][i], par);
1935                 aty_st_8(DAC_DATA, atyfb_save.g[1 - enter][i], par);
1936                 aty_st_8(DAC_DATA, atyfb_save.b[1 - enter][i], par);
1937         }
1938 }
1939
1940 static void atyfb_palette(int enter)
1941 {
1942         struct atyfb_par *par;
1943         struct fb_info *info;
1944         int i;
1945
1946         for (i = 0; i < FB_MAX; i++) {
1947                 info = registered_fb[i];
1948                 if (info && info->fbops == &atyfb_ops) {
1949                         par = (struct atyfb_par *) info->par;
1950
1951                         atyfb_save_palette(par, enter);
1952                         if (enter) {
1953                                 atyfb_save.yoffset = info->var.yoffset;
1954                                 info->var.yoffset = 0;
1955                                 set_off_pitch(par, info);
1956                         } else {
1957                                 info->var.yoffset = atyfb_save.yoffset;
1958                                 set_off_pitch(par, info);
1959                         }
1960                         aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1961                         break;
1962                 }
1963         }
1964 }
1965 #endif /* __sparc__ */
1966
1967
1968
1969 #if defined(CONFIG_PM) && defined(CONFIG_PCI)
1970
1971 #ifdef CONFIG_PPC_PMAC
1972 /* Power management routines. Those are used for PowerBook sleep.
1973  */
1974 static int aty_power_mgmt(int sleep, struct atyfb_par *par)
1975 {
1976         u32 pm;
1977         int timeout;
1978
1979         pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1980         pm = (pm & ~PWR_MGT_MODE_MASK) | PWR_MGT_MODE_REG;
1981         aty_st_lcd(POWER_MANAGEMENT, pm, par);
1982         pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1983
1984         timeout = 2000;
1985         if (sleep) {
1986                 /* Sleep */
1987                 pm &= ~PWR_MGT_ON;
1988                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1989                 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1990                 udelay(10);
1991                 pm &= ~(PWR_BLON | AUTO_PWR_UP);
1992                 pm |= SUSPEND_NOW;
1993                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1994                 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1995                 udelay(10);
1996                 pm |= PWR_MGT_ON;
1997                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1998                 do {
1999                         pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2000                         mdelay(1);
2001                         if ((--timeout) == 0)
2002                                 break;
2003                 } while ((pm & PWR_MGT_STATUS_MASK) != PWR_MGT_STATUS_SUSPEND);
2004         } else {
2005                 /* Wakeup */
2006                 pm &= ~PWR_MGT_ON;
2007                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2008                 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2009                 udelay(10);
2010                 pm &= ~SUSPEND_NOW;
2011                 pm |= (PWR_BLON | AUTO_PWR_UP);
2012                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2013                 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2014                 udelay(10);
2015                 pm |= PWR_MGT_ON;
2016                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2017                 do {
2018                         pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2019                         mdelay(1);
2020                         if ((--timeout) == 0)
2021                                 break;
2022                 } while ((pm & PWR_MGT_STATUS_MASK) != 0);
2023         }
2024         mdelay(500);
2025
2026         return timeout ? 0 : -EIO;
2027 }
2028 #endif
2029
2030 static int atyfb_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2031 {
2032         struct fb_info *info = pci_get_drvdata(pdev);
2033         struct atyfb_par *par = (struct atyfb_par *) info->par;
2034
2035         if (state.event == pdev->dev.power.power_state.event)
2036                 return 0;
2037
2038         acquire_console_sem();
2039
2040         fb_set_suspend(info, 1);
2041
2042         /* Idle & reset engine */
2043         wait_for_idle(par);
2044         aty_reset_engine(par);
2045
2046         /* Blank display and LCD */
2047         atyfb_blank(FB_BLANK_POWERDOWN, info);
2048
2049         par->asleep = 1;
2050         par->lock_blank = 1;
2051
2052 #ifdef CONFIG_PPC_PMAC
2053         /* Set chip to "suspend" mode */
2054         if (aty_power_mgmt(1, par)) {
2055                 par->asleep = 0;
2056                 par->lock_blank = 0;
2057                 atyfb_blank(FB_BLANK_UNBLANK, info);
2058                 fb_set_suspend(info, 0);
2059                 release_console_sem();
2060                 return -EIO;
2061         }
2062 #else
2063         pci_set_power_state(pdev, pci_choose_state(pdev, state));
2064 #endif
2065
2066         release_console_sem();
2067
2068         pdev->dev.power.power_state = state;
2069
2070         return 0;
2071 }
2072
2073 static int atyfb_pci_resume(struct pci_dev *pdev)
2074 {
2075         struct fb_info *info = pci_get_drvdata(pdev);
2076         struct atyfb_par *par = (struct atyfb_par *) info->par;
2077
2078         if (pdev->dev.power.power_state.event == PM_EVENT_ON)
2079                 return 0;
2080
2081         acquire_console_sem();
2082
2083 #ifdef CONFIG_PPC_PMAC
2084         if (pdev->dev.power.power_state.event == 2)
2085                 aty_power_mgmt(0, par);
2086 #else
2087         pci_set_power_state(pdev, PCI_D0);
2088 #endif
2089
2090         aty_resume_chip(info);
2091
2092         par->asleep = 0;
2093
2094         /* Restore display */
2095         atyfb_set_par(info);
2096
2097         /* Refresh */
2098         fb_set_suspend(info, 0);
2099
2100         /* Unblank */
2101         par->lock_blank = 0;
2102         atyfb_blank(FB_BLANK_UNBLANK, info);
2103
2104         release_console_sem();
2105
2106         pdev->dev.power.power_state = PMSG_ON;
2107
2108         return 0;
2109 }
2110
2111 #endif /*  defined(CONFIG_PM) && defined(CONFIG_PCI) */
2112
2113 /* Backlight */
2114 #ifdef CONFIG_FB_ATY_BACKLIGHT
2115 #define MAX_LEVEL 0xFF
2116
2117 static struct backlight_properties aty_bl_data;
2118
2119 /* Call with fb_info->bl_mutex held */
2120 static int aty_bl_get_level_brightness(struct atyfb_par *par, int level)
2121 {
2122         struct fb_info *info = pci_get_drvdata(par->pdev);
2123         int atylevel;
2124
2125         /* Get and convert the value */
2126         atylevel = info->bl_curve[level] * FB_BACKLIGHT_MAX / MAX_LEVEL;
2127
2128         if (atylevel < 0)
2129                 atylevel = 0;
2130         else if (atylevel > MAX_LEVEL)
2131                 atylevel = MAX_LEVEL;
2132
2133         return atylevel;
2134 }
2135
2136 /* Call with fb_info->bl_mutex held */
2137 static int __aty_bl_update_status(struct backlight_device *bd)
2138 {
2139         struct atyfb_par *par = class_get_devdata(&bd->class_dev);
2140         unsigned int reg = aty_ld_lcd(LCD_MISC_CNTL, par);
2141         int level;
2142
2143         if (bd->props->power != FB_BLANK_UNBLANK ||
2144             bd->props->fb_blank != FB_BLANK_UNBLANK)
2145                 level = 0;
2146         else
2147                 level = bd->props->brightness;
2148
2149         reg |= (BLMOD_EN | BIASMOD_EN);
2150         if (level > 0) {
2151                 reg &= ~BIAS_MOD_LEVEL_MASK;
2152                 reg |= (aty_bl_get_level_brightness(par, level) << BIAS_MOD_LEVEL_SHIFT);
2153         } else {
2154                 reg &= ~BIAS_MOD_LEVEL_MASK;
2155                 reg |= (aty_bl_get_level_brightness(par, 0) << BIAS_MOD_LEVEL_SHIFT);
2156         }
2157         aty_st_lcd(LCD_MISC_CNTL, reg, par);
2158
2159         return 0;
2160 }
2161
2162 static int aty_bl_update_status(struct backlight_device *bd)
2163 {
2164         struct atyfb_par *par = class_get_devdata(&bd->class_dev);
2165         struct fb_info *info = pci_get_drvdata(par->pdev);
2166         int ret;
2167
2168         mutex_lock(&info->bl_mutex);
2169         ret = __aty_bl_update_status(bd);
2170         mutex_unlock(&info->bl_mutex);
2171
2172         return ret;
2173 }
2174
2175 static int aty_bl_get_brightness(struct backlight_device *bd)
2176 {
2177         return bd->props->brightness;
2178 }
2179
2180 static struct backlight_properties aty_bl_data = {
2181         .get_brightness = aty_bl_get_brightness,
2182         .update_status  = aty_bl_update_status,
2183         .max_brightness = (FB_BACKLIGHT_LEVELS - 1),
2184 };
2185
2186 static void aty_bl_set_power(struct fb_info *info, int power)
2187 {
2188         mutex_lock(&info->bl_mutex);
2189
2190         if (info->bl_dev) {
2191                 down(&info->bl_dev->sem);
2192                 info->bl_dev->props->power = power;
2193                 __aty_bl_update_status(info->bl_dev);
2194                 up(&info->bl_dev->sem);
2195         }
2196
2197         mutex_unlock(&info->bl_mutex);
2198 }
2199
2200 static void aty_bl_init(struct atyfb_par *par)
2201 {
2202         struct fb_info *info = pci_get_drvdata(par->pdev);
2203         struct backlight_device *bd;
2204         char name[12];
2205
2206 #ifdef CONFIG_PMAC_BACKLIGHT
2207         if (!pmac_has_backlight_type("ati"))
2208                 return;
2209 #endif
2210
2211         snprintf(name, sizeof(name), "atybl%d", info->node);
2212
2213         bd = backlight_device_register(name, info->dev, par, &aty_bl_data);
2214         if (IS_ERR(bd)) {
2215                 info->bl_dev = NULL;
2216                 printk(KERN_WARNING "aty: Backlight registration failed\n");
2217                 goto error;
2218         }
2219
2220         mutex_lock(&info->bl_mutex);
2221         info->bl_dev = bd;
2222         fb_bl_default_curve(info, 0,
2223                 0x3F * FB_BACKLIGHT_MAX / MAX_LEVEL,
2224                 0xFF * FB_BACKLIGHT_MAX / MAX_LEVEL);
2225         mutex_unlock(&info->bl_mutex);
2226
2227         down(&bd->sem);
2228         bd->props->brightness = aty_bl_data.max_brightness;
2229         bd->props->power = FB_BLANK_UNBLANK;
2230         bd->props->update_status(bd);
2231         up(&bd->sem);
2232
2233 #ifdef CONFIG_PMAC_BACKLIGHT
2234         mutex_lock(&pmac_backlight_mutex);
2235         if (!pmac_backlight)
2236                 pmac_backlight = bd;
2237         mutex_unlock(&pmac_backlight_mutex);
2238 #endif
2239
2240         printk("aty: Backlight initialized (%s)\n", name);
2241
2242         return;
2243
2244 error:
2245         return;
2246 }
2247
2248 static void aty_bl_exit(struct atyfb_par *par)
2249 {
2250         struct fb_info *info = pci_get_drvdata(par->pdev);
2251
2252 #ifdef CONFIG_PMAC_BACKLIGHT
2253         mutex_lock(&pmac_backlight_mutex);
2254 #endif
2255
2256         mutex_lock(&info->bl_mutex);
2257         if (info->bl_dev) {
2258 #ifdef CONFIG_PMAC_BACKLIGHT
2259                 if (pmac_backlight == info->bl_dev)
2260                         pmac_backlight = NULL;
2261 #endif
2262
2263                 backlight_device_unregister(info->bl_dev);
2264
2265                 printk("aty: Backlight unloaded\n");
2266         }
2267         mutex_unlock(&info->bl_mutex);
2268
2269 #ifdef CONFIG_PMAC_BACKLIGHT
2270         mutex_unlock(&pmac_backlight_mutex);
2271 #endif
2272 }
2273
2274 #endif /* CONFIG_FB_ATY_BACKLIGHT */
2275
2276 static void __devinit aty_calc_mem_refresh(struct atyfb_par *par, int xclk)
2277 {
2278         const int ragepro_tbl[] = {
2279                 44, 50, 55, 66, 75, 80, 100
2280         };
2281         const int ragexl_tbl[] = {
2282                 50, 66, 75, 83, 90, 95, 100, 105,
2283                 110, 115, 120, 125, 133, 143, 166
2284         };
2285         const int *refresh_tbl;
2286         int i, size;
2287
2288         if (IS_XL(par->pci_id) || IS_MOBILITY(par->pci_id)) {
2289                 refresh_tbl = ragexl_tbl;
2290                 size = ARRAY_SIZE(ragexl_tbl);
2291         } else {
2292                 refresh_tbl = ragepro_tbl;
2293                 size = ARRAY_SIZE(ragepro_tbl);
2294         }
2295
2296         for (i=0; i < size; i++) {
2297                 if (xclk < refresh_tbl[i])
2298                 break;
2299         }
2300         par->mem_refresh_rate = i;
2301 }
2302
2303     /*
2304      *  Initialisation
2305      */
2306
2307 static struct fb_info *fb_list = NULL;
2308
2309 #if defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD)
2310 static int __devinit atyfb_get_timings_from_lcd(struct atyfb_par *par,
2311                                                 struct fb_var_screeninfo *var)
2312 {
2313         int ret = -EINVAL;
2314
2315         if (par->lcd_table != 0 && (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2316                 *var = default_var;
2317                 var->xres = var->xres_virtual = par->lcd_hdisp;
2318                 var->right_margin = par->lcd_right_margin;
2319                 var->left_margin = par->lcd_hblank_len -
2320                         (par->lcd_right_margin + par->lcd_hsync_dly +
2321                          par->lcd_hsync_len);
2322                 var->hsync_len = par->lcd_hsync_len + par->lcd_hsync_dly;
2323                 var->yres = var->yres_virtual = par->lcd_vdisp;
2324                 var->lower_margin = par->lcd_lower_margin;
2325                 var->upper_margin = par->lcd_vblank_len -
2326                         (par->lcd_lower_margin + par->lcd_vsync_len);
2327                 var->vsync_len = par->lcd_vsync_len;
2328                 var->pixclock = par->lcd_pixclock;
2329                 ret = 0;
2330         }
2331
2332         return ret;
2333 }
2334 #endif /* defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD) */
2335
2336 static int __devinit aty_init(struct fb_info *info)
2337 {
2338         struct atyfb_par *par = (struct atyfb_par *) info->par;
2339         const char *ramname = NULL, *xtal;
2340         int gtb_memsize, has_var = 0;
2341         struct fb_var_screeninfo var;
2342
2343         init_waitqueue_head(&par->vblank.wait);
2344         spin_lock_init(&par->int_lock);
2345
2346 #ifdef CONFIG_PPC_PMAC
2347         /* The Apple iBook1 uses non-standard memory frequencies. We detect it
2348          * and set the frequency manually. */
2349         if (machine_is_compatible("PowerBook2,1")) {
2350                 par->pll_limits.mclk = 70;
2351                 par->pll_limits.xclk = 53;
2352         }
2353 #endif
2354         if (pll)
2355                 par->pll_limits.pll_max = pll;
2356         if (mclk)
2357                 par->pll_limits.mclk = mclk;
2358         if (xclk)
2359                 par->pll_limits.xclk = xclk;
2360
2361         aty_calc_mem_refresh(par, par->pll_limits.xclk);
2362         par->pll_per = 1000000/par->pll_limits.pll_max;
2363         par->mclk_per = 1000000/par->pll_limits.mclk;
2364         par->xclk_per = 1000000/par->pll_limits.xclk;
2365
2366         par->ref_clk_per = 1000000000000ULL / 14318180;
2367         xtal = "14.31818";
2368
2369 #ifdef CONFIG_FB_ATY_GX
2370         if (!M64_HAS(INTEGRATED)) {
2371                 u32 stat0;
2372                 u8 dac_type, dac_subtype, clk_type;
2373                 stat0 = aty_ld_le32(CONFIG_STAT0, par);
2374                 par->bus_type = (stat0 >> 0) & 0x07;
2375                 par->ram_type = (stat0 >> 3) & 0x07;
2376                 ramname = aty_gx_ram[par->ram_type];
2377                 /* FIXME: clockchip/RAMDAC probing? */
2378                 dac_type = (aty_ld_le32(DAC_CNTL, par) >> 16) & 0x07;
2379 #ifdef CONFIG_ATARI
2380                 clk_type = CLK_ATI18818_1;
2381                 dac_type = (stat0 >> 9) & 0x07;
2382                 if (dac_type == 0x07)
2383                         dac_subtype = DAC_ATT20C408;
2384                 else
2385                         dac_subtype = (aty_ld_8(SCRATCH_REG1 + 1, par) & 0xF0) | dac_type;
2386 #else
2387                 dac_type = DAC_IBMRGB514;
2388                 dac_subtype = DAC_IBMRGB514;
2389                 clk_type = CLK_IBMRGB514;
2390 #endif
2391                 switch (dac_subtype) {
2392                 case DAC_IBMRGB514:
2393                         par->dac_ops = &aty_dac_ibm514;
2394                         break;
2395                 case DAC_ATI68860_B:
2396                 case DAC_ATI68860_C:
2397                         par->dac_ops = &aty_dac_ati68860b;
2398                         break;
2399                 case DAC_ATT20C408:
2400                 case DAC_ATT21C498:
2401                         par->dac_ops = &aty_dac_att21c498;
2402                         break;
2403                 default:
2404                         PRINTKI("aty_init: DAC type not implemented yet!\n");
2405                         par->dac_ops = &aty_dac_unsupported;
2406                         break;
2407                 }
2408                 switch (clk_type) {
2409 #ifdef CONFIG_ATARI
2410                 case CLK_ATI18818_1:
2411                         par->pll_ops = &aty_pll_ati18818_1;
2412                         break;
2413 #else
2414                 case CLK_IBMRGB514:
2415                         par->pll_ops = &aty_pll_ibm514;
2416                         break;
2417 #endif
2418 #if 0 /* dead code */
2419                 case CLK_STG1703:
2420                         par->pll_ops = &aty_pll_stg1703;
2421                         break;
2422                 case CLK_CH8398:
2423                         par->pll_ops = &aty_pll_ch8398;
2424                         break;
2425                 case CLK_ATT20C408:
2426                         par->pll_ops = &aty_pll_att20c408;
2427                         break;
2428 #endif
2429                 default:
2430                         PRINTKI("aty_init: CLK type not implemented yet!");
2431                         par->pll_ops = &aty_pll_unsupported;
2432                         break;
2433                 }
2434         }
2435 #endif /* CONFIG_FB_ATY_GX */
2436 #ifdef CONFIG_FB_ATY_CT
2437         if (M64_HAS(INTEGRATED)) {
2438                 par->dac_ops = &aty_dac_ct;
2439                 par->pll_ops = &aty_pll_ct;
2440                 par->bus_type = PCI;
2441                 par->ram_type = (aty_ld_le32(CONFIG_STAT0, par) & 0x07);
2442                 ramname = aty_ct_ram[par->ram_type];
2443                 /* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */
2444                 if (par->pll_limits.mclk == 67 && par->ram_type < SDRAM)
2445                         par->pll_limits.mclk = 63;
2446         }
2447
2448         if (M64_HAS(GTB_DSP)) {
2449                 u8 pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par);
2450
2451                 if (pll_ref_div) {
2452                         int diff1, diff2;
2453                         diff1 = 510 * 14 / pll_ref_div - par->pll_limits.pll_max;
2454                         diff2 = 510 * 29 / pll_ref_div - par->pll_limits.pll_max;
2455                         if (diff1 < 0)
2456                                 diff1 = -diff1;
2457                         if (diff2 < 0)
2458                                 diff2 = -diff2;
2459                         if (diff2 < diff1) {
2460                                 par->ref_clk_per = 1000000000000ULL / 29498928;
2461                                 xtal = "29.498928";
2462                         }
2463                 }
2464         }
2465 #endif /* CONFIG_FB_ATY_CT */
2466
2467         /* save previous video mode */
2468         aty_get_crtc(par, &saved_crtc);
2469         if(par->pll_ops->get_pll)
2470                 par->pll_ops->get_pll(info, &saved_pll);
2471
2472         par->mem_cntl = aty_ld_le32(MEM_CNTL, par);
2473         gtb_memsize = M64_HAS(GTB_DSP);
2474         if (gtb_memsize)
2475                 switch (par->mem_cntl & 0xF) {  /* 0xF used instead of MEM_SIZE_ALIAS */
2476                 case MEM_SIZE_512K:
2477                         info->fix.smem_len = 0x80000;
2478                         break;
2479                 case MEM_SIZE_1M:
2480                         info->fix.smem_len = 0x100000;
2481                         break;
2482                 case MEM_SIZE_2M_GTB:
2483                         info->fix.smem_len = 0x200000;
2484                         break;
2485                 case MEM_SIZE_4M_GTB:
2486                         info->fix.smem_len = 0x400000;
2487                         break;
2488                 case MEM_SIZE_6M_GTB:
2489                         info->fix.smem_len = 0x600000;
2490                         break;
2491                 case MEM_SIZE_8M_GTB:
2492                         info->fix.smem_len = 0x800000;
2493                         break;
2494                 default:
2495                         info->fix.smem_len = 0x80000;
2496         } else
2497                 switch (par->mem_cntl & MEM_SIZE_ALIAS) {
2498                 case MEM_SIZE_512K:
2499                         info->fix.smem_len = 0x80000;
2500                         break;
2501                 case MEM_SIZE_1M:
2502                         info->fix.smem_len = 0x100000;
2503                         break;
2504                 case MEM_SIZE_2M:
2505                         info->fix.smem_len = 0x200000;
2506                         break;
2507                 case MEM_SIZE_4M:
2508                         info->fix.smem_len = 0x400000;
2509                         break;
2510                 case MEM_SIZE_6M:
2511                         info->fix.smem_len = 0x600000;
2512                         break;
2513                 case MEM_SIZE_8M:
2514                         info->fix.smem_len = 0x800000;
2515                         break;
2516                 default:
2517                         info->fix.smem_len = 0x80000;
2518                 }
2519
2520         if (M64_HAS(MAGIC_VRAM_SIZE)) {
2521                 if (aty_ld_le32(CONFIG_STAT1, par) & 0x40000000)
2522                         info->fix.smem_len += 0x400000;
2523         }
2524
2525         if (vram) {
2526                 info->fix.smem_len = vram * 1024;
2527                 par->mem_cntl &= ~(gtb_memsize ? 0xF : MEM_SIZE_ALIAS);
2528                 if (info->fix.smem_len <= 0x80000)
2529                         par->mem_cntl |= MEM_SIZE_512K;
2530                 else if (info->fix.smem_len <= 0x100000)
2531                         par->mem_cntl |= MEM_SIZE_1M;
2532                 else if (info->fix.smem_len <= 0x200000)
2533                         par->mem_cntl |= gtb_memsize ? MEM_SIZE_2M_GTB : MEM_SIZE_2M;
2534                 else if (info->fix.smem_len <= 0x400000)
2535                         par->mem_cntl |= gtb_memsize ? MEM_SIZE_4M_GTB : MEM_SIZE_4M;
2536                 else if (info->fix.smem_len <= 0x600000)
2537                         par->mem_cntl |= gtb_memsize ? MEM_SIZE_6M_GTB : MEM_SIZE_6M;
2538                 else
2539                         par->mem_cntl |= gtb_memsize ? MEM_SIZE_8M_GTB : MEM_SIZE_8M;
2540                 aty_st_le32(MEM_CNTL, par->mem_cntl, par);
2541         }
2542
2543         /*
2544          *  Reg Block 0 (CT-compatible block) is at mmio_start
2545          *  Reg Block 1 (multimedia extensions) is at mmio_start - 0x400
2546          */
2547         if (M64_HAS(GX)) {
2548                 info->fix.mmio_len = 0x400;
2549                 info->fix.accel = FB_ACCEL_ATI_MACH64GX;
2550         } else if (M64_HAS(CT)) {
2551                 info->fix.mmio_len = 0x400;
2552                 info->fix.accel = FB_ACCEL_ATI_MACH64CT;
2553         } else if (M64_HAS(VT)) {
2554                 info->fix.mmio_start -= 0x400;
2555                 info->fix.mmio_len = 0x800;
2556                 info->fix.accel = FB_ACCEL_ATI_MACH64VT;
2557         } else {/* GT */
2558                 info->fix.mmio_start -= 0x400;
2559                 info->fix.mmio_len = 0x800;
2560                 info->fix.accel = FB_ACCEL_ATI_MACH64GT;
2561         }
2562
2563         PRINTKI("%d%c %s, %s MHz XTAL, %d MHz PLL, %d Mhz MCLK, %d MHz XCLK\n",
2564                info->fix.smem_len == 0x80000 ? 512 : (info->fix.smem_len >> 20),
2565                info->fix.smem_len == 0x80000 ? 'K' : 'M', ramname, xtal, par->pll_limits.pll_max,
2566                par->pll_limits.mclk, par->pll_limits.xclk);
2567
2568 #if defined(DEBUG) && defined(CONFIG_FB_ATY_CT)
2569         if (M64_HAS(INTEGRATED)) {
2570                 int i;
2571                 printk("debug atyfb: BUS_CNTL DAC_CNTL MEM_CNTL EXT_MEM_CNTL CRTC_GEN_CNTL "
2572                        "DSP_CONFIG DSP_ON_OFF CLOCK_CNTL\n"
2573                        "debug atyfb: %08x %08x %08x %08x     %08x      %08x   %08x   %08x\n"
2574                        "debug atyfb: PLL",
2575                         aty_ld_le32(BUS_CNTL, par), aty_ld_le32(DAC_CNTL, par),
2576                         aty_ld_le32(MEM_CNTL, par), aty_ld_le32(EXT_MEM_CNTL, par),
2577                         aty_ld_le32(CRTC_GEN_CNTL, par), aty_ld_le32(DSP_CONFIG, par),
2578                         aty_ld_le32(DSP_ON_OFF, par), aty_ld_le32(CLOCK_CNTL, par));
2579                 for (i = 0; i < 40; i++)
2580                         printk(" %02x", aty_ld_pll_ct(i, par));
2581                 printk("\n");
2582         }
2583 #endif
2584         if(par->pll_ops->init_pll)
2585                 par->pll_ops->init_pll(info, &par->pll);
2586         if (par->pll_ops->resume_pll)
2587                 par->pll_ops->resume_pll(info, &par->pll);
2588
2589         /*
2590          *  Last page of 8 MB (4 MB on ISA) aperture is MMIO,
2591          *  unless the auxiliary register aperture is used.
2592          */
2593
2594         if (!par->aux_start &&
2595                 (info->fix.smem_len == 0x800000 || (par->bus_type == ISA && info->fix.smem_len == 0x400000)))
2596                 info->fix.smem_len -= GUI_RESERVE;
2597
2598         /*
2599          *  Disable register access through the linear aperture
2600          *  if the auxiliary aperture is used so we can access
2601          *  the full 8 MB of video RAM on 8 MB boards.
2602          */
2603         if (par->aux_start)
2604                 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL, par) | BUS_APER_REG_DIS, par);
2605
2606 #ifdef CONFIG_MTRR
2607         par->mtrr_aper = -1;
2608         par->mtrr_reg = -1;
2609         if (!nomtrr) {
2610                 /* Cover the whole resource. */
2611                  par->mtrr_aper = mtrr_add(par->res_start, par->res_size, MTRR_TYPE_WRCOMB, 1);
2612                  if (par->mtrr_aper >= 0 && !par->aux_start) {
2613                         /* Make a hole for mmio. */
2614                         par->mtrr_reg = mtrr_add(par->res_start + 0x800000 - GUI_RESERVE,
2615                                 GUI_RESERVE, MTRR_TYPE_UNCACHABLE, 1);
2616                         if (par->mtrr_reg < 0) {
2617                                 mtrr_del(par->mtrr_aper, 0, 0);
2618                                 par->mtrr_aper = -1;
2619                         }
2620                  }
2621         }
2622 #endif
2623
2624         info->fbops = &atyfb_ops;
2625         info->pseudo_palette = pseudo_palette;
2626         info->flags = FBINFO_DEFAULT           |
2627                       FBINFO_HWACCEL_IMAGEBLIT |
2628                       FBINFO_HWACCEL_FILLRECT  |
2629                       FBINFO_HWACCEL_COPYAREA  |
2630                       FBINFO_HWACCEL_YPAN;
2631
2632 #ifdef CONFIG_PMAC_BACKLIGHT
2633         if (M64_HAS(G3_PB_1_1) && machine_is_compatible("PowerBook1,1")) {
2634                 /* these bits let the 101 powerbook wake up from sleep -- paulus */
2635                 aty_st_lcd(POWER_MANAGEMENT, aty_ld_lcd(POWER_MANAGEMENT, par)
2636                            | (USE_F32KHZ | TRISTATE_MEM_EN), par);
2637         } else
2638 #endif
2639         if (M64_HAS(MOBIL_BUS)) {
2640 #ifdef CONFIG_FB_ATY_BACKLIGHT
2641                 aty_bl_init (par);
2642 #endif
2643         }
2644
2645         memset(&var, 0, sizeof(var));
2646 #ifdef CONFIG_PPC
2647         if (machine_is(powermac)) {
2648                 /*
2649                  *  FIXME: The NVRAM stuff should be put in a Mac-specific file, as it
2650                  *         applies to all Mac video cards
2651                  */
2652                 if (mode) {
2653                         if (mac_find_mode(&var, info, mode, 8))
2654                                 has_var = 1;
2655                 } else {
2656                         if (default_vmode == VMODE_CHOOSE) {
2657                                 int sense;
2658                                 if (M64_HAS(G3_PB_1024x768))
2659                                         /* G3 PowerBook with 1024x768 LCD */
2660                                         default_vmode = VMODE_1024_768_60;
2661                                 else if (machine_is_compatible("iMac"))
2662                                         default_vmode = VMODE_1024_768_75;
2663                                 else if (machine_is_compatible
2664                                          ("PowerBook2,1"))
2665                                         /* iBook with 800x600 LCD */
2666                                         default_vmode = VMODE_800_600_60;
2667                                 else
2668                                         default_vmode = VMODE_640_480_67;
2669                                 sense = read_aty_sense(par);
2670                                 PRINTKI("monitor sense=%x, mode %d\n",
2671                                         sense,  mac_map_monitor_sense(sense));
2672                         }
2673                         if (default_vmode <= 0 || default_vmode > VMODE_MAX)
2674                                 default_vmode = VMODE_640_480_60;
2675                         if (default_cmode < CMODE_8 || default_cmode > CMODE_32)
2676                                 default_cmode = CMODE_8;
2677                         if (!mac_vmode_to_var(default_vmode, default_cmode,
2678                                                &var))
2679                                 has_var = 1;
2680                 }
2681         }
2682
2683 #endif /* !CONFIG_PPC */
2684
2685 #if defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD)
2686         if (!atyfb_get_timings_from_lcd(par, &var))
2687                 has_var = 1;
2688 #endif
2689
2690         if (mode && fb_find_mode(&var, info, mode, NULL, 0, &defmode, 8))
2691                 has_var = 1;
2692
2693         if (!has_var)
2694                 var = default_var;
2695
2696         if (noaccel)
2697                 var.accel_flags &= ~FB_ACCELF_TEXT;
2698         else
2699                 var.accel_flags |= FB_ACCELF_TEXT;
2700
2701         if (comp_sync != -1) {
2702                 if (!comp_sync)
2703                         var.sync &= ~FB_SYNC_COMP_HIGH_ACT;
2704                 else
2705                         var.sync |= FB_SYNC_COMP_HIGH_ACT;
2706         }
2707
2708         if (var.yres == var.yres_virtual) {
2709                 u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
2710                 var.yres_virtual = ((videoram * 8) / var.bits_per_pixel) / var.xres_virtual;
2711                 if (var.yres_virtual < var.yres)
2712                         var.yres_virtual = var.yres;
2713         }
2714
2715         if (atyfb_check_var(&var, info)) {
2716                 PRINTKE("can't set default video mode\n");
2717                 goto aty_init_exit;
2718         }
2719
2720 #ifdef __sparc__
2721         atyfb_save_palette(par, 0);
2722 #endif
2723
2724 #ifdef CONFIG_FB_ATY_CT
2725         if (!noaccel && M64_HAS(INTEGRATED))
2726                 aty_init_cursor(info);
2727 #endif /* CONFIG_FB_ATY_CT */
2728         info->var = var;
2729
2730         fb_alloc_cmap(&info->cmap, 256, 0);
2731
2732         if (register_framebuffer(info) < 0)
2733                 goto aty_init_exit;
2734
2735         fb_list = info;
2736
2737         PRINTKI("fb%d: %s frame buffer device on %s\n",
2738                 info->node, info->fix.id, par->bus_type == ISA ? "ISA" : "PCI");
2739         return 0;
2740
2741 aty_init_exit:
2742         /* restore video mode */
2743         aty_set_crtc(par, &saved_crtc);
2744         par->pll_ops->set_pll(info, &saved_pll);
2745
2746 #ifdef CONFIG_MTRR
2747         if (par->mtrr_reg >= 0) {
2748             mtrr_del(par->mtrr_reg, 0, 0);
2749             par->mtrr_reg = -1;
2750         }
2751         if (par->mtrr_aper >= 0) {
2752             mtrr_del(par->mtrr_aper, 0, 0);
2753             par->mtrr_aper = -1;
2754         }
2755 #endif
2756         return -1;
2757 }
2758
2759 static void aty_resume_chip(struct fb_info *info)
2760 {
2761         struct atyfb_par *par = info->par;
2762
2763         aty_st_le32(MEM_CNTL, par->mem_cntl, par);
2764
2765         if (par->pll_ops->resume_pll)
2766                 par->pll_ops->resume_pll(info, &par->pll);
2767
2768         if (par->aux_start)
2769                 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL, par) | BUS_APER_REG_DIS, par);
2770 }
2771
2772 #ifdef CONFIG_ATARI
2773 static int __devinit store_video_par(char *video_str, unsigned char m64_num)
2774 {
2775         char *p;
2776         unsigned long vmembase, size, guiregbase;
2777
2778         PRINTKI("store_video_par() '%s' \n", video_str);
2779
2780         if (!(p = strsep(&video_str, ";")) || !*p)
2781                 goto mach64_invalid;
2782         vmembase = simple_strtoul(p, NULL, 0);
2783         if (!(p = strsep(&video_str, ";")) || !*p)
2784                 goto mach64_invalid;
2785         size = simple_strtoul(p, NULL, 0);
2786         if (!(p = strsep(&video_str, ";")) || !*p)
2787                 goto mach64_invalid;
2788         guiregbase = simple_strtoul(p, NULL, 0);
2789
2790         phys_vmembase[m64_num] = vmembase;
2791         phys_size[m64_num] = size;
2792         phys_guiregbase[m64_num] = guiregbase;
2793         PRINTKI("stored them all: $%08lX $%08lX $%08lX \n", vmembase, size,
2794                guiregbase);
2795         return 0;
2796
2797       mach64_invalid:
2798         phys_vmembase[m64_num] = 0;
2799         return -1;
2800 }
2801 #endif /* CONFIG_ATARI */
2802
2803     /*
2804      *  Blank the display.
2805      */
2806
2807 static int atyfb_blank(int blank, struct fb_info *info)
2808 {
2809         struct atyfb_par *par = (struct atyfb_par *) info->par;
2810         u32 gen_cntl;
2811
2812         if (par->lock_blank || par->asleep)
2813                 return 0;
2814
2815 #ifdef CONFIG_FB_ATY_BACKLIGHT
2816         if (machine_is(powermac) && blank > FB_BLANK_NORMAL)
2817                 aty_bl_set_power(info, FB_BLANK_POWERDOWN);
2818 #elif defined(CONFIG_FB_ATY_GENERIC_LCD)
2819         if (par->lcd_table && blank > FB_BLANK_NORMAL &&
2820             (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2821                 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2822                 pm &= ~PWR_BLON;
2823                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2824         }
2825 #endif
2826
2827         gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
2828         gen_cntl &= ~0x400004c;
2829         switch (blank) {
2830                 case FB_BLANK_UNBLANK:
2831                         break;
2832                 case FB_BLANK_NORMAL:
2833                         gen_cntl |= 0x4000040;
2834                         break;
2835                 case FB_BLANK_VSYNC_SUSPEND:
2836                         gen_cntl |= 0x4000048;
2837                         break;
2838                 case FB_BLANK_HSYNC_SUSPEND:
2839                         gen_cntl |= 0x4000044;
2840                         break;
2841                 case FB_BLANK_POWERDOWN:
2842                         gen_cntl |= 0x400004c;
2843                         break;
2844         }
2845         aty_st_le32(CRTC_GEN_CNTL, gen_cntl, par);
2846
2847 #ifdef CONFIG_FB_ATY_BACKLIGHT
2848         if (machine_is(powermac) && blank <= FB_BLANK_NORMAL)
2849                 aty_bl_set_power(info, FB_BLANK_UNBLANK);
2850 #elif defined(CONFIG_FB_ATY_GENERIC_LCD)
2851         if (par->lcd_table && blank <= FB_BLANK_NORMAL &&
2852             (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2853                 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2854                 pm |= PWR_BLON;
2855                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2856         }
2857 #endif
2858
2859         return 0;
2860 }
2861
2862 static void aty_st_pal(u_int regno, u_int red, u_int green, u_int blue,
2863                        const struct atyfb_par *par)
2864 {
2865         aty_st_8(DAC_W_INDEX, regno, par);
2866         aty_st_8(DAC_DATA, red, par);
2867         aty_st_8(DAC_DATA, green, par);
2868         aty_st_8(DAC_DATA, blue, par);
2869 }
2870
2871     /*
2872      *  Set a single color register. The values supplied are already
2873      *  rounded down to the hardware's capabilities (according to the
2874      *  entries in the var structure). Return != 0 for invalid regno.
2875      *  !! 4 & 8 =  PSEUDO, > 8 = DIRECTCOLOR
2876      */
2877
2878 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
2879         u_int transp, struct fb_info *info)
2880 {
2881         struct atyfb_par *par = (struct atyfb_par *) info->par;
2882         int i, depth;
2883         u32 *pal = info->pseudo_palette;
2884
2885         depth = info->var.bits_per_pixel;
2886         if (depth == 16)
2887                 depth = (info->var.green.length == 5) ? 15 : 16;
2888
2889         if (par->asleep)
2890                 return 0;
2891
2892         if (regno > 255 ||
2893             (depth == 16 && regno > 63) ||
2894             (depth == 15 && regno > 31))
2895                 return 1;
2896
2897         red >>= 8;
2898         green >>= 8;
2899         blue >>= 8;
2900
2901         par->palette[regno].red = red;
2902         par->palette[regno].green = green;
2903         par->palette[regno].blue = blue;
2904
2905         if (regno < 16) {
2906                 switch (depth) {
2907                 case 15:
2908                         pal[regno] = (regno << 10) | (regno << 5) | regno;
2909                         break;
2910                 case 16:
2911                         pal[regno] = (regno << 11) | (regno << 5) | regno;
2912                         break;
2913                 case 24:
2914                         pal[regno] = (regno << 16) | (regno << 8) | regno;
2915                         break;
2916                 case 32:
2917                         i = (regno << 8) | regno;
2918                         pal[regno] = (i << 16) | i;
2919                         break;
2920                 }
2921         }
2922
2923         i = aty_ld_8(DAC_CNTL, par) & 0xfc;
2924         if (M64_HAS(EXTRA_BRIGHT))
2925                 i |= 0x2; /* DAC_CNTL | 0x2 turns off the extra brightness for gt */
2926         aty_st_8(DAC_CNTL, i, par);
2927         aty_st_8(DAC_MASK, 0xff, par);
2928
2929         if (M64_HAS(INTEGRATED)) {
2930                 if (depth == 16) {
2931                         if (regno < 32)
2932                                 aty_st_pal(regno << 3, red,
2933                                            par->palette[regno<<1].green,
2934                                            blue, par);
2935                         red = par->palette[regno>>1].red;
2936                         blue = par->palette[regno>>1].blue;
2937                         regno <<= 2;
2938                 } else if (depth == 15) {
2939                         regno <<= 3;
2940                         for(i = 0; i < 8; i++) {
2941                             aty_st_pal(regno + i, red, green, blue, par);
2942                         }
2943                 }
2944         }
2945         aty_st_pal(regno, red, green, blue, par);
2946
2947         return 0;
2948 }
2949
2950 #ifdef CONFIG_PCI
2951
2952 #ifdef __sparc__
2953
2954 extern void (*prom_palette) (int);
2955
2956 static int __devinit atyfb_setup_sparc(struct pci_dev *pdev,
2957                         struct fb_info *info, unsigned long addr)
2958 {
2959         struct atyfb_par *par = info->par;
2960         struct pcidev_cookie *pcp;
2961         char prop[128];
2962         int node, len, i, j, ret;
2963         u32 mem, chip_id;
2964
2965         /* Do not attach when we have a serial console. */
2966         if (!con_is_present())
2967                 return -ENXIO;
2968
2969         /*
2970          * Map memory-mapped registers.
2971          */
2972         par->ati_regbase = (void *)addr + 0x7ffc00UL;
2973         info->fix.mmio_start = addr + 0x7ffc00UL;
2974
2975         /*
2976          * Map in big-endian aperture.
2977          */
2978         info->screen_base = (char *) (addr + 0x800000UL);
2979         info->fix.smem_start = addr + 0x800000UL;
2980
2981         /*
2982          * Figure mmap addresses from PCI config space.
2983          * Split Framebuffer in big- and little-endian halfs.
2984          */
2985         for (i = 0; i < 6 && pdev->resource[i].start; i++)
2986                 /* nothing */ ;
2987         j = i + 4;
2988
2989         par->mmap_map = kmalloc(j * sizeof(*par->mmap_map), GFP_ATOMIC);
2990         if (!par->mmap_map) {
2991                 PRINTKE("atyfb_setup_sparc() can't alloc mmap_map\n");
2992                 return -ENOMEM;
2993         }
2994         memset(par->mmap_map, 0, j * sizeof(*par->mmap_map));
2995
2996         for (i = 0, j = 2; i < 6 && pdev->resource[i].start; i++) {
2997                 struct resource *rp = &pdev->resource[i];
2998                 int io, breg = PCI_BASE_ADDRESS_0 + (i << 2);
2999                 unsigned long base;
3000                 u32 size, pbase;
3001
3002                 base = rp->start;
3003
3004                 io = (rp->flags & IORESOURCE_IO);
3005
3006                 size = rp->end - base + 1;
3007
3008                 pci_read_config_dword(pdev, breg, &pbase);
3009
3010                 if (io)
3011                         size &= ~1;
3012
3013                 /*
3014                  * Map the framebuffer a second time, this time without
3015                  * the braindead _PAGE_IE setting. This is used by the
3016                  * fixed Xserver, but we need to maintain the old mapping
3017                  * to stay compatible with older ones...
3018                  */
3019                 if (base == addr) {
3020                         par->mmap_map[j].voff = (pbase + 0x10000000) & PAGE_MASK;
3021                         par->mmap_map[j].poff = base & PAGE_MASK;
3022                         par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
3023                         par->mmap_map[j].prot_mask = _PAGE_CACHE;
3024                         par->mmap_map[j].prot_flag = _PAGE_E;
3025                         j++;
3026                 }
3027
3028                 /*
3029                  * Here comes the old framebuffer mapping with _PAGE_IE
3030                  * set for the big endian half of the framebuffer...
3031                  */
3032                 if (base == addr) {
3033                         par->mmap_map[j].voff = (pbase + 0x800000) & PAGE_MASK;
3034                         par->mmap_map[j].poff = (base + 0x800000) & PAGE_MASK;
3035                         par->mmap_map[j].size = 0x800000;
3036                         par->mmap_map[j].prot_mask = _PAGE_CACHE;
3037                         par->mmap_map[j].prot_flag = _PAGE_E | _PAGE_IE;
3038                         size -= 0x800000;
3039                         j++;
3040                 }
3041
3042                 par->mmap_map[j].voff = pbase & PAGE_MASK;
3043                 par->mmap_map[j].poff = base & PAGE_MASK;
3044                 par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
3045                 par->mmap_map[j].prot_mask = _PAGE_CACHE;
3046                 par->mmap_map[j].prot_flag = _PAGE_E;
3047                 j++;
3048         }
3049
3050         if((ret = correct_chipset(par)))
3051                 return ret;
3052
3053         if (IS_XL(pdev->device)) {
3054                 /*
3055                  * Fix PROMs idea of MEM_CNTL settings...
3056                  */
3057                 mem = aty_ld_le32(MEM_CNTL, par);
3058                 chip_id = aty_ld_le32(CONFIG_CHIP_ID, par);
3059                 if (((chip_id & CFG_CHIP_TYPE) == VT_CHIP_ID) && !((chip_id >> 24) & 1)) {
3060                         switch (mem & 0x0f) {
3061                         case 3:
3062                                 mem = (mem & ~(0x0f)) | 2;
3063                                 break;
3064                         case 7:
3065                                 mem = (mem & ~(0x0f)) | 3;
3066                                 break;
3067                         case 9:
3068                                 mem = (mem & ~(0x0f)) | 4;
3069                                 break;
3070                         case 11:
3071                                 mem = (mem & ~(0x0f)) | 5;
3072                                 break;
3073                         default:
3074                                 break;
3075                         }
3076                         if ((aty_ld_le32(CONFIG_STAT0, par) & 7) >= SDRAM)
3077                                 mem &= ~(0x00700000);
3078                 }
3079                 mem &= ~(0xcf80e000);   /* Turn off all undocumented bits. */
3080                 aty_st_le32(MEM_CNTL, mem, par);
3081         }
3082
3083         /*
3084          * If this is the console device, we will set default video
3085          * settings to what the PROM left us with.
3086          */
3087         node = prom_getchild(prom_root_node);
3088         node = prom_searchsiblings(node, "aliases");
3089         if (node) {
3090                 len = prom_getproperty(node, "screen", prop, sizeof(prop));
3091                 if (len > 0) {
3092                         prop[len] = '\0';
3093                         node = prom_finddevice(prop);
3094                 } else
3095                         node = 0;
3096         }
3097
3098         pcp = pdev->sysdata;
3099         if (node == pcp->prom_node->node) {
3100                 struct fb_var_screeninfo *var = &default_var;
3101                 unsigned int N, P, Q, M, T, R;
3102                 u32 v_total, h_total;
3103                 struct crtc crtc;
3104                 u8 pll_regs[16];
3105                 u8 clock_cntl;
3106
3107                 crtc.vxres = prom_getintdefault(node, "width", 1024);
3108                 crtc.vyres = prom_getintdefault(node, "height", 768);
3109                 var->bits_per_pixel = prom_getintdefault(node, "depth", 8);
3110                 var->xoffset = var->yoffset = 0;
3111                 crtc.h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
3112                 crtc.h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
3113                 crtc.v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
3114                 crtc.v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
3115                 crtc.gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
3116                 aty_crtc_to_var(&crtc, var);
3117
3118                 h_total = var->xres + var->right_margin + var->hsync_len + var->left_margin;
3119                 v_total = var->yres + var->lower_margin + var->vsync_len + var->upper_margin;
3120
3121                 /*
3122                  * Read the PLL to figure actual Refresh Rate.
3123                  */
3124                 clock_cntl = aty_ld_8(CLOCK_CNTL, par);
3125                 /* DPRINTK("CLOCK_CNTL %02x\n", clock_cntl); */
3126                 for (i = 0; i < 16; i++)
3127                         pll_regs[i] = aty_ld_pll_ct(i, par);
3128
3129                 /*
3130                  * PLL Reference Divider M:
3131                  */
3132                 M = pll_regs[2];
3133
3134                 /*
3135                  * PLL Feedback Divider N (Dependant on CLOCK_CNTL):
3136                  */
3137                 N = pll_regs[7 + (clock_cntl & 3)];
3138
3139                 /*
3140                  * PLL Post Divider P (Dependant on CLOCK_CNTL):
3141                  */
3142                 P = 1 << (pll_regs[6] >> ((clock_cntl & 3) << 1));
3143
3144                 /*
3145                  * PLL Divider Q:
3146                  */
3147                 Q = N / P;
3148
3149                 /*
3150                  * Target Frequency:
3151                  *
3152                  *      T * M
3153                  * Q = -------
3154                  *      2 * R
3155                  *
3156                  * where R is XTALIN (= 14318 or 29498 kHz).
3157                  */
3158                 if (IS_XL(pdev->device))
3159                         R = 29498;
3160                 else
3161                         R = 14318;
3162
3163                 T = 2 * Q * R / M;
3164
3165                 default_var.pixclock = 1000000000 / T;
3166         }
3167
3168         return 0;
3169 }
3170
3171 #else /* __sparc__ */
3172
3173 #ifdef __i386__
3174 #ifdef CONFIG_FB_ATY_GENERIC_LCD
3175 static void __devinit aty_init_lcd(struct atyfb_par *par, u32 bios_base)
3176 {
3177         u32 driv_inf_tab, sig;
3178         u16 lcd_ofs;
3179
3180         /* To support an LCD panel, we should know it's dimensions and
3181          *  it's desired pixel clock.
3182          * There are two ways to do it:
3183          *  - Check the startup video mode and calculate the panel
3184          *    size from it. This is unreliable.
3185          *  - Read it from the driver information table in the video BIOS.
3186         */
3187         /* Address of driver information table is at offset 0x78. */
3188         driv_inf_tab = bios_base + *((u16 *)(bios_base+0x78));
3189
3190         /* Check for the driver information table signature. */
3191         sig = (*(u32 *)driv_inf_tab);
3192         if ((sig == 0x54504c24) || /* Rage LT pro */
3193                 (sig == 0x544d5224) || /* Rage mobility */
3194                 (sig == 0x54435824) || /* Rage XC */
3195                 (sig == 0x544c5824)) { /* Rage XL */
3196                 PRINTKI("BIOS contains driver information table.\n");
3197                 lcd_ofs = (*(u16 *)(driv_inf_tab + 10));
3198                 par->lcd_table = 0;
3199                 if (lcd_ofs != 0) {
3200                         par->lcd_table = bios_base + lcd_ofs;
3201                 }
3202         }
3203
3204         if (par->lcd_table != 0) {
3205                 char model[24];
3206                 char strbuf[16];
3207                 char refresh_rates_buf[100];
3208                 int id, tech, f, i, m, default_refresh_rate;
3209                 char *txtcolour;
3210                 char *txtmonitor;
3211                 char *txtdual;
3212                 char *txtformat;
3213                 u16 width, height, panel_type, refresh_rates;
3214                 u16 *lcdmodeptr;
3215                 u32 format;
3216                 u8 lcd_refresh_rates[16] = {50,56,60,67,70,72,75,76,85,90,100,120,140,150,160,200};
3217                 /* The most important information is the panel size at
3218                  * offset 25 and 27, but there's some other nice information
3219                  * which we print to the screen.
3220                  */
3221                 id = *(u8 *)par->lcd_table;
3222                 strncpy(model,(char *)par->lcd_table+1,24);
3223                 model[23]=0;
3224
3225                 width = par->lcd_width = *(u16 *)(par->lcd_table+25);
3226                 height = par->lcd_height = *(u16 *)(par->lcd_table+27);
3227                 panel_type = *(u16 *)(par->lcd_table+29);
3228                 if (panel_type & 1)
3229                         txtcolour = "colour";
3230                 else
3231                         txtcolour = "monochrome";
3232                 if (panel_type & 2)
3233                         txtdual = "dual (split) ";
3234                 else
3235                         txtdual = "";
3236                 tech = (panel_type>>2) & 63;
3237                 switch (tech) {
3238                 case 0:
3239                         txtmonitor = "passive matrix";
3240                         break;
3241                 case 1:
3242                         txtmonitor = "active matrix";
3243                         break;
3244                 case 2:
3245                         txtmonitor = "active addressed STN";
3246                         break;
3247                 case 3:
3248                         txtmonitor = "EL";
3249                         break;
3250                 case 4:
3251                         txtmonitor = "plasma";
3252                         break;
3253                 default:
3254                         txtmonitor = "unknown";
3255                 }
3256                 format = *(u32 *)(par->lcd_table+57);
3257                 if (tech == 0 || tech == 2) {
3258                         switch (format & 7) {
3259                         case 0:
3260                                 txtformat = "12 bit interface";
3261                                 break;
3262                         case 1:
3263                                 txtformat = "16 bit interface";
3264                                 break;
3265                         case 2:
3266                                 txtformat = "24 bit interface";
3267                                 break;
3268                         default:
3269                                 txtformat = "unkown format";
3270                         }
3271                 } else {
3272                         switch (format & 7) {
3273                         case 0:
3274                                 txtformat = "8 colours";
3275                                 break;
3276                         case 1:
3277                                 txtformat = "512 colours";
3278                                 break;
3279                         case 2:
3280                                 txtformat = "4096 colours";
3281                                 break;
3282                         case 4:
3283                                 txtformat = "262144 colours (LT mode)";
3284                                 break;
3285                         case 5:
3286                                 txtformat = "16777216 colours";
3287                                 break;
3288                         case 6:
3289                                 txtformat = "262144 colours (FDPI-2 mode)";
3290                                 break;
3291                         default:
3292                                 txtformat = "unkown format";
3293                         }
3294                 }
3295                 PRINTKI("%s%s %s monitor detected: %s\n",
3296                         txtdual ,txtcolour, txtmonitor, model);
3297                 PRINTKI("       id=%d, %dx%d pixels, %s\n",
3298                         id, width, height, txtformat);
3299                 refresh_rates_buf[0] = 0;
3300                 refresh_rates = *(u16 *)(par->lcd_table+62);
3301                 m = 1;
3302                 f = 0;
3303                 for (i=0;i<16;i++) {
3304                         if (refresh_rates & m) {
3305                                 if (f == 0) {
3306                                         sprintf(strbuf, "%d", lcd_refresh_rates[i]);
3307                                         f++;
3308                                 } else {
3309                                         sprintf(strbuf, ",%d", lcd_refresh_rates[i]);
3310                                 }
3311                                 strcat(refresh_rates_buf,strbuf);
3312                         }
3313                         m = m << 1;
3314                 }
3315                 default_refresh_rate = (*(u8 *)(par->lcd_table+61) & 0xf0) >> 4;
3316                 PRINTKI("       supports refresh rates [%s], default %d Hz\n",
3317                         refresh_rates_buf, lcd_refresh_rates[default_refresh_rate]);
3318                 par->lcd_refreshrate = lcd_refresh_rates[default_refresh_rate];
3319                 /* We now need to determine the crtc parameters for the
3320                  * LCD monitor. This is tricky, because they are not stored
3321                  * individually in the BIOS. Instead, the BIOS contains a
3322                  * table of display modes that work for this monitor.
3323                  *
3324                  * The idea is that we search for a mode of the same dimensions
3325                  * as the dimensions of the LCD monitor. Say our LCD monitor
3326                  * is 800x600 pixels, we search for a 800x600 monitor.
3327                  * The CRTC parameters we find here are the ones that we need
3328                  * to use to simulate other resolutions on the LCD screen.
3329                  */
3330                 lcdmodeptr = (u16 *)(par->lcd_table + 64);
3331                 while (*lcdmodeptr != 0) {
3332                         u32 modeptr;
3333                         u16 mwidth, mheight, lcd_hsync_start, lcd_vsync_start;
3334                         modeptr = bios_base + *lcdmodeptr;
3335
3336                         mwidth = *((u16 *)(modeptr+0));
3337                         mheight = *((u16 *)(modeptr+2));
3338
3339                         if (mwidth == width && mheight == height) {
3340                                 par->lcd_pixclock = 100000000 / *((u16 *)(modeptr+9));
3341                                 par->lcd_htotal = *((u16 *)(modeptr+17)) & 511;
3342                                 par->lcd_hdisp = *((u16 *)(modeptr+19)) & 511;
3343                                 lcd_hsync_start = *((u16 *)(modeptr+21)) & 511;
3344                                 par->lcd_hsync_dly = (*((u16 *)(modeptr+21)) >> 9) & 7;
3345                                 par->lcd_hsync_len = *((u8 *)(modeptr+23)) & 63;
3346
3347                                 par->lcd_vtotal = *((u16 *)(modeptr+24)) & 2047;
3348                                 par->lcd_vdisp = *((u16 *)(modeptr+26)) & 2047;
3349                                 lcd_vsync_start = *((u16 *)(modeptr+28)) & 2047;
3350                                 par->lcd_vsync_len = (*((u16 *)(modeptr+28)) >> 11) & 31;
3351
3352                                 par->lcd_htotal = (par->lcd_htotal + 1) * 8;
3353                                 par->lcd_hdisp = (par->lcd_hdisp + 1) * 8;
3354                                 lcd_hsync_start = (lcd_hsync_start + 1) * 8;
3355                                 par->lcd_hsync_len = par->lcd_hsync_len * 8;
3356
3357                                 par->lcd_vtotal++;
3358                                 par->lcd_vdisp++;
3359                                 lcd_vsync_start++;
3360
3361                                 par->lcd_right_margin = lcd_hsync_start - par->lcd_hdisp;
3362                                 par->lcd_lower_margin = lcd_vsync_start - par->lcd_vdisp;
3363                                 par->lcd_hblank_len = par->lcd_htotal - par->lcd_hdisp;
3364                                 par->lcd_vblank_len = par->lcd_vtotal - par->lcd_vdisp;
3365                                 break;
3366                         }
3367
3368                         lcdmodeptr++;
3369                 }
3370                 if (*lcdmodeptr == 0) {
3371                         PRINTKE("LCD monitor CRTC parameters not found!!!\n");
3372                         /* To do: Switch to CRT if possible. */
3373                 } else {
3374                         PRINTKI("       LCD CRTC parameters: %d.%d  %d %d %d %d  %d %d %d %d\n",
3375                                 1000000 / par->lcd_pixclock, 1000000 % par->lcd_pixclock,
3376                                 par->lcd_hdisp,
3377                                 par->lcd_hdisp + par->lcd_right_margin,
3378                                 par->lcd_hdisp + par->lcd_right_margin
3379                                         + par->lcd_hsync_dly + par->lcd_hsync_len,
3380                                 par->lcd_htotal,
3381                                 par->lcd_vdisp,
3382                                 par->lcd_vdisp + par->lcd_lower_margin,
3383                                 par->lcd_vdisp + par->lcd_lower_margin + par->lcd_vsync_len,
3384                                 par->lcd_vtotal);
3385                         PRINTKI("                          : %d %d %d %d %d %d %d %d %d\n",
3386                                 par->lcd_pixclock,
3387                                 par->lcd_hblank_len - (par->lcd_right_margin +
3388                                         par->lcd_hsync_dly + par->lcd_hsync_len),
3389                                 par->lcd_hdisp,
3390                                 par->lcd_right_margin,
3391                                 par->lcd_hsync_len,
3392                                 par->lcd_vblank_len - (par->lcd_lower_margin + par->lcd_vsync_len),
3393                                 par->lcd_vdisp,
3394                                 par->lcd_lower_margin,
3395                                 par->lcd_vsync_len);
3396                 }
3397         }
3398 }
3399 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
3400
3401 static int __devinit init_from_bios(struct atyfb_par *par)
3402 {
3403         u32 bios_base, rom_addr;
3404         int ret;
3405
3406         rom_addr = 0xc0000 + ((aty_ld_le32(SCRATCH_REG1, par) & 0x7f) << 11);
3407         bios_base = (unsigned long)ioremap(rom_addr, 0x10000);
3408
3409         /* The BIOS starts with 0xaa55. */
3410         if (*((u16 *)bios_base) == 0xaa55) {
3411
3412                 u8 *bios_ptr;
3413                 u16 rom_table_offset, freq_table_offset;
3414                 PLL_BLOCK_MACH64 pll_block;
3415
3416                 PRINTKI("Mach64 BIOS is located at %x, mapped at %x.\n", rom_addr, bios_base);
3417
3418                 /* check for frequncy table */
3419                 bios_ptr = (u8*)bios_base;
3420                 rom_table_offset = (u16)(bios_ptr[0x48] | (bios_ptr[0x49] << 8));
3421                 freq_table_offset = bios_ptr[rom_table_offset + 16] | (bios_ptr[rom_table_offset + 17] << 8);
3422                 memcpy(&pll_block, bios_ptr + freq_table_offset, sizeof(PLL_BLOCK_MACH64));
3423
3424                 PRINTKI("BIOS frequency table:\n");
3425                 PRINTKI("PCLK_min_freq %d, PCLK_max_freq %d, ref_freq %d, ref_divider %d\n",
3426                         pll_block.PCLK_min_freq, pll_block.PCLK_max_freq,
3427                         pll_block.ref_freq, pll_block.ref_divider);
3428                 PRINTKI("MCLK_pwd %d, MCLK_max_freq %d, XCLK_max_freq %d, SCLK_freq %d\n",
3429                         pll_block.MCLK_pwd, pll_block.MCLK_max_freq,
3430                         pll_block.XCLK_max_freq, pll_block.SCLK_freq);
3431
3432                 par->pll_limits.pll_min = pll_block.PCLK_min_freq/100;
3433                 par->pll_limits.pll_max = pll_block.PCLK_max_freq/100;
3434                 par->pll_limits.ref_clk = pll_block.ref_freq/100;
3435                 par->pll_limits.ref_div = pll_block.ref_divider;
3436                 par->pll_limits.sclk = pll_block.SCLK_freq/100;
3437                 par->pll_limits.mclk = pll_block.MCLK_max_freq/100;
3438                 par->pll_limits.mclk_pm = pll_block.MCLK_pwd/100;
3439                 par->pll_limits.xclk = pll_block.XCLK_max_freq/100;
3440 #ifdef CONFIG_FB_ATY_GENERIC_LCD
3441                 aty_init_lcd(par, bios_base);
3442 #endif
3443                 ret = 0;
3444         } else {
3445                 PRINTKE("no BIOS frequency table found, use parameters\n");
3446                 ret = -ENXIO;
3447         }
3448         iounmap((void* __iomem )bios_base);
3449
3450         return ret;
3451 }
3452 #endif /* __i386__ */
3453
3454 static int __devinit atyfb_setup_generic(struct pci_dev *pdev, struct fb_info *info, unsigned long addr)
3455 {
3456         struct atyfb_par *par = info->par;
3457         u16 tmp;
3458         unsigned long raddr;
3459         struct resource *rrp;
3460         int ret = 0;
3461
3462         raddr = addr + 0x7ff000UL;
3463         rrp = &pdev->resource[2];
3464         if ((rrp->flags & IORESOURCE_MEM) && request_mem_region(rrp->start, rrp->end - rrp->start + 1, "atyfb")) {
3465                 par->aux_start = rrp->start;
3466                 par->aux_size = rrp->end - rrp->start + 1;
3467                 raddr = rrp->start;
3468                 PRINTKI("using auxiliary register aperture\n");
3469         }
3470
3471         info->fix.mmio_start = raddr;
3472         par->ati_regbase = ioremap(info->fix.mmio_start, 0x1000);
3473         if (par->ati_regbase == 0)
3474                 return -ENOMEM;
3475
3476         info->fix.mmio_start += par->aux_start ? 0x400 : 0xc00;
3477         par->ati_regbase += par->aux_start ? 0x400 : 0xc00;
3478
3479         /*
3480          * Enable memory-space accesses using config-space
3481          * command register.
3482          */
3483         pci_read_config_word(pdev, PCI_COMMAND, &tmp);
3484         if (!(tmp & PCI_COMMAND_MEMORY)) {
3485                 tmp |= PCI_COMMAND_MEMORY;
3486                 pci_write_config_word(pdev, PCI_COMMAND, tmp);
3487         }
3488 #ifdef __BIG_ENDIAN
3489         /* Use the big-endian aperture */
3490         addr += 0x800000;
3491 #endif
3492
3493         /* Map in frame buffer */
3494         info->fix.smem_start = addr;
3495         info->screen_base = ioremap(addr, 0x800000);
3496         if (info->screen_base == NULL) {
3497                 ret = -ENOMEM;
3498                 goto atyfb_setup_generic_fail;
3499         }
3500
3501         if((ret = correct_chipset(par)))
3502                 goto atyfb_setup_generic_fail;
3503 #ifdef __i386__
3504         if((ret = init_from_bios(par)))
3505                 goto atyfb_setup_generic_fail;
3506 #endif
3507         if (!(aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_EXT_DISP_EN))
3508                 par->clk_wr_offset = (inb(R_GENMO) & 0x0CU) >> 2;
3509         else
3510                 par->clk_wr_offset = aty_ld_8(CLOCK_CNTL, par) & 0x03U;
3511
3512         /* according to ATI, we should use clock 3 for acelerated mode */
3513         par->clk_wr_offset = 3;
3514
3515         return 0;
3516
3517 atyfb_setup_generic_fail:
3518         iounmap(par->ati_regbase);
3519         par->ati_regbase = NULL;
3520         if (info->screen_base) {
3521                 iounmap(info->screen_base);
3522                 info->screen_base = NULL;
3523         }
3524         return ret;
3525 }
3526
3527 #endif /* !__sparc__ */
3528
3529 static int __devinit atyfb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3530 {
3531         unsigned long addr, res_start, res_size;
3532         struct fb_info *info;
3533         struct resource *rp;
3534         struct atyfb_par *par;
3535         int i, rc = -ENOMEM;
3536
3537         for (i = ARRAY_SIZE(aty_chips) - 1; i >= 0; i--)
3538                 if (pdev->device == aty_chips[i].pci_id)
3539                         break;
3540
3541         if (i < 0)
3542                 return -ENODEV;
3543
3544         /* Enable device in PCI config */
3545         if (pci_enable_device(pdev)) {
3546                 PRINTKE("Cannot enable PCI device\n");
3547                 return -ENXIO;
3548         }
3549
3550         /* Find which resource to use */
3551         rp = &pdev->resource[0];
3552         if (rp->flags & IORESOURCE_IO)
3553                 rp = &pdev->resource[1];
3554         addr = rp->start;
3555         if (!addr)
3556                 return -ENXIO;
3557
3558         /* Reserve space */
3559         res_start = rp->start;
3560         res_size = rp->end - rp->start + 1;
3561         if (!request_mem_region (res_start, res_size, "atyfb"))
3562                 return -EBUSY;
3563
3564         /* Allocate framebuffer */
3565         info = framebuffer_alloc(sizeof(struct atyfb_par), &pdev->dev);
3566         if (!info) {
3567                 PRINTKE("atyfb_pci_probe() can't alloc fb_info\n");
3568                 return -ENOMEM;
3569         }
3570         par = info->par;
3571         info->fix = atyfb_fix;
3572         info->device = &pdev->dev;
3573         par->pci_id = aty_chips[i].pci_id;
3574         par->res_start = res_start;
3575         par->res_size = res_size;
3576         par->irq = pdev->irq;
3577         par->pdev = pdev;
3578
3579         /* Setup "info" structure */
3580 #ifdef __sparc__
3581         rc = atyfb_setup_sparc(pdev, info, addr);
3582 #else
3583         rc = atyfb_setup_generic(pdev, info, addr);
3584 #endif
3585         if (rc)
3586                 goto err_release_mem;
3587
3588         pci_set_drvdata(pdev, info);
3589
3590         /* Init chip & register framebuffer */
3591         if (aty_init(info))
3592                 goto err_release_io;
3593
3594 #ifdef __sparc__
3595         if (!prom_palette)
3596                 prom_palette = atyfb_palette;
3597
3598         /*
3599          * Add /dev/fb mmap values.
3600          */
3601         par->mmap_map[0].voff = 0x8000000000000000UL;
3602         par->mmap_map[0].poff = (unsigned long) info->screen_base & PAGE_MASK;
3603         par->mmap_map[0].size = info->fix.smem_len;
3604         par->mmap_map[0].prot_mask = _PAGE_CACHE;
3605         par->mmap_map[0].prot_flag = _PAGE_E;
3606         par->mmap_map[1].voff = par->mmap_map[0].voff + info->fix.smem_len;
3607         par->mmap_map[1].poff = (long)par->ati_regbase & PAGE_MASK;
3608         par->mmap_map[1].size = PAGE_SIZE;
3609         par->mmap_map[1].prot_mask = _PAGE_CACHE;
3610         par->mmap_map[1].prot_flag = _PAGE_E;
3611 #endif /* __sparc__ */
3612
3613         return 0;
3614
3615 err_release_io:
3616 #ifdef __sparc__
3617         kfree(par->mmap_map);
3618 #else
3619         if (par->ati_regbase)
3620                 iounmap(par->ati_regbase);
3621         if (info->screen_base)
3622                 iounmap(info->screen_base);
3623 #endif
3624 err_release_mem:
3625         if (par->aux_start)
3626                 release_mem_region(par->aux_start, par->aux_size);
3627
3628         release_mem_region(par->res_start, par->res_size);
3629         framebuffer_release(info);
3630
3631         return rc;
3632 }
3633
3634 #endif /* CONFIG_PCI */
3635
3636 #ifdef CONFIG_ATARI
3637
3638 static int __init atyfb_atari_probe(void)
3639 {
3640         struct atyfb_par *par;
3641         struct fb_info *info;
3642         int m64_num;
3643         u32 clock_r;
3644         int num_found = 0;
3645
3646         for (m64_num = 0; m64_num < mach64_count; m64_num++) {
3647                 if (!phys_vmembase[m64_num] || !phys_size[m64_num] ||
3648                     !phys_guiregbase[m64_num]) {
3649                     PRINTKI("phys_*[%d] parameters not set => returning early. \n", m64_num);
3650                         continue;
3651                 }
3652
3653                 info = framebuffer_alloc(sizeof(struct atyfb_par), NULL);
3654                 if (!info) {
3655                         PRINTKE("atyfb_atari_probe() can't alloc fb_info\n");
3656                         return -ENOMEM;
3657                 }
3658                 par = info->par;
3659
3660                 info->fix = atyfb_fix;
3661
3662                 par->irq = (unsigned int) -1; /* something invalid */
3663
3664                 /*
3665                  *  Map the video memory (physical address given) to somewhere in the
3666                  *  kernel address space.
3667                  */
3668                 info->screen_base = ioremap(phys_vmembase[m64_num], phys_size[m64_num]);
3669                 info->fix.smem_start = (unsigned long)info->screen_base; /* Fake! */
3670                 par->ati_regbase = ioremap(phys_guiregbase[m64_num], 0x10000) +
3671                                                 0xFC00ul;
3672                 info->fix.mmio_start = (unsigned long)par->ati_regbase; /* Fake! */
3673
3674                 aty_st_le32(CLOCK_CNTL, 0x12345678, par);
3675                 clock_r = aty_ld_le32(CLOCK_CNTL, par);
3676
3677                 switch (clock_r & 0x003F) {
3678                 case 0x12:
3679                         par->clk_wr_offset = 3; /*  */
3680                         break;
3681                 case 0x34:
3682                         par->clk_wr_offset = 2; /* Medusa ST-IO ISA Adapter etc. */
3683                         break;
3684                 case 0x16:
3685                         par->clk_wr_offset = 1; /*  */
3686                         break;
3687                 case 0x38:
3688                         par->clk_wr_offset = 0; /* Panther 1 ISA Adapter (Gerald) */
3689                         break;
3690                 }
3691
3692                 /* Fake pci_id for correct_chipset() */
3693                 switch (aty_ld_le32(CONFIG_CHIP_ID, par) & CFG_CHIP_TYPE) {
3694                 case 0x00d7:
3695                         par->pci_id = PCI_CHIP_MACH64GX;
3696                         break;
3697                 case 0x0057:
3698                         par->pci_id = PCI_CHIP_MACH64CX;
3699                         break;
3700                 default:
3701                         break;
3702                 }
3703
3704                 if (correct_chipset(par) || aty_init(info)) {
3705                         iounmap(info->screen_base);
3706                         iounmap(par->ati_regbase);
3707                         framebuffer_release(info);
3708                 } else {
3709                         num_found++;
3710                 }
3711         }
3712
3713         return num_found ? 0 : -ENXIO;
3714 }
3715
3716 #endif /* CONFIG_ATARI */
3717
3718 #ifdef CONFIG_PCI
3719
3720 static void __devexit atyfb_remove(struct fb_info *info)
3721 {
3722         struct atyfb_par *par = (struct atyfb_par *) info->par;
3723
3724         /* restore video mode */
3725         aty_set_crtc(par, &saved_crtc);
3726         par->pll_ops->set_pll(info, &saved_pll);
3727
3728 #ifdef CONFIG_FB_ATY_BACKLIGHT
3729         if (M64_HAS(MOBIL_BUS))
3730                 aty_bl_exit(par);
3731 #endif
3732
3733         unregister_framebuffer(info);
3734
3735 #ifdef CONFIG_MTRR
3736         if (par->mtrr_reg >= 0) {
3737             mtrr_del(par->mtrr_reg, 0, 0);
3738             par->mtrr_reg = -1;
3739         }
3740         if (par->mtrr_aper >= 0) {
3741             mtrr_del(par->mtrr_aper, 0, 0);
3742             par->mtrr_aper = -1;
3743         }
3744 #endif
3745 #ifndef __sparc__
3746         if (par->ati_regbase)
3747                 iounmap(par->ati_regbase);
3748         if (info->screen_base)
3749                 iounmap(info->screen_base);
3750 #ifdef __BIG_ENDIAN
3751         if (info->sprite.addr)
3752                 iounmap(info->sprite.addr);
3753 #endif
3754 #endif
3755 #ifdef __sparc__
3756         kfree(par->mmap_map);
3757 #endif
3758         if (par->aux_start)
3759                 release_mem_region(par->aux_start, par->aux_size);
3760
3761         if (par->res_start)
3762                 release_mem_region(par->res_start, par->res_size);
3763
3764         framebuffer_release(info);
3765 }
3766
3767
3768 static void __devexit atyfb_pci_remove(struct pci_dev *pdev)
3769 {
3770         struct fb_info *info = pci_get_drvdata(pdev);
3771
3772         atyfb_remove(info);
3773 }
3774
3775 /*
3776  * This driver uses its own matching table. That will be more difficult
3777  * to fix, so for now, we just match against any ATI ID and let the
3778  * probe() function find out what's up. That also mean we don't have
3779  * a module ID table though.
3780  */
3781 static struct pci_device_id atyfb_pci_tbl[] = {
3782         { PCI_VENDOR_ID_ATI, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
3783           PCI_BASE_CLASS_DISPLAY << 16, 0xff0000, 0 },
3784         { 0, }
3785 };
3786
3787 static struct pci_driver atyfb_driver = {
3788         .name           = "atyfb",
3789         .id_table       = atyfb_pci_tbl,
3790         .probe          = atyfb_pci_probe,
3791         .remove         = __devexit_p(atyfb_pci_remove),
3792 #ifdef CONFIG_PM
3793         .suspend        = atyfb_pci_suspend,
3794         .resume         = atyfb_pci_resume,
3795 #endif /* CONFIG_PM */
3796 };
3797
3798 #endif /* CONFIG_PCI */
3799
3800 #ifndef MODULE
3801 static int __init atyfb_setup(char *options)
3802 {
3803         char *this_opt;
3804
3805         if (!options || !*options)
3806                 return 0;
3807
3808         while ((this_opt = strsep(&options, ",")) != NULL) {
3809                 if (!strncmp(this_opt, "noaccel", 7)) {
3810                         noaccel = 1;
3811 #ifdef CONFIG_MTRR
3812                 } else if (!strncmp(this_opt, "nomtrr", 6)) {
3813                         nomtrr = 1;
3814 #endif
3815                 } else if (!strncmp(this_opt, "vram:", 5))
3816                         vram = simple_strtoul(this_opt + 5, NULL, 0);
3817                 else if (!strncmp(this_opt, "pll:", 4))
3818                         pll = simple_strtoul(this_opt + 4, NULL, 0);
3819                 else if (!strncmp(this_opt, "mclk:", 5))
3820                         mclk = simple_strtoul(this_opt + 5, NULL, 0);
3821                 else if (!strncmp(this_opt, "xclk:", 5))
3822                         xclk = simple_strtoul(this_opt+5, NULL, 0);
3823                 else if (!strncmp(this_opt, "comp_sync:", 10))
3824                         comp_sync = simple_strtoul(this_opt+10, NULL, 0);
3825 #ifdef CONFIG_PPC
3826                 else if (!strncmp(this_opt, "vmode:", 6)) {
3827                         unsigned int vmode =
3828                             simple_strtoul(this_opt + 6, NULL, 0);
3829                         if (vmode > 0 && vmode <= VMODE_MAX)
3830                                 default_vmode = vmode;
3831                 } else if (!strncmp(this_opt, "cmode:", 6)) {
3832                         unsigned int cmode =
3833                             simple_strtoul(this_opt + 6, NULL, 0);
3834                         switch (cmode) {
3835                         case 0:
3836                         case 8:
3837                                 default_cmode = CMODE_8;
3838                                 break;
3839                         case 15:
3840                         case 16:
3841                                 default_cmode = CMODE_16;
3842                                 break;
3843                         case 24:
3844                         case 32:
3845                                 default_cmode = CMODE_32;
3846                                 break;
3847                         }
3848                 }
3849 #endif
3850 #ifdef CONFIG_ATARI
3851                 /*
3852                  * Why do we need this silly Mach64 argument?
3853                  * We are already here because of mach64= so its redundant.
3854                  */
3855                 else if (MACH_IS_ATARI
3856                          && (!strncmp(this_opt, "Mach64:", 7))) {
3857                         static unsigned char m64_num;
3858                         static char mach64_str[80];
3859                         strlcpy(mach64_str, this_opt + 7, sizeof(mach64_str));
3860                         if (!store_video_par(mach64_str, m64_num)) {
3861                                 m64_num++;
3862                                 mach64_count = m64_num;
3863                         }
3864                 }
3865 #endif
3866                 else
3867                         mode = this_opt;
3868         }
3869         return 0;
3870 }
3871 #endif  /*  MODULE  */
3872
3873 static int __init atyfb_init(void)
3874 {
3875     int err1 = 1, err2 = 1;
3876 #ifndef MODULE
3877     char *option = NULL;
3878
3879     if (fb_get_options("atyfb", &option))
3880         return -ENODEV;
3881     atyfb_setup(option);
3882 #endif
3883
3884 #ifdef CONFIG_PCI
3885     err1 = pci_register_driver(&atyfb_driver);
3886 #endif
3887 #ifdef CONFIG_ATARI
3888     err2 = atyfb_atari_probe();
3889 #endif
3890
3891     return (err1 && err2) ? -ENODEV : 0;
3892 }
3893
3894 static void __exit atyfb_exit(void)
3895 {
3896 #ifdef CONFIG_PCI
3897         pci_unregister_driver(&atyfb_driver);
3898 #endif
3899 }
3900
3901 module_init(atyfb_init);
3902 module_exit(atyfb_exit);
3903
3904 MODULE_DESCRIPTION("FBDev driver for ATI Mach64 cards");
3905 MODULE_LICENSE("GPL");
3906 module_param(noaccel, bool, 0);
3907 MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
3908 module_param(vram, int, 0);
3909 MODULE_PARM_DESC(vram, "int: override size of video ram");
3910 module_param(pll, int, 0);
3911 MODULE_PARM_DESC(pll, "int: override video clock");
3912 module_param(mclk, int, 0);
3913 MODULE_PARM_DESC(mclk, "int: override memory clock");
3914 module_param(xclk, int, 0);
3915 MODULE_PARM_DESC(xclk, "int: override accelerated engine clock");
3916 module_param(comp_sync, int, 0);
3917 MODULE_PARM_DESC(comp_sync,
3918                  "Set composite sync signal to low (0) or high (1)");
3919 module_param(mode, charp, 0);
3920 MODULE_PARM_DESC(mode, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
3921 #ifdef CONFIG_MTRR
3922 module_param(nomtrr, bool, 0);
3923 MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
3924 #endif