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   1 /*
   2  * SPU core / file system interface and HW structures
   3  *
   4  * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
   5  *
   6  * Author: Arnd Bergmann <arndb@de.ibm.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2, or (at your option)
  11  * any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #ifndef _SPU_H
  24 #define _SPU_H
  25 #ifdef __KERNEL__
  26
  27 #include <linux/config.h>
  28 #include <linux/kref.h>
  29 #include <linux/workqueue.h>
  30
  31 #define LS_SIZE (256 * 1024)
  32 #define LS_ADDR_MASK (LS_SIZE - 1)
  33
  34 #define MFC_PUT_CMD             0x20
  35 #define MFC_PUTS_CMD            0x28
  36 #define MFC_PUTR_CMD            0x30
  37 #define MFC_PUTF_CMD            0x22
  38 #define MFC_PUTB_CMD            0x21
  39 #define MFC_PUTFS_CMD           0x2A
  40 #define MFC_PUTBS_CMD           0x29
  41 #define MFC_PUTRF_CMD           0x32
  42 #define MFC_PUTRB_CMD           0x31
  43 #define MFC_PUTL_CMD            0x24
  44 #define MFC_PUTRL_CMD           0x34
  45 #define MFC_PUTLF_CMD           0x26
  46 #define MFC_PUTLB_CMD           0x25
  47 #define MFC_PUTRLF_CMD          0x36
  48 #define MFC_PUTRLB_CMD          0x35
  49
  50 #define MFC_GET_CMD             0x40
  51 #define MFC_GETS_CMD            0x48
  52 #define MFC_GETF_CMD            0x42
  53 #define MFC_GETB_CMD            0x41
  54 #define MFC_GETFS_CMD           0x4A
  55 #define MFC_GETBS_CMD           0x49
  56 #define MFC_GETL_CMD            0x44
  57 #define MFC_GETLF_CMD           0x46
  58 #define MFC_GETLB_CMD           0x45
  59
  60 #define MFC_SDCRT_CMD           0x80
  61 #define MFC_SDCRTST_CMD         0x81
  62 #define MFC_SDCRZ_CMD           0x89
  63 #define MFC_SDCRS_CMD           0x8D
  64 #define MFC_SDCRF_CMD           0x8F
  65
  66 #define MFC_GETLLAR_CMD         0xD0
  67 #define MFC_PUTLLC_CMD          0xB4
  68 #define MFC_PUTLLUC_CMD         0xB0
  69 #define MFC_PUTQLLUC_CMD        0xB8
  70 #define MFC_SNDSIG_CMD          0xA0
  71 #define MFC_SNDSIGB_CMD         0xA1
  72 #define MFC_SNDSIGF_CMD         0xA2
  73 #define MFC_BARRIER_CMD         0xC0
  74 #define MFC_EIEIO_CMD           0xC8
  75 #define MFC_SYNC_CMD            0xCC
  76
  77 #define MFC_MIN_DMA_SIZE_SHIFT  4       /* 16 bytes */
  78 #define MFC_MAX_DMA_SIZE_SHIFT  14      /* 16384 bytes */
  79 #define MFC_MIN_DMA_SIZE        (1 << MFC_MIN_DMA_SIZE_SHIFT)
  80 #define MFC_MAX_DMA_SIZE        (1 << MFC_MAX_DMA_SIZE_SHIFT)
  81 #define MFC_MIN_DMA_SIZE_MASK   (MFC_MIN_DMA_SIZE - 1)
  82 #define MFC_MAX_DMA_SIZE_MASK   (MFC_MAX_DMA_SIZE - 1)
  83 #define MFC_MIN_DMA_LIST_SIZE   0x0008  /*   8 bytes */
  84 #define MFC_MAX_DMA_LIST_SIZE   0x4000  /* 16K bytes */
  85
  86 #define MFC_TAGID_TO_TAGMASK(tag_id)  (1 << (tag_id & 0x1F))
  87
  88 /* Events for Channels 0-2 */
  89 #define MFC_DMA_TAG_STATUS_UPDATE_EVENT     0x00000001
  90 #define MFC_DMA_TAG_CMD_STALL_NOTIFY_EVENT  0x00000002
  91 #define MFC_DMA_QUEUE_AVAILABLE_EVENT       0x00000008
  92 #define MFC_SPU_MAILBOX_WRITTEN_EVENT       0x00000010
  93 #define MFC_DECREMENTER_EVENT               0x00000020
  94 #define MFC_PU_INT_MAILBOX_AVAILABLE_EVENT  0x00000040
  95 #define MFC_PU_MAILBOX_AVAILABLE_EVENT      0x00000080
  96 #define MFC_SIGNAL_2_EVENT                  0x00000100
  97 #define MFC_SIGNAL_1_EVENT                  0x00000200
  98 #define MFC_LLR_LOST_EVENT                  0x00000400
  99 #define MFC_PRIV_ATTN_EVENT                 0x00000800
 100 #define MFC_MULTI_SRC_EVENT                 0x00001000
 101
 102 /* Flags indicating progress during context switch. */
 103 #define SPU_CONTEXT_SWITCH_PENDING      0UL
 104 #define SPU_CONTEXT_SWITCH_ACTIVE       1UL
 105
 106 struct spu_context;
 107 struct spu_runqueue;
 108
 109 struct spu {
 110         char *name;
 111         unsigned long local_store_phys;
 112         u8 *local_store;
 113         struct spu_problem __iomem *problem;
 114         struct spu_priv1 __iomem *priv1;
 115         struct spu_priv2 __iomem *priv2;
 116         struct list_head list;
 117         struct list_head sched_list;
 118         int number;
 119         u32 isrc;
 120         u32 node;
 121         u64 flags;
 122         u64 dar;
 123         u64 dsisr;
 124         struct kref kref;
 125         size_t ls_size;
 126         unsigned int slb_replace;
 127         struct mm_struct *mm;
 128         struct spu_context *ctx;
 129         struct spu_runqueue *rq;
 130         unsigned long long timestamp;
 131         pid_t pid;
 132         int prio;
 133         int class_0_pending;
 134         spinlock_t register_lock;
 135
 136         u32 stop_code;
 137         void (* wbox_callback)(struct spu *spu);
 138         void (* ibox_callback)(struct spu *spu);
 139         void (* stop_callback)(struct spu *spu);
 140
 141         char irq_c0[8];
 142         char irq_c1[8];
 143         char irq_c2[8];
 144 };
 145
 146 struct spu *spu_alloc(void);
 147 void spu_free(struct spu *spu);
 148 int spu_irq_class_0_bottom(struct spu *spu);
 149 int spu_irq_class_1_bottom(struct spu *spu);
 150 void spu_irq_setaffinity(struct spu *spu, int cpu);
 151
 152 extern struct spufs_calls {
 153         asmlinkage long (*create_thread)(const char __user *name,
 154                                         unsigned int flags, mode_t mode);
 155         asmlinkage long (*spu_run)(struct file *filp, __u32 __user *unpc,
 156                                                 __u32 __user *ustatus);
 157         struct module *owner;
 158 } spufs_calls;
 159
 160 #ifdef CONFIG_SPU_FS_MODULE
 161 int register_spu_syscalls(struct spufs_calls *calls);
 162 void unregister_spu_syscalls(struct spufs_calls *calls);
 163 #else
 164 static inline int register_spu_syscalls(struct spufs_calls *calls)
 165 {
 166         return 0;
 167 }
 168 static inline void unregister_spu_syscalls(struct spufs_calls *calls)
 169 {
 170 }
 171 #endif /* MODULE */
 172
 173
 174 /* access to priv1 registers */
 175 void spu_int_mask_and(struct spu *spu, int class, u64 mask);
 176 void spu_int_mask_or(struct spu *spu, int class, u64 mask);
 177 void spu_int_mask_set(struct spu *spu, int class, u64 mask);
 178 u64 spu_int_mask_get(struct spu *spu, int class);
 179 void spu_int_stat_clear(struct spu *spu, int class, u64 stat);
 180 u64 spu_int_stat_get(struct spu *spu, int class);
 181 void spu_int_route_set(struct spu *spu, u64 route);
 182 u64 spu_mfc_dar_get(struct spu *spu);
 183 u64 spu_mfc_dsisr_get(struct spu *spu);
 184 void spu_mfc_dsisr_set(struct spu *spu, u64 dsisr);
 185 void spu_mfc_sdr_set(struct spu *spu, u64 sdr);
 186 void spu_mfc_sr1_set(struct spu *spu, u64 sr1);
 187 u64 spu_mfc_sr1_get(struct spu *spu);
 188 void spu_mfc_tclass_id_set(struct spu *spu, u64 tclass_id);
 189 u64 spu_mfc_tclass_id_get(struct spu *spu);
 190 void spu_tlb_invalidate(struct spu *spu);
 191 void spu_resource_allocation_groupID_set(struct spu *spu, u64 id);
 192 u64 spu_resource_allocation_groupID_get(struct spu *spu);
 193 void spu_resource_allocation_enable_set(struct spu *spu, u64 enable);
 194 u64 spu_resource_allocation_enable_get(struct spu *spu);
 195
 196
 197 /*
 198  * This defines the Local Store, Problem Area and Privlege Area of an SPU.
 199  */
 200
 201 union mfc_tag_size_class_cmd {
 202         struct {
 203                 u16 mfc_size;
 204                 u16 mfc_tag;
 205                 u8  pad;
 206                 u8  mfc_rclassid;
 207                 u16 mfc_cmd;
 208         } u;
 209         struct {
 210                 u32 mfc_size_tag32;
 211                 u32 mfc_class_cmd32;
 212         } by32;
 213         u64 all64;
 214 };
 215
 216 struct mfc_cq_sr {
 217         u64 mfc_cq_data0_RW;
 218         u64 mfc_cq_data1_RW;
 219         u64 mfc_cq_data2_RW;
 220         u64 mfc_cq_data3_RW;
 221 };
 222
 223 struct spu_problem {
 224 #define MS_SYNC_PENDING         1L
 225         u64 spc_mssync_RW;                                      /* 0x0000 */
 226         u8  pad_0x0008_0x3000[0x3000 - 0x0008];
 227
 228         /* DMA Area */
 229         u8  pad_0x3000_0x3004[0x4];                             /* 0x3000 */
 230         u32 mfc_lsa_W;                                          /* 0x3004 */
 231         u64 mfc_ea_W;                                           /* 0x3008 */
 232         union mfc_tag_size_class_cmd mfc_union_W;                       /* 0x3010 */
 233         u8  pad_0x3018_0x3104[0xec];                            /* 0x3018 */
 234         u32 dma_qstatus_R;                                      /* 0x3104 */
 235         u8  pad_0x3108_0x3204[0xfc];                            /* 0x3108 */
 236         u32 dma_querytype_RW;                                   /* 0x3204 */
 237         u8  pad_0x3208_0x321c[0x14];                            /* 0x3208 */
 238         u32 dma_querymask_RW;                                   /* 0x321c */
 239         u8  pad_0x3220_0x322c[0xc];                             /* 0x3220 */
 240         u32 dma_tagstatus_R;                                    /* 0x322c */
 241 #define DMA_TAGSTATUS_INTR_ANY  1u
 242 #define DMA_TAGSTATUS_INTR_ALL  2u
 243         u8  pad_0x3230_0x4000[0x4000 - 0x3230];                 /* 0x3230 */
 244
 245         /* SPU Control Area */
 246         u8  pad_0x4000_0x4004[0x4];                             /* 0x4000 */
 247         u32 pu_mb_R;                                            /* 0x4004 */
 248         u8  pad_0x4008_0x400c[0x4];                             /* 0x4008 */
 249         u32 spu_mb_W;                                           /* 0x400c */
 250         u8  pad_0x4010_0x4014[0x4];                             /* 0x4010 */
 251         u32 mb_stat_R;                                          /* 0x4014 */
 252         u8  pad_0x4018_0x401c[0x4];                             /* 0x4018 */
 253         u32 spu_runcntl_RW;                                     /* 0x401c */
 254 #define SPU_RUNCNTL_STOP        0L
 255 #define SPU_RUNCNTL_RUNNABLE    1L
 256         u8  pad_0x4020_0x4024[0x4];                             /* 0x4020 */
 257         u32 spu_status_R;                                       /* 0x4024 */
 258 #define SPU_STOP_STATUS_SHIFT           16
 259 #define SPU_STATUS_STOPPED              0x0
 260 #define SPU_STATUS_RUNNING              0x1
 261 #define SPU_STATUS_STOPPED_BY_STOP      0x2
 262 #define SPU_STATUS_STOPPED_BY_HALT      0x4
 263 #define SPU_STATUS_WAITING_FOR_CHANNEL  0x8
 264 #define SPU_STATUS_SINGLE_STEP          0x10
 265 #define SPU_STATUS_INVALID_INSTR        0x20
 266 #define SPU_STATUS_INVALID_CH           0x40
 267 #define SPU_STATUS_ISOLATED_STATE       0x80
 268 #define SPU_STATUS_ISOLATED_LOAD_STAUTUS 0x200
 269 #define SPU_STATUS_ISOLATED_EXIT_STAUTUS 0x400
 270         u8  pad_0x4028_0x402c[0x4];                             /* 0x4028 */
 271         u32 spu_spe_R;                                          /* 0x402c */
 272         u8  pad_0x4030_0x4034[0x4];                             /* 0x4030 */
 273         u32 spu_npc_RW;                                         /* 0x4034 */
 274         u8  pad_0x4038_0x14000[0x14000 - 0x4038];               /* 0x4038 */
 275
 276         /* Signal Notification Area */
 277         u8  pad_0x14000_0x1400c[0xc];                           /* 0x14000 */
 278         u32 signal_notify1;                                     /* 0x1400c */
 279         u8  pad_0x14010_0x1c00c[0x7ffc];                        /* 0x14010 */
 280         u32 signal_notify2;                                     /* 0x1c00c */
 281 } __attribute__ ((aligned(0x20000)));
 282
 283 /* SPU Privilege 2 State Area */
 284 struct spu_priv2 {
 285         /* MFC Registers */
 286         u8  pad_0x0000_0x1100[0x1100 - 0x0000];                 /* 0x0000 */
 287
 288         /* SLB Management Registers */
 289         u8  pad_0x1100_0x1108[0x8];                             /* 0x1100 */
 290         u64 slb_index_W;                                        /* 0x1108 */
 291 #define SLB_INDEX_MASK                          0x7L
 292         u64 slb_esid_RW;                                        /* 0x1110 */
 293         u64 slb_vsid_RW;                                        /* 0x1118 */
 294 #define SLB_VSID_SUPERVISOR_STATE       (0x1ull << 11)
 295 #define SLB_VSID_SUPERVISOR_STATE_MASK  (0x1ull << 11)
 296 #define SLB_VSID_PROBLEM_STATE          (0x1ull << 10)
 297 #define SLB_VSID_PROBLEM_STATE_MASK     (0x1ull << 10)
 298 #define SLB_VSID_EXECUTE_SEGMENT        (0x1ull << 9)
 299 #define SLB_VSID_NO_EXECUTE_SEGMENT     (0x1ull << 9)
 300 #define SLB_VSID_EXECUTE_SEGMENT_MASK   (0x1ull << 9)
 301 #define SLB_VSID_4K_PAGE                (0x0 << 8)
 302 #define SLB_VSID_LARGE_PAGE             (0x1ull << 8)
 303 #define SLB_VSID_PAGE_SIZE_MASK         (0x1ull << 8)
 304 #define SLB_VSID_CLASS_MASK             (0x1ull << 7)
 305 #define SLB_VSID_VIRTUAL_PAGE_SIZE_MASK (0x1ull << 6)
 306         u64 slb_invalidate_entry_W;                             /* 0x1120 */
 307         u64 slb_invalidate_all_W;                               /* 0x1128 */
 308         u8  pad_0x1130_0x2000[0x2000 - 0x1130];                 /* 0x1130 */
 309
 310         /* Context Save / Restore Area */
 311         struct mfc_cq_sr spuq[16];                              /* 0x2000 */
 312         struct mfc_cq_sr puq[8];                                /* 0x2200 */
 313         u8  pad_0x2300_0x3000[0x3000 - 0x2300];                 /* 0x2300 */
 314
 315         /* MFC Control */
 316         u64 mfc_control_RW;                                     /* 0x3000 */
 317 #define MFC_CNTL_RESUME_DMA_QUEUE               (0ull << 0)
 318 #define MFC_CNTL_SUSPEND_DMA_QUEUE              (1ull << 0)
 319 #define MFC_CNTL_SUSPEND_DMA_QUEUE_MASK         (1ull << 0)
 320 #define MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION     (0ull << 8)
 321 #define MFC_CNTL_SUSPEND_IN_PROGRESS            (1ull << 8)
 322 #define MFC_CNTL_SUSPEND_COMPLETE               (3ull << 8)
 323 #define MFC_CNTL_SUSPEND_DMA_STATUS_MASK        (3ull << 8)
 324 #define MFC_CNTL_DMA_QUEUES_EMPTY               (1ull << 14)
 325 #define MFC_CNTL_DMA_QUEUES_EMPTY_MASK          (1ull << 14)
 326 #define MFC_CNTL_PURGE_DMA_REQUEST              (1ull << 15)
 327 #define MFC_CNTL_PURGE_DMA_IN_PROGRESS          (1ull << 24)
 328 #define MFC_CNTL_PURGE_DMA_COMPLETE             (3ull << 24)
 329 #define MFC_CNTL_PURGE_DMA_STATUS_MASK          (3ull << 24)
 330 #define MFC_CNTL_RESTART_DMA_COMMAND            (1ull << 32)
 331 #define MFC_CNTL_DMA_COMMAND_REISSUE_PENDING    (1ull << 32)
 332 #define MFC_CNTL_DMA_COMMAND_REISSUE_STATUS_MASK (1ull << 32)
 333 #define MFC_CNTL_MFC_PRIVILEGE_STATE            (2ull << 33)
 334 #define MFC_CNTL_MFC_PROBLEM_STATE              (3ull << 33)
 335 #define MFC_CNTL_MFC_KEY_PROTECTION_STATE_MASK  (3ull << 33)
 336 #define MFC_CNTL_DECREMENTER_HALTED             (1ull << 35)
 337 #define MFC_CNTL_DECREMENTER_RUNNING            (1ull << 40)
 338 #define MFC_CNTL_DECREMENTER_STATUS_MASK        (1ull << 40)
 339         u8  pad_0x3008_0x4000[0x4000 - 0x3008];                 /* 0x3008 */
 340
 341         /* Interrupt Mailbox */
 342         u64 puint_mb_R;                                         /* 0x4000 */
 343         u8  pad_0x4008_0x4040[0x4040 - 0x4008];                 /* 0x4008 */
 344
 345         /* SPU Control */
 346         u64 spu_privcntl_RW;                                    /* 0x4040 */
 347 #define SPU_PRIVCNTL_MODE_NORMAL                (0x0ull << 0)
 348 #define SPU_PRIVCNTL_MODE_SINGLE_STEP           (0x1ull << 0)
 349 #define SPU_PRIVCNTL_MODE_MASK                  (0x1ull << 0)
 350 #define SPU_PRIVCNTL_NO_ATTENTION_EVENT         (0x0ull << 1)
 351 #define SPU_PRIVCNTL_ATTENTION_EVENT            (0x1ull << 1)
 352 #define SPU_PRIVCNTL_ATTENTION_EVENT_MASK       (0x1ull << 1)
 353 #define SPU_PRIVCNT_LOAD_REQUEST_NORMAL         (0x0ull << 2)
 354 #define SPU_PRIVCNT_LOAD_REQUEST_ENABLE_MASK    (0x1ull << 2)
 355         u8  pad_0x4048_0x4058[0x10];                            /* 0x4048 */
 356         u64 spu_lslr_RW;                                        /* 0x4058 */
 357         u64 spu_chnlcntptr_RW;                                  /* 0x4060 */
 358         u64 spu_chnlcnt_RW;                                     /* 0x4068 */
 359         u64 spu_chnldata_RW;                                    /* 0x4070 */
 360         u64 spu_cfg_RW;                                         /* 0x4078 */
 361         u8  pad_0x4080_0x5000[0x5000 - 0x4080];                 /* 0x4080 */
 362
 363         /* PV2_ImplRegs: Implementation-specific privileged-state 2 regs */
 364         u64 spu_pm_trace_tag_status_RW;                         /* 0x5000 */
 365         u64 spu_tag_status_query_RW;                            /* 0x5008 */
 366 #define TAG_STATUS_QUERY_CONDITION_BITS (0x3ull << 32)
 367 #define TAG_STATUS_QUERY_MASK_BITS (0xffffffffull)
 368         u64 spu_cmd_buf1_RW;                                    /* 0x5010 */
 369 #define SPU_COMMAND_BUFFER_1_LSA_BITS (0x7ffffull << 32)
 370 #define SPU_COMMAND_BUFFER_1_EAH_BITS (0xffffffffull)
 371         u64 spu_cmd_buf2_RW;                                    /* 0x5018 */
 372 #define SPU_COMMAND_BUFFER_2_EAL_BITS ((0xffffffffull) << 32)
 373 #define SPU_COMMAND_BUFFER_2_TS_BITS (0xffffull << 16)
 374 #define SPU_COMMAND_BUFFER_2_TAG_BITS (0x3full)
 375         u64 spu_atomic_status_RW;                               /* 0x5020 */
 376 } __attribute__ ((aligned(0x20000)));
 377
 378 /* SPU Privilege 1 State Area */
 379 struct spu_priv1 {
 380         /* Control and Configuration Area */
 381         u64 mfc_sr1_RW;                                         /* 0x000 */
 382 #define MFC_STATE1_LOCAL_STORAGE_DECODE_MASK    0x01ull
 383 #define MFC_STATE1_BUS_TLBIE_MASK               0x02ull
 384 #define MFC_STATE1_REAL_MODE_OFFSET_ENABLE_MASK 0x04ull
 385 #define MFC_STATE1_PROBLEM_STATE_MASK           0x08ull
 386 #define MFC_STATE1_RELOCATE_MASK                0x10ull
 387 #define MFC_STATE1_MASTER_RUN_CONTROL_MASK      0x20ull
 388         u64 mfc_lpid_RW;                                        /* 0x008 */
 389         u64 spu_idr_RW;                                         /* 0x010 */
 390         u64 mfc_vr_RO;                                          /* 0x018 */
 391 #define MFC_VERSION_BITS                (0xffff << 16)
 392 #define MFC_REVISION_BITS               (0xffff)
 393 #define MFC_GET_VERSION_BITS(vr)        (((vr) & MFC_VERSION_BITS) >> 16)
 394 #define MFC_GET_REVISION_BITS(vr)       ((vr) & MFC_REVISION_BITS)
 395         u64 spu_vr_RO;                                          /* 0x020 */
 396 #define SPU_VERSION_BITS                (0xffff << 16)
 397 #define SPU_REVISION_BITS               (0xffff)
 398 #define SPU_GET_VERSION_BITS(vr)        (vr & SPU_VERSION_BITS) >> 16
 399 #define SPU_GET_REVISION_BITS(vr)       (vr & SPU_REVISION_BITS)
 400         u8  pad_0x28_0x100[0x100 - 0x28];                       /* 0x28 */
 401
 402
 403         /* Interrupt Area */
 404         u64 int_mask_RW[3];                                     /* 0x100 */
 405 #define CLASS0_ENABLE_DMA_ALIGNMENT_INTR                0x1L
 406 #define CLASS0_ENABLE_INVALID_DMA_COMMAND_INTR          0x2L
 407 #define CLASS0_ENABLE_SPU_ERROR_INTR                    0x4L
 408 #define CLASS0_ENABLE_MFC_FIR_INTR                      0x8L
 409 #define CLASS1_ENABLE_SEGMENT_FAULT_INTR                0x1L
 410 #define CLASS1_ENABLE_STORAGE_FAULT_INTR                0x2L
 411 #define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_GET_INTR    0x4L
 412 #define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_PUT_INTR    0x8L
 413 #define CLASS2_ENABLE_MAILBOX_INTR                      0x1L
 414 #define CLASS2_ENABLE_SPU_STOP_INTR                     0x2L
 415 #define CLASS2_ENABLE_SPU_HALT_INTR                     0x4L
 416 #define CLASS2_ENABLE_SPU_DMA_TAG_GROUP_COMPLETE_INTR   0x8L
 417         u8  pad_0x118_0x140[0x28];                              /* 0x118 */
 418         u64 int_stat_RW[3];                                     /* 0x140 */
 419         u8  pad_0x158_0x180[0x28];                              /* 0x158 */
 420         u64 int_route_RW;                                       /* 0x180 */
 421
 422         /* Interrupt Routing */
 423         u8  pad_0x188_0x200[0x200 - 0x188];                     /* 0x188 */
 424
 425         /* Atomic Unit Control Area */
 426         u64 mfc_atomic_flush_RW;                                /* 0x200 */
 427 #define mfc_atomic_flush_enable                 0x1L
 428         u8  pad_0x208_0x280[0x78];                              /* 0x208 */
 429         u64 resource_allocation_groupID_RW;                     /* 0x280 */
 430         u64 resource_allocation_enable_RW;                      /* 0x288 */
 431         u8  pad_0x290_0x3c8[0x3c8 - 0x290];                     /* 0x290 */
 432
 433         /* SPU_Cache_ImplRegs: Implementation-dependent cache registers */
 434
 435         u64 smf_sbi_signal_sel;                                 /* 0x3c8 */
 436 #define smf_sbi_mask_lsb        56
 437 #define smf_sbi_shift           (63 - smf_sbi_mask_lsb)
 438 #define smf_sbi_mask            (0x301LL << smf_sbi_shift)
 439 #define smf_sbi_bus0_bits       (0x001LL << smf_sbi_shift)
 440 #define smf_sbi_bus2_bits       (0x100LL << smf_sbi_shift)
 441 #define smf_sbi2_bus0_bits      (0x201LL << smf_sbi_shift)
 442 #define smf_sbi2_bus2_bits      (0x300LL << smf_sbi_shift)
 443         u64 smf_ato_signal_sel;                                 /* 0x3d0 */
 444 #define smf_ato_mask_lsb        35
 445 #define smf_ato_shift           (63 - smf_ato_mask_lsb)
 446 #define smf_ato_mask            (0x3LL << smf_ato_shift)
 447 #define smf_ato_bus0_bits       (0x2LL << smf_ato_shift)
 448 #define smf_ato_bus2_bits       (0x1LL << smf_ato_shift)
 449         u8  pad_0x3d8_0x400[0x400 - 0x3d8];                     /* 0x3d8 */
 450
 451         /* TLB Management Registers */
 452         u64 mfc_sdr_RW;                                         /* 0x400 */
 453         u8  pad_0x408_0x500[0xf8];                              /* 0x408 */
 454         u64 tlb_index_hint_RO;                                  /* 0x500 */
 455         u64 tlb_index_W;                                        /* 0x508 */
 456         u64 tlb_vpn_RW;                                         /* 0x510 */
 457         u64 tlb_rpn_RW;                                         /* 0x518 */
 458         u8  pad_0x520_0x540[0x20];                              /* 0x520 */
 459         u64 tlb_invalidate_entry_W;                             /* 0x540 */
 460         u64 tlb_invalidate_all_W;                               /* 0x548 */
 461         u8  pad_0x550_0x580[0x580 - 0x550];                     /* 0x550 */
 462
 463         /* SPU_MMU_ImplRegs: Implementation-dependent MMU registers */
 464         u64 smm_hid;                                            /* 0x580 */
 465 #define PAGE_SIZE_MASK          0xf000000000000000ull
 466 #define PAGE_SIZE_16MB_64KB     0x2000000000000000ull
 467         u8  pad_0x588_0x600[0x600 - 0x588];                     /* 0x588 */
 468
 469         /* MFC Status/Control Area */
 470         u64 mfc_accr_RW;                                        /* 0x600 */
 471 #define MFC_ACCR_EA_ACCESS_GET          (1 << 0)
 472 #define MFC_ACCR_EA_ACCESS_PUT          (1 << 1)
 473 #define MFC_ACCR_LS_ACCESS_GET          (1 << 3)
 474 #define MFC_ACCR_LS_ACCESS_PUT          (1 << 4)
 475         u8  pad_0x608_0x610[0x8];                               /* 0x608 */
 476         u64 mfc_dsisr_RW;                                       /* 0x610 */
 477 #define MFC_DSISR_PTE_NOT_FOUND         (1 << 30)
 478 #define MFC_DSISR_ACCESS_DENIED         (1 << 27)
 479 #define MFC_DSISR_ATOMIC                (1 << 26)
 480 #define MFC_DSISR_ACCESS_PUT            (1 << 25)
 481 #define MFC_DSISR_ADDR_MATCH            (1 << 22)
 482 #define MFC_DSISR_LS                    (1 << 17)
 483 #define MFC_DSISR_L                     (1 << 16)
 484 #define MFC_DSISR_ADDRESS_OVERFLOW      (1 << 0)
 485         u8  pad_0x618_0x620[0x8];                               /* 0x618 */
 486         u64 mfc_dar_RW;                                         /* 0x620 */
 487         u8  pad_0x628_0x700[0x700 - 0x628];                     /* 0x628 */
 488
 489         /* Replacement Management Table (RMT) Area */
 490         u64 rmt_index_RW;                                       /* 0x700 */
 491         u8  pad_0x708_0x710[0x8];                               /* 0x708 */
 492         u64 rmt_data1_RW;                                       /* 0x710 */
 493         u8  pad_0x718_0x800[0x800 - 0x718];                     /* 0x718 */
 494
 495         /* Control/Configuration Registers */
 496         u64 mfc_dsir_R;                                         /* 0x800 */
 497 #define MFC_DSIR_Q                      (1 << 31)
 498 #define MFC_DSIR_SPU_QUEUE              MFC_DSIR_Q
 499         u64 mfc_lsacr_RW;                                       /* 0x808 */
 500 #define MFC_LSACR_COMPARE_MASK          ((~0ull) << 32)
 501 #define MFC_LSACR_COMPARE_ADDR          ((~0ull) >> 32)
 502         u64 mfc_lscrr_R;                                        /* 0x810 */
 503 #define MFC_LSCRR_Q                     (1 << 31)
 504 #define MFC_LSCRR_SPU_QUEUE             MFC_LSCRR_Q
 505 #define MFC_LSCRR_QI_SHIFT              32
 506 #define MFC_LSCRR_QI_MASK               ((~0ull) << MFC_LSCRR_QI_SHIFT)
 507         u8  pad_0x818_0x820[0x8];                               /* 0x818 */
 508         u64 mfc_tclass_id_RW;                                   /* 0x820 */
 509 #define MFC_TCLASS_ID_ENABLE            (1L << 0L)
 510 #define MFC_TCLASS_SLOT2_ENABLE         (1L << 5L)
 511 #define MFC_TCLASS_SLOT1_ENABLE         (1L << 6L)
 512 #define MFC_TCLASS_SLOT0_ENABLE         (1L << 7L)
 513 #define MFC_TCLASS_QUOTA_2_SHIFT        8L
 514 #define MFC_TCLASS_QUOTA_1_SHIFT        16L
 515 #define MFC_TCLASS_QUOTA_0_SHIFT        24L
 516 #define MFC_TCLASS_QUOTA_2_MASK         (0x1FL << MFC_TCLASS_QUOTA_2_SHIFT)
 517 #define MFC_TCLASS_QUOTA_1_MASK         (0x1FL << MFC_TCLASS_QUOTA_1_SHIFT)
 518 #define MFC_TCLASS_QUOTA_0_MASK         (0x1FL << MFC_TCLASS_QUOTA_0_SHIFT)
 519         u8  pad_0x828_0x900[0x900 - 0x828];                     /* 0x828 */
 520
 521         /* Real Mode Support Registers */
 522         u64 mfc_rm_boundary;                                    /* 0x900 */
 523         u8  pad_0x908_0x938[0x30];                              /* 0x908 */
 524         u64 smf_dma_signal_sel;                                 /* 0x938 */
 525 #define mfc_dma1_mask_lsb       41
 526 #define mfc_dma1_shift          (63 - mfc_dma1_mask_lsb)
 527 #define mfc_dma1_mask           (0x3LL << mfc_dma1_shift)
 528 #define mfc_dma1_bits           (0x1LL << mfc_dma1_shift)
 529 #define mfc_dma2_mask_lsb       43
 530 #define mfc_dma2_shift          (63 - mfc_dma2_mask_lsb)
 531 #define mfc_dma2_mask           (0x3LL << mfc_dma2_shift)
 532 #define mfc_dma2_bits           (0x1LL << mfc_dma2_shift)
 533         u8  pad_0x940_0xa38[0xf8];                              /* 0x940 */
 534         u64 smm_signal_sel;                                     /* 0xa38 */
 535 #define smm_sig_mask_lsb        12
 536 #define smm_sig_shift           (63 - smm_sig_mask_lsb)
 537 #define smm_sig_mask            (0x3LL << smm_sig_shift)
 538 #define smm_sig_bus0_bits       (0x2LL << smm_sig_shift)
 539 #define smm_sig_bus2_bits       (0x1LL << smm_sig_shift)
 540         u8  pad_0xa40_0xc00[0xc00 - 0xa40];                     /* 0xa40 */
 541
 542         /* DMA Command Error Area */
 543         u64 mfc_cer_R;                                          /* 0xc00 */
 544 #define MFC_CER_Q               (1 << 31)
 545 #define MFC_CER_SPU_QUEUE       MFC_CER_Q
 546         u8  pad_0xc08_0x1000[0x1000 - 0xc08];                   /* 0xc08 */
 547
 548         /* PV1_ImplRegs: Implementation-dependent privileged-state 1 regs */
 549         /* DMA Command Error Area */
 550         u64 spu_ecc_cntl_RW;                                    /* 0x1000 */
 551 #define SPU_ECC_CNTL_E                  (1ull << 0ull)
 552 #define SPU_ECC_CNTL_ENABLE             SPU_ECC_CNTL_E
 553 #define SPU_ECC_CNTL_DISABLE            (~SPU_ECC_CNTL_E & 1L)
 554 #define SPU_ECC_CNTL_S                  (1ull << 1ull)
 555 #define SPU_ECC_STOP_AFTER_ERROR        SPU_ECC_CNTL_S
 556 #define SPU_ECC_CONTINUE_AFTER_ERROR    (~SPU_ECC_CNTL_S & 2L)
 557 #define SPU_ECC_CNTL_B                  (1ull << 2ull)
 558 #define SPU_ECC_BACKGROUND_ENABLE       SPU_ECC_CNTL_B
 559 #define SPU_ECC_BACKGROUND_DISABLE      (~SPU_ECC_CNTL_B & 4L)
 560 #define SPU_ECC_CNTL_I_SHIFT            3ull
 561 #define SPU_ECC_CNTL_I_MASK             (3ull << SPU_ECC_CNTL_I_SHIFT)
 562 #define SPU_ECC_WRITE_ALWAYS            (~SPU_ECC_CNTL_I & 12L)
 563 #define SPU_ECC_WRITE_CORRECTABLE       (1ull << SPU_ECC_CNTL_I_SHIFT)
 564 #define SPU_ECC_WRITE_UNCORRECTABLE     (3ull << SPU_ECC_CNTL_I_SHIFT)
 565 #define SPU_ECC_CNTL_D                  (1ull << 5ull)
 566 #define SPU_ECC_DETECTION_ENABLE        SPU_ECC_CNTL_D
 567 #define SPU_ECC_DETECTION_DISABLE       (~SPU_ECC_CNTL_D & 32L)
 568         u64 spu_ecc_stat_RW;                                    /* 0x1008 */
 569 #define SPU_ECC_CORRECTED_ERROR         (1ull << 0ul)
 570 #define SPU_ECC_UNCORRECTED_ERROR       (1ull << 1ul)
 571 #define SPU_ECC_SCRUB_COMPLETE          (1ull << 2ul)
 572 #define SPU_ECC_SCRUB_IN_PROGRESS       (1ull << 3ul)
 573 #define SPU_ECC_INSTRUCTION_ERROR       (1ull << 4ul)
 574 #define SPU_ECC_DATA_ERROR              (1ull << 5ul)
 575 #define SPU_ECC_DMA_ERROR               (1ull << 6ul)
 576 #define SPU_ECC_STATUS_CNT_MASK         (256ull << 8)
 577         u64 spu_ecc_addr_RW;                                    /* 0x1010 */
 578         u64 spu_err_mask_RW;                                    /* 0x1018 */
 579 #define SPU_ERR_ILLEGAL_INSTR           (1ull << 0ul)
 580 #define SPU_ERR_ILLEGAL_CHANNEL         (1ull << 1ul)
 581         u8  pad_0x1020_0x1028[0x1028 - 0x1020];                 /* 0x1020 */
 582
 583         /* SPU Debug-Trace Bus (DTB) Selection Registers */
 584         u64 spu_trig0_sel;                                      /* 0x1028 */
 585         u64 spu_trig1_sel;                                      /* 0x1030 */
 586         u64 spu_trig2_sel;                                      /* 0x1038 */
 587         u64 spu_trig3_sel;                                      /* 0x1040 */
 588         u64 spu_trace_sel;                                      /* 0x1048 */
 589 #define spu_trace_sel_mask              0x1f1fLL
 590 #define spu_trace_sel_bus0_bits         0x1000LL
 591 #define spu_trace_sel_bus2_bits         0x0010LL
 592         u64 spu_event0_sel;                                     /* 0x1050 */
 593         u64 spu_event1_sel;                                     /* 0x1058 */
 594         u64 spu_event2_sel;                                     /* 0x1060 */
 595         u64 spu_event3_sel;                                     /* 0x1068 */
 596         u64 spu_trace_cntl;                                     /* 0x1070 */
 597 } __attribute__ ((aligned(0x2000)));
 598
 599 #endif /* __KERNEL__ */
 600 #endif