Pull error-inject into release branch
[linux-2.6] / drivers / ide / pci / cmd64x.c
1 /* $Id: cmd64x.c,v 1.21 2000/01/30 23:23:16
2  *
3  * linux/drivers/ide/pci/cmd64x.c               Version 1.42    Feb 8, 2007
4  *
5  * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
6  *           Note, this driver is not used at all on other systems because
7  *           there the "BIOS" has done all of the following already.
8  *           Due to massive hardware bugs, UltraDMA is only supported
9  *           on the 646U2 and not on the 646U.
10  *
11  * Copyright (C) 1998           Eddie C. Dost  (ecd@skynet.be)
12  * Copyright (C) 1998           David S. Miller (davem@redhat.com)
13  *
14  * Copyright (C) 1999-2002      Andre Hedrick <andre@linux-ide.org>
15  * Copyright (C) 2007           MontaVista Software, Inc. <source@mvista.com>
16  */
17
18 #include <linux/module.h>
19 #include <linux/types.h>
20 #include <linux/pci.h>
21 #include <linux/delay.h>
22 #include <linux/hdreg.h>
23 #include <linux/ide.h>
24 #include <linux/init.h>
25
26 #include <asm/io.h>
27
28 #define DISPLAY_CMD64X_TIMINGS
29
30 #define CMD_DEBUG 0
31
32 #if CMD_DEBUG
33 #define cmdprintk(x...) printk(x)
34 #else
35 #define cmdprintk(x...)
36 #endif
37
38 /*
39  * CMD64x specific registers definition.
40  */
41 #define CFR             0x50
42 #define   CFR_INTR_CH0          0x02
43 #define CNTRL           0x51
44 #define   CNTRL_DIS_RA0         0x40
45 #define   CNTRL_DIS_RA1         0x80
46 #define   CNTRL_ENA_2ND         0x08
47
48 #define CMDTIM          0x52
49 #define ARTTIM0         0x53
50 #define DRWTIM0         0x54
51 #define ARTTIM1         0x55
52 #define DRWTIM1         0x56
53 #define ARTTIM23        0x57
54 #define   ARTTIM23_DIS_RA2      0x04
55 #define   ARTTIM23_DIS_RA3      0x08
56 #define   ARTTIM23_INTR_CH1     0x10
57 #define ARTTIM2         0x57
58 #define ARTTIM3         0x57
59 #define DRWTIM23        0x58
60 #define DRWTIM2         0x58
61 #define BRST            0x59
62 #define DRWTIM3         0x5b
63
64 #define BMIDECR0        0x70
65 #define MRDMODE         0x71
66 #define   MRDMODE_INTR_CH0      0x04
67 #define   MRDMODE_INTR_CH1      0x08
68 #define   MRDMODE_BLK_CH0       0x10
69 #define   MRDMODE_BLK_CH1       0x20
70 #define BMIDESR0        0x72
71 #define UDIDETCR0       0x73
72 #define DTPR0           0x74
73 #define BMIDECR1        0x78
74 #define BMIDECSR        0x79
75 #define BMIDESR1        0x7A
76 #define UDIDETCR1       0x7B
77 #define DTPR1           0x7C
78
79 #if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_PROC_FS)
80 #include <linux/stat.h>
81 #include <linux/proc_fs.h>
82
83 static u8 cmd64x_proc = 0;
84
85 #define CMD_MAX_DEVS            5
86
87 static struct pci_dev *cmd_devs[CMD_MAX_DEVS];
88 static int n_cmd_devs;
89
90 static char * print_cmd64x_get_info (char *buf, struct pci_dev *dev, int index)
91 {
92         char *p = buf;
93
94         u8 reg53 = 0, reg54 = 0, reg55 = 0, reg56 = 0;  /* primary */
95         u8 reg57 = 0, reg58 = 0, reg5b;                 /* secondary */
96         u8 reg72 = 0, reg73 = 0;                        /* primary */
97         u8 reg7a = 0, reg7b = 0;                        /* secondary */
98         u8 reg50 = 0, reg71 = 0;                        /* extra */
99
100         p += sprintf(p, "\nController: %d\n", index);
101         p += sprintf(p, "CMD%x Chipset.\n", dev->device);
102         (void) pci_read_config_byte(dev, CFR,       &reg50);
103         (void) pci_read_config_byte(dev, ARTTIM0,   &reg53);
104         (void) pci_read_config_byte(dev, DRWTIM0,   &reg54);
105         (void) pci_read_config_byte(dev, ARTTIM1,   &reg55);
106         (void) pci_read_config_byte(dev, DRWTIM1,   &reg56);
107         (void) pci_read_config_byte(dev, ARTTIM2,   &reg57);
108         (void) pci_read_config_byte(dev, DRWTIM2,   &reg58);
109         (void) pci_read_config_byte(dev, DRWTIM3,   &reg5b);
110         (void) pci_read_config_byte(dev, MRDMODE,   &reg71);
111         (void) pci_read_config_byte(dev, BMIDESR0,  &reg72);
112         (void) pci_read_config_byte(dev, UDIDETCR0, &reg73);
113         (void) pci_read_config_byte(dev, BMIDESR1,  &reg7a);
114         (void) pci_read_config_byte(dev, UDIDETCR1, &reg7b);
115
116         p += sprintf(p, "--------------- Primary Channel "
117                         "---------------- Secondary Channel "
118                         "-------------\n");
119         p += sprintf(p, "                %sabled           "
120                         "              %sabled\n",
121                 (reg72&0x80)?"dis":" en",
122                 (reg7a&0x80)?"dis":" en");
123         p += sprintf(p, "--------------- drive0 "
124                 "--------- drive1 -------- drive0 "
125                 "---------- drive1 ------\n");
126         p += sprintf(p, "DMA enabled:    %s              %s"
127                         "             %s               %s\n",
128                 (reg72&0x20)?"yes":"no ", (reg72&0x40)?"yes":"no ",
129                 (reg7a&0x20)?"yes":"no ", (reg7a&0x40)?"yes":"no ");
130
131         p += sprintf(p, "DMA Mode:       %s(%s)          %s(%s)",
132                 (reg72&0x20)?((reg73&0x01)?"UDMA":" DMA"):" PIO",
133                 (reg72&0x20)?(
134                         ((reg73&0x30)==0x30)?(((reg73&0x35)==0x35)?"3":"0"):
135                         ((reg73&0x20)==0x20)?(((reg73&0x25)==0x25)?"3":"1"):
136                         ((reg73&0x10)==0x10)?(((reg73&0x15)==0x15)?"4":"2"):
137                         ((reg73&0x00)==0x00)?(((reg73&0x05)==0x05)?"5":"2"):
138                         "X"):"?",
139                 (reg72&0x40)?((reg73&0x02)?"UDMA":" DMA"):" PIO",
140                 (reg72&0x40)?(
141                         ((reg73&0xC0)==0xC0)?(((reg73&0xC5)==0xC5)?"3":"0"):
142                         ((reg73&0x80)==0x80)?(((reg73&0x85)==0x85)?"3":"1"):
143                         ((reg73&0x40)==0x40)?(((reg73&0x4A)==0x4A)?"4":"2"):
144                         ((reg73&0x00)==0x00)?(((reg73&0x0A)==0x0A)?"5":"2"):
145                         "X"):"?");
146         p += sprintf(p, "         %s(%s)           %s(%s)\n",
147                 (reg7a&0x20)?((reg7b&0x01)?"UDMA":" DMA"):" PIO",
148                 (reg7a&0x20)?(
149                         ((reg7b&0x30)==0x30)?(((reg7b&0x35)==0x35)?"3":"0"):
150                         ((reg7b&0x20)==0x20)?(((reg7b&0x25)==0x25)?"3":"1"):
151                         ((reg7b&0x10)==0x10)?(((reg7b&0x15)==0x15)?"4":"2"):
152                         ((reg7b&0x00)==0x00)?(((reg7b&0x05)==0x05)?"5":"2"):
153                         "X"):"?",
154                 (reg7a&0x40)?((reg7b&0x02)?"UDMA":" DMA"):" PIO",
155                 (reg7a&0x40)?(
156                         ((reg7b&0xC0)==0xC0)?(((reg7b&0xC5)==0xC5)?"3":"0"):
157                         ((reg7b&0x80)==0x80)?(((reg7b&0x85)==0x85)?"3":"1"):
158                         ((reg7b&0x40)==0x40)?(((reg7b&0x4A)==0x4A)?"4":"2"):
159                         ((reg7b&0x00)==0x00)?(((reg7b&0x0A)==0x0A)?"5":"2"):
160                         "X"):"?" );
161         p += sprintf(p, "PIO Mode:       %s                %s"
162                         "               %s                 %s\n",
163                         "?", "?", "?", "?");
164         p += sprintf(p, "                %s                     %s\n",
165                 (reg50 & CFR_INTR_CH0) ? "interrupting" : "polling     ",
166                 (reg57 & ARTTIM23_INTR_CH1) ? "interrupting" : "polling");
167         p += sprintf(p, "                %s                          %s\n",
168                 (reg71 & MRDMODE_INTR_CH0) ? "pending" : "clear  ",
169                 (reg71 & MRDMODE_INTR_CH1) ? "pending" : "clear");
170         p += sprintf(p, "                %s                          %s\n",
171                 (reg71 & MRDMODE_BLK_CH0) ? "blocked" : "enabled",
172                 (reg71 & MRDMODE_BLK_CH1) ? "blocked" : "enabled");
173
174         return (char *)p;
175 }
176
177 static int cmd64x_get_info (char *buffer, char **addr, off_t offset, int count)
178 {
179         char *p = buffer;
180         int i;
181
182         p += sprintf(p, "\n");
183         for (i = 0; i < n_cmd_devs; i++) {
184                 struct pci_dev *dev     = cmd_devs[i];
185                 p = print_cmd64x_get_info(p, dev, i);
186         }
187         return p-buffer;        /* => must be less than 4k! */
188 }
189
190 #endif  /* defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_PROC_FS) */
191
192 static u8 quantize_timing(int timing, int quant)
193 {
194         return (timing + quant - 1) / quant;
195 }
196
197 /*
198  * This routine writes the prepared setup/active/recovery counts
199  * for a drive into the cmd646 chipset registers to active them.
200  */
201 static void program_drive_counts (ide_drive_t *drive, int setup_count, int active_count, int recovery_count)
202 {
203         unsigned long flags;
204         struct pci_dev *dev = HWIF(drive)->pci_dev;
205         ide_drive_t *drives = HWIF(drive)->drives;
206         u8 temp_b;
207         static const u8 setup_counts[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
208         static const u8 recovery_counts[] =
209                 {15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0};
210         static const u8 arttim_regs[2][2] = {
211                         { ARTTIM0, ARTTIM1 },
212                         { ARTTIM23, ARTTIM23 }
213                 };
214         static const u8 drwtim_regs[2][2] = {
215                         { DRWTIM0, DRWTIM1 },
216                         { DRWTIM2, DRWTIM3 }
217                 };
218         int channel = (int) HWIF(drive)->channel;
219         int slave = (drives != drive);  /* Is this really the best way to determine this?? */
220
221         cmdprintk("program_drive_count parameters = s(%d),a(%d),r(%d),p(%d)\n",
222                 setup_count, active_count, recovery_count, drive->present);
223         /*
224          * Set up address setup count registers.
225          * Primary interface has individual count/timing registers for
226          * each drive.  Secondary interface has one common set of registers,
227          * for address setup so we merge these timings, using the slowest
228          * value.
229          */
230         if (channel) {
231                 drive->drive_data = setup_count;
232                 setup_count = max(drives[0].drive_data,
233                                         drives[1].drive_data);
234                 cmdprintk("Secondary interface, setup_count = %d\n",
235                                         setup_count);
236         }
237
238         /*
239          * Convert values to internal chipset representation
240          */
241         setup_count = (setup_count > 5) ? 0xc0 : (int) setup_counts[setup_count];
242         active_count &= 0xf; /* Remember, max value is 16 */
243         recovery_count = (int) recovery_counts[recovery_count];
244
245         cmdprintk("Final values = %d,%d,%d\n",
246                 setup_count, active_count, recovery_count);
247
248         /*
249          * Now that everything is ready, program the new timings
250          */
251         local_irq_save(flags);
252         /*
253          * Program the address_setup clocks into ARTTIM reg,
254          * and then the active/recovery counts into the DRWTIM reg
255          */
256         (void) pci_read_config_byte(dev, arttim_regs[channel][slave], &temp_b);
257         (void) pci_write_config_byte(dev, arttim_regs[channel][slave],
258                 ((u8) setup_count) | (temp_b & 0x3f));
259         (void) pci_write_config_byte(dev, drwtim_regs[channel][slave],
260                 (u8) ((active_count << 4) | recovery_count));
261         cmdprintk ("Write %x to %x\n",
262                 ((u8) setup_count) | (temp_b & 0x3f),
263                 arttim_regs[channel][slave]);
264         cmdprintk ("Write %x to %x\n",
265                 (u8) ((active_count << 4) | recovery_count),
266                 drwtim_regs[channel][slave]);
267         local_irq_restore(flags);
268 }
269
270 /*
271  * This routine selects drive's best PIO mode, calculates setup/active/recovery
272  * counts, and then writes them into the chipset registers.
273  */
274 static u8 cmd64x_tune_pio (ide_drive_t *drive, u8 mode_wanted)
275 {
276         int setup_time, active_time, cycle_time;
277         u8  cycle_count, setup_count, active_count, recovery_count;
278         u8  pio_mode;
279         int clock_time = 1000 / system_bus_clock();
280         ide_pio_data_t pio;
281
282         pio_mode = ide_get_best_pio_mode(drive, mode_wanted, 5, &pio);
283         cycle_time = pio.cycle_time;
284
285         setup_time  = ide_pio_timings[pio_mode].setup_time;
286         active_time = ide_pio_timings[pio_mode].active_time;
287
288         setup_count  = quantize_timing( setup_time, clock_time);
289         cycle_count  = quantize_timing( cycle_time, clock_time);
290         active_count = quantize_timing(active_time, clock_time);
291
292         recovery_count = cycle_count - active_count;
293         /* program_drive_counts() takes care of zero recovery cycles */
294         if (recovery_count > 16) {
295                 active_count += recovery_count - 16;
296                 recovery_count = 16;
297         }
298         if (active_count > 16)
299                 active_count = 16; /* maximum allowed by cmd64x */
300
301         program_drive_counts (drive, setup_count, active_count, recovery_count);
302
303         cmdprintk("%s: PIO mode wanted %d, selected %d (%dns)%s, "
304                 "clocks=%d/%d/%d\n",
305                 drive->name, mode_wanted, pio_mode, cycle_time,
306                 pio.overridden ? " (overriding vendor mode)" : "",
307                 setup_count, active_count, recovery_count);
308
309         return pio_mode;
310 }
311
312 /*
313  * Attempts to set drive's PIO mode.
314  * Special cases are 8: prefetch off, 9: prefetch on (both never worked),
315  * and 255: auto-select best mode (used at boot time).
316  */
317 static void cmd64x_tune_drive (ide_drive_t *drive, u8 pio)
318 {
319         /*
320          * Filter out the prefetch control values
321          * to prevent PIO5 from being programmed
322          */
323         if (pio == 8 || pio == 9)
324                 return;
325
326         pio = cmd64x_tune_pio(drive, pio);
327         (void) ide_config_drive_speed(drive, XFER_PIO_0 + pio);
328 }
329
330 static u8 cmd64x_ratemask (ide_drive_t *drive)
331 {
332         struct pci_dev *dev     = HWIF(drive)->pci_dev;
333         u8 mode = 0;
334
335         switch(dev->device) {
336                 case PCI_DEVICE_ID_CMD_649:
337                         mode = 3;
338                         break;
339                 case PCI_DEVICE_ID_CMD_648:
340                         mode = 2;
341                         break;
342                 case PCI_DEVICE_ID_CMD_643:
343                         return 0;
344
345                 case PCI_DEVICE_ID_CMD_646:
346                 {
347                         unsigned int class_rev  = 0;
348                         pci_read_config_dword(dev,
349                                 PCI_CLASS_REVISION, &class_rev);
350                         class_rev &= 0xff;
351                 /*
352                  * UltraDMA only supported on PCI646U and PCI646U2, which
353                  * correspond to revisions 0x03, 0x05 and 0x07 respectively.
354                  * Actually, although the CMD tech support people won't
355                  * tell me the details, the 0x03 revision cannot support
356                  * UDMA correctly without hardware modifications, and even
357                  * then it only works with Quantum disks due to some
358                  * hold time assumptions in the 646U part which are fixed
359                  * in the 646U2.
360                  *
361                  * So we only do UltraDMA on revision 0x05 and 0x07 chipsets.
362                  */
363                         switch(class_rev) {
364                                 case 0x07:
365                                 case 0x05:
366                                         return 1;
367                                 case 0x03:
368                                 case 0x01:
369                                 default:
370                                         return 0;
371                         }
372                 }
373         }
374         if (!eighty_ninty_three(drive))
375                 mode = min(mode, (u8)1);
376         return mode;
377 }
378
379 static int cmd64x_tune_chipset (ide_drive_t *drive, u8 xferspeed)
380 {
381         ide_hwif_t *hwif        = HWIF(drive);
382         struct pci_dev *dev     = hwif->pci_dev;
383
384         u8 unit                 = (drive->select.b.unit & 0x01);
385         u8 regU = 0, pciU       = (hwif->channel) ? UDIDETCR1 : UDIDETCR0;
386         u8 regD = 0, pciD       = (hwif->channel) ? BMIDESR1 : BMIDESR0;
387
388         u8 speed        = ide_rate_filter(cmd64x_ratemask(drive), xferspeed);
389
390         if (speed >= XFER_SW_DMA_0) {
391                 (void) pci_read_config_byte(dev, pciD, &regD);
392                 (void) pci_read_config_byte(dev, pciU, &regU);
393                 regD &= ~(unit ? 0x40 : 0x20);
394                 regU &= ~(unit ? 0xCA : 0x35);
395                 (void) pci_write_config_byte(dev, pciD, regD);
396                 (void) pci_write_config_byte(dev, pciU, regU);
397                 (void) pci_read_config_byte(dev, pciD, &regD);
398                 (void) pci_read_config_byte(dev, pciU, &regU);
399         }
400
401         switch(speed) {
402                 case XFER_UDMA_5:       regU |= (unit ? 0x0A : 0x05); break;
403                 case XFER_UDMA_4:       regU |= (unit ? 0x4A : 0x15); break;
404                 case XFER_UDMA_3:       regU |= (unit ? 0x8A : 0x25); break;
405                 case XFER_UDMA_2:       regU |= (unit ? 0x42 : 0x11); break;
406                 case XFER_UDMA_1:       regU |= (unit ? 0x82 : 0x21); break;
407                 case XFER_UDMA_0:       regU |= (unit ? 0xC2 : 0x31); break;
408                 case XFER_MW_DMA_2:     regD |= (unit ? 0x40 : 0x10); break;
409                 case XFER_MW_DMA_1:     regD |= (unit ? 0x80 : 0x20); break;
410                 case XFER_MW_DMA_0:     regD |= (unit ? 0xC0 : 0x30); break;
411                 case XFER_SW_DMA_2:     regD |= (unit ? 0x40 : 0x10); break;
412                 case XFER_SW_DMA_1:     regD |= (unit ? 0x80 : 0x20); break;
413                 case XFER_SW_DMA_0:     regD |= (unit ? 0xC0 : 0x30); break;
414                 case XFER_PIO_5:
415                 case XFER_PIO_4:
416                 case XFER_PIO_3:
417                 case XFER_PIO_2:
418                 case XFER_PIO_1:
419                 case XFER_PIO_0:
420                         (void) cmd64x_tune_pio(drive, speed - XFER_PIO_0);
421                         break;
422
423                 default:
424                         return 1;
425         }
426
427         if (speed >= XFER_SW_DMA_0) {
428                 (void) pci_write_config_byte(dev, pciU, regU);
429                 regD |= (unit ? 0x40 : 0x20);
430                 (void) pci_write_config_byte(dev, pciD, regD);
431         }
432
433         return (ide_config_drive_speed(drive, speed));
434 }
435
436 static int config_chipset_for_dma (ide_drive_t *drive)
437 {
438         u8 speed        = ide_dma_speed(drive, cmd64x_ratemask(drive));
439
440         if (!speed)
441                 return 0;
442
443         if (cmd64x_tune_chipset(drive, speed))
444                 return 0;
445
446         return ide_dma_enable(drive);
447 }
448
449 static int cmd64x_config_drive_for_dma (ide_drive_t *drive)
450 {
451         if (ide_use_dma(drive) && config_chipset_for_dma(drive))
452                 return 0;
453
454         if (ide_use_fast_pio(drive))
455                 cmd64x_tune_drive(drive, 255);
456
457         return -1;
458 }
459
460 static int cmd64x_alt_dma_status (struct pci_dev *dev)
461 {
462         switch(dev->device) {
463                 case PCI_DEVICE_ID_CMD_648:
464                 case PCI_DEVICE_ID_CMD_649:
465                         return 1;
466                 default:
467                         break;
468         }
469         return 0;
470 }
471
472 static int cmd64x_ide_dma_end (ide_drive_t *drive)
473 {
474         u8 dma_stat = 0, dma_cmd = 0;
475         ide_hwif_t *hwif        = HWIF(drive);
476         struct pci_dev *dev     = hwif->pci_dev;
477
478         drive->waiting_for_dma = 0;
479         /* read DMA command state */
480         dma_cmd = inb(hwif->dma_command);
481         /* stop DMA */
482         outb(dma_cmd & ~1, hwif->dma_command);
483         /* get DMA status */
484         dma_stat = inb(hwif->dma_status);
485         /* clear the INTR & ERROR bits */
486         outb(dma_stat | 6, hwif->dma_status);
487         if (cmd64x_alt_dma_status(dev)) {
488                 u8 dma_intr     = 0;
489                 u8 dma_mask     = (hwif->channel) ? ARTTIM23_INTR_CH1 :
490                                                     CFR_INTR_CH0;
491                 u8 dma_reg      = (hwif->channel) ? ARTTIM2 : CFR;
492                 (void) pci_read_config_byte(dev, dma_reg, &dma_intr);
493                 /* clear the INTR bit */
494                 (void) pci_write_config_byte(dev, dma_reg, dma_intr|dma_mask);
495         }
496         /* purge DMA mappings */
497         ide_destroy_dmatable(drive);
498         /* verify good DMA status */
499         return (dma_stat & 7) != 4;
500 }
501
502 static int cmd64x_ide_dma_test_irq (ide_drive_t *drive)
503 {
504         ide_hwif_t *hwif                = HWIF(drive);
505         struct pci_dev *dev             = hwif->pci_dev;
506         u8 dma_alt_stat = 0, mask       = (hwif->channel) ? MRDMODE_INTR_CH1 :
507                                                             MRDMODE_INTR_CH0;
508         u8 dma_stat = inb(hwif->dma_status);
509
510         (void) pci_read_config_byte(dev, MRDMODE, &dma_alt_stat);
511 #ifdef DEBUG
512         printk("%s: dma_stat: 0x%02x dma_alt_stat: "
513                 "0x%02x mask: 0x%02x\n", drive->name,
514                 dma_stat, dma_alt_stat, mask);
515 #endif
516         if (!(dma_alt_stat & mask))
517                 return 0;
518
519         /* return 1 if INTR asserted */
520         if ((dma_stat & 4) == 4)
521                 return 1;
522
523         return 0;
524 }
525
526 /*
527  * ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old
528  * event order for DMA transfers.
529  */
530
531 static int cmd646_1_ide_dma_end (ide_drive_t *drive)
532 {
533         ide_hwif_t *hwif = HWIF(drive);
534         u8 dma_stat = 0, dma_cmd = 0;
535
536         drive->waiting_for_dma = 0;
537         /* get DMA status */
538         dma_stat = inb(hwif->dma_status);
539         /* read DMA command state */
540         dma_cmd = inb(hwif->dma_command);
541         /* stop DMA */
542         outb(dma_cmd & ~1, hwif->dma_command);
543         /* clear the INTR & ERROR bits */
544         outb(dma_stat | 6, hwif->dma_status);
545         /* and free any DMA resources */
546         ide_destroy_dmatable(drive);
547         /* verify good DMA status */
548         return (dma_stat & 7) != 4;
549 }
550
551 static unsigned int __devinit init_chipset_cmd64x(struct pci_dev *dev, const char *name)
552 {
553         u32 class_rev = 0;
554         u8 mrdmode = 0;
555
556         pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
557         class_rev &= 0xff;
558
559         switch(dev->device) {
560                 case PCI_DEVICE_ID_CMD_643:
561                         break;
562                 case PCI_DEVICE_ID_CMD_646:
563                         printk(KERN_INFO "%s: chipset revision 0x%02X, ", name, class_rev);
564                         switch(class_rev) {
565                                 case 0x07:
566                                 case 0x05:
567                                         printk("UltraDMA Capable");
568                                         break;
569                                 case 0x03:
570                                         printk("MultiWord DMA Force Limited");
571                                         break;
572                                 case 0x01:
573                                 default:
574                                         printk("MultiWord DMA Limited, IRQ workaround enabled");
575                                         break;
576                                 }
577                         printk("\n");
578                         break;
579                 case PCI_DEVICE_ID_CMD_648:
580                 case PCI_DEVICE_ID_CMD_649:
581                         break;
582                 default:
583                         break;
584         }
585
586         /* Set a good latency timer and cache line size value. */
587         (void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
588         /* FIXME: pci_set_master() to ensure a good latency timer value */
589
590         /* Setup interrupts. */
591         (void) pci_read_config_byte(dev, MRDMODE, &mrdmode);
592         mrdmode &= ~(0x30);
593         (void) pci_write_config_byte(dev, MRDMODE, mrdmode);
594
595         /* Use MEMORY READ LINE for reads.
596          * NOTE: Although not mentioned in the PCI0646U specs,
597          *       these bits are write only and won't be read
598          *       back as set or not.  The PCI0646U2 specs clarify
599          *       this point.
600          */
601         (void) pci_write_config_byte(dev, MRDMODE, mrdmode | 0x02);
602
603         /* Set reasonable active/recovery/address-setup values. */
604         (void) pci_write_config_byte(dev, ARTTIM0,  0x40);
605         (void) pci_write_config_byte(dev, DRWTIM0,  0x3f);
606         (void) pci_write_config_byte(dev, ARTTIM1,  0x40);
607         (void) pci_write_config_byte(dev, DRWTIM1,  0x3f);
608 #ifdef __i386__
609         (void) pci_write_config_byte(dev, ARTTIM23, 0x1c);
610 #else
611         (void) pci_write_config_byte(dev, ARTTIM23, 0x5c);
612 #endif
613         (void) pci_write_config_byte(dev, DRWTIM23, 0x3f);
614         (void) pci_write_config_byte(dev, DRWTIM3,  0x3f);
615 #ifdef CONFIG_PPC
616         (void) pci_write_config_byte(dev, UDIDETCR0, 0xf0);
617 #endif /* CONFIG_PPC */
618
619 #if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_PROC_FS)
620
621         cmd_devs[n_cmd_devs++] = dev;
622
623         if (!cmd64x_proc) {
624                 cmd64x_proc = 1;
625                 ide_pci_create_host_proc("cmd64x", cmd64x_get_info);
626         }
627 #endif /* DISPLAY_CMD64X_TIMINGS && CONFIG_PROC_FS */
628
629         return 0;
630 }
631
632 static unsigned int __devinit ata66_cmd64x(ide_hwif_t *hwif)
633 {
634         u8 ata66 = 0, mask = (hwif->channel) ? 0x02 : 0x01;
635
636         switch(hwif->pci_dev->device) {
637                 case PCI_DEVICE_ID_CMD_643:
638                 case PCI_DEVICE_ID_CMD_646:
639                         return ata66;
640                 default:
641                         break;
642         }
643         pci_read_config_byte(hwif->pci_dev, BMIDECSR, &ata66);
644         return (ata66 & mask) ? 1 : 0;
645 }
646
647 static void __devinit init_hwif_cmd64x(ide_hwif_t *hwif)
648 {
649         struct pci_dev *dev     = hwif->pci_dev;
650         unsigned int class_rev;
651
652         hwif->autodma = 0;
653         pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
654         class_rev &= 0xff;
655
656         hwif->tuneproc  = &cmd64x_tune_drive;
657         hwif->speedproc = &cmd64x_tune_chipset;
658
659         hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
660
661         if (!hwif->dma_base)
662                 return;
663
664         hwif->atapi_dma = 1;
665
666         hwif->ultra_mask = 0x3f;
667         hwif->mwdma_mask = 0x07;
668         hwif->swdma_mask = 0x07;
669
670         if (dev->device == PCI_DEVICE_ID_CMD_643)
671                 hwif->ultra_mask = 0x80;
672         if (dev->device == PCI_DEVICE_ID_CMD_646)
673                 hwif->ultra_mask = (class_rev > 0x04) ? 0x07 : 0x80;
674         if (dev->device == PCI_DEVICE_ID_CMD_648)
675                 hwif->ultra_mask = 0x1f;
676
677         hwif->ide_dma_check = &cmd64x_config_drive_for_dma;
678         if (!(hwif->udma_four))
679                 hwif->udma_four = ata66_cmd64x(hwif);
680
681         if (dev->device == PCI_DEVICE_ID_CMD_646) {
682                 hwif->chipset = ide_cmd646;
683                 if (class_rev == 0x01) {
684                         hwif->ide_dma_end = &cmd646_1_ide_dma_end;
685                 } else {
686                         hwif->ide_dma_end = &cmd64x_ide_dma_end;
687                         hwif->ide_dma_test_irq = &cmd64x_ide_dma_test_irq;
688                 }
689         } else {
690                 hwif->ide_dma_end = &cmd64x_ide_dma_end;
691                 hwif->ide_dma_test_irq = &cmd64x_ide_dma_test_irq;
692         }
693
694
695         if (!noautodma)
696                 hwif->autodma = 1;
697         hwif->drives[0].autodma = hwif->autodma;
698         hwif->drives[1].autodma = hwif->autodma;
699 }
700
701 static ide_pci_device_t cmd64x_chipsets[] __devinitdata = {
702         {       /* 0 */
703                 .name           = "CMD643",
704                 .init_chipset   = init_chipset_cmd64x,
705                 .init_hwif      = init_hwif_cmd64x,
706                 .channels       = 2,
707                 .autodma        = AUTODMA,
708                 .bootable       = ON_BOARD,
709         },{     /* 1 */
710                 .name           = "CMD646",
711                 .init_chipset   = init_chipset_cmd64x,
712                 .init_hwif      = init_hwif_cmd64x,
713                 .channels       = 2,
714                 .autodma        = AUTODMA,
715                 .enablebits     = {{0x00,0x00,0x00}, {0x51,0x80,0x80}},
716                 .bootable       = ON_BOARD,
717         },{     /* 2 */
718                 .name           = "CMD648",
719                 .init_chipset   = init_chipset_cmd64x,
720                 .init_hwif      = init_hwif_cmd64x,
721                 .channels       = 2,
722                 .autodma        = AUTODMA,
723                 .bootable       = ON_BOARD,
724         },{     /* 3 */
725                 .name           = "CMD649",
726                 .init_chipset   = init_chipset_cmd64x,
727                 .init_hwif      = init_hwif_cmd64x,
728                 .channels       = 2,
729                 .autodma        = AUTODMA,
730                 .bootable       = ON_BOARD,
731         }
732 };
733
734 static int __devinit cmd64x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
735 {
736         return ide_setup_pci_device(dev, &cmd64x_chipsets[id->driver_data]);
737 }
738
739 static struct pci_device_id cmd64x_pci_tbl[] = {
740         { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_643, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
741         { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
742         { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_648, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
743         { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
744         { 0, },
745 };
746 MODULE_DEVICE_TABLE(pci, cmd64x_pci_tbl);
747
748 static struct pci_driver driver = {
749         .name           = "CMD64x_IDE",
750         .id_table       = cmd64x_pci_tbl,
751         .probe          = cmd64x_init_one,
752 };
753
754 static int __init cmd64x_ide_init(void)
755 {
756         return ide_pci_register_driver(&driver);
757 }
758
759 module_init(cmd64x_ide_init);
760
761 MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick");
762 MODULE_DESCRIPTION("PCI driver module for CMD64x IDE");
763 MODULE_LICENSE("GPL");