Merge rsync://www.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[linux-2.6] / arch / m32r / kernel / setup_oaks32r.c
1 /*
2  *  linux/arch/m32r/kernel/setup_oaks32r.c
3  *
4  *  Setup routines for OAKS32R Board
5  *
6  *  Copyright (c) 2002-2005  Hiroyuki Kondo, Hirokazu Takata,
7  *                           Hitoshi Yamamoto, Mamoru Sakugawa
8  */
9
10 #include <linux/config.h>
11 #include <linux/irq.h>
12 #include <linux/kernel.h>
13 #include <linux/init.h>
14
15 #include <asm/system.h>
16 #include <asm/m32r.h>
17 #include <asm/io.h>
18
19 #define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
20
21 #ifndef CONFIG_SMP
22 typedef struct {
23         unsigned long icucr;  /* ICU Control Register */
24 } icu_data_t;
25 #endif /* CONFIG_SMP */
26
27 icu_data_t icu_data[NR_IRQS];
28
29 static void disable_oaks32r_irq(unsigned int irq)
30 {
31         unsigned long port, data;
32
33         port = irq2port(irq);
34         data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
35         outl(data, port);
36 }
37
38 static void enable_oaks32r_irq(unsigned int irq)
39 {
40         unsigned long port, data;
41
42         port = irq2port(irq);
43         data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
44         outl(data, port);
45 }
46
47 static void mask_and_ack_mappi(unsigned int irq)
48 {
49         disable_oaks32r_irq(irq);
50 }
51
52 static void end_oaks32r_irq(unsigned int irq)
53 {
54         enable_oaks32r_irq(irq);
55 }
56
57 static unsigned int startup_oaks32r_irq(unsigned int irq)
58 {
59         enable_oaks32r_irq(irq);
60         return (0);
61 }
62
63 static void shutdown_oaks32r_irq(unsigned int irq)
64 {
65         unsigned long port;
66
67         port = irq2port(irq);
68         outl(M32R_ICUCR_ILEVEL7, port);
69 }
70
71 static struct hw_interrupt_type oaks32r_irq_type =
72 {
73         .typename = "OAKS32R-IRQ",
74         .startup = startup_oaks32r_irq,
75         .shutdown = shutdown_oaks32r_irq,
76         .enable = enable_oaks32r_irq,
77         .disable = disable_oaks32r_irq,
78         .ack = mask_and_ack_mappi,
79         .end = end_oaks32r_irq
80 };
81
82 void __init init_IRQ(void)
83 {
84         static int once = 0;
85
86         if (once)
87                 return;
88         else
89                 once++;
90
91 #ifdef CONFIG_NE2000
92         /* INT3 : LAN controller (RTL8019AS) */
93         irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED;
94         irq_desc[M32R_IRQ_INT3].handler = &oaks32r_irq_type;
95         irq_desc[M32R_IRQ_INT3].action = 0;
96         irq_desc[M32R_IRQ_INT3].depth = 1;
97         icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
98         disable_oaks32r_irq(M32R_IRQ_INT3);
99 #endif /* CONFIG_M32R_NE2000 */
100
101         /* MFT2 : system timer */
102         irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
103         irq_desc[M32R_IRQ_MFT2].handler = &oaks32r_irq_type;
104         irq_desc[M32R_IRQ_MFT2].action = 0;
105         irq_desc[M32R_IRQ_MFT2].depth = 1;
106         icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
107         disable_oaks32r_irq(M32R_IRQ_MFT2);
108
109 #ifdef CONFIG_SERIAL_M32R_SIO
110         /* SIO0_R : uart receive data */
111         irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
112         irq_desc[M32R_IRQ_SIO0_R].handler = &oaks32r_irq_type;
113         irq_desc[M32R_IRQ_SIO0_R].action = 0;
114         irq_desc[M32R_IRQ_SIO0_R].depth = 1;
115         icu_data[M32R_IRQ_SIO0_R].icucr = 0;
116         disable_oaks32r_irq(M32R_IRQ_SIO0_R);
117
118         /* SIO0_S : uart send data */
119         irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
120         irq_desc[M32R_IRQ_SIO0_S].handler = &oaks32r_irq_type;
121         irq_desc[M32R_IRQ_SIO0_S].action = 0;
122         irq_desc[M32R_IRQ_SIO0_S].depth = 1;
123         icu_data[M32R_IRQ_SIO0_S].icucr = 0;
124         disable_oaks32r_irq(M32R_IRQ_SIO0_S);
125
126         /* SIO1_R : uart receive data */
127         irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
128         irq_desc[M32R_IRQ_SIO1_R].handler = &oaks32r_irq_type;
129         irq_desc[M32R_IRQ_SIO1_R].action = 0;
130         irq_desc[M32R_IRQ_SIO1_R].depth = 1;
131         icu_data[M32R_IRQ_SIO1_R].icucr = 0;
132         disable_oaks32r_irq(M32R_IRQ_SIO1_R);
133
134         /* SIO1_S : uart send data */
135         irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
136         irq_desc[M32R_IRQ_SIO1_S].handler = &oaks32r_irq_type;
137         irq_desc[M32R_IRQ_SIO1_S].action = 0;
138         irq_desc[M32R_IRQ_SIO1_S].depth = 1;
139         icu_data[M32R_IRQ_SIO1_S].icucr = 0;
140         disable_oaks32r_irq(M32R_IRQ_SIO1_S);
141 #endif /* CONFIG_SERIAL_M32R_SIO */
142 }