git.oblomov.eu Git - linux-2.6/blob - arch/powerpc/boot/dts/mpc8548cds.dts

   1 /*
   2  * MPC8548 CDS Device Tree Source
   3  *
   4  * Copyright 2006, 2008 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 /dts-v1/;
  13
  14 / {
  15         model = "MPC8548CDS";
  16         compatible = "MPC8548CDS", "MPC85xxCDS";
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         aliases {
  21                 ethernet0 = &enet0;
  22                 ethernet1 = &enet1;
  23 /*
  24                 ethernet2 = &enet2;
  25                 ethernet3 = &enet3;
  26 */
  27                 serial0 = &serial0;
  28                 serial1 = &serial1;
  29                 pci0 = &pci0;
  30                 pci1 = &pci1;
  31                 pci2 = &pci2;
  32         };
  33
  34         cpus {
  35                 #address-cells = <1>;
  36                 #size-cells = <0>;
  37
  38                 PowerPC,8548@0 {
  39                         device_type = "cpu";
  40                         reg = <0x0>;
  41                         d-cache-line-size = <32>;       // 32 bytes
  42                         i-cache-line-size = <32>;       // 32 bytes
  43                         d-cache-size = <0x8000>;                // L1, 32K
  44                         i-cache-size = <0x8000>;                // L1, 32K
  45                         timebase-frequency = <0>;       //  33 MHz, from uboot
  46                         bus-frequency = <0>;    // 166 MHz
  47                         clock-frequency = <0>;  // 825 MHz, from uboot
  48                         next-level-cache = <&L2>;
  49                 };
  50         };
  51
  52         memory {
  53                 device_type = "memory";
  54                 reg = <0x0 0x8000000>;  // 128M at 0x0
  55         };
  56
  57         soc8548@e0000000 {
  58                 #address-cells = <1>;
  59                 #size-cells = <1>;
  60                 device_type = "soc";
  61                 compatible = "simple-bus";
  62                 ranges = <0x0 0xe0000000 0x100000>;
  63                 reg = <0xe0000000 0x1000>;      // CCSRBAR
  64                 bus-frequency = <0>;
  65
  66                 ecm-law@0 {
  67                         compatible = "fsl,ecm-law";
  68                         reg = <0x0 0x1000>;
  69                         fsl,num-laws = <10>;
  70                 };
  71
  72                 ecm@1000 {
  73                         compatible = "fsl,mpc8548-ecm", "fsl,ecm";
  74                         reg = <0x1000 0x1000>;
  75                         interrupts = <17 2>;
  76                         interrupt-parent = <&mpic>;
  77                 };
  78
  79                 memory-controller@2000 {
  80                         compatible = "fsl,8548-memory-controller";
  81                         reg = <0x2000 0x1000>;
  82                         interrupt-parent = <&mpic>;
  83                         interrupts = <18 2>;
  84                 };
  85
  86                 L2: l2-cache-controller@20000 {
  87                         compatible = "fsl,8548-l2-cache-controller";
  88                         reg = <0x20000 0x1000>;
  89                         cache-line-size = <32>; // 32 bytes
  90                         cache-size = <0x80000>; // L2, 512K
  91                         interrupt-parent = <&mpic>;
  92                         interrupts = <16 2>;
  93                 };
  94
  95                 i2c@3000 {
  96                         #address-cells = <1>;
  97                         #size-cells = <0>;
  98                         cell-index = <0>;
  99                         compatible = "fsl-i2c";
 100                         reg = <0x3000 0x100>;
 101                         interrupts = <43 2>;
 102                         interrupt-parent = <&mpic>;
 103                         dfsrr;
 104                 };
 105
 106                 i2c@3100 {
 107                         #address-cells = <1>;
 108                         #size-cells = <0>;
 109                         cell-index = <1>;
 110                         compatible = "fsl-i2c";
 111                         reg = <0x3100 0x100>;
 112                         interrupts = <43 2>;
 113                         interrupt-parent = <&mpic>;
 114                         dfsrr;
 115                 };
 116
 117                 dma@21300 {
 118                         #address-cells = <1>;
 119                         #size-cells = <1>;
 120                         compatible = "fsl,mpc8548-dma", "fsl,eloplus-dma";
 121                         reg = <0x21300 0x4>;
 122                         ranges = <0x0 0x21100 0x200>;
 123                         cell-index = <0>;
 124                         dma-channel@0 {
 125                                 compatible = "fsl,mpc8548-dma-channel",
 126                                                 "fsl,eloplus-dma-channel";
 127                                 reg = <0x0 0x80>;
 128                                 cell-index = <0>;
 129                                 interrupt-parent = <&mpic>;
 130                                 interrupts = <20 2>;
 131                         };
 132                         dma-channel@80 {
 133                                 compatible = "fsl,mpc8548-dma-channel",
 134                                                 "fsl,eloplus-dma-channel";
 135                                 reg = <0x80 0x80>;
 136                                 cell-index = <1>;
 137                                 interrupt-parent = <&mpic>;
 138                                 interrupts = <21 2>;
 139                         };
 140                         dma-channel@100 {
 141                                 compatible = "fsl,mpc8548-dma-channel",
 142                                                 "fsl,eloplus-dma-channel";
 143                                 reg = <0x100 0x80>;
 144                                 cell-index = <2>;
 145                                 interrupt-parent = <&mpic>;
 146                                 interrupts = <22 2>;
 147                         };
 148                         dma-channel@180 {
 149                                 compatible = "fsl,mpc8548-dma-channel",
 150                                                 "fsl,eloplus-dma-channel";
 151                                 reg = <0x180 0x80>;
 152                                 cell-index = <3>;
 153                                 interrupt-parent = <&mpic>;
 154                                 interrupts = <23 2>;
 155                         };
 156                 };
 157
 158                 enet0: ethernet@24000 {
 159                         #address-cells = <1>;
 160                         #size-cells = <1>;
 161                         cell-index = <0>;
 162                         device_type = "network";
 163                         model = "eTSEC";
 164                         compatible = "gianfar";
 165                         reg = <0x24000 0x1000>;
 166                         ranges = <0x0 0x24000 0x1000>;
 167                         local-mac-address = [ 00 00 00 00 00 00 ];
 168                         interrupts = <29 2 30 2 34 2>;
 169                         interrupt-parent = <&mpic>;
 170                         tbi-handle = <&tbi0>;
 171                         phy-handle = <&phy0>;
 172
 173                         mdio@520 {
 174                                 #address-cells = <1>;
 175                                 #size-cells = <0>;
 176                                 compatible = "fsl,gianfar-mdio";
 177                                 reg = <0x520 0x20>;
 178
 179                                 phy0: ethernet-phy@0 {
 180                                         interrupt-parent = <&mpic>;
 181                                         interrupts = <5 1>;
 182                                         reg = <0x0>;
 183                                         device_type = "ethernet-phy";
 184                                 };
 185                                 phy1: ethernet-phy@1 {
 186                                         interrupt-parent = <&mpic>;
 187                                         interrupts = <5 1>;
 188                                         reg = <0x1>;
 189                                         device_type = "ethernet-phy";
 190                                 };
 191                                 phy2: ethernet-phy@2 {
 192                                         interrupt-parent = <&mpic>;
 193                                         interrupts = <5 1>;
 194                                         reg = <0x2>;
 195                                         device_type = "ethernet-phy";
 196                                 };
 197                                 phy3: ethernet-phy@3 {
 198                                         interrupt-parent = <&mpic>;
 199                                         interrupts = <5 1>;
 200                                         reg = <0x3>;
 201                                         device_type = "ethernet-phy";
 202                                 };
 203                                 tbi0: tbi-phy@11 {
 204                                         reg = <0x11>;
 205                                         device_type = "tbi-phy";
 206                                 };
 207                         };
 208                 };
 209
 210                 enet1: ethernet@25000 {
 211                         #address-cells = <1>;
 212                         #size-cells = <1>;
 213                         cell-index = <1>;
 214                         device_type = "network";
 215                         model = "eTSEC";
 216                         compatible = "gianfar";
 217                         reg = <0x25000 0x1000>;
 218                         ranges = <0x0 0x25000 0x1000>;
 219                         local-mac-address = [ 00 00 00 00 00 00 ];
 220                         interrupts = <35 2 36 2 40 2>;
 221                         interrupt-parent = <&mpic>;
 222                         tbi-handle = <&tbi1>;
 223                         phy-handle = <&phy1>;
 224
 225                         mdio@520 {
 226                                 #address-cells = <1>;
 227                                 #size-cells = <0>;
 228                                 compatible = "fsl,gianfar-tbi";
 229                                 reg = <0x520 0x20>;
 230
 231                                 tbi1: tbi-phy@11 {
 232                                         reg = <0x11>;
 233                                         device_type = "tbi-phy";
 234                                 };
 235                         };
 236                 };
 237
 238 /* eTSEC 3/4 are currently broken
 239                 enet2: ethernet@26000 {
 240                         #address-cells = <1>;
 241                         #size-cells = <1>;
 242                         cell-index = <2>;
 243                         device_type = "network";
 244                         model = "eTSEC";
 245                         compatible = "gianfar";
 246                         reg = <0x26000 0x1000>;
 247                         ranges = <0x0 0x26000 0x1000>;
 248                         local-mac-address = [ 00 00 00 00 00 00 ];
 249                         interrupts = <31 2 32 2 33 2>;
 250                         interrupt-parent = <&mpic>;
 251                         tbi-handle = <&tbi2>;
 252                         phy-handle = <&phy2>;
 253
 254                         mdio@520 {
 255                                 #address-cells = <1>;
 256                                 #size-cells = <0>;
 257                                 compatible = "fsl,gianfar-tbi";
 258                                 reg = <0x520 0x20>;
 259
 260                                 tbi2: tbi-phy@11 {
 261                                         reg = <0x11>;
 262                                         device_type = "tbi-phy";
 263                                 };
 264                         };
 265                 };
 266
 267                 enet3: ethernet@27000 {
 268                         #address-cells = <1>;
 269                         #size-cells = <1>;
 270                         cell-index = <3>;
 271                         device_type = "network";
 272                         model = "eTSEC";
 273                         compatible = "gianfar";
 274                         reg = <0x27000 0x1000>;
 275                         ranges = <0x0 0x27000 0x1000>;
 276                         local-mac-address = [ 00 00 00 00 00 00 ];
 277                         interrupts = <37 2 38 2 39 2>;
 278                         interrupt-parent = <&mpic>;
 279                         tbi-handle = <&tbi3>;
 280                         phy-handle = <&phy3>;
 281
 282                         mdio@520 {
 283                                 #address-cells = <1>;
 284                                 #size-cells = <0>;
 285                                 compatible = "fsl,gianfar-tbi";
 286                                 reg = <0x520 0x20>;
 287
 288                                 tbi3: tbi-phy@11 {
 289                                         reg = <0x11>;
 290                                         device_type = "tbi-phy";
 291                                 };
 292                         };
 293                 };
 294  */
 295
 296                 serial0: serial@4500 {
 297                         cell-index = <0>;
 298                         device_type = "serial";
 299                         compatible = "ns16550";
 300                         reg = <0x4500 0x100>;   // reg base, size
 301                         clock-frequency = <0>;  // should we fill in in uboot?
 302                         interrupts = <42 2>;
 303                         interrupt-parent = <&mpic>;
 304                 };
 305
 306                 serial1: serial@4600 {
 307                         cell-index = <1>;
 308                         device_type = "serial";
 309                         compatible = "ns16550";
 310                         reg = <0x4600 0x100>;   // reg base, size
 311                         clock-frequency = <0>;  // should we fill in in uboot?
 312                         interrupts = <42 2>;
 313                         interrupt-parent = <&mpic>;
 314                 };
 315
 316                 global-utilities@e0000 {        //global utilities reg
 317                         compatible = "fsl,mpc8548-guts";
 318                         reg = <0xe0000 0x1000>;
 319                         fsl,has-rstcr;
 320                 };
 321
 322                 crypto@30000 {
 323                         compatible = "fsl,sec2.1", "fsl,sec2.0";
 324                         reg = <0x30000 0x10000>;
 325                         interrupts = <45 2>;
 326                         interrupt-parent = <&mpic>;
 327                         fsl,num-channels = <4>;
 328                         fsl,channel-fifo-len = <24>;
 329                         fsl,exec-units-mask = <0xfe>;
 330                         fsl,descriptor-types-mask = <0x12b0ebf>;
 331                 };
 332
 333                 mpic: pic@40000 {
 334                         interrupt-controller;
 335                         #address-cells = <0>;
 336                         #interrupt-cells = <2>;
 337                         reg = <0x40000 0x40000>;
 338                         compatible = "chrp,open-pic";
 339                         device_type = "open-pic";
 340                 };
 341         };
 342
 343         pci0: pci@e0008000 {
 344                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 345                 interrupt-map = <
 346                         /* IDSEL 0x4 (PCIX Slot 2) */
 347                         0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
 348                         0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
 349                         0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
 350                         0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
 351
 352                         /* IDSEL 0x5 (PCIX Slot 3) */
 353                         0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
 354                         0x2800 0x0 0x0 0x2 &mpic 0x2 0x1
 355                         0x2800 0x0 0x0 0x3 &mpic 0x3 0x1
 356                         0x2800 0x0 0x0 0x4 &mpic 0x0 0x1
 357
 358                         /* IDSEL 0x6 (PCIX Slot 4) */
 359                         0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
 360                         0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
 361                         0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
 362                         0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
 363
 364                         /* IDSEL 0x8 (PCIX Slot 5) */
 365                         0x4000 0x0 0x0 0x1 &mpic 0x0 0x1
 366                         0x4000 0x0 0x0 0x2 &mpic 0x1 0x1
 367                         0x4000 0x0 0x0 0x3 &mpic 0x2 0x1
 368                         0x4000 0x0 0x0 0x4 &mpic 0x3 0x1
 369
 370                         /* IDSEL 0xC (Tsi310 bridge) */
 371                         0x6000 0x0 0x0 0x1 &mpic 0x0 0x1
 372                         0x6000 0x0 0x0 0x2 &mpic 0x1 0x1
 373                         0x6000 0x0 0x0 0x3 &mpic 0x2 0x1
 374                         0x6000 0x0 0x0 0x4 &mpic 0x3 0x1
 375
 376                         /* IDSEL 0x14 (Slot 2) */
 377                         0xa000 0x0 0x0 0x1 &mpic 0x0 0x1
 378                         0xa000 0x0 0x0 0x2 &mpic 0x1 0x1
 379                         0xa000 0x0 0x0 0x3 &mpic 0x2 0x1
 380                         0xa000 0x0 0x0 0x4 &mpic 0x3 0x1
 381
 382                         /* IDSEL 0x15 (Slot 3) */
 383                         0xa800 0x0 0x0 0x1 &mpic 0x1 0x1
 384                         0xa800 0x0 0x0 0x2 &mpic 0x2 0x1
 385                         0xa800 0x0 0x0 0x3 &mpic 0x3 0x1
 386                         0xa800 0x0 0x0 0x4 &mpic 0x0 0x1
 387
 388                         /* IDSEL 0x16 (Slot 4) */
 389                         0xb000 0x0 0x0 0x1 &mpic 0x2 0x1
 390                         0xb000 0x0 0x0 0x2 &mpic 0x3 0x1
 391                         0xb000 0x0 0x0 0x3 &mpic 0x0 0x1
 392                         0xb000 0x0 0x0 0x4 &mpic 0x1 0x1
 393
 394                         /* IDSEL 0x18 (Slot 5) */
 395                         0xc000 0x0 0x0 0x1 &mpic 0x0 0x1
 396                         0xc000 0x0 0x0 0x2 &mpic 0x1 0x1
 397                         0xc000 0x0 0x0 0x3 &mpic 0x2 0x1
 398                         0xc000 0x0 0x0 0x4 &mpic 0x3 0x1
 399
 400                         /* IDSEL 0x1C (Tsi310 bridge PCI primary) */
 401                         0xe000 0x0 0x0 0x1 &mpic 0x0 0x1
 402                         0xe000 0x0 0x0 0x2 &mpic 0x1 0x1
 403                         0xe000 0x0 0x0 0x3 &mpic 0x2 0x1
 404                         0xe000 0x0 0x0 0x4 &mpic 0x3 0x1>;
 405
 406                 interrupt-parent = <&mpic>;
 407                 interrupts = <24 2>;
 408                 bus-range = <0 0>;
 409                 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x10000000
 410                           0x1000000 0x0 0x0 0xe2000000 0x0 0x800000>;
 411                 clock-frequency = <66666666>;
 412                 #interrupt-cells = <1>;
 413                 #size-cells = <2>;
 414                 #address-cells = <3>;
 415                 reg = <0xe0008000 0x1000>;
 416                 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
 417                 device_type = "pci";
 418
 419                 pci_bridge@1c {
 420                         interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 421                         interrupt-map = <
 422
 423                                 /* IDSEL 0x00 (PrPMC Site) */
 424                                 0000 0x0 0x0 0x1 &mpic 0x0 0x1
 425                                 0000 0x0 0x0 0x2 &mpic 0x1 0x1
 426                                 0000 0x0 0x0 0x3 &mpic 0x2 0x1
 427                                 0000 0x0 0x0 0x4 &mpic 0x3 0x1
 428
 429                                 /* IDSEL 0x04 (VIA chip) */
 430                                 0x2000 0x0 0x0 0x1 &mpic 0x0 0x1
 431                                 0x2000 0x0 0x0 0x2 &mpic 0x1 0x1
 432                                 0x2000 0x0 0x0 0x3 &mpic 0x2 0x1
 433                                 0x2000 0x0 0x0 0x4 &mpic 0x3 0x1
 434
 435                                 /* IDSEL 0x05 (8139) */
 436                                 0x2800 0x0 0x0 0x1 &mpic 0x1 0x1
 437
 438                                 /* IDSEL 0x06 (Slot 6) */
 439                                 0x3000 0x0 0x0 0x1 &mpic 0x2 0x1
 440                                 0x3000 0x0 0x0 0x2 &mpic 0x3 0x1
 441                                 0x3000 0x0 0x0 0x3 &mpic 0x0 0x1
 442                                 0x3000 0x0 0x0 0x4 &mpic 0x1 0x1
 443
 444                                 /* IDESL 0x07 (Slot 7) */
 445                                 0x3800 0x0 0x0 0x1 &mpic 0x3 0x1
 446                                 0x3800 0x0 0x0 0x2 &mpic 0x0 0x1
 447                                 0x3800 0x0 0x0 0x3 &mpic 0x1 0x1
 448                                 0x3800 0x0 0x0 0x4 &mpic 0x2 0x1>;
 449
 450                         reg = <0xe000 0x0 0x0 0x0 0x0>;
 451                         #interrupt-cells = <1>;
 452                         #size-cells = <2>;
 453                         #address-cells = <3>;
 454                         ranges = <0x2000000 0x0 0x80000000
 455                                   0x2000000 0x0 0x80000000
 456                                   0x0 0x20000000
 457                                   0x1000000 0x0 0x0
 458                                   0x1000000 0x0 0x0
 459                                   0x0 0x80000>;
 460                         clock-frequency = <33333333>;
 461
 462                         isa@4 {
 463                                 device_type = "isa";
 464                                 #interrupt-cells = <2>;
 465                                 #size-cells = <1>;
 466                                 #address-cells = <2>;
 467                                 reg = <0x2000 0x0 0x0 0x0 0x0>;
 468                                 ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>;
 469                                 interrupt-parent = <&i8259>;
 470
 471                                 i8259: interrupt-controller@20 {
 472                                         interrupt-controller;
 473                                         device_type = "interrupt-controller";
 474                                         reg = <0x1 0x20 0x2
 475                                                0x1 0xa0 0x2
 476                                                0x1 0x4d0 0x2>;
 477                                         #address-cells = <0>;
 478                                         #interrupt-cells = <2>;
 479                                         compatible = "chrp,iic";
 480                                         interrupts = <0 1>;
 481                                         interrupt-parent = <&mpic>;
 482                                 };
 483
 484                                 rtc@70 {
 485                                         compatible = "pnpPNP,b00";
 486                                         reg = <0x1 0x70 0x2>;
 487                                 };
 488                         };
 489                 };
 490         };
 491
 492         pci1: pci@e0009000 {
 493                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 494                 interrupt-map = <
 495
 496                         /* IDSEL 0x15 */
 497                         0xa800 0x0 0x0 0x1 &mpic 0xb 0x1
 498                         0xa800 0x0 0x0 0x2 &mpic 0x1 0x1
 499                         0xa800 0x0 0x0 0x3 &mpic 0x2 0x1
 500                         0xa800 0x0 0x0 0x4 &mpic 0x3 0x1>;
 501
 502                 interrupt-parent = <&mpic>;
 503                 interrupts = <25 2>;
 504                 bus-range = <0 0>;
 505                 ranges = <0x2000000 0x0 0x90000000 0x90000000 0x0 0x10000000
 506                           0x1000000 0x0 0x0 0xe2800000 0x0 0x800000>;
 507                 clock-frequency = <66666666>;
 508                 #interrupt-cells = <1>;
 509                 #size-cells = <2>;
 510                 #address-cells = <3>;
 511                 reg = <0xe0009000 0x1000>;
 512                 compatible = "fsl,mpc8540-pci";
 513                 device_type = "pci";
 514         };
 515
 516         pci2: pcie@e000a000 {
 517                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 518                 interrupt-map = <
 519
 520                         /* IDSEL 0x0 (PEX) */
 521                         00000 0x0 0x0 0x1 &mpic 0x0 0x1
 522                         00000 0x0 0x0 0x2 &mpic 0x1 0x1
 523                         00000 0x0 0x0 0x3 &mpic 0x2 0x1
 524                         00000 0x0 0x0 0x4 &mpic 0x3 0x1>;
 525
 526                 interrupt-parent = <&mpic>;
 527                 interrupts = <26 2>;
 528                 bus-range = <0 255>;
 529                 ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
 530                           0x1000000 0x0 0x0 0xe3000000 0x0 0x100000>;
 531                 clock-frequency = <33333333>;
 532                 #interrupt-cells = <1>;
 533                 #size-cells = <2>;
 534                 #address-cells = <3>;
 535                 reg = <0xe000a000 0x1000>;
 536                 compatible = "fsl,mpc8548-pcie";
 537                 device_type = "pci";
 538                 pcie@0 {
 539                         reg = <0x0 0x0 0x0 0x0 0x0>;
 540                         #size-cells = <2>;
 541                         #address-cells = <3>;
 542                         device_type = "pci";
 543                         ranges = <0x2000000 0x0 0xa0000000
 544                                   0x2000000 0x0 0xa0000000
 545                                   0x0 0x20000000
 546
 547                                   0x1000000 0x0 0x0
 548                                   0x1000000 0x0 0x0
 549                                   0x0 0x100000>;
 550                 };
 551         };
 552 };