2 * sata_svw.c - ServerWorks / Apple K2 SATA
4 * Maintained by: Benjamin Herrenschmidt <benh@kernel.crashing.org> and
5 * Jeff Garzik <jgarzik@pobox.com>
6 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>
11 * Bits from Jeff Garzik, Copyright RedHat, Inc.
13 * This driver probably works with non-Apple versions of the
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License as published by
19 * the Free Software Foundation; either version 2, or (at your option)
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
27 * You should have received a copy of the GNU General Public License
28 * along with this program; see the file COPYING. If not, write to
29 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
32 * libata documentation is available via 'make {ps|pdf}docs',
33 * as Documentation/DocBook/libata.*
35 * Hardware documentation available under NDA.
39 #include <linux/config.h>
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/pci.h>
43 #include <linux/init.h>
44 #include <linux/blkdev.h>
45 #include <linux/delay.h>
46 #include <linux/interrupt.h>
47 #include <linux/device.h>
48 #include <scsi/scsi_host.h>
49 #include <linux/libata.h>
53 #include <asm/pci-bridge.h>
54 #endif /* CONFIG_PPC_OF */
56 #define DRV_NAME "sata_svw"
57 #define DRV_VERSION "1.07"
59 /* Taskfile registers offsets */
60 #define K2_SATA_TF_CMD_OFFSET 0x00
61 #define K2_SATA_TF_DATA_OFFSET 0x00
62 #define K2_SATA_TF_ERROR_OFFSET 0x04
63 #define K2_SATA_TF_NSECT_OFFSET 0x08
64 #define K2_SATA_TF_LBAL_OFFSET 0x0c
65 #define K2_SATA_TF_LBAM_OFFSET 0x10
66 #define K2_SATA_TF_LBAH_OFFSET 0x14
67 #define K2_SATA_TF_DEVICE_OFFSET 0x18
68 #define K2_SATA_TF_CMDSTAT_OFFSET 0x1c
69 #define K2_SATA_TF_CTL_OFFSET 0x20
72 #define K2_SATA_DMA_CMD_OFFSET 0x30
75 #define K2_SATA_SCR_STATUS_OFFSET 0x40
76 #define K2_SATA_SCR_ERROR_OFFSET 0x44
77 #define K2_SATA_SCR_CONTROL_OFFSET 0x48
80 #define K2_SATA_SICR1_OFFSET 0x80
81 #define K2_SATA_SICR2_OFFSET 0x84
82 #define K2_SATA_SIM_OFFSET 0x88
85 #define K2_SATA_PORT_OFFSET 0x100
87 static u8 k2_stat_check_status(struct ata_port *ap);
90 static u32 k2_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
92 if (sc_reg > SCR_CONTROL)
94 return readl((void *) ap->ioaddr.scr_addr + (sc_reg * 4));
98 static void k2_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
101 if (sc_reg > SCR_CONTROL)
103 writel(val, (void *) ap->ioaddr.scr_addr + (sc_reg * 4));
107 static void k2_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
109 struct ata_ioports *ioaddr = &ap->ioaddr;
110 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
112 if (tf->ctl != ap->last_ctl) {
113 writeb(tf->ctl, ioaddr->ctl_addr);
114 ap->last_ctl = tf->ctl;
117 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
118 writew(tf->feature | (((u16)tf->hob_feature) << 8), ioaddr->feature_addr);
119 writew(tf->nsect | (((u16)tf->hob_nsect) << 8), ioaddr->nsect_addr);
120 writew(tf->lbal | (((u16)tf->hob_lbal) << 8), ioaddr->lbal_addr);
121 writew(tf->lbam | (((u16)tf->hob_lbam) << 8), ioaddr->lbam_addr);
122 writew(tf->lbah | (((u16)tf->hob_lbah) << 8), ioaddr->lbah_addr);
123 } else if (is_addr) {
124 writew(tf->feature, ioaddr->feature_addr);
125 writew(tf->nsect, ioaddr->nsect_addr);
126 writew(tf->lbal, ioaddr->lbal_addr);
127 writew(tf->lbam, ioaddr->lbam_addr);
128 writew(tf->lbah, ioaddr->lbah_addr);
131 if (tf->flags & ATA_TFLAG_DEVICE)
132 writeb(tf->device, ioaddr->device_addr);
138 static void k2_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
140 struct ata_ioports *ioaddr = &ap->ioaddr;
141 u16 nsect, lbal, lbam, lbah, feature;
143 tf->command = k2_stat_check_status(ap);
144 tf->device = readw(ioaddr->device_addr);
145 feature = readw(ioaddr->error_addr);
146 nsect = readw(ioaddr->nsect_addr);
147 lbal = readw(ioaddr->lbal_addr);
148 lbam = readw(ioaddr->lbam_addr);
149 lbah = readw(ioaddr->lbah_addr);
151 tf->feature = feature;
157 if (tf->flags & ATA_TFLAG_LBA48) {
158 tf->hob_feature = feature >> 8;
159 tf->hob_nsect = nsect >> 8;
160 tf->hob_lbal = lbal >> 8;
161 tf->hob_lbam = lbam >> 8;
162 tf->hob_lbah = lbah >> 8;
167 * k2_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction (MMIO)
168 * @qc: Info associated with this ATA transaction.
171 * spin_lock_irqsave(host_set lock)
174 static void k2_bmdma_setup_mmio (struct ata_queued_cmd *qc)
176 struct ata_port *ap = qc->ap;
177 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
179 void *mmio = (void *) ap->ioaddr.bmdma_addr;
180 /* load PRD table addr. */
181 mb(); /* make sure PRD table writes are visible to controller */
182 writel(ap->prd_dma, mmio + ATA_DMA_TABLE_OFS);
184 /* specify data direction, triple-check start bit is clear */
185 dmactl = readb(mmio + ATA_DMA_CMD);
186 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
188 dmactl |= ATA_DMA_WR;
189 writeb(dmactl, mmio + ATA_DMA_CMD);
191 /* issue r/w command if this is not a ATA DMA command*/
192 if (qc->tf.protocol != ATA_PROT_DMA)
193 ap->ops->exec_command(ap, &qc->tf);
197 * k2_bmdma_start_mmio - Start a PCI IDE BMDMA transaction (MMIO)
198 * @qc: Info associated with this ATA transaction.
201 * spin_lock_irqsave(host_set lock)
204 static void k2_bmdma_start_mmio (struct ata_queued_cmd *qc)
206 struct ata_port *ap = qc->ap;
207 void *mmio = (void *) ap->ioaddr.bmdma_addr;
210 /* start host DMA transaction */
211 dmactl = readb(mmio + ATA_DMA_CMD);
212 writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD);
213 /* There is a race condition in certain SATA controllers that can
214 be seen when the r/w command is given to the controller before the
215 host DMA is started. On a Read command, the controller would initiate
216 the command to the drive even before it sees the DMA start. When there
217 are very fast drives connected to the controller, or when the data request
218 hits in the drive cache, there is the possibility that the drive returns a part
219 or all of the requested data to the controller before the DMA start is issued.
220 In this case, the controller would become confused as to what to do with the data.
221 In the worst case when all the data is returned back to the controller, the
222 controller could hang. In other cases it could return partial data returning
223 in data corruption. This problem has been seen in PPC systems and can also appear
224 on an system with very fast disks, where the SATA controller is sitting behind a
225 number of bridges, and hence there is significant latency between the r/w command
226 and the start command. */
227 /* issue r/w command if the access is to ATA*/
228 if (qc->tf.protocol == ATA_PROT_DMA)
229 ap->ops->exec_command(ap, &qc->tf);
233 static u8 k2_stat_check_status(struct ata_port *ap)
235 return readl((void *) ap->ioaddr.status_addr);
241 * inout : decides on the direction of the dataflow and the meaning of the
243 * buffer: If inout==FALSE data is being written to it else read from it
244 * *start: If inout==FALSE start of the valid data in the buffer
245 * offset: If inout==FALSE offset from the beginning of the imaginary file
246 * from which we start writing into the buffer
247 * length: If inout==FALSE max number of bytes to be written into the buffer
248 * else number of bytes in the buffer
250 static int k2_sata_proc_info(struct Scsi_Host *shost, char *page, char **start,
251 off_t offset, int count, int inout)
254 struct device_node *np;
257 /* Find the ata_port */
258 ap = (struct ata_port *) &shost->hostdata[0];
262 /* Find the OF node for the PCI device proper */
263 np = pci_device_to_OF_node(to_pci_dev(ap->host_set->dev));
267 /* Match it to a port node */
268 index = (ap == ap->host_set->ports[0]) ? 0 : 1;
269 for (np = np->child; np != NULL; np = np->sibling) {
270 u32 *reg = (u32 *)get_property(np, "reg", NULL);
279 len = sprintf(page, "devspec: %s\n", np->full_name);
283 #endif /* CONFIG_PPC_OF */
286 static struct scsi_host_template k2_sata_sht = {
287 .module = THIS_MODULE,
289 .ioctl = ata_scsi_ioctl,
290 .queuecommand = ata_scsi_queuecmd,
291 .eh_strategy_handler = ata_scsi_error,
292 .can_queue = ATA_DEF_QUEUE,
293 .this_id = ATA_SHT_THIS_ID,
294 .sg_tablesize = LIBATA_MAX_PRD,
295 .max_sectors = ATA_MAX_SECTORS,
296 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
297 .emulated = ATA_SHT_EMULATED,
298 .use_clustering = ATA_SHT_USE_CLUSTERING,
299 .proc_name = DRV_NAME,
300 .dma_boundary = ATA_DMA_BOUNDARY,
301 .slave_configure = ata_scsi_slave_config,
303 .proc_info = k2_sata_proc_info,
305 .bios_param = ata_std_bios_param,
310 static const struct ata_port_operations k2_sata_ops = {
311 .port_disable = ata_port_disable,
312 .tf_load = k2_sata_tf_load,
313 .tf_read = k2_sata_tf_read,
314 .check_status = k2_stat_check_status,
315 .exec_command = ata_exec_command,
316 .dev_select = ata_std_dev_select,
317 .phy_reset = sata_phy_reset,
318 .bmdma_setup = k2_bmdma_setup_mmio,
319 .bmdma_start = k2_bmdma_start_mmio,
320 .bmdma_stop = ata_bmdma_stop,
321 .bmdma_status = ata_bmdma_status,
322 .qc_prep = ata_qc_prep,
323 .qc_issue = ata_qc_issue_prot,
324 .eng_timeout = ata_eng_timeout,
325 .irq_handler = ata_interrupt,
326 .irq_clear = ata_bmdma_irq_clear,
327 .scr_read = k2_sata_scr_read,
328 .scr_write = k2_sata_scr_write,
329 .port_start = ata_port_start,
330 .port_stop = ata_port_stop,
331 .host_stop = ata_pci_host_stop,
334 static void k2_sata_setup_port(struct ata_ioports *port, unsigned long base)
336 port->cmd_addr = base + K2_SATA_TF_CMD_OFFSET;
337 port->data_addr = base + K2_SATA_TF_DATA_OFFSET;
339 port->error_addr = base + K2_SATA_TF_ERROR_OFFSET;
340 port->nsect_addr = base + K2_SATA_TF_NSECT_OFFSET;
341 port->lbal_addr = base + K2_SATA_TF_LBAL_OFFSET;
342 port->lbam_addr = base + K2_SATA_TF_LBAM_OFFSET;
343 port->lbah_addr = base + K2_SATA_TF_LBAH_OFFSET;
344 port->device_addr = base + K2_SATA_TF_DEVICE_OFFSET;
346 port->status_addr = base + K2_SATA_TF_CMDSTAT_OFFSET;
347 port->altstatus_addr =
348 port->ctl_addr = base + K2_SATA_TF_CTL_OFFSET;
349 port->bmdma_addr = base + K2_SATA_DMA_CMD_OFFSET;
350 port->scr_addr = base + K2_SATA_SCR_STATUS_OFFSET;
354 static int k2_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
356 static int printed_version;
357 struct ata_probe_ent *probe_ent = NULL;
359 void __iomem *mmio_base;
360 int pci_dev_busy = 0;
364 if (!printed_version++)
365 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
368 * If this driver happens to only be useful on Apple's K2, then
369 * we should check that here as it has a normal Serverworks ID
371 rc = pci_enable_device(pdev);
375 * Check if we have resources mapped at all (second function may
376 * have been disabled by firmware)
378 if (pci_resource_len(pdev, 5) == 0)
381 /* Request PCI regions */
382 rc = pci_request_regions(pdev, DRV_NAME);
388 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
390 goto err_out_regions;
391 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
393 goto err_out_regions;
395 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
396 if (probe_ent == NULL) {
398 goto err_out_regions;
401 memset(probe_ent, 0, sizeof(*probe_ent));
402 probe_ent->dev = pci_dev_to_dev(pdev);
403 INIT_LIST_HEAD(&probe_ent->node);
405 mmio_base = pci_iomap(pdev, 5, 0);
406 if (mmio_base == NULL) {
408 goto err_out_free_ent;
410 base = (unsigned long) mmio_base;
412 /* Clear a magic bit in SCR1 according to Darwin, those help
413 * some funky seagate drives (though so far, those were already
414 * set by the firmware on the machines I had access to)
416 writel(readl(mmio_base + K2_SATA_SICR1_OFFSET) & ~0x00040000,
417 mmio_base + K2_SATA_SICR1_OFFSET);
419 /* Clear SATA error & interrupts we don't use */
420 writel(0xffffffff, mmio_base + K2_SATA_SCR_ERROR_OFFSET);
421 writel(0x0, mmio_base + K2_SATA_SIM_OFFSET);
423 probe_ent->sht = &k2_sata_sht;
424 probe_ent->host_flags = ATA_FLAG_SATA | ATA_FLAG_SATA_RESET |
425 ATA_FLAG_NO_LEGACY | ATA_FLAG_MMIO;
426 probe_ent->port_ops = &k2_sata_ops;
427 probe_ent->n_ports = 4;
428 probe_ent->irq = pdev->irq;
429 probe_ent->irq_flags = SA_SHIRQ;
430 probe_ent->mmio_base = mmio_base;
432 /* We don't care much about the PIO/UDMA masks, but the core won't like us
433 * if we don't fill these
435 probe_ent->pio_mask = 0x1f;
436 probe_ent->mwdma_mask = 0x7;
437 probe_ent->udma_mask = 0x7f;
439 /* different controllers have different number of ports - currently 4 or 8 */
440 /* All ports are on the same function. Multi-function device is no
441 * longer available. This should not be seen in any system. */
442 for (i = 0; i < ent->driver_data; i++)
443 k2_sata_setup_port(&probe_ent->port[i], base + i * K2_SATA_PORT_OFFSET);
445 pci_set_master(pdev);
447 /* FIXME: check ata_device_add return value */
448 ata_device_add(probe_ent);
456 pci_release_regions(pdev);
459 pci_disable_device(pdev);
463 /* 0x240 is device ID for Apple K2 device
464 * 0x241 is device ID for Serverworks Frodo4
465 * 0x242 is device ID for Serverworks Frodo8
466 * 0x24a is device ID for BCM5785 (aka HT1000) HT southbridge integrated SATA
469 static const struct pci_device_id k2_sata_pci_tbl[] = {
470 { 0x1166, 0x0240, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
471 { 0x1166, 0x0241, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
472 { 0x1166, 0x0242, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 },
473 { 0x1166, 0x024a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
478 static struct pci_driver k2_sata_pci_driver = {
480 .id_table = k2_sata_pci_tbl,
481 .probe = k2_sata_init_one,
482 .remove = ata_pci_remove_one,
486 static int __init k2_sata_init(void)
488 return pci_module_init(&k2_sata_pci_driver);
492 static void __exit k2_sata_exit(void)
494 pci_unregister_driver(&k2_sata_pci_driver);
498 MODULE_AUTHOR("Benjamin Herrenschmidt");
499 MODULE_DESCRIPTION("low-level driver for K2 SATA controller");
500 MODULE_LICENSE("GPL");
501 MODULE_DEVICE_TABLE(pci, k2_sata_pci_tbl);
502 MODULE_VERSION(DRV_VERSION);
504 module_init(k2_sata_init);
505 module_exit(k2_sata_exit);