2 * linux/arch/arm/kernel/entry-armv.S
4 * Copyright (C) 1996,1997,1998 Russell King.
5 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk)
6 * nommu support by Hyok S. Choi (hyok.choi@samsung.com)
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * Low-level vector interface routines
14 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction that causes
15 * it to save wrong values... Be aware!
18 #include <asm/memory.h>
20 #include <asm/vfpmacros.h>
21 #include <asm/arch/entry-macro.S>
22 #include <asm/thread_notify.h>
24 #include "entry-header.S"
27 * Interrupt handling. Preserves r7, r8, r9
30 1: get_irqnr_and_base r0, r6, r5, lr
33 @ routine called with r0 = irq number, r1 = struct pt_regs *
42 * this macro assumes that irqstat (r6) and base (r5) are
43 * preserved from get_irqnr_and_base above
45 test_for_ipi r0, r6, r5, lr
50 #ifdef CONFIG_LOCAL_TIMERS
51 test_for_ltirq r0, r6, r5, lr
61 * Invalid mode handlers
63 .macro inv_entry, reason
64 sub sp, sp, #S_FRAME_SIZE
70 inv_entry BAD_PREFETCH
82 inv_entry BAD_UNDEFINSTR
85 @ XXX fall through to common_invalid
89 @ common_invalid - generic code for failed exception (re-entrant version of handlers)
95 add r0, sp, #S_PC @ here for interlock avoidance
96 mov r7, #-1 @ "" "" "" ""
97 str r4, [sp] @ save preserved r0
98 stmia r0, {r5 - r7} @ lr_<exception>,
99 @ cpsr_<exception>, "old_r0"
109 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
110 #define SPFIX(code...) code
112 #define SPFIX(code...)
116 sub sp, sp, #S_FRAME_SIZE
118 SPFIX( bicne sp, sp, #4 )
122 add r5, sp, #S_SP @ here for interlock avoidance
123 mov r4, #-1 @ "" "" "" ""
124 add r0, sp, #S_FRAME_SIZE @ "" "" "" ""
125 SPFIX( addne r0, r0, #4 )
126 str r1, [sp] @ save the "real" r0 copied
127 @ from the exception stack
132 @ We are now ready to fill in the remaining blanks on the stack:
136 @ r2 - lr_<exception>, already fixed up for correct return/restart
137 @ r3 - spsr_<exception>
138 @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
148 @ get ready to re-enable interrupts if appropriate
152 biceq r9, r9, #PSR_I_BIT
155 @ Call the processor-specific abort handler:
157 @ r2 - aborted context pc
158 @ r3 - aborted context cpsr
160 @ The abort handler must return the aborted address in r0, and
161 @ the fault status register in r1. r9 must be preserved.
172 @ set desired IRQ state, then call main handler
179 @ IRQs off again before pulling preserved data off the stack
184 @ restore SPSR and restart the instruction
188 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
194 #ifdef CONFIG_PREEMPT
196 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
197 add r7, r8, #1 @ increment it
198 str r7, [tsk, #TI_PREEMPT]
202 #ifdef CONFIG_PREEMPT
203 ldr r0, [tsk, #TI_FLAGS] @ get flags
204 tst r0, #_TIF_NEED_RESCHED
207 ldr r0, [tsk, #TI_PREEMPT] @ read preempt value
208 str r8, [tsk, #TI_PREEMPT] @ restore preempt count
210 strne r0, [r0, -r0] @ bug()
212 ldr r0, [sp, #S_PSR] @ irqs are already disabled
214 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
218 #ifdef CONFIG_PREEMPT
220 teq r8, #0 @ was preempt count = 0
221 ldreq r6, .LCirq_stat
223 ldr r0, [r6, #4] @ local_irq_count
224 ldr r1, [r6, #8] @ local_bh_count
227 mov r7, #0 @ preempt_schedule_irq
228 str r7, [tsk, #TI_PREEMPT] @ expects preempt_count == 0
229 1: bl preempt_schedule_irq @ irq en/disable is done inside
230 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS
231 tst r0, #_TIF_NEED_RESCHED
232 beq preempt_return @ go again
241 @ call emulation code, which returns using r9 if it has emulated
242 @ the instruction, or the more conventional lr if we are to treat
243 @ this as a real undefined instruction
251 mov r0, sp @ struct pt_regs *regs
255 @ IRQs off again before pulling preserved data off the stack
260 @ restore SPSR and restart the instruction
262 ldr lr, [sp, #S_PSR] @ Get SVC cpsr
264 ldmia sp, {r0 - pc}^ @ Restore SVC registers
271 @ re-enable interrupts if appropriate
275 biceq r9, r9, #PSR_I_BIT
279 @ set args, then call main handler
281 @ r0 - address of faulting instruction
282 @ r1 - pointer to registers on stack
284 mov r0, r2 @ address (pc)
286 bl do_PrefetchAbort @ call abort handler
289 @ IRQs off again before pulling preserved data off the stack
294 @ restore SPSR and restart the instruction
298 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
309 #ifdef CONFIG_PREEMPT
317 * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE
320 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7)
321 #error "sizeof(struct pt_regs) must be a multiple of 8"
325 sub sp, sp, #S_FRAME_SIZE
329 add r0, sp, #S_PC @ here for interlock avoidance
330 mov r4, #-1 @ "" "" "" ""
332 str r1, [sp] @ save the "real" r0 copied
333 @ from the exception stack
335 #if __LINUX_ARM_ARCH__ < 6 && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
337 #warning "NPTL on non MMU needs fixing"
339 @ make sure our user space atomic helper is aborted
341 bichs r3, r3, #PSR_Z_BIT
346 @ We are now ready to fill in the remaining blanks on the stack:
348 @ r2 - lr_<exception>, already fixed up for correct return/restart
349 @ r3 - spsr_<exception>
350 @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
352 @ Also, separately save sp_usr and lr_usr
358 @ Enable the alignment trap while in kernel mode
363 @ Clear FP to mark the first stack frame
373 @ Call the processor-specific abort handler:
375 @ r2 - aborted context pc
376 @ r3 - aborted context cpsr
378 @ The abort handler must return the aborted address in r0, and
379 @ the fault status register in r1.
390 @ IRQs on, then call the main handler
394 adr lr, ret_from_exception
402 #ifdef CONFIG_PREEMPT
403 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
404 add r7, r8, #1 @ increment it
405 str r7, [tsk, #TI_PREEMPT]
409 #ifdef CONFIG_PREEMPT
410 ldr r0, [tsk, #TI_PREEMPT]
411 str r8, [tsk, #TI_PREEMPT]
425 tst r3, #PSR_T_BIT @ Thumb mode?
426 bne fpundefinstr @ ignore FP
430 @ fall through to the emulation code, which returns using r9 if
431 @ it has emulated the instruction, or the more conventional lr
432 @ if we are to treat this as a real undefined instruction
437 adr r9, ret_from_exception
440 @ fallthrough to call_fpe
444 * The out of line fixup for the ldrt above.
446 .section .fixup, "ax"
449 .section __ex_table,"a"
454 * Check whether the instruction is a co-processor instruction.
455 * If yes, we need to call the relevant co-processor handler.
457 * Note that we don't do a full check here for the co-processor
458 * instructions; all instructions with bit 27 set are well
459 * defined. The only instructions that should fault are the
460 * co-processor instructions. However, we have to watch out
461 * for the ARM6/ARM7 SWI bug.
463 * Emulators may wish to make use of the following registers:
464 * r0 = instruction opcode.
466 * r10 = this threads thread_info structure.
469 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
470 #if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
471 and r8, r0, #0x0f000000 @ mask out op-code bits
472 teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)?
475 get_thread_info r10 @ get current thread
476 and r8, r0, #0x00000f00 @ mask out CP number
478 add r6, r10, #TI_USED_CP
479 strb r7, [r6, r8, lsr #8] @ set appropriate used_cp[]
481 @ Test if we need to give access to iWMMXt coprocessors
482 ldr r5, [r10, #TI_FLAGS]
483 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only
484 movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1)
485 bcs iwmmxt_task_enable
487 add pc, pc, r8, lsr #6
491 b do_fpe @ CP#1 (FPE)
492 b do_fpe @ CP#2 (FPE)
495 b crunch_task_enable @ CP#4 (MaverickCrunch)
496 b crunch_task_enable @ CP#5 (MaverickCrunch)
497 b crunch_task_enable @ CP#6 (MaverickCrunch)
507 b do_vfp @ CP#10 (VFP)
508 b do_vfp @ CP#11 (VFP)
510 mov pc, lr @ CP#10 (VFP)
511 mov pc, lr @ CP#11 (VFP)
515 mov pc, lr @ CP#14 (Debug)
516 mov pc, lr @ CP#15 (Control)
521 add r10, r10, #TI_FPSTATE @ r10 = workspace
522 ldr pc, [r4] @ Call FP module USR entry point
525 * The FP module is called with these registers set:
528 * r9 = normal "successful" return address
530 * lr = unrecognised FP instruction return address
540 adr lr, ret_from_exception
547 enable_irq @ Enable interrupts
548 mov r0, r2 @ address (pc)
550 bl do_PrefetchAbort @ call abort handler
553 * This is the return code to user mode for abort handlers
555 ENTRY(ret_from_exception)
561 * Register switch for ARMv3 and ARMv4 processors
562 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
563 * previous and next are guaranteed not to be the same.
566 add ip, r1, #TI_CPU_SAVE
567 ldr r3, [r2, #TI_TP_VALUE]
568 stmia ip!, {r4 - sl, fp, sp, lr} @ Store most regs on stack
570 ldr r6, [r2, #TI_CPU_DOMAIN]
572 #if __LINUX_ARM_ARCH__ >= 6
573 #ifdef CONFIG_CPU_32v6K
576 strex r5, r4, [ip] @ Clear exclusive monitor
579 #if defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_IWMMXT)
583 #if defined(CONFIG_HAS_TLS_REG)
584 mcr p15, 0, r3, c13, c0, 3 @ set TLS register
585 #elif !defined(CONFIG_TLS_REG_EMUL)
587 str r3, [r4, #-15] @ TLS val at 0xffff0ff0
590 mcr p15, 0, r6, c3, c0, 0 @ Set domain register
592 #if defined(CONFIG_IWMMXT)
593 bl iwmmxt_task_switch
594 #elif defined(CONFIG_CPU_XSCALE)
595 add r4, r2, #TI_CPU_DOMAIN + 40 @ cpu_context_save->extra
600 add r4, r2, #TI_CPU_SAVE
601 ldr r0, =thread_notify_head
602 mov r1, #THREAD_NOTIFY_SWITCH
603 bl atomic_notifier_call_chain
605 ldmia r4, {r4 - sl, fp, sp, pc} @ Load all regs saved previously
612 * These are segment of kernel provided user code reachable from user space
613 * at a fixed address in kernel memory. This is used to provide user space
614 * with some operations which require kernel help because of unimplemented
615 * native feature and/or instructions in many ARM CPUs. The idea is for
616 * this code to be executed directly in user mode for best efficiency but
617 * which is too intimate with the kernel counter part to be left to user
618 * libraries. In fact this code might even differ from one CPU to another
619 * depending on the available instruction set and restrictions like on
620 * SMP systems. In other words, the kernel reserves the right to change
621 * this code as needed without warning. Only the entry points and their
622 * results are guaranteed to be stable.
624 * Each segment is 32-byte aligned and will be moved to the top of the high
625 * vector page. New segments (if ever needed) must be added in front of
626 * existing ones. This mechanism should be used only for things that are
627 * really small and justified, and not be abused freely.
629 * User space is expected to implement those things inline when optimizing
630 * for a processor that has the necessary native support, but only if such
631 * resulting binaries are already to be incompatible with earlier ARM
632 * processors due to the use of unsupported instructions other than what
633 * is provided here. In other words don't make binaries unable to run on
634 * earlier processors just for the sake of not using these kernel helpers
635 * if your compiled code is not going to use the new instructions for other
640 .globl __kuser_helper_start
641 __kuser_helper_start:
644 * Reference prototype:
646 * void __kernel_memory_barrier(void)
650 * lr = return address
658 * the Z flag might be lost
660 * Definition and user space usage example:
662 * typedef void (__kernel_dmb_t)(void);
663 * #define __kernel_dmb (*(__kernel_dmb_t *)0xffff0fa0)
665 * Apply any needed memory barrier to preserve consistency with data modified
666 * manually and __kuser_cmpxchg usage.
668 * This could be used as follows:
670 * #define __kernel_dmb() \
671 * asm volatile ( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #95" \
672 * : : : "r0", "lr","cc" )
675 __kuser_memory_barrier: @ 0xffff0fa0
677 #if __LINUX_ARM_ARCH__ >= 6 && defined(CONFIG_SMP)
678 mcr p15, 0, r0, c7, c10, 5 @ dmb
685 * Reference prototype:
687 * int __kernel_cmpxchg(int oldval, int newval, int *ptr)
694 * lr = return address
698 * r0 = returned value (zero or non-zero)
699 * C flag = set if r0 == 0, clear if r0 != 0
705 * Definition and user space usage example:
707 * typedef int (__kernel_cmpxchg_t)(int oldval, int newval, int *ptr);
708 * #define __kernel_cmpxchg (*(__kernel_cmpxchg_t *)0xffff0fc0)
710 * Atomically store newval in *ptr if *ptr is equal to oldval for user space.
711 * Return zero if *ptr was changed or non-zero if no exchange happened.
712 * The C flag is also set if *ptr was changed to allow for assembly
713 * optimization in the calling code.
717 * - This routine already includes memory barriers as needed.
719 * - A failure might be transient, i.e. it is possible, although unlikely,
720 * that "failure" be returned even if *ptr == oldval.
722 * For example, a user space atomic_add implementation could look like this:
724 * #define atomic_add(ptr, val) \
725 * ({ register unsigned int *__ptr asm("r2") = (ptr); \
726 * register unsigned int __result asm("r1"); \
728 * "1: @ atomic_add\n\t" \
729 * "ldr r0, [r2]\n\t" \
730 * "mov r3, #0xffff0fff\n\t" \
731 * "add lr, pc, #4\n\t" \
732 * "add r1, r0, %2\n\t" \
733 * "add pc, r3, #(0xffff0fc0 - 0xffff0fff)\n\t" \
735 * : "=&r" (__result) \
736 * : "r" (__ptr), "rIL" (val) \
737 * : "r0","r3","ip","lr","cc","memory" ); \
741 __kuser_cmpxchg: @ 0xffff0fc0
743 #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
746 * Poor you. No fast solution possible...
747 * The kernel itself must perform the operation.
748 * A special ghost syscall is used for that (see traps.c).
751 mov r7, #0xff00 @ 0xfff0 into r7 for EABI
756 #elif __LINUX_ARM_ARCH__ < 6
759 * Theory of operation:
761 * We set the Z flag before loading oldval. If ever an exception
762 * occurs we can not be sure the loaded value will still be the same
763 * when the exception returns, therefore the user exception handler
764 * will clear the Z flag whenever the interrupted user code was
765 * actually from the kernel address space (see the usr_entry macro).
767 * The post-increment on the str is used to prevent a race with an
768 * exception happening just after the str instruction which would
769 * clear the Z flag although the exchange was done.
772 teq ip, ip @ set Z flag
773 ldr ip, [r2] @ load current val
774 add r3, r2, #1 @ prepare store ptr
775 teqeq ip, r0 @ compare with oldval if still allowed
776 streq r1, [r3, #-1]! @ store newval if still allowed
777 subs r0, r2, r3 @ if r2 == r3 the str occured
779 #warning "NPTL on non MMU needs fixing"
788 mcr p15, 0, r0, c7, c10, 5 @ dmb
795 mcr p15, 0, r0, c7, c10, 5 @ dmb
804 * Reference prototype:
806 * int __kernel_get_tls(void)
810 * lr = return address
818 * the Z flag might be lost
820 * Definition and user space usage example:
822 * typedef int (__kernel_get_tls_t)(void);
823 * #define __kernel_get_tls (*(__kernel_get_tls_t *)0xffff0fe0)
825 * Get the TLS value as previously set via the __ARM_NR_set_tls syscall.
827 * This could be used as follows:
829 * #define __kernel_get_tls() \
830 * ({ register unsigned int __val asm("r0"); \
831 * asm( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #31" \
832 * : "=r" (__val) : : "lr","cc" ); \
836 __kuser_get_tls: @ 0xffff0fe0
838 #if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL)
840 ldr r0, [pc, #(16 - 8)] @ TLS stored at 0xffff0ff0
845 mrc p15, 0, r0, c13, c0, 3 @ read TLS register
851 .word 0 @ pad up to __kuser_helper_version
855 * Reference declaration:
857 * extern unsigned int __kernel_helper_version;
859 * Definition and user space usage example:
861 * #define __kernel_helper_version (*(unsigned int *)0xffff0ffc)
863 * User space may read this to determine the curent number of helpers
867 __kuser_helper_version: @ 0xffff0ffc
868 .word ((__kuser_helper_end - __kuser_helper_start) >> 5)
870 .globl __kuser_helper_end
877 * This code is copied to 0xffff0200 so we can use branches in the
878 * vectors, rather than ldr's. Note that this code must not
879 * exceed 0x300 bytes.
881 * Common stub entry macro:
882 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
884 * SP points to a minimal amount of processor-private memory, the address
885 * of which is copied into r0 for the mode specific abort handler.
887 .macro vector_stub, name, mode, correction=0
892 sub lr, lr, #\correction
896 @ Save r0, lr_<exception> (parent PC) and spsr_<exception>
899 stmia sp, {r0, lr} @ save r0, lr
901 str lr, [sp, #8] @ save spsr
904 @ Prepare for SVC32 mode. IRQs remain disabled.
907 eor r0, r0, #(\mode ^ SVC_MODE)
911 @ the branch table must immediately follow this code
915 ldr lr, [pc, lr, lsl #2]
916 movs pc, lr @ branch to handler in SVC mode
922 * Interrupt dispatcher
924 vector_stub irq, IRQ_MODE, 4
926 .long __irq_usr @ 0 (USR_26 / USR_32)
927 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32)
928 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32)
929 .long __irq_svc @ 3 (SVC_26 / SVC_32)
930 .long __irq_invalid @ 4
931 .long __irq_invalid @ 5
932 .long __irq_invalid @ 6
933 .long __irq_invalid @ 7
934 .long __irq_invalid @ 8
935 .long __irq_invalid @ 9
936 .long __irq_invalid @ a
937 .long __irq_invalid @ b
938 .long __irq_invalid @ c
939 .long __irq_invalid @ d
940 .long __irq_invalid @ e
941 .long __irq_invalid @ f
944 * Data abort dispatcher
945 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
947 vector_stub dabt, ABT_MODE, 8
949 .long __dabt_usr @ 0 (USR_26 / USR_32)
950 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32)
951 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32)
952 .long __dabt_svc @ 3 (SVC_26 / SVC_32)
953 .long __dabt_invalid @ 4
954 .long __dabt_invalid @ 5
955 .long __dabt_invalid @ 6
956 .long __dabt_invalid @ 7
957 .long __dabt_invalid @ 8
958 .long __dabt_invalid @ 9
959 .long __dabt_invalid @ a
960 .long __dabt_invalid @ b
961 .long __dabt_invalid @ c
962 .long __dabt_invalid @ d
963 .long __dabt_invalid @ e
964 .long __dabt_invalid @ f
967 * Prefetch abort dispatcher
968 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
970 vector_stub pabt, ABT_MODE, 4
972 .long __pabt_usr @ 0 (USR_26 / USR_32)
973 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32)
974 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32)
975 .long __pabt_svc @ 3 (SVC_26 / SVC_32)
976 .long __pabt_invalid @ 4
977 .long __pabt_invalid @ 5
978 .long __pabt_invalid @ 6
979 .long __pabt_invalid @ 7
980 .long __pabt_invalid @ 8
981 .long __pabt_invalid @ 9
982 .long __pabt_invalid @ a
983 .long __pabt_invalid @ b
984 .long __pabt_invalid @ c
985 .long __pabt_invalid @ d
986 .long __pabt_invalid @ e
987 .long __pabt_invalid @ f
990 * Undef instr entry dispatcher
991 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
993 vector_stub und, UND_MODE
995 .long __und_usr @ 0 (USR_26 / USR_32)
996 .long __und_invalid @ 1 (FIQ_26 / FIQ_32)
997 .long __und_invalid @ 2 (IRQ_26 / IRQ_32)
998 .long __und_svc @ 3 (SVC_26 / SVC_32)
999 .long __und_invalid @ 4
1000 .long __und_invalid @ 5
1001 .long __und_invalid @ 6
1002 .long __und_invalid @ 7
1003 .long __und_invalid @ 8
1004 .long __und_invalid @ 9
1005 .long __und_invalid @ a
1006 .long __und_invalid @ b
1007 .long __und_invalid @ c
1008 .long __und_invalid @ d
1009 .long __und_invalid @ e
1010 .long __und_invalid @ f
1014 /*=============================================================================
1016 *-----------------------------------------------------------------------------
1017 * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC
1018 * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg.
1019 * Basically to switch modes, we *HAVE* to clobber one register... brain
1020 * damage alert! I don't think that we can execute any code in here in any
1021 * other mode than FIQ... Ok you can switch to another mode, but you can't
1022 * get out of that mode without clobbering one register.
1028 /*=============================================================================
1029 * Address exception handler
1030 *-----------------------------------------------------------------------------
1031 * These aren't too critical.
1032 * (they're not supposed to happen, and won't happen in 32-bit data mode).
1039 * We group all the following data together to optimise
1040 * for CPUs with separate I & D caches.
1050 .equ stubs_offset, __vectors_start + 0x200 - __stubs_start
1052 .globl __vectors_start
1055 b vector_und + stubs_offset
1056 ldr pc, .LCvswi + stubs_offset
1057 b vector_pabt + stubs_offset
1058 b vector_dabt + stubs_offset
1059 b vector_addrexcptn + stubs_offset
1060 b vector_irq + stubs_offset
1061 b vector_fiq + stubs_offset
1063 .globl __vectors_end
1069 .globl cr_no_alignment
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