2 * drivers/video/aty/radeon_base.c
4 * framebuffer driver for ATI Radeon chipset video boards
6 * Copyright 2003 Ben. Herrenschmidt <benh@kernel.crashing.org>
7 * Copyright 2000 Ani Joshi <ajoshi@kernel.crashing.org>
9 * i2c bits from Luca Tettamanti <kronos@kronoz.cjb.net>
11 * Special thanks to ATI DevRel team for their hardware donations.
13 * ...Insert GPL boilerplate here...
15 * Significant portions of this driver apdated from XFree86 Radeon
16 * driver which has the following copyright notice:
18 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
19 * VA Linux Systems Inc., Fremont, California.
21 * All Rights Reserved.
23 * Permission is hereby granted, free of charge, to any person obtaining
24 * a copy of this software and associated documentation files (the
25 * "Software"), to deal in the Software without restriction, including
26 * without limitation on the rights to use, copy, modify, merge,
27 * publish, distribute, sublicense, and/or sell copies of the Software,
28 * and to permit persons to whom the Software is furnished to do so,
29 * subject to the following conditions:
31 * The above copyright notice and this permission notice (including the
32 * next paragraph) shall be included in all copies or substantial
33 * portions of the Software.
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
37 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
39 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
41 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
42 * DEALINGS IN THE SOFTWARE.
44 * XFree86 driver authors:
46 * Kevin E. Martin <martin@xfree86.org>
47 * Rickard E. Faith <faith@valinux.com>
48 * Alan Hourihane <alanh@fairlite.demon.co.uk>
53 #define RADEON_VERSION "0.2.0"
55 #include <linux/module.h>
56 #include <linux/moduleparam.h>
57 #include <linux/kernel.h>
58 #include <linux/errno.h>
59 #include <linux/string.h>
61 #include <linux/tty.h>
62 #include <linux/slab.h>
63 #include <linux/delay.h>
64 #include <linux/time.h>
66 #include <linux/ioport.h>
67 #include <linux/init.h>
68 #include <linux/pci.h>
69 #include <linux/vmalloc.h>
70 #include <linux/device.h>
73 #include <asm/uaccess.h>
77 #include <asm/pci-bridge.h>
78 #include "../macmodes.h"
80 #ifdef CONFIG_BOOTX_TEXT
81 #include <asm/btext.h>
84 #endif /* CONFIG_PPC_OF */
90 #include <video/radeon.h>
91 #include <linux/radeonfb.h>
93 #include "../edid.h" // MOVE THAT TO include/video
97 #define MAX_MAPPED_VRAM (2048*2048*4)
98 #define MIN_MAPPED_VRAM (1024*768*1)
100 #define CHIP_DEF(id, family, flags) \
101 { PCI_VENDOR_ID_ATI, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (flags) | (CHIP_FAMILY_##family) }
103 static struct pci_device_id radeonfb_pci_table[] = {
105 CHIP_DEF(PCI_CHIP_RADEON_LY, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
106 CHIP_DEF(PCI_CHIP_RADEON_LZ, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
108 CHIP_DEF(PCI_CHIP_RV100_QY, RV100, CHIP_HAS_CRTC2),
109 CHIP_DEF(PCI_CHIP_RV100_QZ, RV100, CHIP_HAS_CRTC2),
110 CHIP_DEF(PCI_CHIP_RN50, RV100, CHIP_HAS_CRTC2),
111 /* Radeon IGP320M (U1) */
112 CHIP_DEF(PCI_CHIP_RS100_4336, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
113 /* Radeon IGP320 (A3) */
114 CHIP_DEF(PCI_CHIP_RS100_4136, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
115 /* IGP330M/340M/350M (U2) */
116 CHIP_DEF(PCI_CHIP_RS200_4337, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
117 /* IGP330/340/350 (A4) */
118 CHIP_DEF(PCI_CHIP_RS200_4137, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
119 /* Mobility 7000 IGP */
120 CHIP_DEF(PCI_CHIP_RS250_4437, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
122 CHIP_DEF(PCI_CHIP_RS250_4237, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
124 CHIP_DEF(PCI_CHIP_R200_BB, R200, CHIP_HAS_CRTC2),
125 CHIP_DEF(PCI_CHIP_R200_BC, R200, CHIP_HAS_CRTC2),
127 CHIP_DEF(PCI_CHIP_R200_QH, R200, CHIP_HAS_CRTC2),
129 CHIP_DEF(PCI_CHIP_R200_QL, R200, CHIP_HAS_CRTC2),
131 CHIP_DEF(PCI_CHIP_R200_QM, R200, CHIP_HAS_CRTC2),
133 CHIP_DEF(PCI_CHIP_RADEON_LW, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
134 CHIP_DEF(PCI_CHIP_RADEON_LX, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
136 CHIP_DEF(PCI_CHIP_RV200_QW, RV200, CHIP_HAS_CRTC2),
137 CHIP_DEF(PCI_CHIP_RV200_QX, RV200, CHIP_HAS_CRTC2),
139 CHIP_DEF(PCI_CHIP_RV250_Ld, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
140 CHIP_DEF(PCI_CHIP_RV250_Le, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
141 CHIP_DEF(PCI_CHIP_RV250_Lf, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
142 CHIP_DEF(PCI_CHIP_RV250_Lg, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
144 CHIP_DEF(PCI_CHIP_RV250_If, RV250, CHIP_HAS_CRTC2),
145 CHIP_DEF(PCI_CHIP_RV250_Ig, RV250, CHIP_HAS_CRTC2),
146 /* Mobility 9100 IGP (U3) */
147 CHIP_DEF(PCI_CHIP_RS300_5835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
148 CHIP_DEF(PCI_CHIP_RS350_7835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
150 CHIP_DEF(PCI_CHIP_RS300_5834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
151 CHIP_DEF(PCI_CHIP_RS350_7834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
152 /* Mobility 9200 (M9+) */
153 CHIP_DEF(PCI_CHIP_RV280_5C61, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
154 CHIP_DEF(PCI_CHIP_RV280_5C63, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
156 CHIP_DEF(PCI_CHIP_RV280_5960, RV280, CHIP_HAS_CRTC2),
157 CHIP_DEF(PCI_CHIP_RV280_5961, RV280, CHIP_HAS_CRTC2),
158 CHIP_DEF(PCI_CHIP_RV280_5962, RV280, CHIP_HAS_CRTC2),
159 CHIP_DEF(PCI_CHIP_RV280_5964, RV280, CHIP_HAS_CRTC2),
161 CHIP_DEF(PCI_CHIP_R300_AD, R300, CHIP_HAS_CRTC2),
162 CHIP_DEF(PCI_CHIP_R300_AE, R300, CHIP_HAS_CRTC2),
163 /* 9600TX / FireGL Z1 */
164 CHIP_DEF(PCI_CHIP_R300_AF, R300, CHIP_HAS_CRTC2),
165 CHIP_DEF(PCI_CHIP_R300_AG, R300, CHIP_HAS_CRTC2),
166 /* 9700/9500/Pro/FireGL X1 */
167 CHIP_DEF(PCI_CHIP_R300_ND, R300, CHIP_HAS_CRTC2),
168 CHIP_DEF(PCI_CHIP_R300_NE, R300, CHIP_HAS_CRTC2),
169 CHIP_DEF(PCI_CHIP_R300_NF, R300, CHIP_HAS_CRTC2),
170 CHIP_DEF(PCI_CHIP_R300_NG, R300, CHIP_HAS_CRTC2),
171 /* Mobility M10/M11 */
172 CHIP_DEF(PCI_CHIP_RV350_NP, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
173 CHIP_DEF(PCI_CHIP_RV350_NQ, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
174 CHIP_DEF(PCI_CHIP_RV350_NR, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
175 CHIP_DEF(PCI_CHIP_RV350_NS, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
176 CHIP_DEF(PCI_CHIP_RV350_NT, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
177 CHIP_DEF(PCI_CHIP_RV350_NV, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
179 CHIP_DEF(PCI_CHIP_RV350_AP, RV350, CHIP_HAS_CRTC2),
180 CHIP_DEF(PCI_CHIP_RV350_AQ, RV350, CHIP_HAS_CRTC2),
181 CHIP_DEF(PCI_CHIP_RV360_AR, RV350, CHIP_HAS_CRTC2),
182 CHIP_DEF(PCI_CHIP_RV350_AS, RV350, CHIP_HAS_CRTC2),
183 CHIP_DEF(PCI_CHIP_RV350_AT, RV350, CHIP_HAS_CRTC2),
184 CHIP_DEF(PCI_CHIP_RV350_AV, RV350, CHIP_HAS_CRTC2),
185 /* 9800/Pro/FileGL X2 */
186 CHIP_DEF(PCI_CHIP_R350_AH, R350, CHIP_HAS_CRTC2),
187 CHIP_DEF(PCI_CHIP_R350_AI, R350, CHIP_HAS_CRTC2),
188 CHIP_DEF(PCI_CHIP_R350_AJ, R350, CHIP_HAS_CRTC2),
189 CHIP_DEF(PCI_CHIP_R350_AK, R350, CHIP_HAS_CRTC2),
190 CHIP_DEF(PCI_CHIP_R350_NH, R350, CHIP_HAS_CRTC2),
191 CHIP_DEF(PCI_CHIP_R350_NI, R350, CHIP_HAS_CRTC2),
192 CHIP_DEF(PCI_CHIP_R360_NJ, R350, CHIP_HAS_CRTC2),
193 CHIP_DEF(PCI_CHIP_R350_NK, R350, CHIP_HAS_CRTC2),
195 CHIP_DEF(PCI_CHIP_RV380_3E50, RV380, CHIP_HAS_CRTC2),
196 CHIP_DEF(PCI_CHIP_RV380_3E54, RV380, CHIP_HAS_CRTC2),
197 CHIP_DEF(PCI_CHIP_RV380_3150, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
198 CHIP_DEF(PCI_CHIP_RV380_3154, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
199 CHIP_DEF(PCI_CHIP_RV370_5B60, RV380, CHIP_HAS_CRTC2),
200 CHIP_DEF(PCI_CHIP_RV370_5B62, RV380, CHIP_HAS_CRTC2),
201 CHIP_DEF(PCI_CHIP_RV370_5B64, RV380, CHIP_HAS_CRTC2),
202 CHIP_DEF(PCI_CHIP_RV370_5B65, RV380, CHIP_HAS_CRTC2),
203 CHIP_DEF(PCI_CHIP_RV370_5460, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
204 CHIP_DEF(PCI_CHIP_RV370_5464, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
205 CHIP_DEF(PCI_CHIP_R420_JH, R420, CHIP_HAS_CRTC2),
206 CHIP_DEF(PCI_CHIP_R420_JI, R420, CHIP_HAS_CRTC2),
207 CHIP_DEF(PCI_CHIP_R420_JJ, R420, CHIP_HAS_CRTC2),
208 CHIP_DEF(PCI_CHIP_R420_JK, R420, CHIP_HAS_CRTC2),
209 CHIP_DEF(PCI_CHIP_R420_JL, R420, CHIP_HAS_CRTC2),
210 CHIP_DEF(PCI_CHIP_R420_JM, R420, CHIP_HAS_CRTC2),
211 CHIP_DEF(PCI_CHIP_R420_JN, R420, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
212 CHIP_DEF(PCI_CHIP_R420_JP, R420, CHIP_HAS_CRTC2),
213 CHIP_DEF(PCI_CHIP_R423_UH, R420, CHIP_HAS_CRTC2),
214 CHIP_DEF(PCI_CHIP_R423_UI, R420, CHIP_HAS_CRTC2),
215 CHIP_DEF(PCI_CHIP_R423_UJ, R420, CHIP_HAS_CRTC2),
216 CHIP_DEF(PCI_CHIP_R423_UK, R420, CHIP_HAS_CRTC2),
217 CHIP_DEF(PCI_CHIP_R423_UQ, R420, CHIP_HAS_CRTC2),
218 CHIP_DEF(PCI_CHIP_R423_UR, R420, CHIP_HAS_CRTC2),
219 CHIP_DEF(PCI_CHIP_R423_UT, R420, CHIP_HAS_CRTC2),
220 CHIP_DEF(PCI_CHIP_R423_5D57, R420, CHIP_HAS_CRTC2),
221 /* Original Radeon/7200 */
222 CHIP_DEF(PCI_CHIP_RADEON_QD, RADEON, 0),
223 CHIP_DEF(PCI_CHIP_RADEON_QE, RADEON, 0),
224 CHIP_DEF(PCI_CHIP_RADEON_QF, RADEON, 0),
225 CHIP_DEF(PCI_CHIP_RADEON_QG, RADEON, 0),
228 MODULE_DEVICE_TABLE(pci, radeonfb_pci_table);
237 /* these common regs are cleared before mode setting so they do not
238 * interfere with anything
240 static reg_val common_regs[] = {
242 { OVR_WID_LEFT_RIGHT, 0 },
243 { OVR_WID_TOP_BOTTOM, 0 },
244 { OV0_SCALE_CNTL, 0 },
249 { CAP0_TRIG_CNTL, 0 },
250 { CAP1_TRIG_CNTL, 0 },
257 static char *mode_option;
258 static char *monitor_layout;
259 static int noaccel = 0;
260 static int default_dynclk = -2;
261 static int nomodeset = 0;
262 static int ignore_edid = 0;
263 static int mirror = 0;
264 static int panel_yres = 0;
265 static int force_dfp = 0;
266 static int force_measure_pll = 0;
268 static int nomtrr = 0;
275 static void radeon_unmap_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
277 if (!rinfo->bios_seg)
279 pci_unmap_rom(dev, rinfo->bios_seg);
282 static int __devinit radeon_map_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
289 /* If this is a primary card, there is a shadow copy of the
290 * ROM somewhere in the first meg. We will just ignore the copy
291 * and use the ROM directly.
294 /* Fix from ATI for problem with Radeon hardware not leaving ROM enabled */
296 temp = INREG(MPP_TB_CONFIG);
299 OUTREG(MPP_TB_CONFIG, temp);
300 temp = INREG(MPP_TB_CONFIG);
302 rom = pci_map_rom(dev, &rom_size);
304 printk(KERN_ERR "radeonfb (%s): ROM failed to map\n",
305 pci_name(rinfo->pdev));
309 rinfo->bios_seg = rom;
311 /* Very simple test to make sure it appeared */
312 if (BIOS_IN16(0) != 0xaa55) {
313 printk(KERN_DEBUG "radeonfb (%s): Invalid ROM signature %x "
314 "should be 0xaa55\n",
315 pci_name(rinfo->pdev), BIOS_IN16(0));
318 /* Look for the PCI data to check the ROM type */
319 dptr = BIOS_IN16(0x18);
321 /* Check the PCI data signature. If it's wrong, we still assume a normal x86 ROM
322 * for now, until I've verified this works everywhere. The goal here is more
323 * to phase out Open Firmware images.
325 * Currently, we only look at the first PCI data, we could iteratre and deal with
326 * them all, and we should use fb_bios_start relative to start of image and not
327 * relative start of ROM, but so far, I never found a dual-image ATI card
330 * u32 signature; + 0x00
333 * u16 reserved_1; + 0x08
335 * u8 drevision; + 0x0c
336 * u8 class_hi; + 0x0d
337 * u16 class_lo; + 0x0e
339 * u16 irevision; + 0x12
341 * u8 indicator; + 0x15
342 * u16 reserved_2; + 0x16
345 if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) {
346 printk(KERN_WARNING "radeonfb (%s): PCI DATA signature in ROM"
347 "incorrect: %08x\n", pci_name(rinfo->pdev), BIOS_IN32(dptr));
350 rom_type = BIOS_IN8(dptr + 0x14);
353 printk(KERN_INFO "radeonfb: Found Intel x86 BIOS ROM Image\n");
356 printk(KERN_INFO "radeonfb: Found Open Firmware ROM Image\n");
359 printk(KERN_INFO "radeonfb: Found HP PA-RISC ROM Image\n");
362 printk(KERN_INFO "radeonfb: Found unknown type %d ROM Image\n", rom_type);
366 /* Locate the flat panel infos, do some sanity checking !!! */
367 rinfo->fp_bios_start = BIOS_IN16(0x48);
371 rinfo->bios_seg = NULL;
372 radeon_unmap_ROM(rinfo, dev);
377 static int __devinit radeon_find_mem_vbios(struct radeonfb_info *rinfo)
379 /* I simplified this code as we used to miss the signatures in
380 * a lot of case. It's now closer to XFree, we just don't check
381 * for signatures at all... Something better will have to be done
382 * if we end up having conflicts
385 void __iomem *rom_base = NULL;
387 for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
388 rom_base = ioremap(segstart, 0x10000);
389 if (rom_base == NULL)
391 if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa)
396 if (rom_base == NULL)
399 /* Locate the flat panel infos, do some sanity checking !!! */
400 rinfo->bios_seg = rom_base;
401 rinfo->fp_bios_start = BIOS_IN16(0x48);
409 * Read XTAL (ref clock), SCLK and MCLK from Open Firmware device
410 * tree. Hopefully, ATI OF driver is kind enough to fill these
412 static int __devinit radeon_read_xtal_OF (struct radeonfb_info *rinfo)
414 struct device_node *dp = rinfo->of_node;
419 val = (u32 *) get_property(dp, "ATY,RefCLK", NULL);
421 printk(KERN_WARNING "radeonfb: No ATY,RefCLK property !\n");
425 rinfo->pll.ref_clk = (*val) / 10;
427 val = (u32 *) get_property(dp, "ATY,SCLK", NULL);
429 rinfo->pll.sclk = (*val) / 10;
431 val = (u32 *) get_property(dp, "ATY,MCLK", NULL);
433 rinfo->pll.mclk = (*val) / 10;
437 #endif /* CONFIG_PPC_OF */
440 * Read PLL infos from chip registers
442 static int __devinit radeon_probe_pll_params(struct radeonfb_info *rinfo)
444 unsigned char ppll_div_sel;
446 unsigned sclk, mclk, tmp, ref_div;
447 int hTotal, vTotal, num, denom, m, n;
448 unsigned long long hz, vclk;
450 struct timeval start_tv, stop_tv;
451 long total_secs, total_usecs;
454 /* Ugh, we cut interrupts, bad bad bad, but we want some precision
458 /* Flush PCI buffers ? */
459 tmp = INREG16(DEVICE_ID);
463 for(i=0; i<1000000; i++)
464 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
467 do_gettimeofday(&start_tv);
469 for(i=0; i<1000000; i++)
470 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) != 0)
473 for(i=0; i<1000000; i++)
474 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
477 do_gettimeofday(&stop_tv);
481 total_secs = stop_tv.tv_sec - start_tv.tv_sec;
484 total_usecs = stop_tv.tv_usec - start_tv.tv_usec;
485 total_usecs += total_secs * 1000000;
487 total_usecs = -total_usecs;
488 hz = 1000000/total_usecs;
490 hTotal = ((INREG(CRTC_H_TOTAL_DISP) & 0x1ff) + 1) * 8;
491 vTotal = ((INREG(CRTC_V_TOTAL_DISP) & 0x3ff) + 1);
492 vclk = (long long)hTotal * (long long)vTotal * hz;
494 switch((INPLL(PPLL_REF_DIV) & 0x30000) >> 16) {
501 n = ((INPLL(M_SPLL_REF_FB_DIV) >> 16) & 0xff);
502 m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);
507 n = ((INPLL(M_SPLL_REF_FB_DIV) >> 8) & 0xff);
508 m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);
514 ppll_div_sel = INREG8(CLOCK_CNTL_INDEX + 1) & 0x3;
515 radeon_pll_errata_after_index(rinfo);
517 n = (INPLL(PPLL_DIV_0 + ppll_div_sel) & 0x7ff);
518 m = (INPLL(PPLL_REF_DIV) & 0x3ff);
523 switch ((INPLL(PPLL_DIV_0 + ppll_div_sel) >> 16) & 0x7) {
545 do_div(vclk, 1000 * num);
548 if ((xtal > 26900) && (xtal < 27100))
550 else if ((xtal > 14200) && (xtal < 14400))
552 else if ((xtal > 29400) && (xtal < 29600))
555 printk(KERN_WARNING "xtal calculation failed: %ld\n", xtal);
559 tmp = INPLL(M_SPLL_REF_FB_DIV);
560 ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;
562 Ns = (tmp & 0xff0000) >> 16;
563 Nm = (tmp & 0xff00) >> 8;
565 sclk = round_div((2 * Ns * xtal), (2 * M));
566 mclk = round_div((2 * Nm * xtal), (2 * M));
568 /* we're done, hopefully these are sane values */
569 rinfo->pll.ref_clk = xtal;
570 rinfo->pll.ref_div = ref_div;
571 rinfo->pll.sclk = sclk;
572 rinfo->pll.mclk = mclk;
578 * Retrieve PLL infos by different means (BIOS, Open Firmware, register probing...)
580 static void __devinit radeon_get_pllinfo(struct radeonfb_info *rinfo)
583 * In the case nothing works, these are defaults; they are mostly
584 * incomplete, however. It does provide ppll_max and _min values
585 * even for most other methods, however.
587 switch (rinfo->chipset) {
588 case PCI_DEVICE_ID_ATI_RADEON_QW:
589 case PCI_DEVICE_ID_ATI_RADEON_QX:
590 rinfo->pll.ppll_max = 35000;
591 rinfo->pll.ppll_min = 12000;
592 rinfo->pll.mclk = 23000;
593 rinfo->pll.sclk = 23000;
594 rinfo->pll.ref_clk = 2700;
596 case PCI_DEVICE_ID_ATI_RADEON_QL:
597 case PCI_DEVICE_ID_ATI_RADEON_QN:
598 case PCI_DEVICE_ID_ATI_RADEON_QO:
599 case PCI_DEVICE_ID_ATI_RADEON_Ql:
600 case PCI_DEVICE_ID_ATI_RADEON_BB:
601 rinfo->pll.ppll_max = 35000;
602 rinfo->pll.ppll_min = 12000;
603 rinfo->pll.mclk = 27500;
604 rinfo->pll.sclk = 27500;
605 rinfo->pll.ref_clk = 2700;
607 case PCI_DEVICE_ID_ATI_RADEON_Id:
608 case PCI_DEVICE_ID_ATI_RADEON_Ie:
609 case PCI_DEVICE_ID_ATI_RADEON_If:
610 case PCI_DEVICE_ID_ATI_RADEON_Ig:
611 rinfo->pll.ppll_max = 35000;
612 rinfo->pll.ppll_min = 12000;
613 rinfo->pll.mclk = 25000;
614 rinfo->pll.sclk = 25000;
615 rinfo->pll.ref_clk = 2700;
617 case PCI_DEVICE_ID_ATI_RADEON_ND:
618 case PCI_DEVICE_ID_ATI_RADEON_NE:
619 case PCI_DEVICE_ID_ATI_RADEON_NF:
620 case PCI_DEVICE_ID_ATI_RADEON_NG:
621 rinfo->pll.ppll_max = 40000;
622 rinfo->pll.ppll_min = 20000;
623 rinfo->pll.mclk = 27000;
624 rinfo->pll.sclk = 27000;
625 rinfo->pll.ref_clk = 2700;
627 case PCI_DEVICE_ID_ATI_RADEON_QD:
628 case PCI_DEVICE_ID_ATI_RADEON_QE:
629 case PCI_DEVICE_ID_ATI_RADEON_QF:
630 case PCI_DEVICE_ID_ATI_RADEON_QG:
632 rinfo->pll.ppll_max = 35000;
633 rinfo->pll.ppll_min = 12000;
634 rinfo->pll.mclk = 16600;
635 rinfo->pll.sclk = 16600;
636 rinfo->pll.ref_clk = 2700;
639 rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;
644 * Retrieve PLL infos from Open Firmware first
646 if (!force_measure_pll && radeon_read_xtal_OF(rinfo) == 0) {
647 printk(KERN_INFO "radeonfb: Retrieved PLL infos from Open Firmware\n");
650 #endif /* CONFIG_PPC_OF */
653 * Check out if we have an X86 which gave us some PLL informations
654 * and if yes, retrieve them
656 if (!force_measure_pll && rinfo->bios_seg) {
657 u16 pll_info_block = BIOS_IN16(rinfo->fp_bios_start + 0x30);
659 rinfo->pll.sclk = BIOS_IN16(pll_info_block + 0x08);
660 rinfo->pll.mclk = BIOS_IN16(pll_info_block + 0x0a);
661 rinfo->pll.ref_clk = BIOS_IN16(pll_info_block + 0x0e);
662 rinfo->pll.ref_div = BIOS_IN16(pll_info_block + 0x10);
663 rinfo->pll.ppll_min = BIOS_IN32(pll_info_block + 0x12);
664 rinfo->pll.ppll_max = BIOS_IN32(pll_info_block + 0x16);
666 printk(KERN_INFO "radeonfb: Retrieved PLL infos from BIOS\n");
671 * We didn't get PLL parameters from either OF or BIOS, we try to
674 if (radeon_probe_pll_params(rinfo) == 0) {
675 printk(KERN_INFO "radeonfb: Retrieved PLL infos from registers\n");
680 * Fall back to already-set defaults...
682 printk(KERN_INFO "radeonfb: Used default PLL infos\n");
686 * Some methods fail to retrieve SCLK and MCLK values, we apply default
687 * settings in this case (200Mhz). If that really happne often, we could
688 * fetch from registers instead...
690 if (rinfo->pll.mclk == 0)
691 rinfo->pll.mclk = 20000;
692 if (rinfo->pll.sclk == 0)
693 rinfo->pll.sclk = 20000;
695 printk("radeonfb: Reference=%d.%02d MHz (RefDiv=%d) Memory=%d.%02d Mhz, System=%d.%02d MHz\n",
696 rinfo->pll.ref_clk / 100, rinfo->pll.ref_clk % 100,
698 rinfo->pll.mclk / 100, rinfo->pll.mclk % 100,
699 rinfo->pll.sclk / 100, rinfo->pll.sclk % 100);
700 printk("radeonfb: PLL min %d max %d\n", rinfo->pll.ppll_min, rinfo->pll.ppll_max);
703 static int radeonfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info)
705 struct radeonfb_info *rinfo = info->par;
706 struct fb_var_screeninfo v;
710 if (radeon_match_mode(rinfo, &v, var))
713 switch (v.bits_per_pixel) {
715 v.bits_per_pixel = 8;
718 v.bits_per_pixel = 16;
721 #if 0 /* Doesn't seem to work */
722 v.bits_per_pixel = 24;
727 v.bits_per_pixel = 32;
733 switch (var_to_depth(&v)) {
736 v.red.offset = v.green.offset = v.blue.offset = 0;
737 v.red.length = v.green.length = v.blue.length = 8;
738 v.transp.offset = v.transp.length = 0;
746 v.red.length = v.green.length = v.blue.length = 5;
747 v.transp.offset = v.transp.length = 0;
758 v.transp.offset = v.transp.length = 0;
766 v.red.length = v.blue.length = v.green.length = 8;
767 v.transp.offset = v.transp.length = 0;
775 v.red.length = v.blue.length = v.green.length = 8;
776 v.transp.offset = 24;
780 printk ("radeonfb: mode %dx%dx%d rejected, color depth invalid\n",
781 var->xres, var->yres, var->bits_per_pixel);
785 if (v.yres_virtual < v.yres)
786 v.yres_virtual = v.yres;
787 if (v.xres_virtual < v.xres)
788 v.xres_virtual = v.xres;
791 /* XXX I'm adjusting xres_virtual to the pitch, that may help XFree
792 * with some panels, though I don't quite like this solution
794 if (rinfo->info->flags & FBINFO_HWACCEL_DISABLED) {
795 v.xres_virtual = v.xres_virtual & ~7ul;
797 pitch = ((v.xres_virtual * ((v.bits_per_pixel + 1) / 8) + 0x3f)
799 v.xres_virtual = (pitch << 6) / ((v.bits_per_pixel + 1) / 8);
802 if (((v.xres_virtual * v.yres_virtual * nom) / den) > rinfo->mapped_vram)
805 if (v.xres_virtual < v.xres)
806 v.xres = v.xres_virtual;
813 if (v.xoffset > v.xres_virtual - v.xres)
814 v.xoffset = v.xres_virtual - v.xres - 1;
816 if (v.yoffset > v.yres_virtual - v.yres)
817 v.yoffset = v.yres_virtual - v.yres - 1;
819 v.red.msb_right = v.green.msb_right = v.blue.msb_right =
820 v.transp.offset = v.transp.length =
821 v.transp.msb_right = 0;
823 memcpy(var, &v, sizeof(v));
829 static int radeonfb_pan_display (struct fb_var_screeninfo *var,
830 struct fb_info *info)
832 struct radeonfb_info *rinfo = info->par;
834 if ((var->xoffset + var->xres > var->xres_virtual)
835 || (var->yoffset + var->yres > var->yres_virtual))
842 OUTREG(CRTC_OFFSET, ((var->yoffset * var->xres_virtual + var->xoffset)
843 * var->bits_per_pixel / 8) & ~7);
848 static int radeonfb_ioctl (struct fb_info *info, unsigned int cmd,
851 struct radeonfb_info *rinfo = info->par;
858 * TODO: set mirror accordingly for non-Mobility chipsets with 2 CRTC's
859 * and do something better using 2nd CRTC instead of just hackish
860 * routing to second output
862 case FBIO_RADEON_SET_MIRROR:
863 if (!rinfo->is_mobility)
866 rc = get_user(value, (__u32 __user *)arg);
873 tmp = INREG(LVDS_GEN_CNTL);
875 tmp |= (LVDS_ON | LVDS_BLON);
877 tmp = INREG(LVDS_GEN_CNTL);
879 tmp &= ~(LVDS_ON | LVDS_BLON);
882 OUTREG(LVDS_GEN_CNTL, tmp);
885 tmp = INREG(CRTC_EXT_CNTL);
890 tmp = INREG(CRTC_EXT_CNTL);
896 OUTREG(CRTC_EXT_CNTL, tmp);
899 case FBIO_RADEON_GET_MIRROR:
900 if (!rinfo->is_mobility)
903 tmp = INREG(LVDS_GEN_CNTL);
904 if ((LVDS_ON | LVDS_BLON) & tmp)
907 tmp = INREG(CRTC_EXT_CNTL);
908 if (CRTC_CRT_ON & tmp)
911 return put_user(value, (__u32 __user *)arg);
920 int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch)
926 if (rinfo->lock_blank)
929 radeon_engine_idle();
931 val = INREG(CRTC_EXT_CNTL);
932 val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |
935 case FB_BLANK_VSYNC_SUSPEND:
936 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS);
938 case FB_BLANK_HSYNC_SUSPEND:
939 val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS);
941 case FB_BLANK_POWERDOWN:
942 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS |
945 case FB_BLANK_NORMAL:
946 val |= CRTC_DISPLAY_DIS;
948 case FB_BLANK_UNBLANK:
952 OUTREG(CRTC_EXT_CNTL, val);
955 switch (rinfo->mon1_type) {
958 OUTREGP(FP_GEN_CNTL, (FP_FPON | FP_TMDS_EN),
959 ~(FP_FPON | FP_TMDS_EN));
961 if (mode_switch || blank == FB_BLANK_NORMAL)
963 OUTREGP(FP_GEN_CNTL, 0, ~(FP_FPON | FP_TMDS_EN));
967 del_timer_sync(&rinfo->lvds_timer);
968 val = INREG(LVDS_GEN_CNTL);
970 u32 target_val = (val & ~LVDS_DISPLAY_DIS) | LVDS_BLON | LVDS_ON
971 | LVDS_EN | (rinfo->init_state.lvds_gen_cntl
972 & (LVDS_DIGON | LVDS_BL_MOD_EN));
973 if ((val ^ target_val) == LVDS_DISPLAY_DIS)
974 OUTREG(LVDS_GEN_CNTL, target_val);
975 else if ((val ^ target_val) != 0) {
976 OUTREG(LVDS_GEN_CNTL, target_val
977 & ~(LVDS_ON | LVDS_BL_MOD_EN));
978 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
979 rinfo->init_state.lvds_gen_cntl |=
980 target_val & LVDS_STATE_MASK;
982 radeon_msleep(rinfo->panel_info.pwr_delay);
983 OUTREG(LVDS_GEN_CNTL, target_val);
986 rinfo->pending_lvds_gen_cntl = target_val;
987 mod_timer(&rinfo->lvds_timer,
989 msecs_to_jiffies(rinfo->panel_info.pwr_delay));
993 val |= LVDS_DISPLAY_DIS;
994 OUTREG(LVDS_GEN_CNTL, val);
996 /* We don't do a full switch-off on a simple mode switch */
997 if (mode_switch || blank == FB_BLANK_NORMAL)
1000 /* Asic bug, when turning off LVDS_ON, we have to make sure
1001 * RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
1003 tmp_pix_clks = INPLL(PIXCLKS_CNTL);
1004 if (rinfo->is_mobility || rinfo->is_IGP)
1005 OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb);
1006 val &= ~(LVDS_BL_MOD_EN);
1007 OUTREG(LVDS_GEN_CNTL, val);
1009 val &= ~(LVDS_ON | LVDS_EN);
1010 OUTREG(LVDS_GEN_CNTL, val);
1012 rinfo->pending_lvds_gen_cntl = val;
1013 mod_timer(&rinfo->lvds_timer,
1015 msecs_to_jiffies(rinfo->panel_info.pwr_delay));
1016 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
1017 rinfo->init_state.lvds_gen_cntl |= val & LVDS_STATE_MASK;
1018 if (rinfo->is_mobility || rinfo->is_IGP)
1019 OUTPLL(PIXCLKS_CNTL, tmp_pix_clks);
1023 // todo: powerdown DAC
1028 /* let fbcon do a soft blank for us */
1029 return (blank == FB_BLANK_NORMAL) ? -EINVAL : 0;
1032 static int radeonfb_blank (int blank, struct fb_info *info)
1034 struct radeonfb_info *rinfo = info->par;
1039 return radeon_screen_blank(rinfo, blank, 0);
1042 static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
1043 unsigned blue, unsigned transp,
1044 struct radeonfb_info *rinfo)
1056 rinfo->palette[regno].red = red;
1057 rinfo->palette[regno].green = green;
1058 rinfo->palette[regno].blue = blue;
1063 if (!rinfo->asleep) {
1064 radeon_fifo_wait(9);
1066 if (rinfo->bpp == 16) {
1069 if (rinfo->depth == 16 && regno > 63)
1071 if (rinfo->depth == 15 && regno > 31)
1074 /* For 565, the green component is mixed one order
1077 if (rinfo->depth == 16) {
1078 OUTREG(PALETTE_INDEX, pindex>>1);
1079 OUTREG(PALETTE_DATA,
1080 (rinfo->palette[regno>>1].red << 16) |
1082 (rinfo->palette[regno>>1].blue));
1083 green = rinfo->palette[regno<<1].green;
1087 if (rinfo->depth != 16 || regno < 32) {
1088 OUTREG(PALETTE_INDEX, pindex);
1089 OUTREG(PALETTE_DATA, (red << 16) |
1090 (green << 8) | blue);
1094 u32 *pal = rinfo->info->pseudo_palette;
1095 switch (rinfo->depth) {
1097 pal[regno] = (regno << 10) | (regno << 5) | regno;
1100 pal[regno] = (regno << 11) | (regno << 5) | regno;
1103 pal[regno] = (regno << 16) | (regno << 8) | regno;
1106 i = (regno << 8) | regno;
1107 pal[regno] = (i << 16) | i;
1114 static int radeonfb_setcolreg (unsigned regno, unsigned red, unsigned green,
1115 unsigned blue, unsigned transp,
1116 struct fb_info *info)
1118 struct radeonfb_info *rinfo = info->par;
1119 u32 dac_cntl2, vclk_cntl = 0;
1122 if (!rinfo->asleep) {
1123 if (rinfo->is_mobility) {
1124 vclk_cntl = INPLL(VCLK_ECP_CNTL);
1125 OUTPLL(VCLK_ECP_CNTL,
1126 vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1129 /* Make sure we are on first palette */
1130 if (rinfo->has_CRTC2) {
1131 dac_cntl2 = INREG(DAC_CNTL2);
1132 dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;
1133 OUTREG(DAC_CNTL2, dac_cntl2);
1137 rc = radeon_setcolreg (regno, red, green, blue, transp, rinfo);
1139 if (!rinfo->asleep && rinfo->is_mobility)
1140 OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1145 static int radeonfb_setcmap(struct fb_cmap *cmap, struct fb_info *info)
1147 struct radeonfb_info *rinfo = info->par;
1148 u16 *red, *green, *blue, *transp;
1149 u32 dac_cntl2, vclk_cntl = 0;
1150 int i, start, rc = 0;
1152 if (!rinfo->asleep) {
1153 if (rinfo->is_mobility) {
1154 vclk_cntl = INPLL(VCLK_ECP_CNTL);
1155 OUTPLL(VCLK_ECP_CNTL,
1156 vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1159 /* Make sure we are on first palette */
1160 if (rinfo->has_CRTC2) {
1161 dac_cntl2 = INREG(DAC_CNTL2);
1162 dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;
1163 OUTREG(DAC_CNTL2, dac_cntl2);
1168 green = cmap->green;
1170 transp = cmap->transp;
1171 start = cmap->start;
1173 for (i = 0; i < cmap->len; i++) {
1174 u_int hred, hgreen, hblue, htransp = 0xffff;
1180 htransp = *transp++;
1181 rc = radeon_setcolreg (start++, hred, hgreen, hblue, htransp,
1187 if (!rinfo->asleep && rinfo->is_mobility)
1188 OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1193 static void radeon_save_state (struct radeonfb_info *rinfo,
1194 struct radeon_regs *save)
1197 save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1198 save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1199 save->crtc_more_cntl = INREG(CRTC_MORE_CNTL);
1200 save->dac_cntl = INREG(DAC_CNTL);
1201 save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP);
1202 save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID);
1203 save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP);
1204 save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID);
1205 save->crtc_pitch = INREG(CRTC_PITCH);
1206 save->surface_cntl = INREG(SURFACE_CNTL);
1209 save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP);
1210 save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP);
1211 save->fp_gen_cntl = INREG(FP_GEN_CNTL);
1212 save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID);
1213 save->fp_horz_stretch = INREG(FP_HORZ_STRETCH);
1214 save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID);
1215 save->fp_vert_stretch = INREG(FP_VERT_STRETCH);
1216 save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
1217 save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL);
1218 save->tmds_crc = INREG(TMDS_CRC);
1219 save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL);
1220 save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL);
1223 save->clk_cntl_index = INREG(CLOCK_CNTL_INDEX) & ~0x3f;
1224 radeon_pll_errata_after_index(rinfo);
1225 save->ppll_div_3 = INPLL(PPLL_DIV_3);
1226 save->ppll_ref_div = INPLL(PPLL_REF_DIV);
1230 static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode)
1234 radeon_fifo_wait(20);
1236 /* Workaround from XFree */
1237 if (rinfo->is_mobility) {
1238 /* A temporal workaround for the occational blanking on certain laptop
1239 * panels. This appears to related to the PLL divider registers
1240 * (fail to lock?). It occurs even when all dividers are the same
1241 * with their old settings. In this case we really don't need to
1242 * fiddle with PLL registers. By doing this we can avoid the blanking
1243 * problem with some panels.
1245 if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) &&
1246 (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) &
1247 (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) {
1248 /* We still have to force a switch to selected PPLL div thanks to
1249 * an XFree86 driver bug which will switch it away in some cases
1250 * even when using UseFDev */
1251 OUTREGP(CLOCK_CNTL_INDEX,
1252 mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
1253 ~PPLL_DIV_SEL_MASK);
1254 radeon_pll_errata_after_index(rinfo);
1255 radeon_pll_errata_after_data(rinfo);
1260 /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/
1261 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK);
1263 /* Reset PPLL & enable atomic update */
1265 PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN,
1266 ~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1268 /* Switch to selected PPLL divider */
1269 OUTREGP(CLOCK_CNTL_INDEX,
1270 mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
1271 ~PPLL_DIV_SEL_MASK);
1272 radeon_pll_errata_after_index(rinfo);
1273 radeon_pll_errata_after_data(rinfo);
1275 /* Set PPLL ref. div */
1276 if (rinfo->family == CHIP_FAMILY_R300 ||
1277 rinfo->family == CHIP_FAMILY_RS300 ||
1278 rinfo->family == CHIP_FAMILY_R350 ||
1279 rinfo->family == CHIP_FAMILY_RV350) {
1280 if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
1281 /* When restoring console mode, use saved PPLL_REF_DIV
1284 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0);
1286 /* R300 uses ref_div_acc field as real ref divider */
1287 OUTPLLP(PPLL_REF_DIV,
1288 (mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
1289 ~R300_PPLL_REF_DIV_ACC_MASK);
1292 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK);
1294 /* Set PPLL divider 3 & post divider*/
1295 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK);
1296 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK);
1299 while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R)
1301 OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W);
1303 /* Wait read update complete */
1304 /* FIXME: Certain revisions of R300 can't recover here. Not sure of
1305 the cause yet, but this workaround will mask the problem for now.
1306 Other chips usually will pass at the very first test, so the
1307 workaround shouldn't have any effect on them. */
1308 for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++)
1311 OUTPLL(HTOTAL_CNTL, 0);
1313 /* Clear reset & atomic update */
1314 OUTPLLP(PPLL_CNTL, 0,
1315 ~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1317 /* We may want some locking ... oh well */
1320 /* Switch back VCLK source to PPLL */
1321 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK);
1325 * Timer function for delayed LVDS panel power up/down
1327 static void radeon_lvds_timer_func(unsigned long data)
1329 struct radeonfb_info *rinfo = (struct radeonfb_info *)data;
1331 radeon_engine_idle();
1333 OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl);
1337 * Apply a video mode. This will apply the whole register set, including
1338 * the PLL registers, to the card
1340 void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
1344 int primary_mon = PRIMARY_MONITOR(rinfo);
1350 radeon_screen_blank(rinfo, FB_BLANK_NORMAL, 0);
1352 radeon_fifo_wait(31);
1353 for (i=0; i<10; i++)
1354 OUTREG(common_regs[i].reg, common_regs[i].val);
1356 /* Apply surface registers */
1357 for (i=0; i<8; i++) {
1358 OUTREG(SURFACE0_LOWER_BOUND + 0x10*i, mode->surf_lower_bound[i]);
1359 OUTREG(SURFACE0_UPPER_BOUND + 0x10*i, mode->surf_upper_bound[i]);
1360 OUTREG(SURFACE0_INFO + 0x10*i, mode->surf_info[i]);
1363 OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
1364 OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
1365 ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS));
1366 OUTREG(CRTC_MORE_CNTL, mode->crtc_more_cntl);
1367 OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
1368 OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
1369 OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
1370 OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
1371 OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
1372 OUTREG(CRTC_OFFSET, 0);
1373 OUTREG(CRTC_OFFSET_CNTL, 0);
1374 OUTREG(CRTC_PITCH, mode->crtc_pitch);
1375 OUTREG(SURFACE_CNTL, mode->surface_cntl);
1377 radeon_write_pll_regs(rinfo, mode);
1379 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1380 radeon_fifo_wait(10);
1381 OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp);
1382 OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp);
1383 OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid);
1384 OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid);
1385 OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch);
1386 OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch);
1387 OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl);
1388 OUTREG(TMDS_CRC, mode->tmds_crc);
1389 OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl);
1393 radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 0);
1395 radeon_fifo_wait(2);
1396 OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl);
1402 * Calculate the PLL values for a given mode
1404 static void radeon_calc_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *regs,
1422 int fb_div, pll_output_freq = 0;
1425 /* Check if the DVO port is enabled and sourced from the primary CRTC. I'm
1426 * not sure which model starts having FP2_GEN_CNTL, I assume anything more
1427 * recent than an r(v)100...
1430 /* XXX I had reports of flicker happening with the cinema display
1431 * on TMDS1 that seem to be fixed if I also forbit odd dividers in
1432 * this case. This could just be a bandwidth calculation issue, I
1433 * haven't implemented the bandwidth code yet, but in the meantime,
1434 * forcing uses_dvo to 1 fixes it and shouln't have bad side effects,
1435 * I haven't seen a case were were absolutely needed an odd PLL
1436 * divider. I'll find a better fix once I have more infos on the
1437 * real cause of the problem.
1439 while (rinfo->has_CRTC2) {
1440 u32 fp2_gen_cntl = INREG(FP2_GEN_CNTL);
1441 u32 disp_output_cntl;
1444 /* FP2 path not enabled */
1445 if ((fp2_gen_cntl & FP2_ON) == 0)
1447 /* Not all chip revs have the same format for this register,
1448 * extract the source selection
1450 if (rinfo->family == CHIP_FAMILY_R200 ||
1451 rinfo->family == CHIP_FAMILY_R300 ||
1452 rinfo->family == CHIP_FAMILY_R350 ||
1453 rinfo->family == CHIP_FAMILY_RV350) {
1454 source = (fp2_gen_cntl >> 10) & 0x3;
1455 /* sourced from transform unit, check for transform unit
1459 disp_output_cntl = INREG(DISP_OUTPUT_CNTL);
1460 source = (disp_output_cntl >> 12) & 0x3;
1463 source = (fp2_gen_cntl >> 13) & 0x1;
1464 /* sourced from CRTC2 -> exit */
1468 /* so we end up on CRTC1, let's set uses_dvo to 1 now */
1475 if (freq > rinfo->pll.ppll_max)
1476 freq = rinfo->pll.ppll_max;
1477 if (freq*12 < rinfo->pll.ppll_min)
1478 freq = rinfo->pll.ppll_min / 12;
1479 RTRACE("freq = %lu, PLL min = %u, PLL max = %u\n",
1480 freq, rinfo->pll.ppll_min, rinfo->pll.ppll_max);
1482 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
1483 pll_output_freq = post_div->divider * freq;
1484 /* If we output to the DVO port (external TMDS), we don't allow an
1485 * odd PLL divider as those aren't supported on this path
1487 if (uses_dvo && (post_div->divider & 1))
1489 if (pll_output_freq >= rinfo->pll.ppll_min &&
1490 pll_output_freq <= rinfo->pll.ppll_max)
1494 /* If we fall through the bottom, try the "default value"
1495 given by the terminal post_div->bitvalue */
1496 if ( !post_div->divider ) {
1497 post_div = &post_divs[post_div->bitvalue];
1498 pll_output_freq = post_div->divider * freq;
1500 RTRACE("ref_div = %d, ref_clk = %d, output_freq = %d\n",
1501 rinfo->pll.ref_div, rinfo->pll.ref_clk,
1504 /* If we fall through the bottom, try the "default value"
1505 given by the terminal post_div->bitvalue */
1506 if ( !post_div->divider ) {
1507 post_div = &post_divs[post_div->bitvalue];
1508 pll_output_freq = post_div->divider * freq;
1510 RTRACE("ref_div = %d, ref_clk = %d, output_freq = %d\n",
1511 rinfo->pll.ref_div, rinfo->pll.ref_clk,
1514 fb_div = round_div(rinfo->pll.ref_div*pll_output_freq,
1515 rinfo->pll.ref_clk);
1516 regs->ppll_ref_div = rinfo->pll.ref_div;
1517 regs->ppll_div_3 = fb_div | (post_div->bitvalue << 16);
1519 RTRACE("post div = 0x%x\n", post_div->bitvalue);
1520 RTRACE("fb_div = 0x%x\n", fb_div);
1521 RTRACE("ppll_div_3 = 0x%x\n", regs->ppll_div_3);
1524 static int radeonfb_set_par(struct fb_info *info)
1526 struct radeonfb_info *rinfo = info->par;
1527 struct fb_var_screeninfo *mode = &info->var;
1528 struct radeon_regs *newmode;
1529 int hTotal, vTotal, hSyncStart, hSyncEnd,
1530 hSyncPol, vSyncStart, vSyncEnd, vSyncPol, cSync;
1531 u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5};
1532 u8 hsync_fudge_fp[] = {2, 2, 0, 0, 5, 5};
1533 u32 sync, h_sync_pol, v_sync_pol, dotClock, pixClock;
1537 int hsync_start, hsync_fudge, bytpp, hsync_wid, vsync_wid;
1538 int primary_mon = PRIMARY_MONITOR(rinfo);
1539 int depth = var_to_depth(mode);
1542 newmode = kmalloc(sizeof(struct radeon_regs), GFP_KERNEL);
1546 /* We always want engine to be idle on a mode switch, even
1547 * if we won't actually change the mode
1549 radeon_engine_idle();
1551 hSyncStart = mode->xres + mode->right_margin;
1552 hSyncEnd = hSyncStart + mode->hsync_len;
1553 hTotal = hSyncEnd + mode->left_margin;
1555 vSyncStart = mode->yres + mode->lower_margin;
1556 vSyncEnd = vSyncStart + mode->vsync_len;
1557 vTotal = vSyncEnd + mode->upper_margin;
1558 pixClock = mode->pixclock;
1561 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1562 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1564 if (primary_mon == MT_DFP || primary_mon == MT_LCD) {
1565 if (rinfo->panel_info.xres < mode->xres)
1566 mode->xres = rinfo->panel_info.xres;
1567 if (rinfo->panel_info.yres < mode->yres)
1568 mode->yres = rinfo->panel_info.yres;
1570 hTotal = mode->xres + rinfo->panel_info.hblank;
1571 hSyncStart = mode->xres + rinfo->panel_info.hOver_plus;
1572 hSyncEnd = hSyncStart + rinfo->panel_info.hSync_width;
1574 vTotal = mode->yres + rinfo->panel_info.vblank;
1575 vSyncStart = mode->yres + rinfo->panel_info.vOver_plus;
1576 vSyncEnd = vSyncStart + rinfo->panel_info.vSync_width;
1578 h_sync_pol = !rinfo->panel_info.hAct_high;
1579 v_sync_pol = !rinfo->panel_info.vAct_high;
1581 pixClock = 100000000 / rinfo->panel_info.clock;
1583 if (rinfo->panel_info.use_bios_dividers) {
1585 newmode->ppll_div_3 = rinfo->panel_info.fbk_divider |
1586 (rinfo->panel_info.post_divider << 16);
1587 newmode->ppll_ref_div = rinfo->panel_info.ref_divider;
1590 dotClock = 1000000000 / pixClock;
1591 freq = dotClock / 10; /* x100 */
1593 RTRACE("hStart = %d, hEnd = %d, hTotal = %d\n",
1594 hSyncStart, hSyncEnd, hTotal);
1595 RTRACE("vStart = %d, vEnd = %d, vTotal = %d\n",
1596 vSyncStart, vSyncEnd, vTotal);
1598 hsync_wid = (hSyncEnd - hSyncStart) / 8;
1599 vsync_wid = vSyncEnd - vSyncStart;
1602 else if (hsync_wid > 0x3f) /* max */
1607 else if (vsync_wid > 0x1f) /* max */
1610 hSyncPol = mode->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1611 vSyncPol = mode->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1613 cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
1615 format = radeon_get_dstbpp(depth);
1616 bytpp = mode->bits_per_pixel >> 3;
1618 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD))
1619 hsync_fudge = hsync_fudge_fp[format-1];
1621 hsync_fudge = hsync_adj_tab[format-1];
1623 hsync_start = hSyncStart - 8 + hsync_fudge;
1625 newmode->crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN |
1628 /* Clear auto-center etc... */
1629 newmode->crtc_more_cntl = rinfo->init_state.crtc_more_cntl;
1630 newmode->crtc_more_cntl &= 0xfffffff0;
1632 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1633 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN;
1635 newmode->crtc_ext_cntl |= CRTC_CRT_ON;
1637 newmode->crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN |
1640 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN |
1644 newmode->dac_cntl = /* INREG(DAC_CNTL) | */ DAC_MASK_ALL | DAC_VGA_ADR_EN |
1647 newmode->crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) |
1648 (((mode->xres / 8) - 1) << 16));
1650 newmode->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |
1651 (hsync_wid << 16) | (h_sync_pol << 23));
1653 newmode->crtc_v_total_disp = ((vTotal - 1) & 0xffff) |
1654 ((mode->yres - 1) << 16);
1656 newmode->crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) |
1657 (vsync_wid << 16) | (v_sync_pol << 23));
1659 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) {
1660 /* We first calculate the engine pitch */
1661 rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f)
1664 /* Then, re-multiply it to get the CRTC pitch */
1665 newmode->crtc_pitch = (rinfo->pitch << 3) / ((mode->bits_per_pixel + 1) / 8);
1667 newmode->crtc_pitch = (mode->xres_virtual >> 3);
1669 newmode->crtc_pitch |= (newmode->crtc_pitch << 16);
1672 * It looks like recent chips have a problem with SURFACE_CNTL,
1673 * setting SURF_TRANSLATION_DIS completely disables the
1674 * swapper as well, so we leave it unset now.
1676 newmode->surface_cntl = 0;
1678 #if defined(__BIG_ENDIAN)
1680 /* Setup swapping on both apertures, though we currently
1681 * only use aperture 0, enabling swapper on aperture 1
1684 switch (mode->bits_per_pixel) {
1686 newmode->surface_cntl |= NONSURF_AP0_SWP_16BPP;
1687 newmode->surface_cntl |= NONSURF_AP1_SWP_16BPP;
1691 newmode->surface_cntl |= NONSURF_AP0_SWP_32BPP;
1692 newmode->surface_cntl |= NONSURF_AP1_SWP_32BPP;
1697 /* Clear surface registers */
1698 for (i=0; i<8; i++) {
1699 newmode->surf_lower_bound[i] = 0;
1700 newmode->surf_upper_bound[i] = 0x1f;
1701 newmode->surf_info[i] = 0;
1704 RTRACE("h_total_disp = 0x%x\t hsync_strt_wid = 0x%x\n",
1705 newmode->crtc_h_total_disp, newmode->crtc_h_sync_strt_wid);
1706 RTRACE("v_total_disp = 0x%x\t vsync_strt_wid = 0x%x\n",
1707 newmode->crtc_v_total_disp, newmode->crtc_v_sync_strt_wid);
1709 rinfo->bpp = mode->bits_per_pixel;
1710 rinfo->depth = depth;
1712 RTRACE("pixclock = %lu\n", (unsigned long)pixClock);
1713 RTRACE("freq = %lu\n", (unsigned long)freq);
1715 /* We use PPLL_DIV_3 */
1716 newmode->clk_cntl_index = 0x300;
1718 /* Calculate PPLL value if necessary */
1720 radeon_calc_pll_regs(rinfo, newmode, freq);
1722 newmode->vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl;
1724 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1725 unsigned int hRatio, vRatio;
1727 if (mode->xres > rinfo->panel_info.xres)
1728 mode->xres = rinfo->panel_info.xres;
1729 if (mode->yres > rinfo->panel_info.yres)
1730 mode->yres = rinfo->panel_info.yres;
1732 newmode->fp_horz_stretch = (((rinfo->panel_info.xres / 8) - 1)
1733 << HORZ_PANEL_SHIFT);
1734 newmode->fp_vert_stretch = ((rinfo->panel_info.yres - 1)
1735 << VERT_PANEL_SHIFT);
1737 if (mode->xres != rinfo->panel_info.xres) {
1738 hRatio = round_div(mode->xres * HORZ_STRETCH_RATIO_MAX,
1739 rinfo->panel_info.xres);
1740 newmode->fp_horz_stretch = (((((unsigned long)hRatio) & HORZ_STRETCH_RATIO_MASK)) |
1741 (newmode->fp_horz_stretch &
1742 (HORZ_PANEL_SIZE | HORZ_FP_LOOP_STRETCH |
1743 HORZ_AUTO_RATIO_INC)));
1744 newmode->fp_horz_stretch |= (HORZ_STRETCH_BLEND |
1745 HORZ_STRETCH_ENABLE);
1748 newmode->fp_horz_stretch &= ~HORZ_AUTO_RATIO;
1750 if (mode->yres != rinfo->panel_info.yres) {
1751 vRatio = round_div(mode->yres * VERT_STRETCH_RATIO_MAX,
1752 rinfo->panel_info.yres);
1753 newmode->fp_vert_stretch = (((((unsigned long)vRatio) & VERT_STRETCH_RATIO_MASK)) |
1754 (newmode->fp_vert_stretch &
1755 (VERT_PANEL_SIZE | VERT_STRETCH_RESERVED)));
1756 newmode->fp_vert_stretch |= (VERT_STRETCH_BLEND |
1757 VERT_STRETCH_ENABLE);
1760 newmode->fp_vert_stretch &= ~VERT_AUTO_RATIO_EN;
1762 newmode->fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32)
1764 FP_RMX_HVSYNC_CONTROL_EN |
1769 FP_CRTC_USE_SHADOW_VEND |
1772 newmode->fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR |
1773 FP_CRTC_DONT_SHADOW_HEND |
1776 if (IS_R300_VARIANT(rinfo) ||
1777 (rinfo->family == CHIP_FAMILY_R200)) {
1778 newmode->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
1780 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
1782 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
1784 newmode->fp_gen_cntl |= FP_SEL_CRTC1;
1786 newmode->lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl;
1787 newmode->lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl;
1788 newmode->tmds_crc = rinfo->init_state.tmds_crc;
1789 newmode->tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl;
1791 if (primary_mon == MT_LCD) {
1792 newmode->lvds_gen_cntl |= (LVDS_ON | LVDS_BLON);
1793 newmode->fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN);
1796 newmode->fp_gen_cntl |= (FP_FPON | FP_TMDS_EN);
1797 newmode->tmds_transmitter_cntl &= ~(TMDS_PLLRST);
1798 /* TMDS_PLL_EN bit is reversed on RV (and mobility) chips */
1799 if (IS_R300_VARIANT(rinfo) ||
1800 (rinfo->family == CHIP_FAMILY_R200) || !rinfo->has_CRTC2)
1801 newmode->tmds_transmitter_cntl &= ~TMDS_PLL_EN;
1803 newmode->tmds_transmitter_cntl |= TMDS_PLL_EN;
1804 newmode->crtc_ext_cntl &= ~CRTC_CRT_ON;
1807 newmode->fp_crtc_h_total_disp = (((rinfo->panel_info.hblank / 8) & 0x3ff) |
1808 (((mode->xres / 8) - 1) << 16));
1809 newmode->fp_crtc_v_total_disp = (rinfo->panel_info.vblank & 0xffff) |
1810 ((mode->yres - 1) << 16);
1811 newmode->fp_h_sync_strt_wid = ((rinfo->panel_info.hOver_plus & 0x1fff) |
1812 (hsync_wid << 16) | (h_sync_pol << 23));
1813 newmode->fp_v_sync_strt_wid = ((rinfo->panel_info.vOver_plus & 0xfff) |
1814 (vsync_wid << 16) | (v_sync_pol << 23));
1818 if (!rinfo->asleep) {
1819 memcpy(&rinfo->state, newmode, sizeof(*newmode));
1820 radeon_write_mode (rinfo, newmode, 0);
1821 /* (re)initialize the engine */
1822 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1823 radeonfb_engine_init (rinfo);
1826 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1827 info->fix.line_length = rinfo->pitch*64;
1829 info->fix.line_length = mode->xres_virtual
1830 * ((mode->bits_per_pixel + 1) / 8);
1831 info->fix.visual = rinfo->depth == 8 ? FB_VISUAL_PSEUDOCOLOR
1832 : FB_VISUAL_DIRECTCOLOR;
1834 #ifdef CONFIG_BOOTX_TEXT
1835 /* Update debug text engine */
1836 btext_update_display(rinfo->fb_base_phys, mode->xres, mode->yres,
1837 rinfo->depth, info->fix.line_length);
1845 static struct fb_ops radeonfb_ops = {
1846 .owner = THIS_MODULE,
1847 .fb_check_var = radeonfb_check_var,
1848 .fb_set_par = radeonfb_set_par,
1849 .fb_setcolreg = radeonfb_setcolreg,
1850 .fb_setcmap = radeonfb_setcmap,
1851 .fb_pan_display = radeonfb_pan_display,
1852 .fb_blank = radeonfb_blank,
1853 .fb_ioctl = radeonfb_ioctl,
1854 .fb_sync = radeonfb_sync,
1855 .fb_fillrect = radeonfb_fillrect,
1856 .fb_copyarea = radeonfb_copyarea,
1857 .fb_imageblit = radeonfb_imageblit,
1861 static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
1863 struct fb_info *info = rinfo->info;
1866 info->pseudo_palette = rinfo->pseudo_palette;
1867 info->flags = FBINFO_DEFAULT
1868 | FBINFO_HWACCEL_COPYAREA
1869 | FBINFO_HWACCEL_FILLRECT
1870 | FBINFO_HWACCEL_XPAN
1871 | FBINFO_HWACCEL_YPAN;
1872 info->fbops = &radeonfb_ops;
1873 info->screen_base = rinfo->fb_base;
1874 info->screen_size = rinfo->mapped_vram;
1875 /* Fill fix common fields */
1876 strlcpy(info->fix.id, rinfo->name, sizeof(info->fix.id));
1877 info->fix.smem_start = rinfo->fb_base_phys;
1878 info->fix.smem_len = rinfo->video_ram;
1879 info->fix.type = FB_TYPE_PACKED_PIXELS;
1880 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
1881 info->fix.xpanstep = 8;
1882 info->fix.ypanstep = 1;
1883 info->fix.ywrapstep = 0;
1884 info->fix.type_aux = 0;
1885 info->fix.mmio_start = rinfo->mmio_base_phys;
1886 info->fix.mmio_len = RADEON_REGSIZE;
1887 info->fix.accel = FB_ACCEL_ATI_RADEON;
1889 fb_alloc_cmap(&info->cmap, 256, 0);
1892 info->flags |= FBINFO_HWACCEL_DISABLED;
1898 * This reconfigure the card's internal memory map. In theory, we'd like
1899 * to setup the card's memory at the same address as it's PCI bus address,
1900 * and the AGP aperture right after that so that system RAM on 32 bits
1901 * machines at least, is directly accessible. However, doing so would
1902 * conflict with the current XFree drivers...
1903 * Ultimately, I hope XFree, GATOS and ATI binary drivers will all agree
1904 * on the proper way to set this up and duplicate this here. In the meantime,
1905 * I put the card's memory at 0 in card space and AGP at some random high
1906 * local (0xe0000000 for now) that will be changed by XFree/DRI anyway
1908 #ifdef CONFIG_PPC_OF
1909 #undef SET_MC_FB_FROM_APERTURE
1910 static void fixup_memory_mappings(struct radeonfb_info *rinfo)
1912 u32 save_crtc_gen_cntl, save_crtc2_gen_cntl = 0;
1913 u32 save_crtc_ext_cntl;
1914 u32 aper_base, aper_size;
1917 /* First, we disable display to avoid interfering */
1918 if (rinfo->has_CRTC2) {
1919 save_crtc2_gen_cntl = INREG(CRTC2_GEN_CNTL);
1920 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl | CRTC2_DISP_REQ_EN_B);
1922 save_crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1923 save_crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1925 OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl | CRTC_DISPLAY_DIS);
1926 OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl | CRTC_DISP_REQ_EN_B);
1929 aper_base = INREG(CONFIG_APER_0_BASE);
1930 aper_size = INREG(CONFIG_APER_SIZE);
1932 #ifdef SET_MC_FB_FROM_APERTURE
1933 /* Set framebuffer to be at the same address as set in PCI BAR */
1934 OUTREG(MC_FB_LOCATION,
1935 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16));
1936 rinfo->fb_local_base = aper_base;
1938 OUTREG(MC_FB_LOCATION, 0x7fff0000);
1939 rinfo->fb_local_base = 0;
1941 agp_base = aper_base + aper_size;
1942 if (agp_base & 0xf0000000)
1943 agp_base = (aper_base | 0x0fffffff) + 1;
1945 /* Set AGP to be just after the framebuffer on a 256Mb boundary. This
1946 * assumes the FB isn't mapped to 0xf0000000 or above, but this is
1947 * always the case on PPCs afaik.
1949 #ifdef SET_MC_FB_FROM_APERTURE
1950 OUTREG(MC_AGP_LOCATION, 0xffff0000 | (agp_base >> 16));
1952 OUTREG(MC_AGP_LOCATION, 0xffffe000);
1955 /* Fixup the display base addresses & engine offsets while we
1958 #ifdef SET_MC_FB_FROM_APERTURE
1959 OUTREG(DISPLAY_BASE_ADDR, aper_base);
1960 if (rinfo->has_CRTC2)
1961 OUTREG(CRTC2_DISPLAY_BASE_ADDR, aper_base);
1962 OUTREG(OV0_BASE_ADDR, aper_base);
1964 OUTREG(DISPLAY_BASE_ADDR, 0);
1965 if (rinfo->has_CRTC2)
1966 OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0);
1967 OUTREG(OV0_BASE_ADDR, 0);
1971 /* Restore display settings */
1972 OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl);
1973 OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl);
1974 if (rinfo->has_CRTC2)
1975 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl);
1977 RTRACE("aper_base: %08x MC_FB_LOC to: %08x, MC_AGP_LOC to: %08x\n",
1979 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16),
1980 0xffff0000 | (agp_base >> 16));
1982 #endif /* CONFIG_PPC_OF */
1985 static void radeon_identify_vram(struct radeonfb_info *rinfo)
1989 /* framebuffer size */
1990 if ((rinfo->family == CHIP_FAMILY_RS100) ||
1991 (rinfo->family == CHIP_FAMILY_RS200) ||
1992 (rinfo->family == CHIP_FAMILY_RS300)) {
1993 u32 tom = INREG(NB_TOM);
1994 tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024);
1996 radeon_fifo_wait(6);
1997 OUTREG(MC_FB_LOCATION, tom);
1998 OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
1999 OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2000 OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16);
2002 /* This is supposed to fix the crtc2 noise problem. */
2003 OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000);
2005 if ((rinfo->family == CHIP_FAMILY_RS100) ||
2006 (rinfo->family == CHIP_FAMILY_RS200)) {
2007 /* This is to workaround the asic bug for RMX, some versions
2008 of BIOS dosen't have this register initialized correctly.
2010 OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN,
2011 ~CRTC_H_CUTOFF_ACTIVE_EN);
2014 tmp = INREG(CONFIG_MEMSIZE);
2017 /* mem size is bits [28:0], mask off the rest */
2018 rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK;
2021 * Hack to get around some busted production M6's
2024 if (rinfo->video_ram == 0) {
2025 switch (rinfo->pdev->device) {
2026 case PCI_CHIP_RADEON_LY:
2027 case PCI_CHIP_RADEON_LZ:
2028 rinfo->video_ram = 8192 * 1024;
2037 * Now try to identify VRAM type
2039 if (rinfo->is_IGP || (rinfo->family >= CHIP_FAMILY_R300) ||
2040 (INREG(MEM_SDRAM_MODE_REG) & (1<<30)))
2041 rinfo->vram_ddr = 1;
2043 rinfo->vram_ddr = 0;
2045 tmp = INREG(MEM_CNTL);
2046 if (IS_R300_VARIANT(rinfo)) {
2047 tmp &= R300_MEM_NUM_CHANNELS_MASK;
2049 case 0: rinfo->vram_width = 64; break;
2050 case 1: rinfo->vram_width = 128; break;
2051 case 2: rinfo->vram_width = 256; break;
2052 default: rinfo->vram_width = 128; break;
2054 } else if ((rinfo->family == CHIP_FAMILY_RV100) ||
2055 (rinfo->family == CHIP_FAMILY_RS100) ||
2056 (rinfo->family == CHIP_FAMILY_RS200)){
2057 if (tmp & RV100_MEM_HALF_MODE)
2058 rinfo->vram_width = 32;
2060 rinfo->vram_width = 64;
2062 if (tmp & MEM_NUM_CHANNELS_MASK)
2063 rinfo->vram_width = 128;
2065 rinfo->vram_width = 64;
2068 /* This may not be correct, as some cards can have half of channel disabled
2069 * ToDo: identify these cases
2072 RTRACE("radeonfb (%s): Found %ldk of %s %d bits wide videoram\n",
2073 pci_name(rinfo->pdev),
2074 rinfo->video_ram / 1024,
2075 rinfo->vram_ddr ? "DDR" : "SDRAM",
2083 static ssize_t radeon_show_one_edid(char *buf, loff_t off, size_t count, const u8 *edid)
2085 if (off > EDID_LENGTH)
2088 if (off + count > EDID_LENGTH)
2089 count = EDID_LENGTH - off;
2091 memcpy(buf, edid + off, count);
2097 static ssize_t radeon_show_edid1(struct kobject *kobj, char *buf, loff_t off, size_t count)
2099 struct device *dev = container_of(kobj, struct device, kobj);
2100 struct pci_dev *pdev = to_pci_dev(dev);
2101 struct fb_info *info = pci_get_drvdata(pdev);
2102 struct radeonfb_info *rinfo = info->par;
2104 return radeon_show_one_edid(buf, off, count, rinfo->mon1_EDID);
2108 static ssize_t radeon_show_edid2(struct kobject *kobj, char *buf, loff_t off, size_t count)
2110 struct device *dev = container_of(kobj, struct device, kobj);
2111 struct pci_dev *pdev = to_pci_dev(dev);
2112 struct fb_info *info = pci_get_drvdata(pdev);
2113 struct radeonfb_info *rinfo = info->par;
2115 return radeon_show_one_edid(buf, off, count, rinfo->mon2_EDID);
2118 static struct bin_attribute edid1_attr = {
2121 .owner = THIS_MODULE,
2124 .size = EDID_LENGTH,
2125 .read = radeon_show_edid1,
2128 static struct bin_attribute edid2_attr = {
2131 .owner = THIS_MODULE,
2134 .size = EDID_LENGTH,
2135 .read = radeon_show_edid2,
2139 static int __devinit radeonfb_pci_register (struct pci_dev *pdev,
2140 const struct pci_device_id *ent)
2142 struct fb_info *info;
2143 struct radeonfb_info *rinfo;
2146 RTRACE("radeonfb_pci_register BEGIN\n");
2148 /* Enable device in PCI config */
2149 ret = pci_enable_device(pdev);
2151 printk(KERN_ERR "radeonfb (%s): Cannot enable PCI device\n",
2156 info = framebuffer_alloc(sizeof(struct radeonfb_info), &pdev->dev);
2158 printk (KERN_ERR "radeonfb (%s): could not allocate memory\n",
2167 spin_lock_init(&rinfo->reg_lock);
2168 init_timer(&rinfo->lvds_timer);
2169 rinfo->lvds_timer.function = radeon_lvds_timer_func;
2170 rinfo->lvds_timer.data = (unsigned long)rinfo;
2172 strcpy(rinfo->name, "ATI Radeon XX ");
2173 rinfo->name[11] = ent->device >> 8;
2174 rinfo->name[12] = ent->device & 0xFF;
2175 rinfo->family = ent->driver_data & CHIP_FAMILY_MASK;
2176 rinfo->chipset = pdev->device;
2177 rinfo->has_CRTC2 = (ent->driver_data & CHIP_HAS_CRTC2) != 0;
2178 rinfo->is_mobility = (ent->driver_data & CHIP_IS_MOBILITY) != 0;
2179 rinfo->is_IGP = (ent->driver_data & CHIP_IS_IGP) != 0;
2181 /* Set base addrs */
2182 rinfo->fb_base_phys = pci_resource_start (pdev, 0);
2183 rinfo->mmio_base_phys = pci_resource_start (pdev, 2);
2185 /* request the mem regions */
2186 ret = pci_request_region(pdev, 0, "radeonfb framebuffer");
2188 printk( KERN_ERR "radeonfb (%s): cannot request region 0.\n",
2189 pci_name(rinfo->pdev));
2190 goto err_release_fb;
2193 ret = pci_request_region(pdev, 2, "radeonfb mmio");
2195 printk( KERN_ERR "radeonfb (%s): cannot request region 2.\n",
2196 pci_name(rinfo->pdev));
2197 goto err_release_pci0;
2200 /* map the regions */
2201 rinfo->mmio_base = ioremap(rinfo->mmio_base_phys, RADEON_REGSIZE);
2202 if (!rinfo->mmio_base) {
2203 printk(KERN_ERR "radeonfb (%s): cannot map MMIO\n",
2204 pci_name(rinfo->pdev));
2206 goto err_release_pci2;
2209 rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16;
2215 if (rinfo->family == CHIP_FAMILY_R300 &&
2216 (INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK)
2218 rinfo->errata |= CHIP_ERRATA_R300_CG;
2220 if (rinfo->family == CHIP_FAMILY_RV200 ||
2221 rinfo->family == CHIP_FAMILY_RS200)
2222 rinfo->errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2224 if (rinfo->family == CHIP_FAMILY_RV100 ||
2225 rinfo->family == CHIP_FAMILY_RS100 ||
2226 rinfo->family == CHIP_FAMILY_RS200)
2227 rinfo->errata |= CHIP_ERRATA_PLL_DELAY;
2229 #ifdef CONFIG_PPC_OF
2230 /* On PPC, we obtain the OF device-node pointer to the firmware
2231 * data for this chip
2233 rinfo->of_node = pci_device_to_OF_node(pdev);
2234 if (rinfo->of_node == NULL)
2235 printk(KERN_WARNING "radeonfb (%s): Cannot match card to OF node !\n",
2236 pci_name(rinfo->pdev));
2238 /* On PPC, the firmware sets up a memory mapping that tends
2239 * to cause lockups when enabling the engine. We reconfigure
2240 * the card internal memory mappings properly
2242 fixup_memory_mappings(rinfo);
2243 #endif /* CONFIG_PPC_OF */
2245 /* Get VRAM size and type */
2246 radeon_identify_vram(rinfo);
2248 rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM, rinfo->video_ram);
2251 rinfo->fb_base = ioremap (rinfo->fb_base_phys,
2252 rinfo->mapped_vram);
2253 } while ( rinfo->fb_base == 0 &&
2254 ((rinfo->mapped_vram /=2) >= MIN_MAPPED_VRAM) );
2256 if (rinfo->fb_base == NULL) {
2257 printk (KERN_ERR "radeonfb (%s): cannot map FB\n",
2258 pci_name(rinfo->pdev));
2263 RTRACE("radeonfb (%s): mapped %ldk videoram\n", pci_name(rinfo->pdev),
2264 rinfo->mapped_vram/1024);
2267 * Map the BIOS ROM if any and retrieve PLL parameters from
2268 * the BIOS. We skip that on mobility chips as the real panel
2269 * values we need aren't in the ROM but in the BIOS image in
2270 * memory. This is definitely not the best meacnism though,
2271 * we really need the arch code to tell us which is the "primary"
2272 * video adapter to use the memory image (or better, the arch
2273 * should provide us a copy of the BIOS image to shield us from
2274 * archs who would store that elsewhere and/or could initialize
2275 * more than one adapter during boot).
2277 if (!rinfo->is_mobility)
2278 radeon_map_ROM(rinfo, pdev);
2281 * On x86, the primary display on laptop may have it's BIOS
2282 * ROM elsewhere, try to locate it at the legacy memory hole.
2283 * We probably need to make sure this is the primary display,
2284 * but that is difficult without some arch support.
2287 if (rinfo->bios_seg == NULL)
2288 radeon_find_mem_vbios(rinfo);
2291 /* If both above failed, try the BIOS ROM again for mobility
2294 if (rinfo->bios_seg == NULL && rinfo->is_mobility)
2295 radeon_map_ROM(rinfo, pdev);
2297 /* Get informations about the board's PLL */
2298 radeon_get_pllinfo(rinfo);
2300 #ifdef CONFIG_FB_RADEON_I2C
2301 /* Register I2C bus */
2302 radeon_create_i2c_busses(rinfo);
2305 /* set all the vital stuff */
2306 radeon_set_fbinfo (rinfo);
2308 /* Probe screen types */
2309 radeon_probe_screens(rinfo, monitor_layout, ignore_edid);
2311 /* Build mode list, check out panel native model */
2312 radeon_check_modes(rinfo, mode_option);
2314 /* Register some sysfs stuff (should be done better) */
2315 if (rinfo->mon1_EDID)
2316 sysfs_create_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr);
2317 if (rinfo->mon2_EDID)
2318 sysfs_create_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr);
2320 /* save current mode regs before we switch into the new one
2321 * so we can restore this upon __exit
2323 radeon_save_state (rinfo, &rinfo->init_state);
2324 memcpy(&rinfo->state, &rinfo->init_state, sizeof(struct radeon_regs));
2326 /* Setup Power Management capabilities */
2327 if (default_dynclk < -1) {
2328 /* -2 is special: means ON on mobility chips and do not
2331 radeonfb_pm_init(rinfo, rinfo->is_mobility ? 1 : -1);
2333 radeonfb_pm_init(rinfo, default_dynclk);
2335 pci_set_drvdata(pdev, info);
2337 /* Register with fbdev layer */
2338 ret = register_framebuffer(info);
2340 printk (KERN_ERR "radeonfb (%s): could not register framebuffer\n",
2341 pci_name(rinfo->pdev));
2346 rinfo->mtrr_hdl = nomtrr ? -1 : mtrr_add(rinfo->fb_base_phys,
2348 MTRR_TYPE_WRCOMB, 1);
2351 radeonfb_bl_init(rinfo);
2353 printk ("radeonfb (%s): %s\n", pci_name(rinfo->pdev), rinfo->name);
2355 if (rinfo->bios_seg)
2356 radeon_unmap_ROM(rinfo, pdev);
2357 RTRACE("radeonfb_pci_register END\n");
2361 iounmap(rinfo->fb_base);
2363 kfree(rinfo->mon1_EDID);
2364 kfree(rinfo->mon2_EDID);
2365 if (rinfo->mon1_modedb)
2366 fb_destroy_modedb(rinfo->mon1_modedb);
2367 fb_dealloc_cmap(&info->cmap);
2368 #ifdef CONFIG_FB_RADEON_I2C
2369 radeon_delete_i2c_busses(rinfo);
2371 if (rinfo->bios_seg)
2372 radeon_unmap_ROM(rinfo, pdev);
2373 iounmap(rinfo->mmio_base);
2375 pci_release_region(pdev, 2);
2377 pci_release_region(pdev, 0);
2379 framebuffer_release(info);
2387 static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev)
2389 struct fb_info *info = pci_get_drvdata(pdev);
2390 struct radeonfb_info *rinfo = info->par;
2395 radeonfb_bl_exit(rinfo);
2396 radeonfb_pm_exit(rinfo);
2398 if (rinfo->mon1_EDID)
2399 sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr);
2400 if (rinfo->mon2_EDID)
2401 sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr);
2404 /* restore original state
2406 * Doesn't quite work yet, I suspect if we come from a legacy
2407 * VGA mode (or worse, text mode), we need to do some VGA black
2408 * magic here that I know nothing about. --BenH
2410 radeon_write_mode (rinfo, &rinfo->init_state, 1);
2413 del_timer_sync(&rinfo->lvds_timer);
2416 if (rinfo->mtrr_hdl >= 0)
2417 mtrr_del(rinfo->mtrr_hdl, 0, 0);
2420 unregister_framebuffer(info);
2422 iounmap(rinfo->mmio_base);
2423 iounmap(rinfo->fb_base);
2425 pci_release_region(pdev, 2);
2426 pci_release_region(pdev, 0);
2428 kfree(rinfo->mon1_EDID);
2429 kfree(rinfo->mon2_EDID);
2430 if (rinfo->mon1_modedb)
2431 fb_destroy_modedb(rinfo->mon1_modedb);
2432 #ifdef CONFIG_FB_RADEON_I2C
2433 radeon_delete_i2c_busses(rinfo);
2435 fb_dealloc_cmap(&info->cmap);
2436 framebuffer_release(info);
2440 static struct pci_driver radeonfb_driver = {
2442 .id_table = radeonfb_pci_table,
2443 .probe = radeonfb_pci_register,
2444 .remove = __devexit_p(radeonfb_pci_unregister),
2446 .suspend = radeonfb_pci_suspend,
2447 .resume = radeonfb_pci_resume,
2448 #endif /* CONFIG_PM */
2452 static int __init radeonfb_setup (char *options)
2456 if (!options || !*options)
2459 while ((this_opt = strsep (&options, ",")) != NULL) {
2463 if (!strncmp(this_opt, "noaccel", 7)) {
2465 } else if (!strncmp(this_opt, "mirror", 6)) {
2467 } else if (!strncmp(this_opt, "force_dfp", 9)) {
2469 } else if (!strncmp(this_opt, "panel_yres:", 11)) {
2470 panel_yres = simple_strtoul((this_opt+11), NULL, 0);
2472 } else if (!strncmp(this_opt, "nomtrr", 6)) {
2475 } else if (!strncmp(this_opt, "nomodeset", 9)) {
2477 } else if (!strncmp(this_opt, "force_measure_pll", 17)) {
2478 force_measure_pll = 1;
2479 } else if (!strncmp(this_opt, "ignore_edid", 11)) {
2482 mode_option = this_opt;
2488 static int __init radeonfb_init (void)
2491 char *option = NULL;
2493 if (fb_get_options("radeonfb", &option))
2495 radeonfb_setup(option);
2497 return pci_register_driver (&radeonfb_driver);
2501 static void __exit radeonfb_exit (void)
2503 pci_unregister_driver (&radeonfb_driver);
2506 module_init(radeonfb_init);
2507 module_exit(radeonfb_exit);
2509 MODULE_AUTHOR("Ani Joshi");
2510 MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset");
2511 MODULE_LICENSE("GPL");
2512 module_param(noaccel, bool, 0);
2513 module_param(default_dynclk, int, 0);
2514 MODULE_PARM_DESC(default_dynclk, "int: -2=enable on mobility only,-1=do not change,0=off,1=on");
2515 MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
2516 module_param(nomodeset, bool, 0);
2517 MODULE_PARM_DESC(nomodeset, "bool: disable actual setting of video mode");
2518 module_param(mirror, bool, 0);
2519 MODULE_PARM_DESC(mirror, "bool: mirror the display to both monitors");
2520 module_param(force_dfp, bool, 0);
2521 MODULE_PARM_DESC(force_dfp, "bool: force display to dfp");
2522 module_param(ignore_edid, bool, 0);
2523 MODULE_PARM_DESC(ignore_edid, "bool: Ignore EDID data when doing DDC probe");
2524 module_param(monitor_layout, charp, 0);
2525 MODULE_PARM_DESC(monitor_layout, "Specify monitor mapping (like XFree86)");
2526 module_param(force_measure_pll, bool, 0);
2527 MODULE_PARM_DESC(force_measure_pll, "Force measurement of PLL (debug)");
2529 module_param(nomtrr, bool, 0);
2530 MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
2532 module_param(panel_yres, int, 0);
2533 MODULE_PARM_DESC(panel_yres, "int: set panel yres");
2534 module_param(mode_option, charp, 0);
2535 MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
projects / linux-2.6 / blob