git.oblomov.eu Git - linux-2.6/blob - drivers/net/wireless/adm8211.c

   1
   2 /*
   3  * Linux device driver for ADMtek ADM8211 (IEEE 802.11b MAC/BBP)
   4  *
   5  * Copyright (c) 2003, Jouni Malinen <j@w1.fi>
   6  * Copyright (c) 2004-2007, Michael Wu <flamingice@sourmilk.net>
   7  * Some parts copyright (c) 2003 by David Young <dyoung@pobox.com>
   8  * and used with permission.
   9  *
  10  * Much thanks to Infineon-ADMtek for their support of this driver.
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation. See README and COPYING for
  15  * more details.
  16  */
  17
  18 #include <linux/init.h>
  19 #include <linux/if.h>
  20 #include <linux/skbuff.h>
  21 #include <linux/etherdevice.h>
  22 #include <linux/pci.h>
  23 #include <linux/delay.h>
  24 #include <linux/crc32.h>
  25 #include <linux/eeprom_93cx6.h>
  26 #include <net/mac80211.h>
  27
  28 #include "adm8211.h"
  29
  30 MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
  31 MODULE_AUTHOR("Jouni Malinen <j@w1.fi>");
  32 MODULE_DESCRIPTION("Driver for IEEE 802.11b wireless cards based on ADMtek ADM8211");
  33 MODULE_SUPPORTED_DEVICE("ADM8211");
  34 MODULE_LICENSE("GPL");
  35
  36 static unsigned int tx_ring_size __read_mostly = 16;
  37 static unsigned int rx_ring_size __read_mostly = 16;
  38
  39 module_param(tx_ring_size, uint, 0);
  40 module_param(rx_ring_size, uint, 0);
  41
  42 static struct pci_device_id adm8211_pci_id_table[] __devinitdata = {
  43         /* ADMtek ADM8211 */
  44         { PCI_DEVICE(0x10B7, 0x6000) }, /* 3Com 3CRSHPW796 */
  45         { PCI_DEVICE(0x1200, 0x8201) }, /* ? */
  46         { PCI_DEVICE(0x1317, 0x8201) }, /* ADM8211A */
  47         { PCI_DEVICE(0x1317, 0x8211) }, /* ADM8211B/C */
  48         { 0 }
  49 };
  50
  51 static struct ieee80211_rate adm8211_rates[] = {
  52         { .bitrate = 10, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
  53         { .bitrate = 20, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
  54         { .bitrate = 55, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
  55         { .bitrate = 110, .flags = IEEE80211_RATE_SHORT_PREAMBLE },
  56         { .bitrate = 220, .flags = IEEE80211_RATE_SHORT_PREAMBLE }, /* XX ?? */
  57 };
  58
  59 static const struct ieee80211_channel adm8211_channels[] = {
  60         { .center_freq = 2412},
  61         { .center_freq = 2417},
  62         { .center_freq = 2422},
  63         { .center_freq = 2427},
  64         { .center_freq = 2432},
  65         { .center_freq = 2437},
  66         { .center_freq = 2442},
  67         { .center_freq = 2447},
  68         { .center_freq = 2452},
  69         { .center_freq = 2457},
  70         { .center_freq = 2462},
  71         { .center_freq = 2467},
  72         { .center_freq = 2472},
  73         { .center_freq = 2484},
  74 };
  75
  76
  77 static void adm8211_eeprom_register_read(struct eeprom_93cx6 *eeprom)
  78 {
  79         struct adm8211_priv *priv = eeprom->data;
  80         u32 reg = ADM8211_CSR_READ(SPR);
  81
  82         eeprom->reg_data_in = reg & ADM8211_SPR_SDI;
  83         eeprom->reg_data_out = reg & ADM8211_SPR_SDO;
  84         eeprom->reg_data_clock = reg & ADM8211_SPR_SCLK;
  85         eeprom->reg_chip_select = reg & ADM8211_SPR_SCS;
  86 }
  87
  88 static void adm8211_eeprom_register_write(struct eeprom_93cx6 *eeprom)
  89 {
  90         struct adm8211_priv *priv = eeprom->data;
  91         u32 reg = 0x4000 | ADM8211_SPR_SRS;
  92
  93         if (eeprom->reg_data_in)
  94                 reg |= ADM8211_SPR_SDI;
  95         if (eeprom->reg_data_out)
  96                 reg |= ADM8211_SPR_SDO;
  97         if (eeprom->reg_data_clock)
  98                 reg |= ADM8211_SPR_SCLK;
  99         if (eeprom->reg_chip_select)
 100                 reg |= ADM8211_SPR_SCS;
 101
 102         ADM8211_CSR_WRITE(SPR, reg);
 103         ADM8211_CSR_READ(SPR);          /* eeprom_delay */
 104 }
 105
 106 static int adm8211_read_eeprom(struct ieee80211_hw *dev)
 107 {
 108         struct adm8211_priv *priv = dev->priv;
 109         unsigned int words, i;
 110         struct ieee80211_chan_range chan_range;
 111         u16 cr49;
 112         struct eeprom_93cx6 eeprom = {
 113                 .data           = priv,
 114                 .register_read  = adm8211_eeprom_register_read,
 115                 .register_write = adm8211_eeprom_register_write
 116         };
 117
 118         if (ADM8211_CSR_READ(CSR_TEST0) & ADM8211_CSR_TEST0_EPTYP) {
 119                 /* 256 * 16-bit = 512 bytes */
 120                 eeprom.width = PCI_EEPROM_WIDTH_93C66;
 121                 words = 256;
 122         } else {
 123                 /* 64 * 16-bit = 128 bytes */
 124                 eeprom.width = PCI_EEPROM_WIDTH_93C46;
 125                 words = 64;
 126         }
 127
 128         priv->eeprom_len = words * 2;
 129         priv->eeprom = kmalloc(priv->eeprom_len, GFP_KERNEL);
 130         if (!priv->eeprom)
 131                 return -ENOMEM;
 132
 133         eeprom_93cx6_multiread(&eeprom, 0, (__le16 *)priv->eeprom, words);
 134
 135         cr49 = le16_to_cpu(priv->eeprom->cr49);
 136         priv->rf_type = (cr49 >> 3) & 0x7;
 137         switch (priv->rf_type) {
 138         case ADM8211_TYPE_INTERSIL:
 139         case ADM8211_TYPE_RFMD:
 140         case ADM8211_TYPE_MARVEL:
 141         case ADM8211_TYPE_AIROHA:
 142         case ADM8211_TYPE_ADMTEK:
 143                 break;
 144
 145         default:
 146                 if (priv->pdev->revision < ADM8211_REV_CA)
 147                         priv->rf_type = ADM8211_TYPE_RFMD;
 148                 else
 149                         priv->rf_type = ADM8211_TYPE_AIROHA;
 150
 151                 printk(KERN_WARNING "%s (adm8211): Unknown RFtype %d\n",
 152                        pci_name(priv->pdev), (cr49 >> 3) & 0x7);
 153         }
 154
 155         priv->bbp_type = cr49 & 0x7;
 156         switch (priv->bbp_type) {
 157         case ADM8211_TYPE_INTERSIL:
 158         case ADM8211_TYPE_RFMD:
 159         case ADM8211_TYPE_MARVEL:
 160         case ADM8211_TYPE_AIROHA:
 161         case ADM8211_TYPE_ADMTEK:
 162                 break;
 163         default:
 164                 if (priv->pdev->revision < ADM8211_REV_CA)
 165                         priv->bbp_type = ADM8211_TYPE_RFMD;
 166                 else
 167                         priv->bbp_type = ADM8211_TYPE_ADMTEK;
 168
 169                 printk(KERN_WARNING "%s (adm8211): Unknown BBPtype: %d\n",
 170                        pci_name(priv->pdev), cr49 >> 3);
 171         }
 172
 173         if (priv->eeprom->country_code >= ARRAY_SIZE(cranges)) {
 174                 printk(KERN_WARNING "%s (adm8211): Invalid country code (%d)\n",
 175                        pci_name(priv->pdev), priv->eeprom->country_code);
 176
 177                 chan_range = cranges[2];
 178         } else
 179                 chan_range = cranges[priv->eeprom->country_code];
 180
 181         printk(KERN_DEBUG "%s (adm8211): Channel range: %d - %d\n",
 182                pci_name(priv->pdev), (int)chan_range.min, (int)chan_range.max);
 183
 184         BUILD_BUG_ON(sizeof(priv->channels) != sizeof(adm8211_channels));
 185
 186         memcpy(priv->channels, adm8211_channels, sizeof(priv->channels));
 187         priv->band.channels = priv->channels;
 188         priv->band.n_channels = ARRAY_SIZE(adm8211_channels);
 189         priv->band.bitrates = adm8211_rates;
 190         priv->band.n_bitrates = ARRAY_SIZE(adm8211_rates);
 191
 192         for (i = 1; i <= ARRAY_SIZE(adm8211_channels); i++)
 193                 if (i < chan_range.min || i > chan_range.max)
 194                         priv->channels[i - 1].flags |= IEEE80211_CHAN_DISABLED;
 195
 196         switch (priv->eeprom->specific_bbptype) {
 197         case ADM8211_BBP_RFMD3000:
 198         case ADM8211_BBP_RFMD3002:
 199         case ADM8211_BBP_ADM8011:
 200                 priv->specific_bbptype = priv->eeprom->specific_bbptype;
 201                 break;
 202
 203         default:
 204                 if (priv->pdev->revision < ADM8211_REV_CA)
 205                         priv->specific_bbptype = ADM8211_BBP_RFMD3000;
 206                 else
 207                         priv->specific_bbptype = ADM8211_BBP_ADM8011;
 208
 209                 printk(KERN_WARNING "%s (adm8211): Unknown specific BBP: %d\n",
 210                        pci_name(priv->pdev), priv->eeprom->specific_bbptype);
 211         }
 212
 213         switch (priv->eeprom->specific_rftype) {
 214         case ADM8211_RFMD2948:
 215         case ADM8211_RFMD2958:
 216         case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
 217         case ADM8211_MAX2820:
 218         case ADM8211_AL2210L:
 219                 priv->transceiver_type = priv->eeprom->specific_rftype;
 220                 break;
 221
 222         default:
 223                 if (priv->pdev->revision == ADM8211_REV_BA)
 224                         priv->transceiver_type = ADM8211_RFMD2958_RF3000_CONTROL_POWER;
 225                 else if (priv->pdev->revision == ADM8211_REV_CA)
 226                         priv->transceiver_type = ADM8211_AL2210L;
 227                 else if (priv->pdev->revision == ADM8211_REV_AB)
 228                         priv->transceiver_type = ADM8211_RFMD2948;
 229
 230                 printk(KERN_WARNING "%s (adm8211): Unknown transceiver: %d\n",
 231                        pci_name(priv->pdev), priv->eeprom->specific_rftype);
 232
 233                 break;
 234         }
 235
 236         printk(KERN_DEBUG "%s (adm8211): RFtype=%d BBPtype=%d Specific BBP=%d "
 237                "Transceiver=%d\n", pci_name(priv->pdev), priv->rf_type,
 238                priv->bbp_type, priv->specific_bbptype, priv->transceiver_type);
 239
 240         return 0;
 241 }
 242
 243 static inline void adm8211_write_sram(struct ieee80211_hw *dev,
 244                                       u32 addr, u32 data)
 245 {
 246         struct adm8211_priv *priv = dev->priv;
 247
 248         ADM8211_CSR_WRITE(WEPCTL, addr | ADM8211_WEPCTL_TABLE_WR |
 249                           (priv->pdev->revision < ADM8211_REV_BA ?
 250                            0 : ADM8211_WEPCTL_SEL_WEPTABLE ));
 251         ADM8211_CSR_READ(WEPCTL);
 252         msleep(1);
 253
 254         ADM8211_CSR_WRITE(WESK, data);
 255         ADM8211_CSR_READ(WESK);
 256         msleep(1);
 257 }
 258
 259 static void adm8211_write_sram_bytes(struct ieee80211_hw *dev,
 260                                      unsigned int addr, u8 *buf,
 261                                      unsigned int len)
 262 {
 263         struct adm8211_priv *priv = dev->priv;
 264         u32 reg = ADM8211_CSR_READ(WEPCTL);
 265         unsigned int i;
 266
 267         if (priv->pdev->revision < ADM8211_REV_BA) {
 268                 for (i = 0; i < len; i += 2) {
 269                         u16 val = buf[i] | (buf[i + 1] << 8);
 270                         adm8211_write_sram(dev, addr + i / 2, val);
 271                 }
 272         } else {
 273                 for (i = 0; i < len; i += 4) {
 274                         u32 val = (buf[i + 0] << 0 ) | (buf[i + 1] << 8 ) |
 275                                   (buf[i + 2] << 16) | (buf[i + 3] << 24);
 276                         adm8211_write_sram(dev, addr + i / 4, val);
 277                 }
 278         }
 279
 280         ADM8211_CSR_WRITE(WEPCTL, reg);
 281 }
 282
 283 static void adm8211_clear_sram(struct ieee80211_hw *dev)
 284 {
 285         struct adm8211_priv *priv = dev->priv;
 286         u32 reg = ADM8211_CSR_READ(WEPCTL);
 287         unsigned int addr;
 288
 289         for (addr = 0; addr < ADM8211_SRAM_SIZE; addr++)
 290                 adm8211_write_sram(dev, addr, 0);
 291
 292         ADM8211_CSR_WRITE(WEPCTL, reg);
 293 }
 294
 295 static int adm8211_get_stats(struct ieee80211_hw *dev,
 296                              struct ieee80211_low_level_stats *stats)
 297 {
 298         struct adm8211_priv *priv = dev->priv;
 299
 300         memcpy(stats, &priv->stats, sizeof(*stats));
 301
 302         return 0;
 303 }
 304
 305 static int adm8211_get_tx_stats(struct ieee80211_hw *dev,
 306                                 struct ieee80211_tx_queue_stats *stats)
 307 {
 308         struct adm8211_priv *priv = dev->priv;
 309
 310         stats[0].len = priv->cur_tx - priv->dirty_tx;
 311         stats[0].limit = priv->tx_ring_size - 2;
 312         stats[0].count = priv->dirty_tx;
 313
 314         return 0;
 315 }
 316
 317 static void adm8211_interrupt_tci(struct ieee80211_hw *dev)
 318 {
 319         struct adm8211_priv *priv = dev->priv;
 320         unsigned int dirty_tx;
 321
 322         spin_lock(&priv->lock);
 323
 324         for (dirty_tx = priv->dirty_tx; priv->cur_tx - dirty_tx; dirty_tx++) {
 325                 unsigned int entry = dirty_tx % priv->tx_ring_size;
 326                 u32 status = le32_to_cpu(priv->tx_ring[entry].status);
 327                 struct ieee80211_tx_status tx_status;
 328                 struct adm8211_tx_ring_info *info;
 329                 struct sk_buff *skb;
 330
 331                 if (status & TDES0_CONTROL_OWN ||
 332                     !(status & TDES0_CONTROL_DONE))
 333                         break;
 334
 335                 info = &priv->tx_buffers[entry];
 336                 skb = info->skb;
 337
 338                 /* TODO: check TDES0_STATUS_TUF and TDES0_STATUS_TRO */
 339
 340                 pci_unmap_single(priv->pdev, info->mapping,
 341                                  info->skb->len, PCI_DMA_TODEVICE);
 342
 343                 memset(&tx_status, 0, sizeof(tx_status));
 344                 skb_pull(skb, sizeof(struct adm8211_tx_hdr));
 345                 memcpy(skb_push(skb, info->hdrlen), skb->cb, info->hdrlen);
 346                 memcpy(&tx_status.control, &info->tx_control,
 347                        sizeof(tx_status.control));
 348                 if (!(tx_status.control.flags & IEEE80211_TXCTL_NO_ACK)) {
 349                         if (status & TDES0_STATUS_ES)
 350                                 tx_status.excessive_retries = 1;
 351                         else
 352                                 tx_status.flags |= IEEE80211_TX_STATUS_ACK;
 353                 }
 354                 ieee80211_tx_status_irqsafe(dev, skb, &tx_status);
 355
 356                 info->skb = NULL;
 357         }
 358
 359         if (priv->cur_tx - dirty_tx < priv->tx_ring_size - 2)
 360                 ieee80211_wake_queue(dev, 0);
 361
 362         priv->dirty_tx = dirty_tx;
 363         spin_unlock(&priv->lock);
 364 }
 365
 366
 367 static void adm8211_interrupt_rci(struct ieee80211_hw *dev)
 368 {
 369         struct adm8211_priv *priv = dev->priv;
 370         unsigned int entry = priv->cur_rx % priv->rx_ring_size;
 371         u32 status;
 372         unsigned int pktlen;
 373         struct sk_buff *skb, *newskb;
 374         unsigned int limit = priv->rx_ring_size;
 375         u8 rssi, rate;
 376
 377         while (!(priv->rx_ring[entry].status & cpu_to_le32(RDES0_STATUS_OWN))) {
 378                 if (!limit--)
 379                         break;
 380
 381                 status = le32_to_cpu(priv->rx_ring[entry].status);
 382                 rate = (status & RDES0_STATUS_RXDR) >> 12;
 383                 rssi = le32_to_cpu(priv->rx_ring[entry].length) &
 384                         RDES1_STATUS_RSSI;
 385
 386                 pktlen = status & RDES0_STATUS_FL;
 387                 if (pktlen > RX_PKT_SIZE) {
 388                         if (net_ratelimit())
 389                                 printk(KERN_DEBUG "%s: frame too long (%d)\n",
 390                                        wiphy_name(dev->wiphy), pktlen);
 391                         pktlen = RX_PKT_SIZE;
 392                 }
 393
 394                 if (!priv->soft_rx_crc && status & RDES0_STATUS_ES) {
 395                         skb = NULL; /* old buffer will be reused */
 396                         /* TODO: update RX error stats */
 397                         /* TODO: check RDES0_STATUS_CRC*E */
 398                 } else if (pktlen < RX_COPY_BREAK) {
 399                         skb = dev_alloc_skb(pktlen);
 400                         if (skb) {
 401                                 pci_dma_sync_single_for_cpu(
 402                                         priv->pdev,
 403                                         priv->rx_buffers[entry].mapping,
 404                                         pktlen, PCI_DMA_FROMDEVICE);
 405                                 memcpy(skb_put(skb, pktlen),
 406                                        skb_tail_pointer(priv->rx_buffers[entry].skb),
 407                                        pktlen);
 408                                 pci_dma_sync_single_for_device(
 409                                         priv->pdev,
 410                                         priv->rx_buffers[entry].mapping,
 411                                         RX_PKT_SIZE, PCI_DMA_FROMDEVICE);
 412                         }
 413                 } else {
 414                         newskb = dev_alloc_skb(RX_PKT_SIZE);
 415                         if (newskb) {
 416                                 skb = priv->rx_buffers[entry].skb;
 417                                 skb_put(skb, pktlen);
 418                                 pci_unmap_single(
 419                                         priv->pdev,
 420                                         priv->rx_buffers[entry].mapping,
 421                                         RX_PKT_SIZE, PCI_DMA_FROMDEVICE);
 422                                 priv->rx_buffers[entry].skb = newskb;
 423                                 priv->rx_buffers[entry].mapping =
 424                                         pci_map_single(priv->pdev,
 425                                                        skb_tail_pointer(newskb),
 426                                                        RX_PKT_SIZE,
 427                                                        PCI_DMA_FROMDEVICE);
 428                         } else {
 429                                 skb = NULL;
 430                                 /* TODO: update rx dropped stats */
 431                         }
 432
 433                         priv->rx_ring[entry].buffer1 =
 434                                 cpu_to_le32(priv->rx_buffers[entry].mapping);
 435                 }
 436
 437                 priv->rx_ring[entry].status = cpu_to_le32(RDES0_STATUS_OWN |
 438                                                           RDES0_STATUS_SQL);
 439                 priv->rx_ring[entry].length =
 440                         cpu_to_le32(RX_PKT_SIZE |
 441                                     (entry == priv->rx_ring_size - 1 ?
 442                                      RDES1_CONTROL_RER : 0));
 443
 444                 if (skb) {
 445                         struct ieee80211_rx_status rx_status = {0};
 446
 447                         if (priv->pdev->revision < ADM8211_REV_CA)
 448                                 rx_status.signal = rssi;
 449                         else
 450                                 rx_status.signal = 100 - rssi;
 451
 452                         rx_status.rate_idx = rate;
 453
 454                         rx_status.freq = adm8211_channels[priv->channel - 1].center_freq;
 455                         rx_status.band = IEEE80211_BAND_2GHZ;
 456
 457                         ieee80211_rx_irqsafe(dev, skb, &rx_status);
 458                 }
 459
 460                 entry = (++priv->cur_rx) % priv->rx_ring_size;
 461         }
 462
 463         /* TODO: check LPC and update stats? */
 464 }
 465
 466
 467 static irqreturn_t adm8211_interrupt(int irq, void *dev_id)
 468 {
 469 #define ADM8211_INT(x)                                                     \
 470 do {                                                                       \
 471         if (unlikely(stsr & ADM8211_STSR_ ## x))                           \
 472                 printk(KERN_DEBUG "%s: " #x "\n", wiphy_name(dev->wiphy)); \
 473 } while (0)
 474
 475         struct ieee80211_hw *dev = dev_id;
 476         struct adm8211_priv *priv = dev->priv;
 477         u32 stsr = ADM8211_CSR_READ(STSR);
 478         ADM8211_CSR_WRITE(STSR, stsr);
 479         if (stsr == 0xffffffff)
 480                 return IRQ_HANDLED;
 481
 482         if (!(stsr & (ADM8211_STSR_NISS | ADM8211_STSR_AISS)))
 483                 return IRQ_HANDLED;
 484
 485         if (stsr & ADM8211_STSR_RCI)
 486                 adm8211_interrupt_rci(dev);
 487         if (stsr & ADM8211_STSR_TCI)
 488                 adm8211_interrupt_tci(dev);
 489
 490         ADM8211_INT(PCF);
 491         ADM8211_INT(BCNTC);
 492         ADM8211_INT(GPINT);
 493         ADM8211_INT(ATIMTC);
 494         ADM8211_INT(TSFTF);
 495         ADM8211_INT(TSCZ);
 496         ADM8211_INT(SQL);
 497         ADM8211_INT(WEPTD);
 498         ADM8211_INT(ATIME);
 499         ADM8211_INT(TEIS);
 500         ADM8211_INT(FBE);
 501         ADM8211_INT(REIS);
 502         ADM8211_INT(GPTT);
 503         ADM8211_INT(RPS);
 504         ADM8211_INT(RDU);
 505         ADM8211_INT(TUF);
 506         ADM8211_INT(TPS);
 507
 508         return IRQ_HANDLED;
 509
 510 #undef ADM8211_INT
 511 }
 512
 513 #define WRITE_SYN(name,v_mask,v_shift,a_mask,a_shift,bits,prewrite,postwrite)\
 514 static void adm8211_rf_write_syn_ ## name (struct ieee80211_hw *dev,         \
 515                                            u16 addr, u32 value) {            \
 516         struct adm8211_priv *priv = dev->priv;                               \
 517         unsigned int i;                                                      \
 518         u32 reg, bitbuf;                                                     \
 519                                                                              \
 520         value &= v_mask;                                                     \
 521         addr &= a_mask;                                                      \
 522         bitbuf = (value << v_shift) | (addr << a_shift);                     \
 523                                                                              \
 524         ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_IF_SELECT_1);                 \
 525         ADM8211_CSR_READ(SYNRF);                                             \
 526         ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_IF_SELECT_0);                 \
 527         ADM8211_CSR_READ(SYNRF);                                             \
 528                                                                              \
 529         if (prewrite) {                                                      \
 530                 ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_WRITE_SYNDATA_0);     \
 531                 ADM8211_CSR_READ(SYNRF);                                     \
 532         }                                                                    \
 533                                                                              \
 534         for (i = 0; i <= bits; i++) {                                        \
 535                 if (bitbuf & (1 << (bits - i)))                              \
 536                         reg = ADM8211_SYNRF_WRITE_SYNDATA_1;                 \
 537                 else                                                         \
 538                         reg = ADM8211_SYNRF_WRITE_SYNDATA_0;                 \
 539                                                                              \
 540                 ADM8211_CSR_WRITE(SYNRF, reg);                               \
 541                 ADM8211_CSR_READ(SYNRF);                                     \
 542                                                                              \
 543                 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_WRITE_CLOCK_1); \
 544                 ADM8211_CSR_READ(SYNRF);                                     \
 545                 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_WRITE_CLOCK_0); \
 546                 ADM8211_CSR_READ(SYNRF);                                     \
 547         }                                                                    \
 548                                                                              \
 549         if (postwrite == 1) {                                                \
 550                 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_IF_SELECT_0);   \
 551                 ADM8211_CSR_READ(SYNRF);                                     \
 552         }                                                                    \
 553         if (postwrite == 2) {                                                \
 554                 ADM8211_CSR_WRITE(SYNRF, reg | ADM8211_SYNRF_IF_SELECT_1);   \
 555                 ADM8211_CSR_READ(SYNRF);                                     \
 556         }                                                                    \
 557                                                                              \
 558         ADM8211_CSR_WRITE(SYNRF, 0);                                         \
 559         ADM8211_CSR_READ(SYNRF);                                             \
 560 }
 561
 562 WRITE_SYN(max2820,  0x00FFF, 0, 0x0F, 12, 15, 1, 1)
 563 WRITE_SYN(al2210l,  0xFFFFF, 4, 0x0F,  0, 23, 1, 1)
 564 WRITE_SYN(rfmd2958, 0x3FFFF, 0, 0x1F, 18, 23, 0, 1)
 565 WRITE_SYN(rfmd2948, 0x0FFFF, 4, 0x0F,  0, 21, 0, 2)
 566
 567 #undef WRITE_SYN
 568
 569 static int adm8211_write_bbp(struct ieee80211_hw *dev, u8 addr, u8 data)
 570 {
 571         struct adm8211_priv *priv = dev->priv;
 572         unsigned int timeout;
 573         u32 reg;
 574
 575         timeout = 10;
 576         while (timeout > 0) {
 577                 reg = ADM8211_CSR_READ(BBPCTL);
 578                 if (!(reg & (ADM8211_BBPCTL_WR | ADM8211_BBPCTL_RD)))
 579                         break;
 580                 timeout--;
 581                 msleep(2);
 582         }
 583
 584         if (timeout == 0) {
 585                 printk(KERN_DEBUG "%s: adm8211_write_bbp(%d,%d) failed"
 586                        " prewrite (reg=0x%08x)\n",
 587                        wiphy_name(dev->wiphy), addr, data, reg);
 588                 return -ETIMEDOUT;
 589         }
 590
 591         switch (priv->bbp_type) {
 592         case ADM8211_TYPE_INTERSIL:
 593                 reg = ADM8211_BBPCTL_MMISEL;    /* three wire interface */
 594                 break;
 595         case ADM8211_TYPE_RFMD:
 596                 reg = (0x20 << 24) | ADM8211_BBPCTL_TXCE | ADM8211_BBPCTL_CCAP |
 597                       (0x01 << 18);
 598                 break;
 599         case ADM8211_TYPE_ADMTEK:
 600                 reg = (0x20 << 24) | ADM8211_BBPCTL_TXCE | ADM8211_BBPCTL_CCAP |
 601                       (0x05 << 18);
 602                 break;
 603         }
 604         reg |= ADM8211_BBPCTL_WR | (addr << 8) | data;
 605
 606         ADM8211_CSR_WRITE(BBPCTL, reg);
 607
 608         timeout = 10;
 609         while (timeout > 0) {
 610                 reg = ADM8211_CSR_READ(BBPCTL);
 611                 if (!(reg & ADM8211_BBPCTL_WR))
 612                         break;
 613                 timeout--;
 614                 msleep(2);
 615         }
 616
 617         if (timeout == 0) {
 618                 ADM8211_CSR_WRITE(BBPCTL, ADM8211_CSR_READ(BBPCTL) &
 619                                   ~ADM8211_BBPCTL_WR);
 620                 printk(KERN_DEBUG "%s: adm8211_write_bbp(%d,%d) failed"
 621                        " postwrite (reg=0x%08x)\n",
 622                        wiphy_name(dev->wiphy), addr, data, reg);
 623                 return -ETIMEDOUT;
 624         }
 625
 626         return 0;
 627 }
 628
 629 static int adm8211_rf_set_channel(struct ieee80211_hw *dev, unsigned int chan)
 630 {
 631         static const u32 adm8211_rfmd2958_reg5[] =
 632                 {0x22BD, 0x22D2, 0x22E8, 0x22FE, 0x2314, 0x232A, 0x2340,
 633                  0x2355, 0x236B, 0x2381, 0x2397, 0x23AD, 0x23C2, 0x23F7};
 634         static const u32 adm8211_rfmd2958_reg6[] =
 635                 {0x05D17, 0x3A2E8, 0x2E8BA, 0x22E8B, 0x1745D, 0x0BA2E, 0x00000,
 636                  0x345D1, 0x28BA2, 0x1D174, 0x11745, 0x05D17, 0x3A2E8, 0x11745};
 637
 638         struct adm8211_priv *priv = dev->priv;
 639         u8 ant_power = priv->ant_power > 0x3F ?
 640                 priv->eeprom->antenna_power[chan - 1] : priv->ant_power;
 641         u8 tx_power = priv->tx_power > 0x3F ?
 642                 priv->eeprom->tx_power[chan - 1] : priv->tx_power;
 643         u8 lpf_cutoff = priv->lpf_cutoff == 0xFF ?
 644                 priv->eeprom->lpf_cutoff[chan - 1] : priv->lpf_cutoff;
 645         u8 lnags_thresh = priv->lnags_threshold == 0xFF ?
 646                 priv->eeprom->lnags_threshold[chan - 1] : priv->lnags_threshold;
 647         u32 reg;
 648
 649         ADM8211_IDLE();
 650
 651         /* Program synthesizer to new channel */
 652         switch (priv->transceiver_type) {
 653         case ADM8211_RFMD2958:
 654         case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
 655                 adm8211_rf_write_syn_rfmd2958(dev, 0x00, 0x04007);
 656                 adm8211_rf_write_syn_rfmd2958(dev, 0x02, 0x00033);
 657
 658                 adm8211_rf_write_syn_rfmd2958(dev, 0x05,
 659                         adm8211_rfmd2958_reg5[chan - 1]);
 660                 adm8211_rf_write_syn_rfmd2958(dev, 0x06,
 661                         adm8211_rfmd2958_reg6[chan - 1]);
 662                 break;
 663
 664         case ADM8211_RFMD2948:
 665                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_MAIN_CONF,
 666                                               SI4126_MAIN_XINDIV2);
 667                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_POWERDOWN,
 668                                               SI4126_POWERDOWN_PDIB |
 669                                               SI4126_POWERDOWN_PDRB);
 670                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_PHASE_DET_GAIN, 0);
 671                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_RF2_N_DIV,
 672                                               (chan == 14 ?
 673                                                2110 : (2033 + (chan * 5))));
 674                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_IF_N_DIV, 1496);
 675                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_RF2_R_DIV, 44);
 676                 adm8211_rf_write_syn_rfmd2948(dev, SI4126_IF_R_DIV, 44);
 677                 break;
 678
 679         case ADM8211_MAX2820:
 680                 adm8211_rf_write_syn_max2820(dev, 0x3,
 681                         (chan == 14 ? 0x054 : (0x7 + (chan * 5))));
 682                 break;
 683
 684         case ADM8211_AL2210L:
 685                 adm8211_rf_write_syn_al2210l(dev, 0x0,
 686                         (chan == 14 ? 0x229B4 : (0x22967 + (chan * 5))));
 687                 break;
 688
 689         default:
 690                 printk(KERN_DEBUG "%s: unsupported transceiver type %d\n",
 691                        wiphy_name(dev->wiphy), priv->transceiver_type);
 692                 break;
 693         }
 694
 695         /* write BBP regs */
 696         if (priv->bbp_type == ADM8211_TYPE_RFMD) {
 697
 698         /* SMC 2635W specific? adm8211b doesn't use the 2948 though.. */
 699         /* TODO: remove if SMC 2635W doesn't need this */
 700         if (priv->transceiver_type == ADM8211_RFMD2948) {
 701                 reg = ADM8211_CSR_READ(GPIO);
 702                 reg &= 0xfffc0000;
 703                 reg |= ADM8211_CSR_GPIO_EN0;
 704                 if (chan != 14)
 705                         reg |= ADM8211_CSR_GPIO_O0;
 706                 ADM8211_CSR_WRITE(GPIO, reg);
 707         }
 708
 709         if (priv->transceiver_type == ADM8211_RFMD2958) {
 710                 /* set PCNT2 */
 711                 adm8211_rf_write_syn_rfmd2958(dev, 0x0B, 0x07100);
 712                 /* set PCNT1 P_DESIRED/MID_BIAS */
 713                 reg = le16_to_cpu(priv->eeprom->cr49);
 714                 reg >>= 13;
 715                 reg <<= 15;
 716                 reg |= ant_power << 9;
 717                 adm8211_rf_write_syn_rfmd2958(dev, 0x0A, reg);
 718                 /* set TXRX TX_GAIN */
 719                 adm8211_rf_write_syn_rfmd2958(dev, 0x09, 0x00050 |
 720                         (priv->pdev->revision < ADM8211_REV_CA ? tx_power : 0));
 721         } else {
 722                 reg = ADM8211_CSR_READ(PLCPHD);
 723                 reg &= 0xff00ffff;
 724                 reg |= tx_power << 18;
 725                 ADM8211_CSR_WRITE(PLCPHD, reg);
 726         }
 727
 728         ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_SELRF |
 729                           ADM8211_SYNRF_PE1 | ADM8211_SYNRF_PHYRST);
 730         ADM8211_CSR_READ(SYNRF);
 731         msleep(30);
 732
 733         /* RF3000 BBP */
 734         if (priv->transceiver_type != ADM8211_RFMD2958)
 735                 adm8211_write_bbp(dev, RF3000_TX_VAR_GAIN__TX_LEN_EXT,
 736                                   tx_power<<2);
 737         adm8211_write_bbp(dev, RF3000_LOW_GAIN_CALIB, lpf_cutoff);
 738         adm8211_write_bbp(dev, RF3000_HIGH_GAIN_CALIB, lnags_thresh);
 739         adm8211_write_bbp(dev, 0x1c, priv->pdev->revision == ADM8211_REV_BA ?
 740                                      priv->eeprom->cr28 : 0);
 741         adm8211_write_bbp(dev, 0x1d, priv->eeprom->cr29);
 742
 743         ADM8211_CSR_WRITE(SYNRF, 0);
 744
 745         /* Nothing to do for ADMtek BBP */
 746         } else if (priv->bbp_type != ADM8211_TYPE_ADMTEK)
 747                 printk(KERN_DEBUG "%s: unsupported BBP type %d\n",
 748                        wiphy_name(dev->wiphy), priv->bbp_type);
 749
 750         ADM8211_RESTORE();
 751
 752         /* update current channel for adhoc (and maybe AP mode) */
 753         reg = ADM8211_CSR_READ(CAP0);
 754         reg &= ~0xF;
 755         reg |= chan;
 756         ADM8211_CSR_WRITE(CAP0, reg);
 757
 758         return 0;
 759 }
 760
 761 static void adm8211_update_mode(struct ieee80211_hw *dev)
 762 {
 763         struct adm8211_priv *priv = dev->priv;
 764
 765         ADM8211_IDLE();
 766
 767         priv->soft_rx_crc = 0;
 768         switch (priv->mode) {
 769         case IEEE80211_IF_TYPE_STA:
 770                 priv->nar &= ~(ADM8211_NAR_PR | ADM8211_NAR_EA);
 771                 priv->nar |= ADM8211_NAR_ST | ADM8211_NAR_SR;
 772                 break;
 773         case IEEE80211_IF_TYPE_IBSS:
 774                 priv->nar &= ~ADM8211_NAR_PR;
 775                 priv->nar |= ADM8211_NAR_EA | ADM8211_NAR_ST | ADM8211_NAR_SR;
 776
 777                 /* don't trust the error bits on rev 0x20 and up in adhoc */
 778                 if (priv->pdev->revision >= ADM8211_REV_BA)
 779                         priv->soft_rx_crc = 1;
 780                 break;
 781         case IEEE80211_IF_TYPE_MNTR:
 782                 priv->nar &= ~(ADM8211_NAR_EA | ADM8211_NAR_ST);
 783                 priv->nar |= ADM8211_NAR_PR | ADM8211_NAR_SR;
 784                 break;
 785         }
 786
 787         ADM8211_RESTORE();
 788 }
 789
 790 static void adm8211_hw_init_syn(struct ieee80211_hw *dev)
 791 {
 792         struct adm8211_priv *priv = dev->priv;
 793
 794         switch (priv->transceiver_type) {
 795         case ADM8211_RFMD2958:
 796         case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
 797                 /* comments taken from ADMtek vendor driver */
 798
 799                 /* Reset RF2958 after power on */
 800                 adm8211_rf_write_syn_rfmd2958(dev, 0x1F, 0x00000);
 801                 /* Initialize RF VCO Core Bias to maximum */
 802                 adm8211_rf_write_syn_rfmd2958(dev, 0x0C, 0x3001F);
 803                 /* Initialize IF PLL */
 804                 adm8211_rf_write_syn_rfmd2958(dev, 0x01, 0x29C03);
 805                 /* Initialize IF PLL Coarse Tuning */
 806                 adm8211_rf_write_syn_rfmd2958(dev, 0x03, 0x1FF6F);
 807                 /* Initialize RF PLL */
 808                 adm8211_rf_write_syn_rfmd2958(dev, 0x04, 0x29403);
 809                 /* Initialize RF PLL Coarse Tuning */
 810                 adm8211_rf_write_syn_rfmd2958(dev, 0x07, 0x1456F);
 811                 /* Initialize TX gain and filter BW (R9) */
 812                 adm8211_rf_write_syn_rfmd2958(dev, 0x09,
 813                         (priv->transceiver_type == ADM8211_RFMD2958 ?
 814                          0x10050 : 0x00050));
 815                 /* Initialize CAL register */
 816                 adm8211_rf_write_syn_rfmd2958(dev, 0x08, 0x3FFF8);
 817                 break;
 818
 819         case ADM8211_MAX2820:
 820                 adm8211_rf_write_syn_max2820(dev, 0x1, 0x01E);
 821                 adm8211_rf_write_syn_max2820(dev, 0x2, 0x001);
 822                 adm8211_rf_write_syn_max2820(dev, 0x3, 0x054);
 823                 adm8211_rf_write_syn_max2820(dev, 0x4, 0x310);
 824                 adm8211_rf_write_syn_max2820(dev, 0x5, 0x000);
 825                 break;
 826
 827         case ADM8211_AL2210L:
 828                 adm8211_rf_write_syn_al2210l(dev, 0x0, 0x0196C);
 829                 adm8211_rf_write_syn_al2210l(dev, 0x1, 0x007CB);
 830                 adm8211_rf_write_syn_al2210l(dev, 0x2, 0x3582F);
 831                 adm8211_rf_write_syn_al2210l(dev, 0x3, 0x010A9);
 832                 adm8211_rf_write_syn_al2210l(dev, 0x4, 0x77280);
 833                 adm8211_rf_write_syn_al2210l(dev, 0x5, 0x45641);
 834                 adm8211_rf_write_syn_al2210l(dev, 0x6, 0xEA130);
 835                 adm8211_rf_write_syn_al2210l(dev, 0x7, 0x80000);
 836                 adm8211_rf_write_syn_al2210l(dev, 0x8, 0x7850F);
 837                 adm8211_rf_write_syn_al2210l(dev, 0x9, 0xF900C);
 838                 adm8211_rf_write_syn_al2210l(dev, 0xA, 0x00000);
 839                 adm8211_rf_write_syn_al2210l(dev, 0xB, 0x00000);
 840                 break;
 841
 842         case ADM8211_RFMD2948:
 843         default:
 844                 break;
 845         }
 846 }
 847
 848 static int adm8211_hw_init_bbp(struct ieee80211_hw *dev)
 849 {
 850         struct adm8211_priv *priv = dev->priv;
 851         u32 reg;
 852
 853         /* write addresses */
 854         if (priv->bbp_type == ADM8211_TYPE_INTERSIL) {
 855                 ADM8211_CSR_WRITE(MMIWA,  0x100E0C0A);
 856                 ADM8211_CSR_WRITE(MMIRD0, 0x00007C7E);
 857                 ADM8211_CSR_WRITE(MMIRD1, 0x00100000);
 858         } else if (priv->bbp_type == ADM8211_TYPE_RFMD ||
 859                    priv->bbp_type == ADM8211_TYPE_ADMTEK) {
 860                 /* check specific BBP type */
 861                 switch (priv->specific_bbptype) {
 862                 case ADM8211_BBP_RFMD3000:
 863                 case ADM8211_BBP_RFMD3002:
 864                         ADM8211_CSR_WRITE(MMIWA,  0x00009101);
 865                         ADM8211_CSR_WRITE(MMIRD0, 0x00000301);
 866                         break;
 867
 868                 case ADM8211_BBP_ADM8011:
 869                         ADM8211_CSR_WRITE(MMIWA,  0x00008903);
 870                         ADM8211_CSR_WRITE(MMIRD0, 0x00001716);
 871
 872                         reg = ADM8211_CSR_READ(BBPCTL);
 873                         reg &= ~ADM8211_BBPCTL_TYPE;
 874                         reg |= 0x5 << 18;
 875                         ADM8211_CSR_WRITE(BBPCTL, reg);
 876                         break;
 877                 }
 878
 879                 switch (priv->pdev->revision) {
 880                 case ADM8211_REV_CA:
 881                         if (priv->transceiver_type == ADM8211_RFMD2958 ||
 882                             priv->transceiver_type == ADM8211_RFMD2958_RF3000_CONTROL_POWER ||
 883                             priv->transceiver_type == ADM8211_RFMD2948)
 884                                 ADM8211_CSR_WRITE(SYNCTL, 0x1 << 22);
 885                         else if (priv->transceiver_type == ADM8211_MAX2820 ||
 886                                  priv->transceiver_type == ADM8211_AL2210L)
 887                                 ADM8211_CSR_WRITE(SYNCTL, 0x3 << 22);
 888                         break;
 889
 890                 case ADM8211_REV_BA:
 891                         reg  = ADM8211_CSR_READ(MMIRD1);
 892                         reg &= 0x0000FFFF;
 893                         reg |= 0x7e100000;
 894                         ADM8211_CSR_WRITE(MMIRD1, reg);
 895                         break;
 896
 897                 case ADM8211_REV_AB:
 898                 case ADM8211_REV_AF:
 899                 default:
 900                         ADM8211_CSR_WRITE(MMIRD1, 0x7e100000);
 901                         break;
 902                 }
 903
 904                 /* For RFMD */
 905                 ADM8211_CSR_WRITE(MACTEST, 0x800);
 906         }
 907
 908         adm8211_hw_init_syn(dev);
 909
 910         /* Set RF Power control IF pin to PE1+PHYRST# */
 911         ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_SELRF |
 912                           ADM8211_SYNRF_PE1 | ADM8211_SYNRF_PHYRST);
 913         ADM8211_CSR_READ(SYNRF);
 914         msleep(20);
 915
 916         /* write BBP regs */
 917         if (priv->bbp_type == ADM8211_TYPE_RFMD) {
 918                 /* RF3000 BBP */
 919                 /* another set:
 920                  * 11: c8
 921                  * 14: 14
 922                  * 15: 50 (chan 1..13; chan 14: d0)
 923                  * 1c: 00
 924                  * 1d: 84
 925                  */
 926                 adm8211_write_bbp(dev, RF3000_CCA_CTRL, 0x80);
 927                 /* antenna selection: diversity */
 928                 adm8211_write_bbp(dev, RF3000_DIVERSITY__RSSI, 0x80);
 929                 adm8211_write_bbp(dev, RF3000_TX_VAR_GAIN__TX_LEN_EXT, 0x74);
 930                 adm8211_write_bbp(dev, RF3000_LOW_GAIN_CALIB, 0x38);
 931                 adm8211_write_bbp(dev, RF3000_HIGH_GAIN_CALIB, 0x40);
 932
 933                 if (priv->eeprom->major_version < 2) {
 934                         adm8211_write_bbp(dev, 0x1c, 0x00);
 935                         adm8211_write_bbp(dev, 0x1d, 0x80);
 936                 } else {
 937                         if (priv->pdev->revision == ADM8211_REV_BA)
 938                                 adm8211_write_bbp(dev, 0x1c, priv->eeprom->cr28);
 939                         else
 940                                 adm8211_write_bbp(dev, 0x1c, 0x00);
 941
 942                         adm8211_write_bbp(dev, 0x1d, priv->eeprom->cr29);
 943                 }
 944         } else if (priv->bbp_type == ADM8211_TYPE_ADMTEK) {
 945                 /* reset baseband */
 946                 adm8211_write_bbp(dev, 0x00, 0xFF);
 947                 /* antenna selection: diversity */
 948                 adm8211_write_bbp(dev, 0x07, 0x0A);
 949
 950                 /* TODO: find documentation for this */
 951                 switch (priv->transceiver_type) {
 952                 case ADM8211_RFMD2958:
 953                 case ADM8211_RFMD2958_RF3000_CONTROL_POWER:
 954                         adm8211_write_bbp(dev, 0x00, 0x00);
 955                         adm8211_write_bbp(dev, 0x01, 0x00);
 956                         adm8211_write_bbp(dev, 0x02, 0x00);
 957                         adm8211_write_bbp(dev, 0x03, 0x00);
 958                         adm8211_write_bbp(dev, 0x06, 0x0f);
 959                         adm8211_write_bbp(dev, 0x09, 0x00);
 960                         adm8211_write_bbp(dev, 0x0a, 0x00);
 961                         adm8211_write_bbp(dev, 0x0b, 0x00);
 962                         adm8211_write_bbp(dev, 0x0c, 0x00);
 963                         adm8211_write_bbp(dev, 0x0f, 0xAA);
 964                         adm8211_write_bbp(dev, 0x10, 0x8c);
 965                         adm8211_write_bbp(dev, 0x11, 0x43);
 966                         adm8211_write_bbp(dev, 0x18, 0x40);
 967                         adm8211_write_bbp(dev, 0x20, 0x23);
 968                         adm8211_write_bbp(dev, 0x21, 0x02);
 969                         adm8211_write_bbp(dev, 0x22, 0x28);
 970                         adm8211_write_bbp(dev, 0x23, 0x30);
 971                         adm8211_write_bbp(dev, 0x24, 0x2d);
 972                         adm8211_write_bbp(dev, 0x28, 0x35);
 973                         adm8211_write_bbp(dev, 0x2a, 0x8c);
 974                         adm8211_write_bbp(dev, 0x2b, 0x81);
 975                         adm8211_write_bbp(dev, 0x2c, 0x44);
 976                         adm8211_write_bbp(dev, 0x2d, 0x0A);
 977                         adm8211_write_bbp(dev, 0x29, 0x40);
 978                         adm8211_write_bbp(dev, 0x60, 0x08);
 979                         adm8211_write_bbp(dev, 0x64, 0x01);
 980                         break;
 981
 982                 case ADM8211_MAX2820:
 983                         adm8211_write_bbp(dev, 0x00, 0x00);
 984                         adm8211_write_bbp(dev, 0x01, 0x00);
 985                         adm8211_write_bbp(dev, 0x02, 0x00);
 986                         adm8211_write_bbp(dev, 0x03, 0x00);
 987                         adm8211_write_bbp(dev, 0x06, 0x0f);
 988                         adm8211_write_bbp(dev, 0x09, 0x05);
 989                         adm8211_write_bbp(dev, 0x0a, 0x02);
 990                         adm8211_write_bbp(dev, 0x0b, 0x00);
 991                         adm8211_write_bbp(dev, 0x0c, 0x0f);
 992                         adm8211_write_bbp(dev, 0x0f, 0x55);
 993                         adm8211_write_bbp(dev, 0x10, 0x8d);
 994                         adm8211_write_bbp(dev, 0x11, 0x43);
 995                         adm8211_write_bbp(dev, 0x18, 0x4a);
 996                         adm8211_write_bbp(dev, 0x20, 0x20);
 997                         adm8211_write_bbp(dev, 0x21, 0x02);
 998                         adm8211_write_bbp(dev, 0x22, 0x23);
 999                         adm8211_write_bbp(dev, 0x23, 0x30);
1000                         adm8211_write_bbp(dev, 0x24, 0x2d);
1001                         adm8211_write_bbp(dev, 0x2a, 0x8c);
1002                         adm8211_write_bbp(dev, 0x2b, 0x81);
1003                         adm8211_write_bbp(dev, 0x2c, 0x44);
1004                         adm8211_write_bbp(dev, 0x29, 0x4a);
1005                         adm8211_write_bbp(dev, 0x60, 0x2b);
1006                         adm8211_write_bbp(dev, 0x64, 0x01);
1007                         break;
1008
1009                 case ADM8211_AL2210L:
1010                         adm8211_write_bbp(dev, 0x00, 0x00);
1011                         adm8211_write_bbp(dev, 0x01, 0x00);
1012                         adm8211_write_bbp(dev, 0x02, 0x00);
1013                         adm8211_write_bbp(dev, 0x03, 0x00);
1014                         adm8211_write_bbp(dev, 0x06, 0x0f);
1015                         adm8211_write_bbp(dev, 0x07, 0x05);
1016                         adm8211_write_bbp(dev, 0x08, 0x03);
1017                         adm8211_write_bbp(dev, 0x09, 0x00);
1018                         adm8211_write_bbp(dev, 0x0a, 0x00);
1019                         adm8211_write_bbp(dev, 0x0b, 0x00);
1020                         adm8211_write_bbp(dev, 0x0c, 0x10);
1021                         adm8211_write_bbp(dev, 0x0f, 0x55);
1022                         adm8211_write_bbp(dev, 0x10, 0x8d);
1023                         adm8211_write_bbp(dev, 0x11, 0x43);
1024                         adm8211_write_bbp(dev, 0x18, 0x4a);
1025                         adm8211_write_bbp(dev, 0x20, 0x20);
1026                         adm8211_write_bbp(dev, 0x21, 0x02);
1027                         adm8211_write_bbp(dev, 0x22, 0x23);
1028                         adm8211_write_bbp(dev, 0x23, 0x30);
1029                         adm8211_write_bbp(dev, 0x24, 0x2d);
1030                         adm8211_write_bbp(dev, 0x2a, 0xaa);
1031                         adm8211_write_bbp(dev, 0x2b, 0x81);
1032                         adm8211_write_bbp(dev, 0x2c, 0x44);
1033                         adm8211_write_bbp(dev, 0x29, 0xfa);
1034                         adm8211_write_bbp(dev, 0x60, 0x2d);
1035                         adm8211_write_bbp(dev, 0x64, 0x01);
1036                         break;
1037
1038                 case ADM8211_RFMD2948:
1039                         break;
1040
1041                 default:
1042                         printk(KERN_DEBUG "%s: unsupported transceiver %d\n",
1043                                wiphy_name(dev->wiphy), priv->transceiver_type);
1044                         break;
1045                 }
1046         } else
1047                 printk(KERN_DEBUG "%s: unsupported BBP %d\n",
1048                        wiphy_name(dev->wiphy), priv->bbp_type);
1049
1050         ADM8211_CSR_WRITE(SYNRF, 0);
1051
1052         /* Set RF CAL control source to MAC control */
1053         reg = ADM8211_CSR_READ(SYNCTL);
1054         reg |= ADM8211_SYNCTL_SELCAL;
1055         ADM8211_CSR_WRITE(SYNCTL, reg);
1056
1057         return 0;
1058 }
1059
1060 /* configures hw beacons/probe responses */
1061 static int adm8211_set_rate(struct ieee80211_hw *dev)
1062 {
1063         struct adm8211_priv *priv = dev->priv;
1064         u32 reg;
1065         int i = 0;
1066         u8 rate_buf[12] = {0};
1067
1068         /* write supported rates */
1069         if (priv->pdev->revision != ADM8211_REV_BA) {
1070                 rate_buf[0] = ARRAY_SIZE(adm8211_rates);
1071                 for (i = 0; i < ARRAY_SIZE(adm8211_rates); i++)
1072                         rate_buf[i + 1] = (adm8211_rates[i].bitrate / 5) | 0x80;
1073         } else {
1074                 /* workaround for rev BA specific bug */
1075                 rate_buf[0] = 0x04;
1076                 rate_buf[1] = 0x82;
1077                 rate_buf[2] = 0x04;
1078                 rate_buf[3] = 0x0b;
1079                 rate_buf[4] = 0x16;
1080         }
1081
1082         adm8211_write_sram_bytes(dev, ADM8211_SRAM_SUPP_RATE, rate_buf,
1083                                  ARRAY_SIZE(adm8211_rates) + 1);
1084
1085         reg = ADM8211_CSR_READ(PLCPHD) & 0x00FFFFFF; /* keep bits 0-23 */
1086         reg |= 1 << 15; /* short preamble */
1087         reg |= 110 << 24;
1088         ADM8211_CSR_WRITE(PLCPHD, reg);
1089
1090         /* MTMLT   = 512 TU (max TX MSDU lifetime)
1091          * BCNTSIG = plcp_signal (beacon, probe resp, and atim TX rate)
1092          * SRTYLIM = 224 (short retry limit, TX header value is default) */
1093         ADM8211_CSR_WRITE(TXLMT, (512 << 16) | (110 << 8) | (224 << 0));
1094
1095         return 0;
1096 }
1097
1098 static void adm8211_hw_init(struct ieee80211_hw *dev)
1099 {
1100         struct adm8211_priv *priv = dev->priv;
1101         u32 reg;
1102         u8 cline;
1103
1104         reg = ADM8211_CSR_READ(PAR);
1105         reg |= ADM8211_PAR_MRLE | ADM8211_PAR_MRME;
1106         reg &= ~(ADM8211_PAR_BAR | ADM8211_PAR_CAL);
1107
1108         if (!pci_set_mwi(priv->pdev)) {
1109                 reg |= 0x1 << 24;
1110                 pci_read_config_byte(priv->pdev, PCI_CACHE_LINE_SIZE, &cline);
1111
1112                 switch (cline) {
1113                 case  0x8: reg |= (0x1 << 14);
1114                            break;
1115                 case 0x16: reg |= (0x2 << 14);
1116                            break;
1117                 case 0x32: reg |= (0x3 << 14);
1118                            break;
1119                   default: reg |= (0x0 << 14);
1120                            break;
1121                 }
1122         }
1123
1124         ADM8211_CSR_WRITE(PAR, reg);
1125
1126         reg = ADM8211_CSR_READ(CSR_TEST1);
1127         reg &= ~(0xF << 28);
1128         reg |= (1 << 28) | (1 << 31);
1129         ADM8211_CSR_WRITE(CSR_TEST1, reg);
1130
1131         /* lose link after 4 lost beacons */
1132         reg = (0x04 << 21) | ADM8211_WCSR_TSFTWE | ADM8211_WCSR_LSOE;
1133         ADM8211_CSR_WRITE(WCSR, reg);
1134
1135         /* Disable APM, enable receive FIFO threshold, and set drain receive
1136          * threshold to store-and-forward */
1137         reg = ADM8211_CSR_READ(CMDR);
1138         reg &= ~(ADM8211_CMDR_APM | ADM8211_CMDR_DRT);
1139         reg |= ADM8211_CMDR_RTE | ADM8211_CMDR_DRT_SF;
1140         ADM8211_CSR_WRITE(CMDR, reg);
1141
1142         adm8211_set_rate(dev);
1143
1144         /* 4-bit values:
1145          * PWR1UP   = 8 * 2 ms
1146          * PWR0PAPE = 8 us or 5 us
1147          * PWR1PAPE = 1 us or 3 us
1148          * PWR0TRSW = 5 us
1149          * PWR1TRSW = 12 us
1150          * PWR0PE2  = 13 us
1151          * PWR1PE2  = 1 us
1152          * PWR0TXPE = 8 or 6 */
1153         if (priv->pdev->revision < ADM8211_REV_CA)
1154                 ADM8211_CSR_WRITE(TOFS2, 0x8815cd18);
1155         else
1156                 ADM8211_CSR_WRITE(TOFS2, 0x8535cd16);
1157
1158         /* Enable store and forward for transmit */
1159         priv->nar = ADM8211_NAR_SF | ADM8211_NAR_PB;
1160         ADM8211_CSR_WRITE(NAR, priv->nar);
1161
1162         /* Reset RF */
1163         ADM8211_CSR_WRITE(SYNRF, ADM8211_SYNRF_RADIO);
1164         ADM8211_CSR_READ(SYNRF);
1165         msleep(10);
1166         ADM8211_CSR_WRITE(SYNRF, 0);
1167         ADM8211_CSR_READ(SYNRF);
1168         msleep(5);
1169
1170         /* Set CFP Max Duration to 0x10 TU */
1171         reg = ADM8211_CSR_READ(CFPP);
1172         reg &= ~(0xffff << 8);
1173         reg |= 0x0010 << 8;
1174         ADM8211_CSR_WRITE(CFPP, reg);
1175
1176         /* USCNT = 0x16 (number of system clocks, 22 MHz, in 1us
1177          * TUCNT = 0x3ff - Tu counter 1024 us  */
1178         ADM8211_CSR_WRITE(TOFS0, (0x16 << 24) | 0x3ff);
1179
1180         /* SLOT=20 us, SIFS=110 cycles of 22 MHz (5 us),
1181          * DIFS=50 us, EIFS=100 us */
1182         if (priv->pdev->revision < ADM8211_REV_CA)
1183                 ADM8211_CSR_WRITE(IFST, (20 << 23) | (110 << 15) |
1184                                         (50 << 9)  | 100);
1185         else
1186                 ADM8211_CSR_WRITE(IFST, (20 << 23) | (24 << 15) |
1187                                         (50 << 9)  | 100);
1188
1189         /* PCNT = 1 (MAC idle time awake/sleep, unit S)
1190          * RMRD = 2346 * 8 + 1 us (max RX duration)  */
1191         ADM8211_CSR_WRITE(RMD, (1 << 16) | 18769);
1192
1193         /* MART=65535 us, MIRT=256 us, TSFTOFST=0 us */
1194         ADM8211_CSR_WRITE(RSPT, 0xffffff00);
1195
1196         /* Initialize BBP (and SYN) */
1197         adm8211_hw_init_bbp(dev);
1198
1199         /* make sure interrupts are off */
1200         ADM8211_CSR_WRITE(IER, 0);
1201
1202         /* ACK interrupts */
1203         ADM8211_CSR_WRITE(STSR, ADM8211_CSR_READ(STSR));
1204
1205         /* Setup WEP (turns it off for now) */
1206         reg = ADM8211_CSR_READ(MACTEST);
1207         reg &= ~(7 << 20);
1208         ADM8211_CSR_WRITE(MACTEST, reg);
1209
1210         reg = ADM8211_CSR_READ(WEPCTL);
1211         reg &= ~ADM8211_WEPCTL_WEPENABLE;
1212         reg |= ADM8211_WEPCTL_WEPRXBYP;
1213         ADM8211_CSR_WRITE(WEPCTL, reg);
1214
1215         /* Clear the missed-packet counter. */
1216         ADM8211_CSR_READ(LPC);
1217 }
1218
1219 static int adm8211_hw_reset(struct ieee80211_hw *dev)
1220 {
1221         struct adm8211_priv *priv = dev->priv;
1222         u32 reg, tmp;
1223         int timeout = 100;
1224
1225         /* Power-on issue */
1226         /* TODO: check if this is necessary */
1227         ADM8211_CSR_WRITE(FRCTL, 0);
1228
1229         /* Reset the chip */
1230         tmp = ADM8211_CSR_READ(PAR);
1231         ADM8211_CSR_WRITE(PAR, ADM8211_PAR_SWR);
1232
1233         while ((ADM8211_CSR_READ(PAR) & ADM8211_PAR_SWR) && timeout--)
1234                 msleep(50);
1235
1236         if (timeout <= 0)
1237                 return -ETIMEDOUT;
1238
1239         ADM8211_CSR_WRITE(PAR, tmp);
1240
1241         if (priv->pdev->revision == ADM8211_REV_BA &&
1242             (priv->transceiver_type == ADM8211_RFMD2958_RF3000_CONTROL_POWER ||
1243              priv->transceiver_type == ADM8211_RFMD2958)) {
1244                 reg = ADM8211_CSR_READ(CSR_TEST1);
1245                 reg |= (1 << 4) | (1 << 5);
1246                 ADM8211_CSR_WRITE(CSR_TEST1, reg);
1247         } else if (priv->pdev->revision == ADM8211_REV_CA) {
1248                 reg = ADM8211_CSR_READ(CSR_TEST1);
1249                 reg &= ~((1 << 4) | (1 << 5));
1250                 ADM8211_CSR_WRITE(CSR_TEST1, reg);
1251         }
1252
1253         ADM8211_CSR_WRITE(FRCTL, 0);
1254
1255         reg = ADM8211_CSR_READ(CSR_TEST0);
1256         reg |= ADM8211_CSR_TEST0_EPRLD; /* EEPROM Recall */
1257         ADM8211_CSR_WRITE(CSR_TEST0, reg);
1258
1259         adm8211_clear_sram(dev);
1260
1261         return 0;
1262 }
1263
1264 static u64 adm8211_get_tsft(struct ieee80211_hw *dev)
1265 {
1266         struct adm8211_priv *priv = dev->priv;
1267         u32 tsftl;
1268         u64 tsft;
1269
1270         tsftl = ADM8211_CSR_READ(TSFTL);
1271         tsft = ADM8211_CSR_READ(TSFTH);
1272         tsft <<= 32;
1273         tsft |= tsftl;
1274
1275         return tsft;
1276 }
1277
1278 static void adm8211_set_interval(struct ieee80211_hw *dev,
1279                                  unsigned short bi, unsigned short li)
1280 {
1281         struct adm8211_priv *priv = dev->priv;
1282         u32 reg;
1283
1284         /* BP (beacon interval) = data->beacon_interval
1285          * LI (listen interval) = data->listen_interval (in beacon intervals) */
1286         reg = (bi << 16) | li;
1287         ADM8211_CSR_WRITE(BPLI, reg);
1288 }
1289
1290 static void adm8211_set_bssid(struct ieee80211_hw *dev, const u8 *bssid)
1291 {
1292         struct adm8211_priv *priv = dev->priv;
1293         u32 reg;
1294
1295         ADM8211_CSR_WRITE(BSSID0, le32_to_cpu(*(__le32 *)bssid));
1296         reg = ADM8211_CSR_READ(ABDA1);
1297         reg &= 0x0000ffff;
1298         reg |= (bssid[4] << 16) | (bssid[5] << 24);
1299         ADM8211_CSR_WRITE(ABDA1, reg);
1300 }
1301
1302 static int adm8211_set_ssid(struct ieee80211_hw *dev, u8 *ssid, size_t ssid_len)
1303 {
1304         struct adm8211_priv *priv = dev->priv;
1305         u8 buf[36];
1306
1307         if (ssid_len > 32)
1308                 return -EINVAL;
1309
1310         memset(buf, 0, sizeof(buf));
1311         buf[0] = ssid_len;
1312         memcpy(buf + 1, ssid, ssid_len);
1313         adm8211_write_sram_bytes(dev, ADM8211_SRAM_SSID, buf, 33);
1314         /* TODO: configure beacon for adhoc? */
1315         return 0;
1316 }
1317
1318 static int adm8211_config(struct ieee80211_hw *dev, struct ieee80211_conf *conf)
1319 {
1320         struct adm8211_priv *priv = dev->priv;
1321         int channel = ieee80211_frequency_to_channel(conf->channel->center_freq);
1322
1323         if (channel != priv->channel) {
1324                 priv->channel = channel;
1325                 adm8211_rf_set_channel(dev, priv->channel);
1326         }
1327
1328         return 0;
1329 }
1330
1331 static int adm8211_config_interface(struct ieee80211_hw *dev,
1332                                     struct ieee80211_vif *vif,
1333                                     struct ieee80211_if_conf *conf)
1334 {
1335         struct adm8211_priv *priv = dev->priv;
1336
1337         if (memcmp(conf->bssid, priv->bssid, ETH_ALEN)) {
1338                 adm8211_set_bssid(dev, conf->bssid);
1339                 memcpy(priv->bssid, conf->bssid, ETH_ALEN);
1340         }
1341
1342         if (conf->ssid_len != priv->ssid_len ||
1343             memcmp(conf->ssid, priv->ssid, conf->ssid_len)) {
1344                 adm8211_set_ssid(dev, conf->ssid, conf->ssid_len);
1345                 priv->ssid_len = conf->ssid_len;
1346                 memcpy(priv->ssid, conf->ssid, conf->ssid_len);
1347         }
1348
1349         return 0;
1350 }
1351
1352 static void adm8211_configure_filter(struct ieee80211_hw *dev,
1353                                      unsigned int changed_flags,
1354                                      unsigned int *total_flags,
1355                                      int mc_count, struct dev_mc_list *mclist)
1356 {
1357         static const u8 bcast[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
1358         struct adm8211_priv *priv = dev->priv;
1359         unsigned int bit_nr, new_flags;
1360         u32 mc_filter[2];
1361         int i;
1362
1363         new_flags = 0;
1364
1365         if (*total_flags & FIF_PROMISC_IN_BSS) {
1366                 new_flags |= FIF_PROMISC_IN_BSS;
1367                 priv->nar |= ADM8211_NAR_PR;
1368                 priv->nar &= ~ADM8211_NAR_MM;
1369                 mc_filter[1] = mc_filter[0] = ~0;
1370         } else if ((*total_flags & FIF_ALLMULTI) || (mc_count > 32)) {
1371                 new_flags |= FIF_ALLMULTI;
1372                 priv->nar &= ~ADM8211_NAR_PR;
1373                 priv->nar |= ADM8211_NAR_MM;
1374                 mc_filter[1] = mc_filter[0] = ~0;
1375         } else {
1376                 priv->nar &= ~(ADM8211_NAR_MM | ADM8211_NAR_PR);
1377                 mc_filter[1] = mc_filter[0] = 0;
1378                 for (i = 0; i < mc_count; i++) {
1379                         if (!mclist)
1380                                 break;
1381                         bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
1382
1383                         bit_nr &= 0x3F;
1384                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1385                         mclist = mclist->next;
1386                 }
1387         }
1388
1389         ADM8211_IDLE_RX();
1390
1391         ADM8211_CSR_WRITE(MAR0, mc_filter[0]);
1392         ADM8211_CSR_WRITE(MAR1, mc_filter[1]);
1393         ADM8211_CSR_READ(NAR);
1394
1395         if (priv->nar & ADM8211_NAR_PR)
1396                 dev->flags |= IEEE80211_HW_RX_INCLUDES_FCS;
1397         else
1398                 dev->flags &= ~IEEE80211_HW_RX_INCLUDES_FCS;
1399
1400         if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
1401                 adm8211_set_bssid(dev, bcast);
1402         else
1403                 adm8211_set_bssid(dev, priv->bssid);
1404
1405         ADM8211_RESTORE();
1406
1407         *total_flags = new_flags;
1408 }
1409
1410 static int adm8211_add_interface(struct ieee80211_hw *dev,
1411                                  struct ieee80211_if_init_conf *conf)
1412 {
1413         struct adm8211_priv *priv = dev->priv;
1414         if (priv->mode != IEEE80211_IF_TYPE_MNTR)
1415                 return -EOPNOTSUPP;
1416
1417         switch (conf->type) {
1418         case IEEE80211_IF_TYPE_STA:
1419                 priv->mode = conf->type;
1420                 break;
1421         default:
1422                 return -EOPNOTSUPP;
1423         }
1424
1425         ADM8211_IDLE();
1426
1427         ADM8211_CSR_WRITE(PAR0, le32_to_cpu(*(__le32 *)conf->mac_addr));
1428         ADM8211_CSR_WRITE(PAR1, le16_to_cpu(*(__le16 *)(conf->mac_addr + 4)));
1429
1430         adm8211_update_mode(dev);
1431
1432         ADM8211_RESTORE();
1433
1434         return 0;
1435 }
1436
1437 static void adm8211_remove_interface(struct ieee80211_hw *dev,
1438                                      struct ieee80211_if_init_conf *conf)
1439 {
1440         struct adm8211_priv *priv = dev->priv;
1441         priv->mode = IEEE80211_IF_TYPE_MNTR;
1442 }
1443
1444 static int adm8211_init_rings(struct ieee80211_hw *dev)
1445 {
1446         struct adm8211_priv *priv = dev->priv;
1447         struct adm8211_desc *desc = NULL;
1448         struct adm8211_rx_ring_info *rx_info;
1449         struct adm8211_tx_ring_info *tx_info;
1450         unsigned int i;
1451
1452         for (i = 0; i < priv->rx_ring_size; i++) {
1453                 desc = &priv->rx_ring[i];
1454                 desc->status = 0;
1455                 desc->length = cpu_to_le32(RX_PKT_SIZE);
1456                 priv->rx_buffers[i].skb = NULL;
1457         }
1458         /* Mark the end of RX ring; hw returns to base address after this
1459          * descriptor */
1460         desc->length |= cpu_to_le32(RDES1_CONTROL_RER);
1461
1462         for (i = 0; i < priv->rx_ring_size; i++) {
1463                 desc = &priv->rx_ring[i];
1464                 rx_info = &priv->rx_buffers[i];
1465
1466                 rx_info->skb = dev_alloc_skb(RX_PKT_SIZE);
1467                 if (rx_info->skb == NULL)
1468                         break;
1469                 rx_info->mapping = pci_map_single(priv->pdev,
1470                                                   skb_tail_pointer(rx_info->skb),
1471                                                   RX_PKT_SIZE,
1472                                                   PCI_DMA_FROMDEVICE);
1473                 desc->buffer1 = cpu_to_le32(rx_info->mapping);
1474                 desc->status = cpu_to_le32(RDES0_STATUS_OWN | RDES0_STATUS_SQL);
1475         }
1476
1477         /* Setup TX ring. TX buffers descriptors will be filled in as needed */
1478         for (i = 0; i < priv->tx_ring_size; i++) {
1479                 desc = &priv->tx_ring[i];
1480                 tx_info = &priv->tx_buffers[i];
1481
1482                 tx_info->skb = NULL;
1483                 tx_info->mapping = 0;
1484                 desc->status = 0;
1485         }
1486         desc->length = cpu_to_le32(TDES1_CONTROL_TER);
1487
1488         priv->cur_rx = priv->cur_tx = priv->dirty_tx = 0;
1489         ADM8211_CSR_WRITE(RDB, priv->rx_ring_dma);
1490         ADM8211_CSR_WRITE(TDBD, priv->tx_ring_dma);
1491
1492         return 0;
1493 }
1494
1495 static void adm8211_free_rings(struct ieee80211_hw *dev)
1496 {
1497         struct adm8211_priv *priv = dev->priv;
1498         unsigned int i;
1499
1500         for (i = 0; i < priv->rx_ring_size; i++) {
1501                 if (!priv->rx_buffers[i].skb)
1502                         continue;
1503
1504                 pci_unmap_single(
1505                         priv->pdev,
1506                         priv->rx_buffers[i].mapping,
1507                         RX_PKT_SIZE, PCI_DMA_FROMDEVICE);
1508
1509                 dev_kfree_skb(priv->rx_buffers[i].skb);
1510         }
1511
1512         for (i = 0; i < priv->tx_ring_size; i++) {
1513                 if (!priv->tx_buffers[i].skb)
1514                         continue;
1515
1516                 pci_unmap_single(priv->pdev,
1517                                  priv->tx_buffers[i].mapping,
1518                                  priv->tx_buffers[i].skb->len,
1519                                  PCI_DMA_TODEVICE);
1520
1521                 dev_kfree_skb(priv->tx_buffers[i].skb);
1522         }
1523 }
1524
1525 static int adm8211_start(struct ieee80211_hw *dev)
1526 {
1527         struct adm8211_priv *priv = dev->priv;
1528         int retval;
1529
1530         /* Power up MAC and RF chips */
1531         retval = adm8211_hw_reset(dev);
1532         if (retval) {
1533                 printk(KERN_ERR "%s: hardware reset failed\n",
1534                        wiphy_name(dev->wiphy));
1535                 goto fail;
1536         }
1537
1538         retval = adm8211_init_rings(dev);
1539         if (retval) {
1540                 printk(KERN_ERR "%s: failed to initialize rings\n",
1541                        wiphy_name(dev->wiphy));
1542                 goto fail;
1543         }
1544
1545         /* Init hardware */
1546         adm8211_hw_init(dev);
1547         adm8211_rf_set_channel(dev, priv->channel);
1548
1549         retval = request_irq(priv->pdev->irq, &adm8211_interrupt,
1550                              IRQF_SHARED, "adm8211", dev);
1551         if (retval) {
1552                 printk(KERN_ERR "%s: failed to register IRQ handler\n",
1553                        wiphy_name(dev->wiphy));
1554                 goto fail;
1555         }
1556
1557         ADM8211_CSR_WRITE(IER, ADM8211_IER_NIE | ADM8211_IER_AIE |
1558                                ADM8211_IER_RCIE | ADM8211_IER_TCIE |
1559                                ADM8211_IER_TDUIE | ADM8211_IER_GPTIE);
1560         priv->mode = IEEE80211_IF_TYPE_MNTR;
1561         adm8211_update_mode(dev);
1562         ADM8211_CSR_WRITE(RDR, 0);
1563
1564         adm8211_set_interval(dev, 100, 10);
1565         return 0;
1566
1567 fail:
1568         return retval;
1569 }
1570
1571 static void adm8211_stop(struct ieee80211_hw *dev)
1572 {
1573         struct adm8211_priv *priv = dev->priv;
1574
1575         priv->mode = IEEE80211_IF_TYPE_INVALID;
1576         priv->nar = 0;
1577         ADM8211_CSR_WRITE(NAR, 0);
1578         ADM8211_CSR_WRITE(IER, 0);
1579         ADM8211_CSR_READ(NAR);
1580
1581         free_irq(priv->pdev->irq, dev);
1582
1583         adm8211_free_rings(dev);
1584 }
1585
1586 static void adm8211_calc_durations(int *dur, int *plcp, size_t payload_len, int len,
1587                                    int plcp_signal, int short_preamble)
1588 {
1589         /* Alternative calculation from NetBSD: */
1590
1591 /* IEEE 802.11b durations for DSSS PHY in microseconds */
1592 #define IEEE80211_DUR_DS_LONG_PREAMBLE  144
1593 #define IEEE80211_DUR_DS_SHORT_PREAMBLE 72
1594 #define IEEE80211_DUR_DS_FAST_PLCPHDR   24
1595 #define IEEE80211_DUR_DS_SLOW_PLCPHDR   48
1596 #define IEEE80211_DUR_DS_SLOW_ACK       112
1597 #define IEEE80211_DUR_DS_FAST_ACK       56
1598 #define IEEE80211_DUR_DS_SLOW_CTS       112
1599 #define IEEE80211_DUR_DS_FAST_CTS       56
1600 #define IEEE80211_DUR_DS_SLOT           20
1601 #define IEEE80211_DUR_DS_SIFS           10
1602
1603         int remainder;
1604
1605         *dur = (80 * (24 + payload_len) + plcp_signal - 1)
1606                 / plcp_signal;
1607
1608         if (plcp_signal <= PLCP_SIGNAL_2M)
1609                 /* 1-2Mbps WLAN: send ACK/CTS at 1Mbps */
1610                 *dur += 3 * (IEEE80211_DUR_DS_SIFS +
1611                              IEEE80211_DUR_DS_SHORT_PREAMBLE +
1612                              IEEE80211_DUR_DS_FAST_PLCPHDR) +
1613                              IEEE80211_DUR_DS_SLOW_CTS + IEEE80211_DUR_DS_SLOW_ACK;
1614         else
1615                 /* 5-11Mbps WLAN: send ACK/CTS at 2Mbps */
1616                 *dur += 3 * (IEEE80211_DUR_DS_SIFS +
1617                              IEEE80211_DUR_DS_SHORT_PREAMBLE +
1618                              IEEE80211_DUR_DS_FAST_PLCPHDR) +
1619                              IEEE80211_DUR_DS_FAST_CTS + IEEE80211_DUR_DS_FAST_ACK;
1620
1621         /* lengthen duration if long preamble */
1622         if (!short_preamble)
1623                 *dur += 3 * (IEEE80211_DUR_DS_LONG_PREAMBLE -
1624                              IEEE80211_DUR_DS_SHORT_PREAMBLE) +
1625                         3 * (IEEE80211_DUR_DS_SLOW_PLCPHDR -
1626                              IEEE80211_DUR_DS_FAST_PLCPHDR);
1627
1628
1629         *plcp = (80 * len) / plcp_signal;
1630         remainder = (80 * len) % plcp_signal;
1631         if (plcp_signal == PLCP_SIGNAL_11M &&
1632             remainder <= 30 && remainder > 0)
1633                 *plcp = (*plcp | 0x8000) + 1;
1634         else if (remainder)
1635                 (*plcp)++;
1636 }
1637
1638 /* Transmit skb w/adm8211_tx_hdr (802.11 header created by hardware) */
1639 static void adm8211_tx_raw(struct ieee80211_hw *dev, struct sk_buff *skb,
1640                            u16 plcp_signal,
1641                            struct ieee80211_tx_control *control,
1642                            size_t hdrlen)
1643 {
1644         struct adm8211_priv *priv = dev->priv;
1645         unsigned long flags;
1646         dma_addr_t mapping;
1647         unsigned int entry;
1648         u32 flag;
1649
1650         mapping = pci_map_single(priv->pdev, skb->data, skb->len,
1651                                  PCI_DMA_TODEVICE);
1652
1653         spin_lock_irqsave(&priv->lock, flags);
1654
1655         if (priv->cur_tx - priv->dirty_tx == priv->tx_ring_size / 2)
1656                 flag = TDES1_CONTROL_IC | TDES1_CONTROL_LS | TDES1_CONTROL_FS;
1657         else
1658                 flag = TDES1_CONTROL_LS | TDES1_CONTROL_FS;
1659
1660         if (priv->cur_tx - priv->dirty_tx == priv->tx_ring_size - 2)
1661                 ieee80211_stop_queue(dev, 0);
1662
1663         entry = priv->cur_tx % priv->tx_ring_size;
1664
1665         priv->tx_buffers[entry].skb = skb;
1666         priv->tx_buffers[entry].mapping = mapping;
1667         memcpy(&priv->tx_buffers[entry].tx_control, control, sizeof(*control));
1668         priv->tx_buffers[entry].hdrlen = hdrlen;
1669         priv->tx_ring[entry].buffer1 = cpu_to_le32(mapping);
1670
1671         if (entry == priv->tx_ring_size - 1)
1672                 flag |= TDES1_CONTROL_TER;
1673         priv->tx_ring[entry].length = cpu_to_le32(flag | skb->len);
1674
1675         /* Set TX rate (SIGNAL field in PLCP PPDU format) */
1676         flag = TDES0_CONTROL_OWN | (plcp_signal << 20) | 8 /* ? */;
1677         priv->tx_ring[entry].status = cpu_to_le32(flag);
1678
1679         priv->cur_tx++;
1680
1681         spin_unlock_irqrestore(&priv->lock, flags);
1682
1683         /* Trigger transmit poll */
1684         ADM8211_CSR_WRITE(TDR, 0);
1685 }
1686
1687 /* Put adm8211_tx_hdr on skb and transmit */
1688 static int adm8211_tx(struct ieee80211_hw *dev, struct sk_buff *skb,
1689                       struct ieee80211_tx_control *control)
1690 {
1691         struct adm8211_tx_hdr *txhdr;
1692         u16 fc;
1693         size_t payload_len, hdrlen;
1694         int plcp, dur, len, plcp_signal, short_preamble;
1695         struct ieee80211_hdr *hdr;
1696
1697         short_preamble = !!(control->tx_rate->flags &
1698                                         IEEE80211_TXCTL_SHORT_PREAMBLE);
1699         plcp_signal = control->tx_rate->bitrate;
1700
1701         hdr = (struct ieee80211_hdr *)skb->data;
1702         fc = le16_to_cpu(hdr->frame_control) & ~IEEE80211_FCTL_PROTECTED;
1703         hdrlen = ieee80211_get_hdrlen(fc);
1704         memcpy(skb->cb, skb->data, hdrlen);
1705         hdr = (struct ieee80211_hdr *)skb->cb;
1706         skb_pull(skb, hdrlen);
1707         payload_len = skb->len;
1708
1709         txhdr = (struct adm8211_tx_hdr *) skb_push(skb, sizeof(*txhdr));
1710         memset(txhdr, 0, sizeof(*txhdr));
1711         memcpy(txhdr->da, ieee80211_get_DA(hdr), ETH_ALEN);
1712         txhdr->signal = plcp_signal;
1713         txhdr->frame_body_size = cpu_to_le16(payload_len);
1714         txhdr->frame_control = hdr->frame_control;
1715
1716         len = hdrlen + payload_len + FCS_LEN;
1717         if (fc & IEEE80211_FCTL_PROTECTED)
1718                 len += 8;
1719
1720         txhdr->frag = cpu_to_le16(0x0FFF);
1721         adm8211_calc_durations(&dur, &plcp, payload_len,
1722                                len, plcp_signal, short_preamble);
1723         txhdr->plcp_frag_head_len = cpu_to_le16(plcp);
1724         txhdr->plcp_frag_tail_len = cpu_to_le16(plcp);
1725         txhdr->dur_frag_head = cpu_to_le16(dur);
1726         txhdr->dur_frag_tail = cpu_to_le16(dur);
1727
1728         txhdr->header_control = cpu_to_le16(ADM8211_TXHDRCTL_ENABLE_EXTEND_HEADER);
1729
1730         if (short_preamble)
1731                 txhdr->header_control |= cpu_to_le16(ADM8211_TXHDRCTL_SHORT_PREAMBLE);
1732
1733         if (control->flags & IEEE80211_TXCTL_USE_RTS_CTS)
1734                 txhdr->header_control |= cpu_to_le16(ADM8211_TXHDRCTL_ENABLE_RTS);
1735
1736         if (fc & IEEE80211_FCTL_PROTECTED)
1737                 txhdr->header_control |= cpu_to_le16(ADM8211_TXHDRCTL_ENABLE_WEP_ENGINE);
1738
1739         txhdr->retry_limit = control->retry_limit;
1740
1741         adm8211_tx_raw(dev, skb, plcp_signal, control, hdrlen);
1742
1743         return NETDEV_TX_OK;
1744 }
1745
1746 static int adm8211_alloc_rings(struct ieee80211_hw *dev)
1747 {
1748         struct adm8211_priv *priv = dev->priv;
1749         unsigned int ring_size;
1750
1751         priv->rx_buffers = kmalloc(sizeof(*priv->rx_buffers) * priv->rx_ring_size +
1752                                    sizeof(*priv->tx_buffers) * priv->tx_ring_size, GFP_KERNEL);
1753         if (!priv->rx_buffers)
1754                 return -ENOMEM;
1755
1756         priv->tx_buffers = (void *)priv->rx_buffers +
1757                            sizeof(*priv->rx_buffers) * priv->rx_ring_size;
1758
1759         /* Allocate TX/RX descriptors */
1760         ring_size = sizeof(struct adm8211_desc) * priv->rx_ring_size +
1761                     sizeof(struct adm8211_desc) * priv->tx_ring_size;
1762         priv->rx_ring = pci_alloc_consistent(priv->pdev, ring_size,
1763                                              &priv->rx_ring_dma);
1764
1765         if (!priv->rx_ring) {
1766                 kfree(priv->rx_buffers);
1767                 priv->rx_buffers = NULL;
1768                 priv->tx_buffers = NULL;
1769                 return -ENOMEM;
1770         }
1771
1772         priv->tx_ring = (struct adm8211_desc *)(priv->rx_ring +
1773                                                 priv->rx_ring_size);
1774         priv->tx_ring_dma = priv->rx_ring_dma +
1775                             sizeof(struct adm8211_desc) * priv->rx_ring_size;
1776
1777         return 0;
1778 }
1779
1780 static const struct ieee80211_ops adm8211_ops = {
1781         .tx                     = adm8211_tx,
1782         .start                  = adm8211_start,
1783         .stop                   = adm8211_stop,
1784         .add_interface          = adm8211_add_interface,
1785         .remove_interface       = adm8211_remove_interface,
1786         .config                 = adm8211_config,
1787         .config_interface       = adm8211_config_interface,
1788         .configure_filter       = adm8211_configure_filter,
1789         .get_stats              = adm8211_get_stats,
1790         .get_tx_stats           = adm8211_get_tx_stats,
1791         .get_tsf                = adm8211_get_tsft
1792 };
1793
1794 static int __devinit adm8211_probe(struct pci_dev *pdev,
1795                                    const struct pci_device_id *id)
1796 {
1797         struct ieee80211_hw *dev;
1798         struct adm8211_priv *priv;
1799         unsigned long mem_addr, mem_len;
1800         unsigned int io_addr, io_len;
1801         int err;
1802         u32 reg;
1803         u8 perm_addr[ETH_ALEN];
1804         DECLARE_MAC_BUF(mac);
1805
1806         err = pci_enable_device(pdev);
1807         if (err) {
1808                 printk(KERN_ERR "%s (adm8211): Cannot enable new PCI device\n",
1809                        pci_name(pdev));
1810                 return err;
1811         }
1812
1813         io_addr = pci_resource_start(pdev, 0);
1814         io_len = pci_resource_len(pdev, 0);
1815         mem_addr = pci_resource_start(pdev, 1);
1816         mem_len = pci_resource_len(pdev, 1);
1817         if (io_len < 256 || mem_len < 1024) {
1818                 printk(KERN_ERR "%s (adm8211): Too short PCI resources\n",
1819                        pci_name(pdev));
1820                 goto err_disable_pdev;
1821         }
1822
1823
1824         /* check signature */
1825         pci_read_config_dword(pdev, 0x80 /* CR32 */, &reg);
1826         if (reg != ADM8211_SIG1 && reg != ADM8211_SIG2) {
1827                 printk(KERN_ERR "%s (adm8211): Invalid signature (0x%x)\n",
1828                        pci_name(pdev), reg);
1829                 goto err_disable_pdev;
1830         }
1831
1832         err = pci_request_regions(pdev, "adm8211");
1833         if (err) {
1834                 printk(KERN_ERR "%s (adm8211): Cannot obtain PCI resources\n",
1835                        pci_name(pdev));
1836                 return err; /* someone else grabbed it? don't disable it */
1837         }
1838
1839         if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) ||
1840             pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) {
1841                 printk(KERN_ERR "%s (adm8211): No suitable DMA available\n",
1842                        pci_name(pdev));
1843                 goto err_free_reg;
1844         }
1845
1846         pci_set_master(pdev);
1847
1848         dev = ieee80211_alloc_hw(sizeof(*priv), &adm8211_ops);
1849         if (!dev) {
1850                 printk(KERN_ERR "%s (adm8211): ieee80211 alloc failed\n",
1851                        pci_name(pdev));
1852                 err = -ENOMEM;
1853                 goto err_free_reg;
1854         }
1855         priv = dev->priv;
1856         priv->pdev = pdev;
1857
1858         spin_lock_init(&priv->lock);
1859
1860         SET_IEEE80211_DEV(dev, &pdev->dev);
1861
1862         pci_set_drvdata(pdev, dev);
1863
1864         priv->map = pci_iomap(pdev, 1, mem_len);
1865         if (!priv->map)
1866                 priv->map = pci_iomap(pdev, 0, io_len);
1867
1868         if (!priv->map) {
1869                 printk(KERN_ERR "%s (adm8211): Cannot map device memory\n",
1870                        pci_name(pdev));
1871                 goto err_free_dev;
1872         }
1873
1874         priv->rx_ring_size = rx_ring_size;
1875         priv->tx_ring_size = tx_ring_size;
1876
1877         if (adm8211_alloc_rings(dev)) {
1878                 printk(KERN_ERR "%s (adm8211): Cannot allocate TX/RX ring\n",
1879                        pci_name(pdev));
1880                 goto err_iounmap;
1881         }
1882
1883         *(__le32 *)perm_addr = cpu_to_le32(ADM8211_CSR_READ(PAR0));
1884         *(__le16 *)&perm_addr[4] =
1885                 cpu_to_le16(ADM8211_CSR_READ(PAR1) & 0xFFFF);
1886
1887         if (!is_valid_ether_addr(perm_addr)) {
1888                 printk(KERN_WARNING "%s (adm8211): Invalid hwaddr in EEPROM!\n",
1889                        pci_name(pdev));
1890                 random_ether_addr(perm_addr);
1891         }
1892         SET_IEEE80211_PERM_ADDR(dev, perm_addr);
1893
1894         dev->extra_tx_headroom = sizeof(struct adm8211_tx_hdr);
1895         /* dev->flags = IEEE80211_HW_RX_INCLUDES_FCS in promisc mode */
1896         dev->flags = IEEE80211_HW_SIGNAL_UNSPEC;
1897
1898         dev->channel_change_time = 1000;
1899         dev->max_signal = 100;    /* FIXME: find better value */
1900
1901         dev->queues = 1; /* ADM8211C supports more, maybe ADM8211B too */
1902
1903         priv->retry_limit = 3;
1904         priv->ant_power = 0x40;
1905         priv->tx_power = 0x40;
1906         priv->lpf_cutoff = 0xFF;
1907         priv->lnags_threshold = 0xFF;
1908         priv->mode = IEEE80211_IF_TYPE_INVALID;
1909
1910         /* Power-on issue. EEPROM won't read correctly without */
1911         if (pdev->revision >= ADM8211_REV_BA) {
1912                 ADM8211_CSR_WRITE(FRCTL, 0);
1913                 ADM8211_CSR_READ(FRCTL);
1914                 ADM8211_CSR_WRITE(FRCTL, 1);
1915                 ADM8211_CSR_READ(FRCTL);
1916                 msleep(100);
1917         }
1918
1919         err = adm8211_read_eeprom(dev);
1920         if (err) {
1921                 printk(KERN_ERR "%s (adm8211): Can't alloc eeprom buffer\n",
1922                        pci_name(pdev));
1923                 goto err_free_desc;
1924         }
1925
1926         priv->channel = 1;
1927
1928         dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
1929
1930         err = ieee80211_register_hw(dev);
1931         if (err) {
1932                 printk(KERN_ERR "%s (adm8211): Cannot register device\n",
1933                        pci_name(pdev));
1934                 goto err_free_desc;
1935         }
1936
1937         printk(KERN_INFO "%s: hwaddr %s, Rev 0x%02x\n",
1938                wiphy_name(dev->wiphy), print_mac(mac, dev->wiphy->perm_addr),
1939                pdev->revision);
1940
1941         return 0;
1942
1943  err_free_desc:
1944         pci_free_consistent(pdev,
1945                             sizeof(struct adm8211_desc) * priv->rx_ring_size +
1946                             sizeof(struct adm8211_desc) * priv->tx_ring_size,
1947                             priv->rx_ring, priv->rx_ring_dma);
1948         kfree(priv->rx_buffers);
1949
1950  err_iounmap:
1951         pci_iounmap(pdev, priv->map);
1952
1953  err_free_dev:
1954         pci_set_drvdata(pdev, NULL);
1955         ieee80211_free_hw(dev);
1956
1957  err_free_reg:
1958         pci_release_regions(pdev);
1959
1960  err_disable_pdev:
1961         pci_disable_device(pdev);
1962         return err;
1963 }
1964
1965
1966 static void __devexit adm8211_remove(struct pci_dev *pdev)
1967 {
1968         struct ieee80211_hw *dev = pci_get_drvdata(pdev);
1969         struct adm8211_priv *priv;
1970
1971         if (!dev)
1972                 return;
1973
1974         ieee80211_unregister_hw(dev);
1975
1976         priv = dev->priv;
1977
1978         pci_free_consistent(pdev,
1979                             sizeof(struct adm8211_desc) * priv->rx_ring_size +
1980                             sizeof(struct adm8211_desc) * priv->tx_ring_size,
1981                             priv->rx_ring, priv->rx_ring_dma);
1982
1983         kfree(priv->rx_buffers);
1984         kfree(priv->eeprom);
1985         pci_iounmap(pdev, priv->map);
1986         pci_release_regions(pdev);
1987         pci_disable_device(pdev);
1988         ieee80211_free_hw(dev);
1989 }
1990
1991
1992 #ifdef CONFIG_PM
1993 static int adm8211_suspend(struct pci_dev *pdev, pm_message_t state)
1994 {
1995         struct ieee80211_hw *dev = pci_get_drvdata(pdev);
1996         struct adm8211_priv *priv = dev->priv;
1997
1998         if (priv->mode != IEEE80211_IF_TYPE_INVALID) {
1999                 ieee80211_stop_queues(dev);
2000                 adm8211_stop(dev);
2001         }
2002
2003         pci_save_state(pdev);
2004         pci_set_power_state(pdev, pci_choose_state(pdev, state));
2005         return 0;
2006 }
2007
2008 static int adm8211_resume(struct pci_dev *pdev)
2009 {
2010         struct ieee80211_hw *dev = pci_get_drvdata(pdev);
2011         struct adm8211_priv *priv = dev->priv;
2012
2013         pci_set_power_state(pdev, PCI_D0);
2014         pci_restore_state(pdev);
2015
2016         if (priv->mode != IEEE80211_IF_TYPE_INVALID) {
2017                 adm8211_start(dev);
2018                 ieee80211_start_queues(dev);
2019         }
2020
2021         return 0;
2022 }
2023 #endif /* CONFIG_PM */
2024
2025
2026 MODULE_DEVICE_TABLE(pci, adm8211_pci_id_table);
2027
2028 /* TODO: implement enable_wake */
2029 static struct pci_driver adm8211_driver = {
2030         .name           = "adm8211",
2031         .id_table       = adm8211_pci_id_table,
2032         .probe          = adm8211_probe,
2033         .remove         = __devexit_p(adm8211_remove),
2034 #ifdef CONFIG_PM
2035         .suspend        = adm8211_suspend,
2036         .resume         = adm8211_resume,
2037 #endif /* CONFIG_PM */
2038 };
2039
2040
2041
2042 static int __init adm8211_init(void)
2043 {
2044         return pci_register_driver(&adm8211_driver);
2045 }
2046
2047
2048 static void __exit adm8211_exit(void)
2049 {
2050         pci_unregister_driver(&adm8211_driver);
2051 }
2052
2053
2054 module_init(adm8211_init);
2055 module_exit(adm8211_exit);