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   1 /* linux/arch/arm/mach-s3c2410/mach-qt2410.c
   2  *
   3  * Copyright (C) 2006 by OpenMoko, Inc.
   4  * Author: Harald Welte <laforge@openmoko.org>
   5  * All rights reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  *
  22  */
  23
  24 #include <linux/kernel.h>
  25 #include <linux/types.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/list.h>
  28 #include <linux/timer.h>
  29 #include <linux/init.h>
  30 #include <linux/sysdev.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/serial_core.h>
  33 #include <linux/spi/spi.h>
  34 #include <linux/spi/spi_bitbang.h>
  35 #include <linux/io.h>
  36 #include <linux/mtd/mtd.h>
  37 #include <linux/mtd/nand.h>
  38 #include <linux/mtd/nand_ecc.h>
  39 #include <linux/mtd/partitions.h>
  40
  41 #include <asm/mach/arch.h>
  42 #include <asm/mach/map.h>
  43 #include <asm/mach/irq.h>
  44
  45 #include <mach/hardware.h>
  46 #include <asm/irq.h>
  47 #include <asm/mach-types.h>
  48
  49 #include <mach/regs-gpio.h>
  50 #include <mach/leds-gpio.h>
  51 #include <plat/regs-serial.h>
  52 #include <mach/fb.h>
  53 #include <asm/plat-s3c/nand.h>
  54 #include <asm/plat-s3c24xx/udc.h>
  55 #include <mach/spi.h>
  56 #include <mach/spi-gpio.h>
  57
  58 #include <plat/common-smdk.h>
  59 #include <plat/devs.h>
  60 #include <plat/cpu.h>
  61 #include <plat/pm.h>
  62
  63 static struct map_desc qt2410_iodesc[] __initdata = {
  64         { 0xe0000000, __phys_to_pfn(S3C2410_CS3+0x01000000), SZ_1M, MT_DEVICE }
  65 };
  66
  67 #define UCON S3C2410_UCON_DEFAULT
  68 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
  69 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
  70
  71 static struct s3c2410_uartcfg smdk2410_uartcfgs[] = {
  72         [0] = {
  73                 .hwport      = 0,
  74                 .flags       = 0,
  75                 .ucon        = UCON,
  76                 .ulcon       = ULCON,
  77                 .ufcon       = UFCON,
  78         },
  79         [1] = {
  80                 .hwport      = 1,
  81                 .flags       = 0,
  82                 .ucon        = UCON,
  83                 .ulcon       = ULCON,
  84                 .ufcon       = UFCON,
  85         },
  86         [2] = {
  87                 .hwport      = 2,
  88                 .flags       = 0,
  89                 .ucon        = UCON,
  90                 .ulcon       = ULCON,
  91                 .ufcon       = UFCON,
  92         }
  93 };
  94
  95 /* LCD driver info */
  96
  97 static struct s3c2410fb_display qt2410_lcd_cfg[] __initdata = {
  98         {
  99                 /* Configuration for 640x480 SHARP LQ080V3DG01 */
 100                 .lcdcon5 = S3C2410_LCDCON5_FRM565 |
 101                            S3C2410_LCDCON5_INVVLINE |
 102                            S3C2410_LCDCON5_INVVFRAME |
 103                            S3C2410_LCDCON5_PWREN |
 104                            S3C2410_LCDCON5_HWSWP,
 105
 106                 .type           = S3C2410_LCDCON1_TFT,
 107                 .width          = 640,
 108                 .height         = 480,
 109
 110                 .pixclock       = 40000, /* HCLK/4 */
 111                 .xres           = 640,
 112                 .yres           = 480,
 113                 .bpp            = 16,
 114                 .left_margin    = 44,
 115                 .right_margin   = 116,
 116                 .hsync_len      = 96,
 117                 .upper_margin   = 19,
 118                 .lower_margin   = 11,
 119                 .vsync_len      = 15,
 120         },
 121         {
 122                 /* Configuration for 480x640 toppoly TD028TTEC1 */
 123                 .lcdcon5 = S3C2410_LCDCON5_FRM565 |
 124                            S3C2410_LCDCON5_INVVLINE |
 125                            S3C2410_LCDCON5_INVVFRAME |
 126                            S3C2410_LCDCON5_PWREN |
 127                            S3C2410_LCDCON5_HWSWP,
 128
 129                 .type           = S3C2410_LCDCON1_TFT,
 130                 .width          = 480,
 131                 .height         = 640,
 132                 .pixclock       = 40000, /* HCLK/4 */
 133                 .xres           = 480,
 134                 .yres           = 640,
 135                 .bpp            = 16,
 136                 .left_margin    = 8,
 137                 .right_margin   = 24,
 138                 .hsync_len      = 8,
 139                 .upper_margin   = 2,
 140                 .lower_margin   = 4,
 141                 .vsync_len      = 2,
 142         },
 143         {
 144                 /* Config for 240x320 LCD */
 145                 .lcdcon5 = S3C2410_LCDCON5_FRM565 |
 146                            S3C2410_LCDCON5_INVVLINE |
 147                            S3C2410_LCDCON5_INVVFRAME |
 148                            S3C2410_LCDCON5_PWREN |
 149                            S3C2410_LCDCON5_HWSWP,
 150
 151                 .type           = S3C2410_LCDCON1_TFT,
 152                 .width          = 240,
 153                 .height         = 320,
 154                 .pixclock       = 100000, /* HCLK/10 */
 155                 .xres           = 240,
 156                 .yres           = 320,
 157                 .bpp            = 16,
 158                 .left_margin    = 13,
 159                 .right_margin   = 8,
 160                 .hsync_len      = 4,
 161                 .upper_margin   = 2,
 162                 .lower_margin   = 7,
 163                 .vsync_len      = 4,
 164         },
 165 };
 166
 167
 168 static struct s3c2410fb_mach_info qt2410_fb_info __initdata = {
 169         .displays       = qt2410_lcd_cfg,
 170         .num_displays   = ARRAY_SIZE(qt2410_lcd_cfg),
 171         .default_display = 0,
 172
 173         .lpcsel         = ((0xCE6) & ~7) | 1<<4,
 174 };
 175
 176 /* CS8900 */
 177
 178 static struct resource qt2410_cs89x0_resources[] = {
 179         [0] = {
 180                 .start  = 0x19000000,
 181                 .end    = 0x19000000 + 16,
 182                 .flags  = IORESOURCE_MEM,
 183         },
 184         [1] = {
 185                 .start  = IRQ_EINT9,
 186                 .end    = IRQ_EINT9,
 187                 .flags  = IORESOURCE_IRQ,
 188         },
 189 };
 190
 191 static struct platform_device qt2410_cs89x0 = {
 192         .name           = "cirrus-cs89x0",
 193         .num_resources  = ARRAY_SIZE(qt2410_cs89x0_resources),
 194         .resource       = qt2410_cs89x0_resources,
 195 };
 196
 197 /* LED */
 198
 199 static struct s3c24xx_led_platdata qt2410_pdata_led = {
 200         .gpio           = S3C2410_GPB0,
 201         .flags          = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
 202         .name           = "led",
 203         .def_trigger    = "timer",
 204 };
 205
 206 static struct platform_device qt2410_led = {
 207         .name           = "s3c24xx_led",
 208         .id             = 0,
 209         .dev            = {
 210                 .platform_data = &qt2410_pdata_led,
 211         },
 212 };
 213
 214 /* SPI */
 215
 216 static void spi_gpio_cs(struct s3c2410_spigpio_info *spi, int cs)
 217 {
 218         switch (cs) {
 219         case BITBANG_CS_ACTIVE:
 220                 s3c2410_gpio_setpin(S3C2410_GPB5, 0);
 221                 break;
 222         case BITBANG_CS_INACTIVE:
 223                 s3c2410_gpio_setpin(S3C2410_GPB5, 1);
 224                 break;
 225         }
 226 }
 227
 228 static struct s3c2410_spigpio_info spi_gpio_cfg = {
 229         .pin_clk        = S3C2410_GPG7,
 230         .pin_mosi       = S3C2410_GPG6,
 231         .pin_miso       = S3C2410_GPG5,
 232         .chip_select    = &spi_gpio_cs,
 233 };
 234
 235
 236 static struct platform_device qt2410_spi = {
 237         .name             = "s3c24xx-spi-gpio",
 238         .id               = 1,
 239         .dev = {
 240                 .platform_data = &spi_gpio_cfg,
 241         },
 242 };
 243
 244 /* Board devices */
 245
 246 static struct platform_device *qt2410_devices[] __initdata = {
 247         &s3c_device_usb,
 248         &s3c_device_lcd,
 249         &s3c_device_wdt,
 250         &s3c_device_i2c,
 251         &s3c_device_iis,
 252         &s3c_device_sdi,
 253         &s3c_device_usbgadget,
 254         &qt2410_spi,
 255         &qt2410_cs89x0,
 256         &qt2410_led,
 257 };
 258
 259 static struct mtd_partition qt2410_nand_part[] = {
 260         [0] = {
 261                 .name   = "U-Boot",
 262                 .size   = 0x30000,
 263                 .offset = 0,
 264         },
 265         [1] = {
 266                 .name   = "U-Boot environment",
 267                 .offset = 0x30000,
 268                 .size   = 0x4000,
 269         },
 270         [2] = {
 271                 .name   = "kernel",
 272                 .offset = 0x34000,
 273                 .size   = SZ_2M,
 274         },
 275         [3] = {
 276                 .name   = "initrd",
 277                 .offset = 0x234000,
 278                 .size   = SZ_4M,
 279         },
 280         [4] = {
 281                 .name   = "jffs2",
 282                 .offset = 0x634000,
 283                 .size   = 0x39cc000,
 284         },
 285 };
 286
 287 static struct s3c2410_nand_set qt2410_nand_sets[] = {
 288         [0] = {
 289                 .name           = "NAND",
 290                 .nr_chips       = 1,
 291                 .nr_partitions  = ARRAY_SIZE(qt2410_nand_part),
 292                 .partitions     = qt2410_nand_part,
 293         },
 294 };
 295
 296 /* choose a set of timings which should suit most 512Mbit
 297  * chips and beyond.
 298  */
 299
 300 static struct s3c2410_platform_nand qt2410_nand_info = {
 301         .tacls          = 20,
 302         .twrph0         = 60,
 303         .twrph1         = 20,
 304         .nr_sets        = ARRAY_SIZE(qt2410_nand_sets),
 305         .sets           = qt2410_nand_sets,
 306 };
 307
 308 /* UDC */
 309
 310 static struct s3c2410_udc_mach_info qt2410_udc_cfg = {
 311 };
 312
 313 static char tft_type = 's';
 314
 315 static int __init qt2410_tft_setup(char *str)
 316 {
 317         tft_type = str[0];
 318         return 1;
 319 }
 320
 321 __setup("tft=", qt2410_tft_setup);
 322
 323 static void __init qt2410_map_io(void)
 324 {
 325         s3c24xx_init_io(qt2410_iodesc, ARRAY_SIZE(qt2410_iodesc));
 326         s3c24xx_init_clocks(12*1000*1000);
 327         s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs));
 328 }
 329
 330 static void __init qt2410_machine_init(void)
 331 {
 332         s3c_device_nand.dev.platform_data = &qt2410_nand_info;
 333
 334         switch (tft_type) {
 335         case 'p': /* production */
 336                 qt2410_fb_info.default_display = 1;
 337                 break;
 338         case 'b': /* big */
 339                 qt2410_fb_info.default_display = 0;
 340                 break;
 341         case 's': /* small */
 342         default:
 343                 qt2410_fb_info.default_display = 2;
 344                 break;
 345         }
 346         s3c24xx_fb_set_platdata(&qt2410_fb_info);
 347
 348         s3c2410_gpio_cfgpin(S3C2410_GPB0, S3C2410_GPIO_OUTPUT);
 349         s3c2410_gpio_setpin(S3C2410_GPB0, 1);
 350
 351         s3c24xx_udc_set_platdata(&qt2410_udc_cfg);
 352
 353         s3c2410_gpio_cfgpin(S3C2410_GPB5, S3C2410_GPIO_OUTPUT);
 354
 355         platform_add_devices(qt2410_devices, ARRAY_SIZE(qt2410_devices));
 356         s3c2410_pm_init();
 357 }
 358
 359 MACHINE_START(QT2410, "QT2410")
 360         .phys_io        = S3C2410_PA_UART,
 361         .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
 362         .boot_params    = S3C2410_SDRAM_PA + 0x100,
 363         .map_io         = qt2410_map_io,
 364         .init_irq       = s3c24xx_init_irq,
 365         .init_machine   = qt2410_machine_init,
 366         .timer          = &s3c24xx_timer,
 367 MACHINE_END
 368
 369