git.oblomov.eu Git - linux-2.6/blob - drivers/media/dvb/frontends/tda18271-fe.c

   1 /*
   2     tda18271-fe.c - driver for the Philips / NXP TDA18271 silicon tuner
   3
   4     Copyright (C) 2007 Michael Krufky (mkrufky@linuxtv.org)
   5
   6     This program is free software; you can redistribute it and/or modify
   7     it under the terms of the GNU General Public License as published by
   8     the Free Software Foundation; either version 2 of the License, or
   9     (at your option) any later version.
  10
  11     This program is distributed in the hope that it will be useful,
  12     but WITHOUT ANY WARRANTY; without even the implied warranty of
  13     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14     GNU General Public License for more details.
  15
  16     You should have received a copy of the GNU General Public License
  17     along with this program; if not, write to the Free Software
  18     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19 */
  20
  21 #include <linux/delay.h>
  22 #include <linux/videodev2.h>
  23 #include "tuner-driver.h"
  24
  25 #include "tda18271.h"
  26 #include "tda18271-priv.h"
  27
  28 int tda18271_debug;
  29 module_param_named(debug, tda18271_debug, int, 0644);
  30 MODULE_PARM_DESC(debug, "set debug level (info=1, map=2, reg=4 (or-able))");
  31
  32 /*---------------------------------------------------------------------*/
  33
  34 enum tda18271_mode {
  35         TDA18271_ANALOG,
  36         TDA18271_DIGITAL,
  37 };
  38
  39 struct tda18271_priv {
  40         u8 i2c_addr;
  41         struct i2c_adapter *i2c_adap;
  42         unsigned char tda18271_regs[TDA18271_NUM_REGS];
  43
  44         enum tda18271_mode mode;
  45         enum tda18271_i2c_gate gate;
  46
  47         u32 frequency;
  48         u32 bandwidth;
  49 };
  50
  51 static int tda18271_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
  52 {
  53         struct tda18271_priv *priv = fe->tuner_priv;
  54         struct analog_tuner_ops *ops = fe->ops.analog_demod_ops;
  55         enum tda18271_i2c_gate gate;
  56         int ret = 0;
  57
  58         switch (priv->gate) {
  59         case TDA18271_GATE_DIGITAL:
  60         case TDA18271_GATE_ANALOG:
  61                 gate = priv->gate;
  62                 break;
  63         case TDA18271_GATE_AUTO:
  64         default:
  65                 switch (priv->mode) {
  66                 case TDA18271_DIGITAL:
  67                         gate = TDA18271_GATE_DIGITAL;
  68                         break;
  69                 case TDA18271_ANALOG:
  70                 default:
  71                         gate = TDA18271_GATE_ANALOG;
  72                         break;
  73                 }
  74         }
  75
  76         switch (gate) {
  77         case TDA18271_GATE_ANALOG:
  78                 if (ops && ops->i2c_gate_ctrl)
  79                         ret = ops->i2c_gate_ctrl(fe, enable);
  80                 break;
  81         case TDA18271_GATE_DIGITAL:
  82                 if (fe->ops.i2c_gate_ctrl)
  83                         ret = fe->ops.i2c_gate_ctrl(fe, enable);
  84                 break;
  85         default:
  86                 ret = -EINVAL;
  87                 break;
  88         }
  89
  90         return ret;
  91 };
  92
  93 /*---------------------------------------------------------------------*/
  94
  95 static void tda18271_dump_regs(struct dvb_frontend *fe)
  96 {
  97         struct tda18271_priv *priv = fe->tuner_priv;
  98         unsigned char *regs = priv->tda18271_regs;
  99
 100         dbg_reg("=== TDA18271 REG DUMP ===\n");
 101         dbg_reg("ID_BYTE            = 0x%02x\n", 0xff & regs[R_ID]);
 102         dbg_reg("THERMO_BYTE        = 0x%02x\n", 0xff & regs[R_TM]);
 103         dbg_reg("POWER_LEVEL_BYTE   = 0x%02x\n", 0xff & regs[R_PL]);
 104         dbg_reg("EASY_PROG_BYTE_1   = 0x%02x\n", 0xff & regs[R_EP1]);
 105         dbg_reg("EASY_PROG_BYTE_2   = 0x%02x\n", 0xff & regs[R_EP2]);
 106         dbg_reg("EASY_PROG_BYTE_3   = 0x%02x\n", 0xff & regs[R_EP3]);
 107         dbg_reg("EASY_PROG_BYTE_4   = 0x%02x\n", 0xff & regs[R_EP4]);
 108         dbg_reg("EASY_PROG_BYTE_5   = 0x%02x\n", 0xff & regs[R_EP5]);
 109         dbg_reg("CAL_POST_DIV_BYTE  = 0x%02x\n", 0xff & regs[R_CPD]);
 110         dbg_reg("CAL_DIV_BYTE_1     = 0x%02x\n", 0xff & regs[R_CD1]);
 111         dbg_reg("CAL_DIV_BYTE_2     = 0x%02x\n", 0xff & regs[R_CD2]);
 112         dbg_reg("CAL_DIV_BYTE_3     = 0x%02x\n", 0xff & regs[R_CD3]);
 113         dbg_reg("MAIN_POST_DIV_BYTE = 0x%02x\n", 0xff & regs[R_MPD]);
 114         dbg_reg("MAIN_DIV_BYTE_1    = 0x%02x\n", 0xff & regs[R_MD1]);
 115         dbg_reg("MAIN_DIV_BYTE_2    = 0x%02x\n", 0xff & regs[R_MD2]);
 116         dbg_reg("MAIN_DIV_BYTE_3    = 0x%02x\n", 0xff & regs[R_MD3]);
 117 }
 118
 119 static void tda18271_read_regs(struct dvb_frontend *fe)
 120 {
 121         struct tda18271_priv *priv = fe->tuner_priv;
 122         unsigned char *regs = priv->tda18271_regs;
 123         unsigned char buf = 0x00;
 124         int ret;
 125         struct i2c_msg msg[] = {
 126                 { .addr = priv->i2c_addr, .flags = 0,
 127                   .buf = &buf, .len = 1 },
 128                 { .addr = priv->i2c_addr, .flags = I2C_M_RD,
 129                   .buf = regs, .len = 16 }
 130         };
 131
 132         tda18271_i2c_gate_ctrl(fe, 1);
 133
 134         /* read all registers */
 135         ret = i2c_transfer(priv->i2c_adap, msg, 2);
 136
 137         tda18271_i2c_gate_ctrl(fe, 0);
 138
 139         if (ret != 2)
 140                 printk("ERROR: %s: i2c_transfer returned: %d\n",
 141                        __FUNCTION__, ret);
 142
 143         if (tda18271_debug & DBG_REG)
 144                 tda18271_dump_regs(fe);
 145 }
 146
 147 static void tda18271_write_regs(struct dvb_frontend *fe, int idx, int len)
 148 {
 149         struct tda18271_priv *priv = fe->tuner_priv;
 150         unsigned char *regs = priv->tda18271_regs;
 151         unsigned char buf[TDA18271_NUM_REGS+1];
 152         struct i2c_msg msg = { .addr = priv->i2c_addr, .flags = 0,
 153                                .buf = buf, .len = len+1 };
 154         int i, ret;
 155
 156         BUG_ON((len == 0) || (idx+len > sizeof(buf)));
 157
 158         buf[0] = idx;
 159         for (i = 1; i <= len; i++) {
 160                 buf[i] = regs[idx-1+i];
 161         }
 162
 163         tda18271_i2c_gate_ctrl(fe, 1);
 164
 165         /* write registers */
 166         ret = i2c_transfer(priv->i2c_adap, &msg, 1);
 167
 168         tda18271_i2c_gate_ctrl(fe, 0);
 169
 170         if (ret != 1)
 171                 printk(KERN_WARNING "ERROR: %s: i2c_transfer returned: %d\n",
 172                        __FUNCTION__, ret);
 173 }
 174
 175 /*---------------------------------------------------------------------*/
 176
 177 static int tda18271_init_regs(struct dvb_frontend *fe)
 178 {
 179         struct tda18271_priv *priv = fe->tuner_priv;
 180         unsigned char *regs = priv->tda18271_regs;
 181
 182         printk(KERN_INFO "tda18271: initializing registers\n");
 183
 184         /* initialize registers */
 185         regs[R_ID]   = 0x83;
 186         regs[R_TM]   = 0x08;
 187         regs[R_PL]   = 0x80;
 188         regs[R_EP1]  = 0xc6;
 189         regs[R_EP2]  = 0xdf;
 190         regs[R_EP3]  = 0x16;
 191         regs[R_EP4]  = 0x60;
 192         regs[R_EP5]  = 0x80;
 193         regs[R_CPD]  = 0x80;
 194         regs[R_CD1]  = 0x00;
 195         regs[R_CD2]  = 0x00;
 196         regs[R_CD3]  = 0x00;
 197         regs[R_MPD]  = 0x00;
 198         regs[R_MD1]  = 0x00;
 199         regs[R_MD2]  = 0x00;
 200         regs[R_MD3]  = 0x00;
 201         regs[R_EB1]  = 0xff;
 202         regs[R_EB2]  = 0x01;
 203         regs[R_EB3]  = 0x84;
 204         regs[R_EB4]  = 0x41;
 205         regs[R_EB5]  = 0x01;
 206         regs[R_EB6]  = 0x84;
 207         regs[R_EB7]  = 0x40;
 208         regs[R_EB8]  = 0x07;
 209         regs[R_EB9]  = 0x00;
 210         regs[R_EB10] = 0x00;
 211         regs[R_EB11] = 0x96;
 212         regs[R_EB12] = 0x0f;
 213         regs[R_EB13] = 0xc1;
 214         regs[R_EB14] = 0x00;
 215         regs[R_EB15] = 0x8f;
 216         regs[R_EB16] = 0x00;
 217         regs[R_EB17] = 0x00;
 218         regs[R_EB18] = 0x00;
 219         regs[R_EB19] = 0x00;
 220         regs[R_EB20] = 0x20;
 221         regs[R_EB21] = 0x33;
 222         regs[R_EB22] = 0x48;
 223         regs[R_EB23] = 0xb0;
 224
 225         tda18271_write_regs(fe, 0x00, TDA18271_NUM_REGS);
 226         /* setup AGC1 & AGC2 */
 227         regs[R_EB17] = 0x00;
 228         tda18271_write_regs(fe, R_EB17, 1);
 229         regs[R_EB17] = 0x03;
 230         tda18271_write_regs(fe, R_EB17, 1);
 231         regs[R_EB17] = 0x43;
 232         tda18271_write_regs(fe, R_EB17, 1);
 233         regs[R_EB17] = 0x4c;
 234         tda18271_write_regs(fe, R_EB17, 1);
 235
 236         regs[R_EB20] = 0xa0;
 237         tda18271_write_regs(fe, R_EB20, 1);
 238         regs[R_EB20] = 0xa7;
 239         tda18271_write_regs(fe, R_EB20, 1);
 240         regs[R_EB20] = 0xe7;
 241         tda18271_write_regs(fe, R_EB20, 1);
 242         regs[R_EB20] = 0xec;
 243         tda18271_write_regs(fe, R_EB20, 1);
 244
 245         /* image rejection calibration */
 246
 247         /* low-band */
 248         regs[R_EP3] = 0x1f;
 249         regs[R_EP4] = 0x66;
 250         regs[R_EP5] = 0x81;
 251         regs[R_CPD] = 0xcc;
 252         regs[R_CD1] = 0x6c;
 253         regs[R_CD2] = 0x00;
 254         regs[R_CD3] = 0x00;
 255         regs[R_MPD] = 0xcd;
 256         regs[R_MD1] = 0x77;
 257         regs[R_MD2] = 0x08;
 258         regs[R_MD3] = 0x00;
 259
 260         tda18271_write_regs(fe, R_EP3, 11);
 261         msleep(5); /* pll locking */
 262
 263         regs[R_EP1] = 0xc6;
 264         tda18271_write_regs(fe, R_EP1, 1);
 265         msleep(5); /* wanted low measurement */
 266
 267         regs[R_EP3] = 0x1f;
 268         regs[R_EP4] = 0x66;
 269         regs[R_EP5] = 0x85;
 270         regs[R_CPD] = 0xcb;
 271         regs[R_CD1] = 0x66;
 272         regs[R_CD2] = 0x70;
 273         regs[R_CD3] = 0x00;
 274
 275         tda18271_write_regs(fe, R_EP3, 7);
 276         msleep(5); /* pll locking */
 277
 278         regs[R_EP2] = 0xdf;
 279         tda18271_write_regs(fe, R_EP2, 1);
 280         msleep(30); /* image low optimization completion */
 281
 282         /* mid-band */
 283         regs[R_EP3] = 0x1f;
 284         regs[R_EP4] = 0x66;
 285         regs[R_EP5] = 0x82;
 286         regs[R_CPD] = 0xa8;
 287         regs[R_CD1] = 0x66;
 288         regs[R_CD2] = 0x00;
 289         regs[R_CD3] = 0x00;
 290         regs[R_MPD] = 0xa9;
 291         regs[R_MD1] = 0x73;
 292         regs[R_MD2] = 0x1a;
 293         regs[R_MD3] = 0x00;
 294
 295         tda18271_write_regs(fe, R_EP3, 11);
 296         msleep(5); /* pll locking */
 297
 298         regs[R_EP1] = 0xc6;
 299         tda18271_write_regs(fe, R_EP1, 1);
 300         msleep(5); /* wanted mid measurement */
 301
 302         regs[R_EP3] = 0x1f;
 303         regs[R_EP4] = 0x66;
 304         regs[R_EP5] = 0x86;
 305         regs[R_CPD] = 0xa8;
 306         regs[R_CD1] = 0x66;
 307         regs[R_CD2] = 0xa0;
 308         regs[R_CD3] = 0x00;
 309
 310         tda18271_write_regs(fe, R_EP3, 7);
 311         msleep(5); /* pll locking */
 312
 313         regs[R_EP2] = 0xdf;
 314         tda18271_write_regs(fe, R_EP2, 1);
 315         msleep(30); /* image mid optimization completion */
 316
 317         /* high-band */
 318         regs[R_EP3] = 0x1f;
 319         regs[R_EP4] = 0x66;
 320         regs[R_EP5] = 0x83;
 321         regs[R_CPD] = 0x98;
 322         regs[R_CD1] = 0x65;
 323         regs[R_CD2] = 0x00;
 324         regs[R_CD3] = 0x00;
 325         regs[R_MPD] = 0x99;
 326         regs[R_MD1] = 0x71;
 327         regs[R_MD2] = 0xcd;
 328         regs[R_MD3] = 0x00;
 329
 330         tda18271_write_regs(fe, R_EP3, 11);
 331         msleep(5); /* pll locking */
 332
 333         regs[R_EP1] = 0xc6;
 334         tda18271_write_regs(fe, R_EP1, 1);
 335         msleep(5); /* wanted high measurement */
 336
 337         regs[R_EP3] = 0x1f;
 338         regs[R_EP4] = 0x66;
 339         regs[R_EP5] = 0x87;
 340         regs[R_CPD] = 0x98;
 341         regs[R_CD1] = 0x65;
 342         regs[R_CD2] = 0x50;
 343         regs[R_CD3] = 0x00;
 344
 345         tda18271_write_regs(fe, R_EP3, 7);
 346         msleep(5); /* pll locking */
 347
 348         regs[R_EP2] = 0xdf;
 349
 350         tda18271_write_regs(fe, R_EP2, 1);
 351         msleep(30); /* image high optimization completion */
 352
 353         regs[R_EP4] = 0x64;
 354         tda18271_write_regs(fe, R_EP4, 1);
 355
 356         regs[R_EP1] = 0xc6;
 357         tda18271_write_regs(fe, R_EP1, 1);
 358
 359         return 0;
 360 }
 361
 362 static int tda18271_init(struct dvb_frontend *fe)
 363 {
 364         struct tda18271_priv *priv = fe->tuner_priv;
 365         unsigned char *regs = priv->tda18271_regs;
 366
 367         tda18271_read_regs(fe);
 368
 369         /* test IR_CAL_OK to see if we need init */
 370         if ((regs[R_EP1] & 0x08) == 0)
 371                 tda18271_init_regs(fe);
 372
 373         return 0;
 374 }
 375
 376 static int tda18271_tune(struct dvb_frontend *fe,
 377                          u32 ifc, u32 freq, u32 bw, u8 std)
 378 {
 379         struct tda18271_priv *priv = fe->tuner_priv;
 380         unsigned char *regs = priv->tda18271_regs;
 381         u32 div, N = 0;
 382         u8 d, pd, val;
 383
 384         tda18271_init(fe);
 385
 386         dbg_info("freq = %d, ifc = %d\n", freq, ifc);
 387
 388         /* RF tracking filter calibration */
 389
 390         /* calculate BP_Filter */
 391         tda18271_calc_bp_filter(&freq, &val);
 392
 393         regs[R_EP1]  &= ~0x07; /* clear bp filter bits */
 394         regs[R_EP1]  |= val;
 395         tda18271_write_regs(fe, R_EP1, 1);
 396
 397         regs[R_EB4]  &= 0x07;
 398         regs[R_EB4]  |= 0x60;
 399         tda18271_write_regs(fe, R_EB4, 1);
 400
 401         regs[R_EB7]   = 0x60;
 402         tda18271_write_regs(fe, R_EB7, 1);
 403
 404         regs[R_EB14]  = 0x00;
 405         tda18271_write_regs(fe, R_EB14, 1);
 406
 407         regs[R_EB20]  = 0xcc;
 408         tda18271_write_regs(fe, R_EB20, 1);
 409
 410         /* set CAL mode to RF tracking filter calibration */
 411         regs[R_EB4]  |= 0x03;
 412
 413         /* calculate CAL PLL */
 414
 415         switch (priv->mode) {
 416         case TDA18271_ANALOG:
 417                 N = freq - 1250000;
 418                 break;
 419         case TDA18271_DIGITAL:
 420                 N = freq + bw / 2;
 421                 break;
 422         }
 423
 424         tda18271_calc_cal_pll(&N, &pd, &d);
 425
 426         regs[R_CPD]   = pd;
 427
 428         div =  ((d * (N / 1000)) << 7) / 125;
 429         regs[R_CD1]   = 0xff & (div >> 16);
 430         regs[R_CD2]   = 0xff & (div >> 8);
 431         regs[R_CD3]   = 0xff & div;
 432
 433         /* calculate MAIN PLL */
 434
 435         switch (priv->mode) {
 436         case TDA18271_ANALOG:
 437                 N = freq - 250000;
 438                 break;
 439         case TDA18271_DIGITAL:
 440                 N = freq + bw / 2 + 1000000;
 441                 break;
 442         }
 443
 444         tda18271_calc_main_pll(&N, &pd, &d);
 445
 446         regs[R_MPD]   = (0x7f & pd);
 447
 448         switch (priv->mode) {
 449         case TDA18271_ANALOG:
 450                 regs[R_MPD]  &= ~0x08;
 451                 break;
 452         case TDA18271_DIGITAL:
 453                 regs[R_MPD]  |=  0x08;
 454                 break;
 455         }
 456
 457         div =  ((d * (N / 1000)) << 7) / 125;
 458         regs[R_MD1]   = 0xff & (div >> 16);
 459         regs[R_MD2]   = 0xff & (div >> 8);
 460         regs[R_MD3]   = 0xff & div;
 461
 462         tda18271_write_regs(fe, R_EP3, 11);
 463         msleep(5); /* RF tracking filter calibration initialization */
 464
 465         /* search for K,M,CO for RF Calibration */
 466         tda18271_calc_km(&freq, &val);
 467
 468         regs[R_EB13] &= 0x83;
 469         regs[R_EB13] |= val;
 470         tda18271_write_regs(fe, R_EB13, 1);
 471
 472         /* search for RF_BAND */
 473         tda18271_calc_rf_band(&freq, &val);
 474
 475         regs[R_EP2]  &= ~0xe0; /* clear rf band bits */
 476         regs[R_EP2]  |= (val << 5);
 477
 478         /* search for Gain_Taper */
 479         tda18271_calc_gain_taper(&freq, &val);
 480
 481         regs[R_EP2]  &= ~0x1f; /* clear gain taper bits */
 482         regs[R_EP2]  |= val;
 483
 484         tda18271_write_regs(fe, R_EP2, 1);
 485         tda18271_write_regs(fe, R_EP1, 1);
 486         tda18271_write_regs(fe, R_EP2, 1);
 487         tda18271_write_regs(fe, R_EP1, 1);
 488
 489         regs[R_EB4]  &= 0x07;
 490         regs[R_EB4]  |= 0x40;
 491         tda18271_write_regs(fe, R_EB4, 1);
 492
 493         regs[R_EB7]   = 0x40;
 494         tda18271_write_regs(fe, R_EB7, 1);
 495         msleep(10);
 496
 497         regs[R_EB20]  = 0xec;
 498         tda18271_write_regs(fe, R_EB20, 1);
 499         msleep(60); /* RF tracking filter calibration completion */
 500
 501         regs[R_EP4]  &= ~0x03; /* set cal mode to normal */
 502         tda18271_write_regs(fe, R_EP4, 1);
 503
 504         tda18271_write_regs(fe, R_EP1, 1);
 505
 506         /* RF tracking filer correction for VHF_Low band */
 507         tda18271_calc_rf_cal(&freq, &val);
 508
 509         /* VHF_Low band only */
 510         if (val != 0) {
 511                 regs[R_EB14] = val;
 512                 tda18271_write_regs(fe, R_EB14, 1);
 513         }
 514
 515         /* Channel Configuration */
 516
 517         switch (priv->mode) {
 518         case TDA18271_ANALOG:
 519                 regs[R_EB22]  = 0x2c;
 520                 break;
 521         case TDA18271_DIGITAL:
 522                 regs[R_EB22]  = 0x37;
 523                 break;
 524         }
 525         tda18271_write_regs(fe, R_EB22, 1);
 526
 527         regs[R_EP1]  |= 0x40; /* set dis power level on */
 528
 529         /* set standard */
 530         regs[R_EP3]  &= ~0x1f; /* clear std bits */
 531
 532         /* see table 22 */
 533         regs[R_EP3]  |= std;
 534
 535         regs[R_EP4]  &= ~0x03; /* set cal mode to normal */
 536
 537         regs[R_EP4]  &= ~0x1c; /* clear if level bits */
 538         switch (priv->mode) {
 539         case TDA18271_ANALOG:
 540                 regs[R_MPD]  &= ~0x80; /* IF notch = 0 */
 541                 break;
 542         case TDA18271_DIGITAL:
 543                 regs[R_EP4]  |= 0x04;
 544                 regs[R_MPD]  |= 0x80;
 545                 break;
 546         }
 547
 548         regs[R_EP4]  &= ~0x80; /* turn this bit on only for fm */
 549
 550         /* image rejection validity EP5[2:0] */
 551         tda18271_calc_ir_measure(&freq, &val);
 552
 553         regs[R_EP5] &= ~0x07;
 554         regs[R_EP5] |= val;
 555
 556         /* calculate MAIN PLL */
 557         N = freq + ifc;
 558
 559         tda18271_calc_main_pll(&N, &pd, &d);
 560
 561         regs[R_MPD]   = (0x7f & pd);
 562         switch (priv->mode) {
 563         case TDA18271_ANALOG:
 564                 regs[R_MPD]  &= ~0x08;
 565                 break;
 566         case TDA18271_DIGITAL:
 567                 regs[R_MPD]  |= 0x08;
 568                 break;
 569         }
 570
 571         div =  ((d * (N / 1000)) << 7) / 125;
 572         regs[R_MD1]   = 0xff & (div >> 16);
 573         regs[R_MD2]   = 0xff & (div >> 8);
 574         regs[R_MD3]   = 0xff & div;
 575
 576         tda18271_write_regs(fe, R_TM, 15);
 577         msleep(5);
 578
 579         return 0;
 580 }
 581
 582 /* ------------------------------------------------------------------ */
 583
 584 static int tda18271_set_params(struct dvb_frontend *fe,
 585                                struct dvb_frontend_parameters *params)
 586 {
 587         struct tda18271_priv *priv = fe->tuner_priv;
 588         u8 std;
 589         u32 bw, sgIF = 0;
 590
 591         u32 freq = params->frequency;
 592
 593         priv->mode = TDA18271_DIGITAL;
 594
 595         /* see table 22 */
 596         if (fe->ops.info.type == FE_ATSC) {
 597                 switch (params->u.vsb.modulation) {
 598                 case VSB_8:
 599                 case VSB_16:
 600                         std = 0x1b; /* device-specific (spec says 0x1c) */
 601                         sgIF = 5380000;
 602                         break;
 603                 case QAM_64:
 604                 case QAM_256:
 605                         std = 0x18; /* device-specific (spec says 0x1d) */
 606                         sgIF = 4000000;
 607                         break;
 608                 default:
 609                         printk(KERN_WARNING "%s: modulation not set!\n",
 610                                __FUNCTION__);
 611                         return -EINVAL;
 612                 }
 613 #if 0
 614                 /* userspace request is already center adjusted */
 615                 freq += 1750000; /* Adjust to center (+1.75MHZ) */
 616 #endif
 617                 bw = 6000000;
 618         } else if (fe->ops.info.type == FE_OFDM) {
 619                 switch (params->u.ofdm.bandwidth) {
 620                 case BANDWIDTH_6_MHZ:
 621                         std = 0x1b; /* device-specific (spec says 0x1c) */
 622                         bw = 6000000;
 623                         sgIF = 3300000;
 624                         break;
 625                 case BANDWIDTH_7_MHZ:
 626                         std = 0x19; /* device-specific (spec says 0x1d) */
 627                         bw = 7000000;
 628                         sgIF = 3800000;
 629                         break;
 630                 case BANDWIDTH_8_MHZ:
 631                         std = 0x1a; /* device-specific (spec says 0x1e) */
 632                         bw = 8000000;
 633                         sgIF = 4300000;
 634                         break;
 635                 default:
 636                         printk(KERN_WARNING "%s: bandwidth not set!\n",
 637                                __FUNCTION__);
 638                         return -EINVAL;
 639                 }
 640         } else {
 641                 printk(KERN_WARNING "%s: modulation type not supported!\n",
 642                        __FUNCTION__);
 643                 return -EINVAL;
 644         }
 645
 646         return tda18271_tune(fe, sgIF, freq, bw, std);
 647 }
 648
 649 static int tda18271_set_analog_params(struct dvb_frontend *fe,
 650                                       struct analog_parameters *params)
 651 {
 652         struct tda18271_priv *priv = fe->tuner_priv;
 653         u8 std;
 654         unsigned int sgIF;
 655         char *mode;
 656
 657         priv->mode = TDA18271_ANALOG;
 658
 659         /* see table 22 */
 660         if (params->std & V4L2_STD_MN) {
 661                 std = 0x0d;
 662                 sgIF =  92;
 663                 mode = "MN";
 664         } else if (params->std & V4L2_STD_B) {
 665                 std = 0x0e;
 666                 sgIF =  108;
 667                 mode = "B";
 668         } else if (params->std & V4L2_STD_GH) {
 669                 std = 0x0f;
 670                 sgIF =  124;
 671                 mode = "GH";
 672         } else if (params->std & V4L2_STD_PAL_I) {
 673                 std = 0x0f;
 674                 sgIF =  124;
 675                 mode = "I";
 676         } else if (params->std & V4L2_STD_DK) {
 677                 std = 0x0f;
 678                 sgIF =  124;
 679                 mode = "DK";
 680         } else if (params->std & V4L2_STD_SECAM_L) {
 681                 std = 0x0f;
 682                 sgIF =  124;
 683                 mode = "L";
 684         } else if (params->std & V4L2_STD_SECAM_LC) {
 685                 std = 0x0f;
 686                 sgIF =  20;
 687                 mode = "LC";
 688         } else {
 689                 std = 0x0f;
 690                 sgIF =  124;
 691                 mode = "xx";
 692         }
 693
 694         if (params->mode == V4L2_TUNER_RADIO)
 695                 sgIF =  88; /* if frequency is 5.5 MHz */
 696
 697         dbg_info("setting tda18271 to system %s\n", mode);
 698
 699         return tda18271_tune(fe, sgIF * 62500, params->frequency * 62500,
 700                              0, std);
 701 }
 702
 703 static int tda18271_release(struct dvb_frontend *fe)
 704 {
 705         kfree(fe->tuner_priv);
 706         fe->tuner_priv = NULL;
 707         return 0;
 708 }
 709
 710 static int tda18271_get_frequency(struct dvb_frontend *fe, u32 *frequency)
 711 {
 712         struct tda18271_priv *priv = fe->tuner_priv;
 713         *frequency = priv->frequency;
 714         return 0;
 715 }
 716
 717 static int tda18271_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
 718 {
 719         struct tda18271_priv *priv = fe->tuner_priv;
 720         *bandwidth = priv->bandwidth;
 721         return 0;
 722 }
 723
 724 static struct dvb_tuner_ops tda18271_tuner_ops = {
 725         .info = {
 726                 .name = "NXP TDA18271HD",
 727                 .frequency_min  =  45000000,
 728                 .frequency_max  = 864000000,
 729                 .frequency_step =     62500
 730         },
 731         .init              = tda18271_init,
 732         .set_params        = tda18271_set_params,
 733         .set_analog_params = tda18271_set_analog_params,
 734         .release           = tda18271_release,
 735         .get_frequency     = tda18271_get_frequency,
 736         .get_bandwidth     = tda18271_get_bandwidth,
 737 };
 738
 739 struct dvb_frontend *tda18271_attach(struct dvb_frontend *fe, u8 addr,
 740                                      struct i2c_adapter *i2c,
 741                                      enum tda18271_i2c_gate gate)
 742 {
 743         struct tda18271_priv *priv = NULL;
 744
 745         dbg_info("@ %d-%04x\n", i2c_adapter_id(i2c), addr);
 746         priv = kzalloc(sizeof(struct tda18271_priv), GFP_KERNEL);
 747         if (priv == NULL)
 748                 return NULL;
 749
 750         priv->i2c_addr = addr;
 751         priv->i2c_adap = i2c;
 752         priv->gate = gate;
 753
 754         memcpy(&fe->ops.tuner_ops, &tda18271_tuner_ops,
 755                sizeof(struct dvb_tuner_ops));
 756
 757         fe->tuner_priv = priv;
 758
 759         tda18271_init_regs(fe);
 760
 761         return fe;
 762 }
 763 EXPORT_SYMBOL_GPL(tda18271_attach);
 764 MODULE_DESCRIPTION("NXP TDA18271HD analog / digital tuner driver");
 765 MODULE_AUTHOR("Michael Krufky <mkrufky@linuxtv.org>");
 766 MODULE_LICENSE("GPL");
 767
 768 /*
 769  * Overrides for Emacs so that we follow Linus's tabbing style.
 770  * ---------------------------------------------------------------------------
 771  * Local variables:
 772  * c-basic-offset: 8
 773  * End:
 774  */