git.oblomov.eu Git - linux-2.6/blob - drivers/infiniband/hw/ipath/ipath_init_chip.c

   1 /*
   2  * Copyright (c) 2006, 2007, 2008 QLogic Corporation. All rights reserved.
   3  * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33
  34 #include <linux/pci.h>
  35 #include <linux/netdevice.h>
  36 #include <linux/vmalloc.h>
  37
  38 #include "ipath_kernel.h"
  39 #include "ipath_common.h"
  40
  41 /*
  42  * min buffers we want to have per port, after driver
  43  */
  44 #define IPATH_MIN_USER_PORT_BUFCNT 8
  45
  46 /*
  47  * Number of ports we are configured to use (to allow for more pio
  48  * buffers per port, etc.)  Zero means use chip value.
  49  */
  50 static ushort ipath_cfgports;
  51
  52 module_param_named(cfgports, ipath_cfgports, ushort, S_IRUGO);
  53 MODULE_PARM_DESC(cfgports, "Set max number of ports to use");
  54
  55 /*
  56  * Number of buffers reserved for driver (verbs and layered drivers.)
  57  * Reserved at end of buffer list.   Initialized based on
  58  * number of PIO buffers if not set via module interface.
  59  * The problem with this is that it's global, but we'll use different
  60  * numbers for different chip types.  So the default value is not
  61  * very useful.  I've redefined it for the 1.3 release so that it's
  62  * zero unless set by the user to something else, in which case we
  63  * try to respect it.
  64  */
  65 static ushort ipath_kpiobufs;
  66
  67 static int ipath_set_kpiobufs(const char *val, struct kernel_param *kp);
  68
  69 module_param_call(kpiobufs, ipath_set_kpiobufs, param_get_ushort,
  70                   &ipath_kpiobufs, S_IWUSR | S_IRUGO);
  71 MODULE_PARM_DESC(kpiobufs, "Set number of PIO buffers for driver");
  72
  73 /**
  74  * create_port0_egr - allocate the eager TID buffers
  75  * @dd: the infinipath device
  76  *
  77  * This code is now quite different for user and kernel, because
  78  * the kernel uses skb's, for the accelerated network performance.
  79  * This is the kernel (port0) version.
  80  *
  81  * Allocate the eager TID buffers and program them into infinipath.
  82  * We use the network layer alloc_skb() allocator to allocate the
  83  * memory, and either use the buffers as is for things like verbs
  84  * packets, or pass the buffers up to the ipath layered driver and
  85  * thence the network layer, replacing them as we do so (see
  86  * ipath_rcv_layer()).
  87  */
  88 static int create_port0_egr(struct ipath_devdata *dd)
  89 {
  90         unsigned e, egrcnt;
  91         struct ipath_skbinfo *skbinfo;
  92         int ret;
  93
  94         egrcnt = dd->ipath_p0_rcvegrcnt;
  95
  96         skbinfo = vmalloc(sizeof(*dd->ipath_port0_skbinfo) * egrcnt);
  97         if (skbinfo == NULL) {
  98                 ipath_dev_err(dd, "allocation error for eager TID "
  99                               "skb array\n");
 100                 ret = -ENOMEM;
 101                 goto bail;
 102         }
 103         for (e = 0; e < egrcnt; e++) {
 104                 /*
 105                  * This is a bit tricky in that we allocate extra
 106                  * space for 2 bytes of the 14 byte ethernet header.
 107                  * These two bytes are passed in the ipath header so
 108                  * the rest of the data is word aligned.  We allocate
 109                  * 4 bytes so that the data buffer stays word aligned.
 110                  * See ipath_kreceive() for more details.
 111                  */
 112                 skbinfo[e].skb = ipath_alloc_skb(dd, GFP_KERNEL);
 113                 if (!skbinfo[e].skb) {
 114                         ipath_dev_err(dd, "SKB allocation error for "
 115                                       "eager TID %u\n", e);
 116                         while (e != 0)
 117                                 dev_kfree_skb(skbinfo[--e].skb);
 118                         vfree(skbinfo);
 119                         ret = -ENOMEM;
 120                         goto bail;
 121                 }
 122         }
 123         /*
 124          * After loop above, so we can test non-NULL to see if ready
 125          * to use at receive, etc.
 126          */
 127         dd->ipath_port0_skbinfo = skbinfo;
 128
 129         for (e = 0; e < egrcnt; e++) {
 130                 dd->ipath_port0_skbinfo[e].phys =
 131                   ipath_map_single(dd->pcidev,
 132                                    dd->ipath_port0_skbinfo[e].skb->data,
 133                                    dd->ipath_ibmaxlen, PCI_DMA_FROMDEVICE);
 134                 dd->ipath_f_put_tid(dd, e + (u64 __iomem *)
 135                                     ((char __iomem *) dd->ipath_kregbase +
 136                                      dd->ipath_rcvegrbase),
 137                                     RCVHQ_RCV_TYPE_EAGER,
 138                                     dd->ipath_port0_skbinfo[e].phys);
 139         }
 140
 141         ret = 0;
 142
 143 bail:
 144         return ret;
 145 }
 146
 147 static int bringup_link(struct ipath_devdata *dd)
 148 {
 149         u64 val, ibc;
 150         int ret = 0;
 151
 152         /* hold IBC in reset */
 153         dd->ipath_control &= ~INFINIPATH_C_LINKENABLE;
 154         ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
 155                          dd->ipath_control);
 156
 157         /*
 158          * set initial max size pkt IBC will send, including ICRC; it's the
 159          * PIO buffer size in dwords, less 1; also see ipath_set_mtu()
 160          */
 161         val = (dd->ipath_ibmaxlen >> 2) + 1;
 162         ibc = val << dd->ibcc_mpl_shift;
 163
 164         /* flowcontrolwatermark is in units of KBytes */
 165         ibc |= 0x5ULL << INFINIPATH_IBCC_FLOWCTRLWATERMARK_SHIFT;
 166         /*
 167          * How often flowctrl sent.  More or less in usecs; balance against
 168          * watermark value, so that in theory senders always get a flow
 169          * control update in time to not let the IB link go idle.
 170          */
 171         ibc |= 0x3ULL << INFINIPATH_IBCC_FLOWCTRLPERIOD_SHIFT;
 172         /* max error tolerance */
 173         ibc |= 0xfULL << INFINIPATH_IBCC_PHYERRTHRESHOLD_SHIFT;
 174         /* use "real" buffer space for */
 175         ibc |= 4ULL << INFINIPATH_IBCC_CREDITSCALE_SHIFT;
 176         /* IB credit flow control. */
 177         ibc |= 0xfULL << INFINIPATH_IBCC_OVERRUNTHRESHOLD_SHIFT;
 178         /* initially come up waiting for TS1, without sending anything. */
 179         dd->ipath_ibcctrl = ibc;
 180         /*
 181          * Want to start out with both LINKCMD and LINKINITCMD in NOP
 182          * (0 and 0).  Don't put linkinitcmd in ipath_ibcctrl, want that
 183          * to stay a NOP. Flag that we are disabled, for the (unlikely)
 184          * case that some recovery path is trying to bring the link up
 185          * before we are ready.
 186          */
 187         ibc |= INFINIPATH_IBCC_LINKINITCMD_DISABLE <<
 188                 INFINIPATH_IBCC_LINKINITCMD_SHIFT;
 189         dd->ipath_flags |= IPATH_IB_LINK_DISABLED;
 190         ipath_cdbg(VERBOSE, "Writing 0x%llx to ibcctrl\n",
 191                    (unsigned long long) ibc);
 192         ipath_write_kreg(dd, dd->ipath_kregs->kr_ibcctrl, ibc);
 193
 194         // be sure chip saw it
 195         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
 196
 197         ret = dd->ipath_f_bringup_serdes(dd);
 198
 199         if (ret)
 200                 dev_info(&dd->pcidev->dev, "Could not initialize SerDes, "
 201                          "not usable\n");
 202         else {
 203                 /* enable IBC */
 204                 dd->ipath_control |= INFINIPATH_C_LINKENABLE;
 205                 ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
 206                                  dd->ipath_control);
 207         }
 208
 209         return ret;
 210 }
 211
 212 static struct ipath_portdata *create_portdata0(struct ipath_devdata *dd)
 213 {
 214         struct ipath_portdata *pd = NULL;
 215
 216         pd = kzalloc(sizeof(*pd), GFP_KERNEL);
 217         if (pd) {
 218                 pd->port_dd = dd;
 219                 pd->port_cnt = 1;
 220                 /* The port 0 pkey table is used by the layer interface. */
 221                 pd->port_pkeys[0] = IPATH_DEFAULT_P_KEY;
 222                 pd->port_seq_cnt = 1;
 223         }
 224         return pd;
 225 }
 226
 227 static int init_chip_first(struct ipath_devdata *dd)
 228 {
 229         struct ipath_portdata *pd;
 230         int ret = 0;
 231         u64 val;
 232
 233         spin_lock_init(&dd->ipath_kernel_tid_lock);
 234         spin_lock_init(&dd->ipath_user_tid_lock);
 235         spin_lock_init(&dd->ipath_sendctrl_lock);
 236         spin_lock_init(&dd->ipath_sdma_lock);
 237         spin_lock_init(&dd->ipath_gpio_lock);
 238         spin_lock_init(&dd->ipath_eep_st_lock);
 239         spin_lock_init(&dd->ipath_sdepb_lock);
 240         mutex_init(&dd->ipath_eep_lock);
 241
 242         /*
 243          * skip cfgports stuff because we are not allocating memory,
 244          * and we don't want problems if the portcnt changed due to
 245          * cfgports.  We do still check and report a difference, if
 246          * not same (should be impossible).
 247          */
 248         dd->ipath_f_config_ports(dd, ipath_cfgports);
 249         if (!ipath_cfgports)
 250                 dd->ipath_cfgports = dd->ipath_portcnt;
 251         else if (ipath_cfgports <= dd->ipath_portcnt) {
 252                 dd->ipath_cfgports = ipath_cfgports;
 253                 ipath_dbg("Configured to use %u ports out of %u in chip\n",
 254                           dd->ipath_cfgports, ipath_read_kreg32(dd,
 255                           dd->ipath_kregs->kr_portcnt));
 256         } else {
 257                 dd->ipath_cfgports = dd->ipath_portcnt;
 258                 ipath_dbg("Tried to configured to use %u ports; chip "
 259                           "only supports %u\n", ipath_cfgports,
 260                           ipath_read_kreg32(dd,
 261                                   dd->ipath_kregs->kr_portcnt));
 262         }
 263         /*
 264          * Allocate full portcnt array, rather than just cfgports, because
 265          * cleanup iterates across all possible ports.
 266          */
 267         dd->ipath_pd = kzalloc(sizeof(*dd->ipath_pd) * dd->ipath_portcnt,
 268                                GFP_KERNEL);
 269
 270         if (!dd->ipath_pd) {
 271                 ipath_dev_err(dd, "Unable to allocate portdata array, "
 272                               "failing\n");
 273                 ret = -ENOMEM;
 274                 goto done;
 275         }
 276
 277         pd = create_portdata0(dd);
 278         if (!pd) {
 279                 ipath_dev_err(dd, "Unable to allocate portdata for port "
 280                               "0, failing\n");
 281                 ret = -ENOMEM;
 282                 goto done;
 283         }
 284         dd->ipath_pd[0] = pd;
 285
 286         dd->ipath_rcvtidcnt =
 287                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidcnt);
 288         dd->ipath_rcvtidbase =
 289                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidbase);
 290         dd->ipath_rcvegrcnt =
 291                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrcnt);
 292         dd->ipath_rcvegrbase =
 293                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrbase);
 294         dd->ipath_palign =
 295                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_pagealign);
 296         dd->ipath_piobufbase =
 297                 ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiobufbase);
 298         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiosize);
 299         dd->ipath_piosize2k = val & ~0U;
 300         dd->ipath_piosize4k = val >> 32;
 301         if (dd->ipath_piosize4k == 0 && ipath_mtu4096)
 302                 ipath_mtu4096 = 0; /* 4KB not supported by this chip */
 303         dd->ipath_ibmtu = ipath_mtu4096 ? 4096 : 2048;
 304         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpiobufcnt);
 305         dd->ipath_piobcnt2k = val & ~0U;
 306         dd->ipath_piobcnt4k = val >> 32;
 307         dd->ipath_pio2kbase =
 308                 (u32 __iomem *) (((char __iomem *) dd->ipath_kregbase) +
 309                                  (dd->ipath_piobufbase & 0xffffffff));
 310         if (dd->ipath_piobcnt4k) {
 311                 dd->ipath_pio4kbase = (u32 __iomem *)
 312                         (((char __iomem *) dd->ipath_kregbase) +
 313                          (dd->ipath_piobufbase >> 32));
 314                 /*
 315                  * 4K buffers take 2 pages; we use roundup just to be
 316                  * paranoid; we calculate it once here, rather than on
 317                  * ever buf allocate
 318                  */
 319                 dd->ipath_4kalign = ALIGN(dd->ipath_piosize4k,
 320                                           dd->ipath_palign);
 321                 ipath_dbg("%u 2k(%x) piobufs @ %p, %u 4k(%x) @ %p "
 322                           "(%x aligned)\n",
 323                           dd->ipath_piobcnt2k, dd->ipath_piosize2k,
 324                           dd->ipath_pio2kbase, dd->ipath_piobcnt4k,
 325                           dd->ipath_piosize4k, dd->ipath_pio4kbase,
 326                           dd->ipath_4kalign);
 327         }
 328         else ipath_dbg("%u 2k piobufs @ %p\n",
 329                        dd->ipath_piobcnt2k, dd->ipath_pio2kbase);
 330
 331 done:
 332         return ret;
 333 }
 334
 335 /**
 336  * init_chip_reset - re-initialize after a reset, or enable
 337  * @dd: the infinipath device
 338  *
 339  * sanity check at least some of the values after reset, and
 340  * ensure no receive or transmit (explictly, in case reset
 341  * failed
 342  */
 343 static int init_chip_reset(struct ipath_devdata *dd)
 344 {
 345         u32 rtmp;
 346         int i;
 347         unsigned long flags;
 348
 349         /*
 350          * ensure chip does no sends or receives, tail updates, or
 351          * pioavail updates while we re-initialize
 352          */
 353         dd->ipath_rcvctrl &= ~(1ULL << dd->ipath_r_tailupd_shift);
 354         for (i = 0; i < dd->ipath_portcnt; i++) {
 355                 clear_bit(dd->ipath_r_portenable_shift + i,
 356                           &dd->ipath_rcvctrl);
 357                 clear_bit(dd->ipath_r_intravail_shift + i,
 358                           &dd->ipath_rcvctrl);
 359         }
 360         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
 361                 dd->ipath_rcvctrl);
 362
 363         spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
 364         dd->ipath_sendctrl = 0U; /* no sdma, etc */
 365         ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, dd->ipath_sendctrl);
 366         ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
 367         spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
 368
 369         ipath_write_kreg(dd, dd->ipath_kregs->kr_control, 0ULL);
 370
 371         rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidcnt);
 372         if (rtmp != dd->ipath_rcvtidcnt)
 373                 dev_info(&dd->pcidev->dev, "tidcnt was %u before "
 374                          "reset, now %u, using original\n",
 375                          dd->ipath_rcvtidcnt, rtmp);
 376         rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvtidbase);
 377         if (rtmp != dd->ipath_rcvtidbase)
 378                 dev_info(&dd->pcidev->dev, "tidbase was %u before "
 379                          "reset, now %u, using original\n",
 380                          dd->ipath_rcvtidbase, rtmp);
 381         rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrcnt);
 382         if (rtmp != dd->ipath_rcvegrcnt)
 383                 dev_info(&dd->pcidev->dev, "egrcnt was %u before "
 384                          "reset, now %u, using original\n",
 385                          dd->ipath_rcvegrcnt, rtmp);
 386         rtmp = ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrbase);
 387         if (rtmp != dd->ipath_rcvegrbase)
 388                 dev_info(&dd->pcidev->dev, "egrbase was %u before "
 389                          "reset, now %u, using original\n",
 390                          dd->ipath_rcvegrbase, rtmp);
 391
 392         return 0;
 393 }
 394
 395 static int init_pioavailregs(struct ipath_devdata *dd)
 396 {
 397         int ret;
 398
 399         dd->ipath_pioavailregs_dma = dma_alloc_coherent(
 400                 &dd->pcidev->dev, PAGE_SIZE, &dd->ipath_pioavailregs_phys,
 401                 GFP_KERNEL);
 402         if (!dd->ipath_pioavailregs_dma) {
 403                 ipath_dev_err(dd, "failed to allocate PIOavail reg area "
 404                               "in memory\n");
 405                 ret = -ENOMEM;
 406                 goto done;
 407         }
 408
 409         /*
 410          * we really want L2 cache aligned, but for current CPUs of
 411          * interest, they are the same.
 412          */
 413         dd->ipath_statusp = (u64 *)
 414                 ((char *)dd->ipath_pioavailregs_dma +
 415                  ((2 * L1_CACHE_BYTES +
 416                    dd->ipath_pioavregs * sizeof(u64)) & ~L1_CACHE_BYTES));
 417         /* copy the current value now that it's really allocated */
 418         *dd->ipath_statusp = dd->_ipath_status;
 419         /*
 420          * setup buffer to hold freeze msg, accessible to apps,
 421          * following statusp
 422          */
 423         dd->ipath_freezemsg = (char *)&dd->ipath_statusp[1];
 424         /* and its length */
 425         dd->ipath_freezelen = L1_CACHE_BYTES - sizeof(dd->ipath_statusp[0]);
 426
 427         ret = 0;
 428
 429 done:
 430         return ret;
 431 }
 432
 433 /**
 434  * init_shadow_tids - allocate the shadow TID array
 435  * @dd: the infinipath device
 436  *
 437  * allocate the shadow TID array, so we can ipath_munlock previous
 438  * entries.  It may make more sense to move the pageshadow to the
 439  * port data structure, so we only allocate memory for ports actually
 440  * in use, since we at 8k per port, now.
 441  */
 442 static void init_shadow_tids(struct ipath_devdata *dd)
 443 {
 444         struct page **pages;
 445         dma_addr_t *addrs;
 446
 447         pages = vmalloc(dd->ipath_cfgports * dd->ipath_rcvtidcnt *
 448                         sizeof(struct page *));
 449         if (!pages) {
 450                 ipath_dev_err(dd, "failed to allocate shadow page * "
 451                               "array, no expected sends!\n");
 452                 dd->ipath_pageshadow = NULL;
 453                 return;
 454         }
 455
 456         addrs = vmalloc(dd->ipath_cfgports * dd->ipath_rcvtidcnt *
 457                         sizeof(dma_addr_t));
 458         if (!addrs) {
 459                 ipath_dev_err(dd, "failed to allocate shadow dma handle "
 460                               "array, no expected sends!\n");
 461                 vfree(dd->ipath_pageshadow);
 462                 dd->ipath_pageshadow = NULL;
 463                 return;
 464         }
 465
 466         memset(pages, 0, dd->ipath_cfgports * dd->ipath_rcvtidcnt *
 467                sizeof(struct page *));
 468
 469         dd->ipath_pageshadow = pages;
 470         dd->ipath_physshadow = addrs;
 471 }
 472
 473 static void enable_chip(struct ipath_devdata *dd, int reinit)
 474 {
 475         u32 val;
 476         u64 rcvmask;
 477         unsigned long flags;
 478         int i;
 479
 480         if (!reinit)
 481                 init_waitqueue_head(&ipath_state_wait);
 482
 483         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
 484                          dd->ipath_rcvctrl);
 485
 486         spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
 487         /* Enable PIO send, and update of PIOavail regs to memory. */
 488         dd->ipath_sendctrl = INFINIPATH_S_PIOENABLE |
 489                 INFINIPATH_S_PIOBUFAVAILUPD;
 490
 491         /*
 492          * Set the PIO avail update threshold to host memory
 493          * on chips that support it.
 494          */
 495         if (dd->ipath_pioupd_thresh)
 496                 dd->ipath_sendctrl |= dd->ipath_pioupd_thresh
 497                         << INFINIPATH_S_UPDTHRESH_SHIFT;
 498         ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, dd->ipath_sendctrl);
 499         ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
 500         spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
 501
 502         /*
 503          * Enable kernel ports' receive and receive interrupt.
 504          * Other ports done as user opens and inits them.
 505          */
 506         rcvmask = 1ULL;
 507         dd->ipath_rcvctrl |= (rcvmask << dd->ipath_r_portenable_shift) |
 508                 (rcvmask << dd->ipath_r_intravail_shift);
 509         if (!(dd->ipath_flags & IPATH_NODMA_RTAIL))
 510                 dd->ipath_rcvctrl |= (1ULL << dd->ipath_r_tailupd_shift);
 511
 512         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
 513                          dd->ipath_rcvctrl);
 514
 515         /*
 516          * now ready for use.  this should be cleared whenever we
 517          * detect a reset, or initiate one.
 518          */
 519         dd->ipath_flags |= IPATH_INITTED;
 520
 521         /*
 522          * Init our shadow copies of head from tail values,
 523          * and write head values to match.
 524          */
 525         val = ipath_read_ureg32(dd, ur_rcvegrindextail, 0);
 526         ipath_write_ureg(dd, ur_rcvegrindexhead, val, 0);
 527
 528         /* Initialize so we interrupt on next packet received */
 529         ipath_write_ureg(dd, ur_rcvhdrhead,
 530                          dd->ipath_rhdrhead_intr_off |
 531                          dd->ipath_pd[0]->port_head, 0);
 532
 533         /*
 534          * by now pioavail updates to memory should have occurred, so
 535          * copy them into our working/shadow registers; this is in
 536          * case something went wrong with abort, but mostly to get the
 537          * initial values of the generation bit correct.
 538          */
 539         for (i = 0; i < dd->ipath_pioavregs; i++) {
 540                 __le64 pioavail;
 541
 542                 /*
 543                  * Chip Errata bug 6641; even and odd qwords>3 are swapped.
 544                  */
 545                 if (i > 3 && (dd->ipath_flags & IPATH_SWAP_PIOBUFS))
 546                         pioavail = dd->ipath_pioavailregs_dma[i ^ 1];
 547                 else
 548                         pioavail = dd->ipath_pioavailregs_dma[i];
 549                 dd->ipath_pioavailshadow[i] = le64_to_cpu(pioavail) |
 550                         (~dd->ipath_pioavailkernel[i] <<
 551                         INFINIPATH_SENDPIOAVAIL_BUSY_SHIFT);
 552         }
 553         /* can get counters, stats, etc. */
 554         dd->ipath_flags |= IPATH_PRESENT;
 555 }
 556
 557 static int init_housekeeping(struct ipath_devdata *dd, int reinit)
 558 {
 559         char boardn[40];
 560         int ret = 0;
 561
 562         /*
 563          * have to clear shadow copies of registers at init that are
 564          * not otherwise set here, or all kinds of bizarre things
 565          * happen with driver on chip reset
 566          */
 567         dd->ipath_rcvhdrsize = 0;
 568
 569         /*
 570          * Don't clear ipath_flags as 8bit mode was set before
 571          * entering this func. However, we do set the linkstate to
 572          * unknown, so we can watch for a transition.
 573          * PRESENT is set because we want register reads to work,
 574          * and the kernel infrastructure saw it in config space;
 575          * We clear it if we have failures.
 576          */
 577         dd->ipath_flags |= IPATH_LINKUNK | IPATH_PRESENT;
 578         dd->ipath_flags &= ~(IPATH_LINKACTIVE | IPATH_LINKARMED |
 579                              IPATH_LINKDOWN | IPATH_LINKINIT);
 580
 581         ipath_cdbg(VERBOSE, "Try to read spc chip revision\n");
 582         dd->ipath_revision =
 583                 ipath_read_kreg64(dd, dd->ipath_kregs->kr_revision);
 584
 585         /*
 586          * set up fundamental info we need to use the chip; we assume
 587          * if the revision reg and these regs are OK, we don't need to
 588          * special case the rest
 589          */
 590         dd->ipath_sregbase =
 591                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_sendregbase);
 592         dd->ipath_cregbase =
 593                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_counterregbase);
 594         dd->ipath_uregbase =
 595                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_userregbase);
 596         ipath_cdbg(VERBOSE, "ipath_kregbase %p, sendbase %x usrbase %x, "
 597                    "cntrbase %x\n", dd->ipath_kregbase, dd->ipath_sregbase,
 598                    dd->ipath_uregbase, dd->ipath_cregbase);
 599         if ((dd->ipath_revision & 0xffffffff) == 0xffffffff
 600             || (dd->ipath_sregbase & 0xffffffff) == 0xffffffff
 601             || (dd->ipath_cregbase & 0xffffffff) == 0xffffffff
 602             || (dd->ipath_uregbase & 0xffffffff) == 0xffffffff) {
 603                 ipath_dev_err(dd, "Register read failures from chip, "
 604                               "giving up initialization\n");
 605                 dd->ipath_flags &= ~IPATH_PRESENT;
 606                 ret = -ENODEV;
 607                 goto done;
 608         }
 609
 610
 611         /* clear diagctrl register, in case diags were running and crashed */
 612         ipath_write_kreg (dd, dd->ipath_kregs->kr_hwdiagctrl, 0);
 613
 614         /* clear the initial reset flag, in case first driver load */
 615         ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear,
 616                          INFINIPATH_E_RESET);
 617
 618         ipath_cdbg(VERBOSE, "Revision %llx (PCI %x)\n",
 619                    (unsigned long long) dd->ipath_revision,
 620                    dd->ipath_pcirev);
 621
 622         if (((dd->ipath_revision >> INFINIPATH_R_SOFTWARE_SHIFT) &
 623              INFINIPATH_R_SOFTWARE_MASK) != IPATH_CHIP_SWVERSION) {
 624                 ipath_dev_err(dd, "Driver only handles version %d, "
 625                               "chip swversion is %d (%llx), failng\n",
 626                               IPATH_CHIP_SWVERSION,
 627                               (int)(dd->ipath_revision >>
 628                                     INFINIPATH_R_SOFTWARE_SHIFT) &
 629                               INFINIPATH_R_SOFTWARE_MASK,
 630                               (unsigned long long) dd->ipath_revision);
 631                 ret = -ENOSYS;
 632                 goto done;
 633         }
 634         dd->ipath_majrev = (u8) ((dd->ipath_revision >>
 635                                   INFINIPATH_R_CHIPREVMAJOR_SHIFT) &
 636                                  INFINIPATH_R_CHIPREVMAJOR_MASK);
 637         dd->ipath_minrev = (u8) ((dd->ipath_revision >>
 638                                   INFINIPATH_R_CHIPREVMINOR_SHIFT) &
 639                                  INFINIPATH_R_CHIPREVMINOR_MASK);
 640         dd->ipath_boardrev = (u8) ((dd->ipath_revision >>
 641                                     INFINIPATH_R_BOARDID_SHIFT) &
 642                                    INFINIPATH_R_BOARDID_MASK);
 643
 644         ret = dd->ipath_f_get_boardname(dd, boardn, sizeof boardn);
 645
 646         snprintf(dd->ipath_boardversion, sizeof(dd->ipath_boardversion),
 647                  "ChipABI %u.%u, %s, InfiniPath%u %u.%u, PCI %u, "
 648                  "SW Compat %u\n",
 649                  IPATH_CHIP_VERS_MAJ, IPATH_CHIP_VERS_MIN, boardn,
 650                  (unsigned)(dd->ipath_revision >> INFINIPATH_R_ARCH_SHIFT) &
 651                  INFINIPATH_R_ARCH_MASK,
 652                  dd->ipath_majrev, dd->ipath_minrev, dd->ipath_pcirev,
 653                  (unsigned)(dd->ipath_revision >>
 654                             INFINIPATH_R_SOFTWARE_SHIFT) &
 655                  INFINIPATH_R_SOFTWARE_MASK);
 656
 657         ipath_dbg("%s", dd->ipath_boardversion);
 658
 659         if (ret)
 660                 goto done;
 661
 662         if (reinit)
 663                 ret = init_chip_reset(dd);
 664         else
 665                 ret = init_chip_first(dd);
 666
 667 done:
 668         return ret;
 669 }
 670
 671 static void verify_interrupt(unsigned long opaque)
 672 {
 673         struct ipath_devdata *dd = (struct ipath_devdata *) opaque;
 674
 675         if (!dd)
 676                 return; /* being torn down */
 677
 678         /*
 679          * If we don't have any interrupts, let the user know and
 680          * don't bother checking again.
 681          */
 682         if (dd->ipath_int_counter == 0) {
 683                 if (!dd->ipath_f_intr_fallback(dd))
 684                         dev_err(&dd->pcidev->dev, "No interrupts detected, "
 685                                 "not usable.\n");
 686                 else /* re-arm the timer to see if fallback works */
 687                         mod_timer(&dd->ipath_intrchk_timer, jiffies + HZ/2);
 688         } else
 689                 ipath_cdbg(VERBOSE, "%u interrupts at timer check\n",
 690                         dd->ipath_int_counter);
 691 }
 692
 693 /**
 694  * ipath_init_chip - do the actual initialization sequence on the chip
 695  * @dd: the infinipath device
 696  * @reinit: reinitializing, so don't allocate new memory
 697  *
 698  * Do the actual initialization sequence on the chip.  This is done
 699  * both from the init routine called from the PCI infrastructure, and
 700  * when we reset the chip, or detect that it was reset internally,
 701  * or it's administratively re-enabled.
 702  *
 703  * Memory allocation here and in called routines is only done in
 704  * the first case (reinit == 0).  We have to be careful, because even
 705  * without memory allocation, we need to re-write all the chip registers
 706  * TIDs, etc. after the reset or enable has completed.
 707  */
 708 int ipath_init_chip(struct ipath_devdata *dd, int reinit)
 709 {
 710         int ret = 0;
 711         u32 val32, kpiobufs;
 712         u32 piobufs, uports;
 713         u64 val;
 714         struct ipath_portdata *pd;
 715         gfp_t gfp_flags = GFP_USER | __GFP_COMP;
 716         unsigned long flags;
 717
 718         ret = init_housekeeping(dd, reinit);
 719         if (ret)
 720                 goto done;
 721
 722         /*
 723          * we ignore most issues after reporting them, but have to specially
 724          * handle hardware-disabled chips.
 725          */
 726         if (ret == 2) {
 727                 /* unique error, known to ipath_init_one */
 728                 ret = -EPERM;
 729                 goto done;
 730         }
 731
 732         /*
 733          * We could bump this to allow for full rcvegrcnt + rcvtidcnt,
 734          * but then it no longer nicely fits power of two, and since
 735          * we now use routines that backend onto __get_free_pages, the
 736          * rest would be wasted.
 737          */
 738         dd->ipath_rcvhdrcnt = max(dd->ipath_p0_rcvegrcnt, dd->ipath_rcvegrcnt);
 739         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrcnt,
 740                          dd->ipath_rcvhdrcnt);
 741
 742         /*
 743          * Set up the shadow copies of the piobufavail registers,
 744          * which we compare against the chip registers for now, and
 745          * the in memory DMA'ed copies of the registers.  This has to
 746          * be done early, before we calculate lastport, etc.
 747          */
 748         piobufs = dd->ipath_piobcnt2k + dd->ipath_piobcnt4k;
 749         /*
 750          * calc number of pioavail registers, and save it; we have 2
 751          * bits per buffer.
 752          */
 753         dd->ipath_pioavregs = ALIGN(piobufs, sizeof(u64) * BITS_PER_BYTE / 2)
 754                 / (sizeof(u64) * BITS_PER_BYTE / 2);
 755         uports = dd->ipath_cfgports ? dd->ipath_cfgports - 1 : 0;
 756         if (ipath_kpiobufs == 0) {
 757                 /* not set by user (this is default) */
 758                 if (piobufs > 144)
 759                         kpiobufs = 32;
 760                 else
 761                         kpiobufs = 16;
 762         }
 763         else
 764                 kpiobufs = ipath_kpiobufs;
 765
 766         if (kpiobufs + (uports * IPATH_MIN_USER_PORT_BUFCNT) > piobufs) {
 767                 int i = (int) piobufs -
 768                         (int) (uports * IPATH_MIN_USER_PORT_BUFCNT);
 769                 if (i < 1)
 770                         i = 1;
 771                 dev_info(&dd->pcidev->dev, "Allocating %d PIO bufs of "
 772                          "%d for kernel leaves too few for %d user ports "
 773                          "(%d each); using %u\n", kpiobufs,
 774                          piobufs, uports, IPATH_MIN_USER_PORT_BUFCNT, i);
 775                 /*
 776                  * shouldn't change ipath_kpiobufs, because could be
 777                  * different for different devices...
 778                  */
 779                 kpiobufs = i;
 780         }
 781         dd->ipath_lastport_piobuf = piobufs - kpiobufs;
 782         dd->ipath_pbufsport =
 783                 uports ? dd->ipath_lastport_piobuf / uports : 0;
 784         val32 = dd->ipath_lastport_piobuf - (dd->ipath_pbufsport * uports);
 785         if (val32 > 0) {
 786                 ipath_dbg("allocating %u pbufs/port leaves %u unused, "
 787                           "add to kernel\n", dd->ipath_pbufsport, val32);
 788                 dd->ipath_lastport_piobuf -= val32;
 789                 kpiobufs += val32;
 790                 ipath_dbg("%u pbufs/port leaves %u unused, add to kernel\n",
 791                           dd->ipath_pbufsport, val32);
 792         }
 793         dd->ipath_lastpioindex = 0;
 794         dd->ipath_lastpioindexl = dd->ipath_piobcnt2k;
 795         ipath_chg_pioavailkernel(dd, 0, piobufs, 1);
 796         ipath_cdbg(VERBOSE, "%d PIO bufs for kernel out of %d total %u "
 797                    "each for %u user ports\n", kpiobufs,
 798                    piobufs, dd->ipath_pbufsport, uports);
 799         if (dd->ipath_pioupd_thresh) {
 800                 if (dd->ipath_pbufsport < dd->ipath_pioupd_thresh)
 801                         dd->ipath_pioupd_thresh = dd->ipath_pbufsport;
 802                 if (kpiobufs < dd->ipath_pioupd_thresh)
 803                         dd->ipath_pioupd_thresh = kpiobufs;
 804         }
 805
 806         ret = dd->ipath_f_early_init(dd);
 807         if (ret) {
 808                 ipath_dev_err(dd, "Early initialization failure\n");
 809                 goto done;
 810         }
 811
 812         /*
 813          * Cancel any possible active sends from early driver load.
 814          * Follows early_init because some chips have to initialize
 815          * PIO buffers in early_init to avoid false parity errors.
 816          */
 817         ipath_cancel_sends(dd, 0);
 818
 819         /*
 820          * Early_init sets rcvhdrentsize and rcvhdrsize, so this must be
 821          * done after early_init.
 822          */
 823         dd->ipath_hdrqlast =
 824                 dd->ipath_rcvhdrentsize * (dd->ipath_rcvhdrcnt - 1);
 825         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrentsize,
 826                          dd->ipath_rcvhdrentsize);
 827         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvhdrsize,
 828                          dd->ipath_rcvhdrsize);
 829
 830         if (!reinit) {
 831                 ret = init_pioavailregs(dd);
 832                 init_shadow_tids(dd);
 833                 if (ret)
 834                         goto done;
 835         }
 836
 837         ipath_write_kreg(dd, dd->ipath_kregs->kr_sendpioavailaddr,
 838                          dd->ipath_pioavailregs_phys);
 839         /*
 840          * this is to detect s/w errors, which the h/w works around by
 841          * ignoring the low 6 bits of address, if it wasn't aligned.
 842          */
 843         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_sendpioavailaddr);
 844         if (val != dd->ipath_pioavailregs_phys) {
 845                 ipath_dev_err(dd, "Catastrophic software error, "
 846                               "SendPIOAvailAddr written as %lx, "
 847                               "read back as %llx\n",
 848                               (unsigned long) dd->ipath_pioavailregs_phys,
 849                               (unsigned long long) val);
 850                 ret = -EINVAL;
 851                 goto done;
 852         }
 853
 854         ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvbthqp, IPATH_KD_QP);
 855
 856         /*
 857          * make sure we are not in freeze, and PIO send enabled, so
 858          * writes to pbc happen
 859          */
 860         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask, 0ULL);
 861         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
 862                          ~0ULL&~INFINIPATH_HWE_MEMBISTFAILED);
 863         ipath_write_kreg(dd, dd->ipath_kregs->kr_control, 0ULL);
 864
 865         spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
 866         dd->ipath_sendctrl = INFINIPATH_S_PIOENABLE;
 867         ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl, dd->ipath_sendctrl);
 868         ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
 869         spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
 870
 871         /*
 872          * before error clears, since we expect serdes pll errors during
 873          * this, the first time after reset
 874          */
 875         if (bringup_link(dd)) {
 876                 dev_info(&dd->pcidev->dev, "Failed to bringup IB link\n");
 877                 ret = -ENETDOWN;
 878                 goto done;
 879         }
 880
 881         /*
 882          * clear any "expected" hwerrs from reset and/or initialization
 883          * clear any that aren't enabled (at least this once), and then
 884          * set the enable mask
 885          */
 886         dd->ipath_f_init_hwerrors(dd);
 887         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
 888                          ~0ULL&~INFINIPATH_HWE_MEMBISTFAILED);
 889         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 890                          dd->ipath_hwerrmask);
 891
 892         /* clear all */
 893         ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, -1LL);
 894         /* enable errors that are masked, at least this first time. */
 895         ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask,
 896                          ~dd->ipath_maskederrs);
 897         dd->ipath_maskederrs = 0; /* don't re-enable ignored in timer */
 898         dd->ipath_errormask =
 899                 ipath_read_kreg64(dd, dd->ipath_kregs->kr_errormask);
 900         /* clear any interrupts up to this point (ints still not enabled) */
 901         ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, -1LL);
 902
 903         dd->ipath_f_tidtemplate(dd);
 904
 905         /*
 906          * Set up the port 0 (kernel) rcvhdr q and egr TIDs.  If doing
 907          * re-init, the simplest way to handle this is to free
 908          * existing, and re-allocate.
 909          * Need to re-create rest of port 0 portdata as well.
 910          */
 911         pd = dd->ipath_pd[0];
 912         if (reinit) {
 913                 struct ipath_portdata *npd;
 914
 915                 /*
 916                  * Alloc and init new ipath_portdata for port0,
 917                  * Then free old pd. Could lead to fragmentation, but also
 918                  * makes later support for hot-swap easier.
 919                  */
 920                 npd = create_portdata0(dd);
 921                 if (npd) {
 922                         ipath_free_pddata(dd, pd);
 923                         dd->ipath_pd[0] = npd;
 924                         pd = npd;
 925                 } else {
 926                         ipath_dev_err(dd, "Unable to allocate portdata"
 927                                       " for port 0, failing\n");
 928                         ret = -ENOMEM;
 929                         goto done;
 930                 }
 931         }
 932         ret = ipath_create_rcvhdrq(dd, pd);
 933         if (!ret)
 934                 ret = create_port0_egr(dd);
 935         if (ret) {
 936                 ipath_dev_err(dd, "failed to allocate kernel port's "
 937                               "rcvhdrq and/or egr bufs\n");
 938                 goto done;
 939         }
 940         else
 941                 enable_chip(dd, reinit);
 942
 943         if (!reinit) {
 944                 /*
 945                  * Used when we close a port, for DMA already in flight
 946                  * at close.
 947                  */
 948                 dd->ipath_dummy_hdrq = dma_alloc_coherent(
 949                         &dd->pcidev->dev, dd->ipath_pd[0]->port_rcvhdrq_size,
 950                         &dd->ipath_dummy_hdrq_phys,
 951                         gfp_flags);
 952                 if (!dd->ipath_dummy_hdrq) {
 953                         dev_info(&dd->pcidev->dev,
 954                                 "Couldn't allocate 0x%lx bytes for dummy hdrq\n",
 955                                 dd->ipath_pd[0]->port_rcvhdrq_size);
 956                         /* fallback to just 0'ing */
 957                         dd->ipath_dummy_hdrq_phys = 0UL;
 958                 }
 959         }
 960
 961         /*
 962          * cause retrigger of pending interrupts ignored during init,
 963          * even if we had errors
 964          */
 965         ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, 0ULL);
 966
 967         if (!dd->ipath_stats_timer_active) {
 968                 /*
 969                  * first init, or after an admin disable/enable
 970                  * set up stats retrieval timer, even if we had errors
 971                  * in last portion of setup
 972                  */
 973                 init_timer(&dd->ipath_stats_timer);
 974                 dd->ipath_stats_timer.function = ipath_get_faststats;
 975                 dd->ipath_stats_timer.data = (unsigned long) dd;
 976                 /* every 5 seconds; */
 977                 dd->ipath_stats_timer.expires = jiffies + 5 * HZ;
 978                 /* takes ~16 seconds to overflow at full IB 4x bandwdith */
 979                 add_timer(&dd->ipath_stats_timer);
 980                 dd->ipath_stats_timer_active = 1;
 981         }
 982
 983         /* Set up SendDMA if chip supports it */
 984         if (dd->ipath_flags & IPATH_HAS_SEND_DMA)
 985                 ret = setup_sdma(dd);
 986
 987         /* Set up HoL state */
 988         init_timer(&dd->ipath_hol_timer);
 989         dd->ipath_hol_timer.function = ipath_hol_event;
 990         dd->ipath_hol_timer.data = (unsigned long)dd;
 991         dd->ipath_hol_state = IPATH_HOL_UP;
 992
 993 done:
 994         if (!ret) {
 995                 *dd->ipath_statusp |= IPATH_STATUS_CHIP_PRESENT;
 996                 if (!dd->ipath_f_intrsetup(dd)) {
 997                         /* now we can enable all interrupts from the chip */
 998                         ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask,
 999                                          -1LL);
1000                         /* force re-interrupt of any pending interrupts. */
1001                         ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear,
1002                                          0ULL);
1003                         /* chip is usable; mark it as initialized */
1004                         *dd->ipath_statusp |= IPATH_STATUS_INITTED;
1005
1006                         /*
1007                          * setup to verify we get an interrupt, and fallback
1008                          * to an alternate if necessary and possible
1009                          */
1010                         if (!reinit) {
1011                                 init_timer(&dd->ipath_intrchk_timer);
1012                                 dd->ipath_intrchk_timer.function =
1013                                         verify_interrupt;
1014                                 dd->ipath_intrchk_timer.data =
1015                                         (unsigned long) dd;
1016                         }
1017                         dd->ipath_intrchk_timer.expires = jiffies + HZ/2;
1018                         add_timer(&dd->ipath_intrchk_timer);
1019                 } else
1020                         ipath_dev_err(dd, "No interrupts enabled, couldn't "
1021                                       "setup interrupt address\n");
1022
1023                 if (dd->ipath_cfgports > ipath_stats.sps_nports)
1024                         /*
1025                          * sps_nports is a global, so, we set it to
1026                          * the highest number of ports of any of the
1027                          * chips we find; we never decrement it, at
1028                          * least for now.  Since this might have changed
1029                          * over disable/enable or prior to reset, always
1030                          * do the check and potentially adjust.
1031                          */
1032                         ipath_stats.sps_nports = dd->ipath_cfgports;
1033         } else
1034                 ipath_dbg("Failed (%d) to initialize chip\n", ret);
1035
1036         /* if ret is non-zero, we probably should do some cleanup
1037            here... */
1038         return ret;
1039 }
1040
1041 static int ipath_set_kpiobufs(const char *str, struct kernel_param *kp)
1042 {
1043         struct ipath_devdata *dd;
1044         unsigned long flags;
1045         unsigned short val;
1046         int ret;
1047
1048         ret = ipath_parse_ushort(str, &val);
1049
1050         spin_lock_irqsave(&ipath_devs_lock, flags);
1051
1052         if (ret < 0)
1053                 goto bail;
1054
1055         if (val == 0) {
1056                 ret = -EINVAL;
1057                 goto bail;
1058         }
1059
1060         list_for_each_entry(dd, &ipath_dev_list, ipath_list) {
1061                 if (dd->ipath_kregbase)
1062                         continue;
1063                 if (val > (dd->ipath_piobcnt2k + dd->ipath_piobcnt4k -
1064                            (dd->ipath_cfgports *
1065                             IPATH_MIN_USER_PORT_BUFCNT)))
1066                 {
1067                         ipath_dev_err(
1068                                 dd,
1069                                 "Allocating %d PIO bufs for kernel leaves "
1070                                 "too few for %d user ports (%d each)\n",
1071                                 val, dd->ipath_cfgports - 1,
1072                                 IPATH_MIN_USER_PORT_BUFCNT);
1073                         ret = -EINVAL;
1074                         goto bail;
1075                 }
1076                 dd->ipath_lastport_piobuf =
1077                         dd->ipath_piobcnt2k + dd->ipath_piobcnt4k - val;
1078         }
1079
1080         ipath_kpiobufs = val;
1081         ret = 0;
1082 bail:
1083         spin_unlock_irqrestore(&ipath_devs_lock, flags);
1084
1085         return ret;
1086 }