2 * Author: MontaVista Software, Inc.
5 * Based on the OMAP devices.c
7 * 2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
12 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
13 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version 2
18 * of the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
29 #include <linux/module.h>
30 #include <linux/kernel.h>
31 #include <linux/init.h>
32 #include <linux/platform_device.h>
33 #include <linux/gpio.h>
35 #include <mach/irqs.h>
36 #include <mach/hardware.h>
37 #include <mach/common.h>
42 * Resource definition for the MXC IrDA
44 static struct resource mxc_irda_resources[] = {
46 .start = UART3_BASE_ADDR,
47 .end = UART3_BASE_ADDR + SZ_4K - 1,
48 .flags = IORESOURCE_MEM,
51 .start = MXC_INT_UART3,
53 .flags = IORESOURCE_IRQ,
57 /* Platform Data for MXC IrDA */
58 struct platform_device mxc_irda_device = {
61 .num_resources = ARRAY_SIZE(mxc_irda_resources),
62 .resource = mxc_irda_resources,
66 * General Purpose Timer
67 * - i.MX1: 2 timer (slighly different register handling)
72 /* We use gpt0 as system timer, so do not add a device for this one */
74 static struct resource timer1_resources[] = {
76 .start = GPT2_BASE_ADDR,
77 .end = GPT2_BASE_ADDR + 0x17,
78 .flags = IORESOURCE_MEM
81 .start = MXC_INT_GPT2,
83 .flags = IORESOURCE_IRQ,
87 struct platform_device mxc_gpt1 = {
90 .num_resources = ARRAY_SIZE(timer1_resources),
91 .resource = timer1_resources
94 static struct resource timer2_resources[] = {
96 .start = GPT3_BASE_ADDR,
97 .end = GPT3_BASE_ADDR + 0x17,
98 .flags = IORESOURCE_MEM
101 .start = MXC_INT_GPT3,
103 .flags = IORESOURCE_IRQ,
107 struct platform_device mxc_gpt2 = {
110 .num_resources = ARRAY_SIZE(timer2_resources),
111 .resource = timer2_resources
114 #ifdef CONFIG_MACH_MX27
115 static struct resource timer3_resources[] = {
117 .start = GPT4_BASE_ADDR,
118 .end = GPT4_BASE_ADDR + 0x17,
119 .flags = IORESOURCE_MEM
122 .start = MXC_INT_GPT4,
124 .flags = IORESOURCE_IRQ,
128 struct platform_device mxc_gpt3 = {
131 .num_resources = ARRAY_SIZE(timer3_resources),
132 .resource = timer3_resources
135 static struct resource timer4_resources[] = {
137 .start = GPT5_BASE_ADDR,
138 .end = GPT5_BASE_ADDR + 0x17,
139 .flags = IORESOURCE_MEM
142 .start = MXC_INT_GPT5,
144 .flags = IORESOURCE_IRQ,
148 struct platform_device mxc_gpt4 = {
151 .num_resources = ARRAY_SIZE(timer4_resources),
152 .resource = timer4_resources
155 static struct resource timer5_resources[] = {
157 .start = GPT6_BASE_ADDR,
158 .end = GPT6_BASE_ADDR + 0x17,
159 .flags = IORESOURCE_MEM
162 .start = MXC_INT_GPT6,
164 .flags = IORESOURCE_IRQ,
168 struct platform_device mxc_gpt5 = {
171 .num_resources = ARRAY_SIZE(timer5_resources),
172 .resource = timer5_resources
182 static struct resource mxc_wdt_resources[] = {
184 .start = WDOG_BASE_ADDR,
185 .end = WDOG_BASE_ADDR + 0x30,
186 .flags = IORESOURCE_MEM,
190 struct platform_device mxc_wdt = {
193 .num_resources = ARRAY_SIZE(mxc_wdt_resources),
194 .resource = mxc_wdt_resources,
197 static struct resource mxc_w1_master_resources[] = {
199 .start = OWIRE_BASE_ADDR,
200 .end = OWIRE_BASE_ADDR + SZ_4K - 1,
201 .flags = IORESOURCE_MEM,
205 struct platform_device mxc_w1_master_device = {
208 .num_resources = ARRAY_SIZE(mxc_w1_master_resources),
209 .resource = mxc_w1_master_resources,
212 static struct resource mxc_nand_resources[] = {
214 .start = NFC_BASE_ADDR,
215 .end = NFC_BASE_ADDR + 0xfff,
216 .flags = IORESOURCE_MEM
218 .start = MXC_INT_NANDFC,
219 .end = MXC_INT_NANDFC,
220 .flags = IORESOURCE_IRQ
224 struct platform_device mxc_nand_device = {
227 .num_resources = ARRAY_SIZE(mxc_nand_resources),
228 .resource = mxc_nand_resources,
234 * - i.MX1: the basic controller
235 * - i.MX21: to be checked
236 * - i.MX27: like i.MX1, with slightly variations
238 static struct resource mxc_fb[] = {
240 .start = LCDC_BASE_ADDR,
241 .end = LCDC_BASE_ADDR + 0xFFF,
242 .flags = IORESOURCE_MEM,
245 .start = MXC_INT_LCDC,
247 .flags = IORESOURCE_IRQ,
252 struct platform_device mxc_fb_device = {
255 .num_resources = ARRAY_SIZE(mxc_fb),
258 .coherent_dma_mask = 0xFFFFFFFF,
264 /* GPIO port description */
265 static struct mxc_gpio_port imx_gpio_ports[] = {
267 .chip.label = "gpio-0",
269 .base = IO_ADDRESS(GPIO_BASE_ADDR),
270 .virtual_irq_start = MXC_GPIO_IRQ_START,
273 .chip.label = "gpio-1",
274 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x100),
275 .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
278 .chip.label = "gpio-2",
279 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x200),
280 .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
283 .chip.label = "gpio-3",
284 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x300),
285 .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
288 .chip.label = "gpio-4",
289 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x400),
290 .virtual_irq_start = MXC_GPIO_IRQ_START + 128,
293 .chip.label = "gpio-5",
294 .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x500),
295 .virtual_irq_start = MXC_GPIO_IRQ_START + 160,
299 int __init mxc_register_gpios(void)
301 return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));