git.oblomov.eu Git - linux-2.6/blob - drivers/net/s2io.c

   1 /************************************************************************
   2  * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
   3  * Copyright(c) 2002-2005 Neterion Inc.
   4
   5  * This software may be used and distributed according to the terms of
   6  * the GNU General Public License (GPL), incorporated herein by reference.
   7  * Drivers based on or derived from this code fall under the GPL and must
   8  * retain the authorship, copyright and license notice.  This file is not
   9  * a complete program and may only be used when the entire operating
  10  * system is licensed under the GPL.
  11  * See the file COPYING in this distribution for more information.
  12  *
  13  * Credits:
  14  * Jeff Garzik          : For pointing out the improper error condition
  15  *                        check in the s2io_xmit routine and also some
  16  *                        issues in the Tx watch dog function. Also for
  17  *                        patiently answering all those innumerable
  18  *                        questions regaring the 2.6 porting issues.
  19  * Stephen Hemminger    : Providing proper 2.6 porting mechanism for some
  20  *                        macros available only in 2.6 Kernel.
  21  * Francois Romieu      : For pointing out all code part that were
  22  *                        deprecated and also styling related comments.
  23  * Grant Grundler       : For helping me get rid of some Architecture
  24  *                        dependent code.
  25  * Christopher Hellwig  : Some more 2.6 specific issues in the driver.
  26  *
  27  * The module loadable parameters that are supported by the driver and a brief
  28  * explaination of all the variables.
  29  *
  30  * rx_ring_num : This can be used to program the number of receive rings used
  31  * in the driver.
  32  * rx_ring_sz: This defines the number of receive blocks each ring can have.
  33  *     This is also an array of size 8.
  34  * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
  35  *              values are 1, 2 and 3.
  36  * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
  37  * tx_fifo_len: This too is an array of 8. Each element defines the number of
  38  * Tx descriptors that can be associated with each corresponding FIFO.
  39  * intr_type: This defines the type of interrupt. The values can be 0(INTA),
  40  *     1(MSI), 2(MSI_X). Default value is '0(INTA)'
  41  * lro: Specifies whether to enable Large Receive Offload (LRO) or not.
  42  *     Possible values '1' for enable '0' for disable. Default is '0'
  43  * lro_max_pkts: This parameter defines maximum number of packets can be
  44  *     aggregated as a single large packet
  45  ************************************************************************/
  46
  47 #include <linux/module.h>
  48 #include <linux/types.h>
  49 #include <linux/errno.h>
  50 #include <linux/ioport.h>
  51 #include <linux/pci.h>
  52 #include <linux/dma-mapping.h>
  53 #include <linux/kernel.h>
  54 #include <linux/netdevice.h>
  55 #include <linux/etherdevice.h>
  56 #include <linux/skbuff.h>
  57 #include <linux/init.h>
  58 #include <linux/delay.h>
  59 #include <linux/stddef.h>
  60 #include <linux/ioctl.h>
  61 #include <linux/timex.h>
  62 #include <linux/sched.h>
  63 #include <linux/ethtool.h>
  64 #include <linux/workqueue.h>
  65 #include <linux/if_vlan.h>
  66 #include <linux/ip.h>
  67 #include <linux/tcp.h>
  68 #include <net/tcp.h>
  69
  70 #include <asm/system.h>
  71 #include <asm/uaccess.h>
  72 #include <asm/io.h>
  73 #include <asm/div64.h>
  74 #include <asm/irq.h>
  75
  76 /* local include */
  77 #include "s2io.h"
  78 #include "s2io-regs.h"
  79
  80 #define DRV_VERSION "2.0.15.2"
  81
  82 /* S2io Driver name & version. */
  83 static char s2io_driver_name[] = "Neterion";
  84 static char s2io_driver_version[] = DRV_VERSION;
  85
  86 static int rxd_size[4] = {32,48,48,64};
  87 static int rxd_count[4] = {127,85,85,63};
  88
  89 static inline int RXD_IS_UP2DT(RxD_t *rxdp)
  90 {
  91         int ret;
  92
  93         ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
  94                 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
  95
  96         return ret;
  97 }
  98
  99 /*
 100  * Cards with following subsystem_id have a link state indication
 101  * problem, 600B, 600C, 600D, 640B, 640C and 640D.
 102  * macro below identifies these cards given the subsystem_id.
 103  */
 104 #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
 105         (dev_type == XFRAME_I_DEVICE) ?                 \
 106                 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
 107                  ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
 108
 109 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
 110                                       ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
 111 #define TASKLET_IN_USE test_and_set_bit(0, (&sp->tasklet_status))
 112 #define PANIC   1
 113 #define LOW     2
 114 static inline int rx_buffer_level(nic_t * sp, int rxb_size, int ring)
 115 {
 116         mac_info_t *mac_control;
 117
 118         mac_control = &sp->mac_control;
 119         if (rxb_size <= rxd_count[sp->rxd_mode])
 120                 return PANIC;
 121         else if ((mac_control->rings[ring].pkt_cnt - rxb_size) > 16)
 122                 return  LOW;
 123         return 0;
 124 }
 125
 126 /* Ethtool related variables and Macros. */
 127 static char s2io_gstrings[][ETH_GSTRING_LEN] = {
 128         "Register test\t(offline)",
 129         "Eeprom test\t(offline)",
 130         "Link test\t(online)",
 131         "RLDRAM test\t(offline)",
 132         "BIST Test\t(offline)"
 133 };
 134
 135 static char ethtool_stats_keys[][ETH_GSTRING_LEN] = {
 136         {"tmac_frms"},
 137         {"tmac_data_octets"},
 138         {"tmac_drop_frms"},
 139         {"tmac_mcst_frms"},
 140         {"tmac_bcst_frms"},
 141         {"tmac_pause_ctrl_frms"},
 142         {"tmac_ttl_octets"},
 143         {"tmac_ucst_frms"},
 144         {"tmac_nucst_frms"},
 145         {"tmac_any_err_frms"},
 146         {"tmac_ttl_less_fb_octets"},
 147         {"tmac_vld_ip_octets"},
 148         {"tmac_vld_ip"},
 149         {"tmac_drop_ip"},
 150         {"tmac_icmp"},
 151         {"tmac_rst_tcp"},
 152         {"tmac_tcp"},
 153         {"tmac_udp"},
 154         {"rmac_vld_frms"},
 155         {"rmac_data_octets"},
 156         {"rmac_fcs_err_frms"},
 157         {"rmac_drop_frms"},
 158         {"rmac_vld_mcst_frms"},
 159         {"rmac_vld_bcst_frms"},
 160         {"rmac_in_rng_len_err_frms"},
 161         {"rmac_out_rng_len_err_frms"},
 162         {"rmac_long_frms"},
 163         {"rmac_pause_ctrl_frms"},
 164         {"rmac_unsup_ctrl_frms"},
 165         {"rmac_ttl_octets"},
 166         {"rmac_accepted_ucst_frms"},
 167         {"rmac_accepted_nucst_frms"},
 168         {"rmac_discarded_frms"},
 169         {"rmac_drop_events"},
 170         {"rmac_ttl_less_fb_octets"},
 171         {"rmac_ttl_frms"},
 172         {"rmac_usized_frms"},
 173         {"rmac_osized_frms"},
 174         {"rmac_frag_frms"},
 175         {"rmac_jabber_frms"},
 176         {"rmac_ttl_64_frms"},
 177         {"rmac_ttl_65_127_frms"},
 178         {"rmac_ttl_128_255_frms"},
 179         {"rmac_ttl_256_511_frms"},
 180         {"rmac_ttl_512_1023_frms"},
 181         {"rmac_ttl_1024_1518_frms"},
 182         {"rmac_ip"},
 183         {"rmac_ip_octets"},
 184         {"rmac_hdr_err_ip"},
 185         {"rmac_drop_ip"},
 186         {"rmac_icmp"},
 187         {"rmac_tcp"},
 188         {"rmac_udp"},
 189         {"rmac_err_drp_udp"},
 190         {"rmac_xgmii_err_sym"},
 191         {"rmac_frms_q0"},
 192         {"rmac_frms_q1"},
 193         {"rmac_frms_q2"},
 194         {"rmac_frms_q3"},
 195         {"rmac_frms_q4"},
 196         {"rmac_frms_q5"},
 197         {"rmac_frms_q6"},
 198         {"rmac_frms_q7"},
 199         {"rmac_full_q0"},
 200         {"rmac_full_q1"},
 201         {"rmac_full_q2"},
 202         {"rmac_full_q3"},
 203         {"rmac_full_q4"},
 204         {"rmac_full_q5"},
 205         {"rmac_full_q6"},
 206         {"rmac_full_q7"},
 207         {"rmac_pause_cnt"},
 208         {"rmac_xgmii_data_err_cnt"},
 209         {"rmac_xgmii_ctrl_err_cnt"},
 210         {"rmac_accepted_ip"},
 211         {"rmac_err_tcp"},
 212         {"rd_req_cnt"},
 213         {"new_rd_req_cnt"},
 214         {"new_rd_req_rtry_cnt"},
 215         {"rd_rtry_cnt"},
 216         {"wr_rtry_rd_ack_cnt"},
 217         {"wr_req_cnt"},
 218         {"new_wr_req_cnt"},
 219         {"new_wr_req_rtry_cnt"},
 220         {"wr_rtry_cnt"},
 221         {"wr_disc_cnt"},
 222         {"rd_rtry_wr_ack_cnt"},
 223         {"txp_wr_cnt"},
 224         {"txd_rd_cnt"},
 225         {"txd_wr_cnt"},
 226         {"rxd_rd_cnt"},
 227         {"rxd_wr_cnt"},
 228         {"txf_rd_cnt"},
 229         {"rxf_wr_cnt"},
 230         {"rmac_ttl_1519_4095_frms"},
 231         {"rmac_ttl_4096_8191_frms"},
 232         {"rmac_ttl_8192_max_frms"},
 233         {"rmac_ttl_gt_max_frms"},
 234         {"rmac_osized_alt_frms"},
 235         {"rmac_jabber_alt_frms"},
 236         {"rmac_gt_max_alt_frms"},
 237         {"rmac_vlan_frms"},
 238         {"rmac_len_discard"},
 239         {"rmac_fcs_discard"},
 240         {"rmac_pf_discard"},
 241         {"rmac_da_discard"},
 242         {"rmac_red_discard"},
 243         {"rmac_rts_discard"},
 244         {"rmac_ingm_full_discard"},
 245         {"link_fault_cnt"},
 246         {"\n DRIVER STATISTICS"},
 247         {"single_bit_ecc_errs"},
 248         {"double_bit_ecc_errs"},
 249         {"parity_err_cnt"},
 250         {"serious_err_cnt"},
 251         {"soft_reset_cnt"},
 252         {"fifo_full_cnt"},
 253         {"ring_full_cnt"},
 254         ("alarm_transceiver_temp_high"),
 255         ("alarm_transceiver_temp_low"),
 256         ("alarm_laser_bias_current_high"),
 257         ("alarm_laser_bias_current_low"),
 258         ("alarm_laser_output_power_high"),
 259         ("alarm_laser_output_power_low"),
 260         ("warn_transceiver_temp_high"),
 261         ("warn_transceiver_temp_low"),
 262         ("warn_laser_bias_current_high"),
 263         ("warn_laser_bias_current_low"),
 264         ("warn_laser_output_power_high"),
 265         ("warn_laser_output_power_low"),
 266         ("lro_aggregated_pkts"),
 267         ("lro_flush_both_count"),
 268         ("lro_out_of_sequence_pkts"),
 269         ("lro_flush_due_to_max_pkts"),
 270         ("lro_avg_aggr_pkts"),
 271 };
 272
 273 #define S2IO_STAT_LEN sizeof(ethtool_stats_keys)/ ETH_GSTRING_LEN
 274 #define S2IO_STAT_STRINGS_LEN S2IO_STAT_LEN * ETH_GSTRING_LEN
 275
 276 #define S2IO_TEST_LEN   sizeof(s2io_gstrings) / ETH_GSTRING_LEN
 277 #define S2IO_STRINGS_LEN        S2IO_TEST_LEN * ETH_GSTRING_LEN
 278
 279 #define S2IO_TIMER_CONF(timer, handle, arg, exp)                \
 280                         init_timer(&timer);                     \
 281                         timer.function = handle;                \
 282                         timer.data = (unsigned long) arg;       \
 283                         mod_timer(&timer, (jiffies + exp))      \
 284
 285 /* Add the vlan */
 286 static void s2io_vlan_rx_register(struct net_device *dev,
 287                                         struct vlan_group *grp)
 288 {
 289         nic_t *nic = dev->priv;
 290         unsigned long flags;
 291
 292         spin_lock_irqsave(&nic->tx_lock, flags);
 293         nic->vlgrp = grp;
 294         spin_unlock_irqrestore(&nic->tx_lock, flags);
 295 }
 296
 297 /* Unregister the vlan */
 298 static void s2io_vlan_rx_kill_vid(struct net_device *dev, unsigned long vid)
 299 {
 300         nic_t *nic = dev->priv;
 301         unsigned long flags;
 302
 303         spin_lock_irqsave(&nic->tx_lock, flags);
 304         if (nic->vlgrp)
 305                 nic->vlgrp->vlan_devices[vid] = NULL;
 306         spin_unlock_irqrestore(&nic->tx_lock, flags);
 307 }
 308
 309 /*
 310  * Constants to be programmed into the Xena's registers, to configure
 311  * the XAUI.
 312  */
 313
 314 #define END_SIGN        0x0
 315 static const u64 herc_act_dtx_cfg[] = {
 316         /* Set address */
 317         0x8000051536750000ULL, 0x80000515367500E0ULL,
 318         /* Write data */
 319         0x8000051536750004ULL, 0x80000515367500E4ULL,
 320         /* Set address */
 321         0x80010515003F0000ULL, 0x80010515003F00E0ULL,
 322         /* Write data */
 323         0x80010515003F0004ULL, 0x80010515003F00E4ULL,
 324         /* Set address */
 325         0x801205150D440000ULL, 0x801205150D4400E0ULL,
 326         /* Write data */
 327         0x801205150D440004ULL, 0x801205150D4400E4ULL,
 328         /* Set address */
 329         0x80020515F2100000ULL, 0x80020515F21000E0ULL,
 330         /* Write data */
 331         0x80020515F2100004ULL, 0x80020515F21000E4ULL,
 332         /* Done */
 333         END_SIGN
 334 };
 335
 336 static const u64 xena_dtx_cfg[] = {
 337         /* Set address */
 338         0x8000051500000000ULL, 0x80000515000000E0ULL,
 339         /* Write data */
 340         0x80000515D9350004ULL, 0x80000515D93500E4ULL,
 341         /* Set address */
 342         0x8001051500000000ULL, 0x80010515000000E0ULL,
 343         /* Write data */
 344         0x80010515001E0004ULL, 0x80010515001E00E4ULL,
 345         /* Set address */
 346         0x8002051500000000ULL, 0x80020515000000E0ULL,
 347         /* Write data */
 348         0x80020515F2100004ULL, 0x80020515F21000E4ULL,
 349         END_SIGN
 350 };
 351
 352 /*
 353  * Constants for Fixing the MacAddress problem seen mostly on
 354  * Alpha machines.
 355  */
 356 static const u64 fix_mac[] = {
 357         0x0060000000000000ULL, 0x0060600000000000ULL,
 358         0x0040600000000000ULL, 0x0000600000000000ULL,
 359         0x0020600000000000ULL, 0x0060600000000000ULL,
 360         0x0020600000000000ULL, 0x0060600000000000ULL,
 361         0x0020600000000000ULL, 0x0060600000000000ULL,
 362         0x0020600000000000ULL, 0x0060600000000000ULL,
 363         0x0020600000000000ULL, 0x0060600000000000ULL,
 364         0x0020600000000000ULL, 0x0060600000000000ULL,
 365         0x0020600000000000ULL, 0x0060600000000000ULL,
 366         0x0020600000000000ULL, 0x0060600000000000ULL,
 367         0x0020600000000000ULL, 0x0060600000000000ULL,
 368         0x0020600000000000ULL, 0x0060600000000000ULL,
 369         0x0020600000000000ULL, 0x0000600000000000ULL,
 370         0x0040600000000000ULL, 0x0060600000000000ULL,
 371         END_SIGN
 372 };
 373
 374 MODULE_AUTHOR("Raghavendra Koushik <raghavendra.koushik@neterion.com>");
 375 MODULE_LICENSE("GPL");
 376 MODULE_VERSION(DRV_VERSION);
 377
 378
 379 /* Module Loadable parameters. */
 380 S2IO_PARM_INT(tx_fifo_num, 1);
 381 S2IO_PARM_INT(rx_ring_num, 1);
 382
 383
 384 S2IO_PARM_INT(rx_ring_mode, 1);
 385 S2IO_PARM_INT(use_continuous_tx_intrs, 1);
 386 S2IO_PARM_INT(rmac_pause_time, 0x100);
 387 S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
 388 S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
 389 S2IO_PARM_INT(shared_splits, 0);
 390 S2IO_PARM_INT(tmac_util_period, 5);
 391 S2IO_PARM_INT(rmac_util_period, 5);
 392 S2IO_PARM_INT(bimodal, 0);
 393 S2IO_PARM_INT(l3l4hdr_size, 128);
 394 /* Frequency of Rx desc syncs expressed as power of 2 */
 395 S2IO_PARM_INT(rxsync_frequency, 3);
 396 /* Interrupt type. Values can be 0(INTA), 1(MSI), 2(MSI_X) */
 397 S2IO_PARM_INT(intr_type, 0);
 398 /* Large receive offload feature */
 399 S2IO_PARM_INT(lro, 0);
 400 /* Max pkts to be aggregated by LRO at one time. If not specified,
 401  * aggregation happens until we hit max IP pkt size(64K)
 402  */
 403 S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
 404 #ifndef CONFIG_S2IO_NAPI
 405 S2IO_PARM_INT(indicate_max_pkts, 0);
 406 #endif
 407
 408 static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
 409     {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
 410 static unsigned int rx_ring_sz[MAX_RX_RINGS] =
 411     {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
 412 static unsigned int rts_frm_len[MAX_RX_RINGS] =
 413     {[0 ...(MAX_RX_RINGS - 1)] = 0 };
 414
 415 module_param_array(tx_fifo_len, uint, NULL, 0);
 416 module_param_array(rx_ring_sz, uint, NULL, 0);
 417 module_param_array(rts_frm_len, uint, NULL, 0);
 418
 419 /*
 420  * S2IO device table.
 421  * This table lists all the devices that this driver supports.
 422  */
 423 static struct pci_device_id s2io_tbl[] __devinitdata = {
 424         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
 425          PCI_ANY_ID, PCI_ANY_ID},
 426         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
 427          PCI_ANY_ID, PCI_ANY_ID},
 428         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
 429          PCI_ANY_ID, PCI_ANY_ID},
 430         {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
 431          PCI_ANY_ID, PCI_ANY_ID},
 432         {0,}
 433 };
 434
 435 MODULE_DEVICE_TABLE(pci, s2io_tbl);
 436
 437 static struct pci_driver s2io_driver = {
 438       .name = "S2IO",
 439       .id_table = s2io_tbl,
 440       .probe = s2io_init_nic,
 441       .remove = __devexit_p(s2io_rem_nic),
 442 };
 443
 444 /* A simplifier macro used both by init and free shared_mem Fns(). */
 445 #define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
 446
 447 /**
 448  * init_shared_mem - Allocation and Initialization of Memory
 449  * @nic: Device private variable.
 450  * Description: The function allocates all the memory areas shared
 451  * between the NIC and the driver. This includes Tx descriptors,
 452  * Rx descriptors and the statistics block.
 453  */
 454
 455 static int init_shared_mem(struct s2io_nic *nic)
 456 {
 457         u32 size;
 458         void *tmp_v_addr, *tmp_v_addr_next;
 459         dma_addr_t tmp_p_addr, tmp_p_addr_next;
 460         RxD_block_t *pre_rxd_blk = NULL;
 461         int i, j, blk_cnt, rx_sz, tx_sz;
 462         int lst_size, lst_per_page;
 463         struct net_device *dev = nic->dev;
 464         unsigned long tmp;
 465         buffAdd_t *ba;
 466
 467         mac_info_t *mac_control;
 468         struct config_param *config;
 469
 470         mac_control = &nic->mac_control;
 471         config = &nic->config;
 472
 473
 474         /* Allocation and initialization of TXDLs in FIOFs */
 475         size = 0;
 476         for (i = 0; i < config->tx_fifo_num; i++) {
 477                 size += config->tx_cfg[i].fifo_len;
 478         }
 479         if (size > MAX_AVAILABLE_TXDS) {
 480                 DBG_PRINT(ERR_DBG, "s2io: Requested TxDs too high, ");
 481                 DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size);
 482                 return -EINVAL;
 483         }
 484
 485         lst_size = (sizeof(TxD_t) * config->max_txds);
 486         tx_sz = lst_size * size;
 487         lst_per_page = PAGE_SIZE / lst_size;
 488
 489         for (i = 0; i < config->tx_fifo_num; i++) {
 490                 int fifo_len = config->tx_cfg[i].fifo_len;
 491                 int list_holder_size = fifo_len * sizeof(list_info_hold_t);
 492                 mac_control->fifos[i].list_info = kmalloc(list_holder_size,
 493                                                           GFP_KERNEL);
 494                 if (!mac_control->fifos[i].list_info) {
 495                         DBG_PRINT(ERR_DBG,
 496                                   "Malloc failed for list_info\n");
 497                         return -ENOMEM;
 498                 }
 499                 memset(mac_control->fifos[i].list_info, 0, list_holder_size);
 500         }
 501         for (i = 0; i < config->tx_fifo_num; i++) {
 502                 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
 503                                                 lst_per_page);
 504                 mac_control->fifos[i].tx_curr_put_info.offset = 0;
 505                 mac_control->fifos[i].tx_curr_put_info.fifo_len =
 506                     config->tx_cfg[i].fifo_len - 1;
 507                 mac_control->fifos[i].tx_curr_get_info.offset = 0;
 508                 mac_control->fifos[i].tx_curr_get_info.fifo_len =
 509                     config->tx_cfg[i].fifo_len - 1;
 510                 mac_control->fifos[i].fifo_no = i;
 511                 mac_control->fifos[i].nic = nic;
 512                 mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 2;
 513
 514                 for (j = 0; j < page_num; j++) {
 515                         int k = 0;
 516                         dma_addr_t tmp_p;
 517                         void *tmp_v;
 518                         tmp_v = pci_alloc_consistent(nic->pdev,
 519                                                      PAGE_SIZE, &tmp_p);
 520                         if (!tmp_v) {
 521                                 DBG_PRINT(ERR_DBG,
 522                                           "pci_alloc_consistent ");
 523                                 DBG_PRINT(ERR_DBG, "failed for TxDL\n");
 524                                 return -ENOMEM;
 525                         }
 526                         /* If we got a zero DMA address(can happen on
 527                          * certain platforms like PPC), reallocate.
 528                          * Store virtual address of page we don't want,
 529                          * to be freed later.
 530                          */
 531                         if (!tmp_p) {
 532                                 mac_control->zerodma_virt_addr = tmp_v;
 533                                 DBG_PRINT(INIT_DBG,
 534                                 "%s: Zero DMA address for TxDL. ", dev->name);
 535                                 DBG_PRINT(INIT_DBG,
 536                                 "Virtual address %p\n", tmp_v);
 537                                 tmp_v = pci_alloc_consistent(nic->pdev,
 538                                                      PAGE_SIZE, &tmp_p);
 539                                 if (!tmp_v) {
 540                                         DBG_PRINT(ERR_DBG,
 541                                           "pci_alloc_consistent ");
 542                                         DBG_PRINT(ERR_DBG, "failed for TxDL\n");
 543                                         return -ENOMEM;
 544                                 }
 545                         }
 546                         while (k < lst_per_page) {
 547                                 int l = (j * lst_per_page) + k;
 548                                 if (l == config->tx_cfg[i].fifo_len)
 549                                         break;
 550                                 mac_control->fifos[i].list_info[l].list_virt_addr =
 551                                     tmp_v + (k * lst_size);
 552                                 mac_control->fifos[i].list_info[l].list_phy_addr =
 553                                     tmp_p + (k * lst_size);
 554                                 k++;
 555                         }
 556                 }
 557         }
 558
 559         nic->ufo_in_band_v = kmalloc((sizeof(u64) * size), GFP_KERNEL);
 560         if (!nic->ufo_in_band_v)
 561                 return -ENOMEM;
 562         memset(nic->ufo_in_band_v, 0, size);
 563
 564         /* Allocation and initialization of RXDs in Rings */
 565         size = 0;
 566         for (i = 0; i < config->rx_ring_num; i++) {
 567                 if (config->rx_cfg[i].num_rxd %
 568                     (rxd_count[nic->rxd_mode] + 1)) {
 569                         DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
 570                         DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ",
 571                                   i);
 572                         DBG_PRINT(ERR_DBG, "RxDs per Block");
 573                         return FAILURE;
 574                 }
 575                 size += config->rx_cfg[i].num_rxd;
 576                 mac_control->rings[i].block_count =
 577                         config->rx_cfg[i].num_rxd /
 578                         (rxd_count[nic->rxd_mode] + 1 );
 579                 mac_control->rings[i].pkt_cnt = config->rx_cfg[i].num_rxd -
 580                         mac_control->rings[i].block_count;
 581         }
 582         if (nic->rxd_mode == RXD_MODE_1)
 583                 size = (size * (sizeof(RxD1_t)));
 584         else
 585                 size = (size * (sizeof(RxD3_t)));
 586         rx_sz = size;
 587
 588         for (i = 0; i < config->rx_ring_num; i++) {
 589                 mac_control->rings[i].rx_curr_get_info.block_index = 0;
 590                 mac_control->rings[i].rx_curr_get_info.offset = 0;
 591                 mac_control->rings[i].rx_curr_get_info.ring_len =
 592                     config->rx_cfg[i].num_rxd - 1;
 593                 mac_control->rings[i].rx_curr_put_info.block_index = 0;
 594                 mac_control->rings[i].rx_curr_put_info.offset = 0;
 595                 mac_control->rings[i].rx_curr_put_info.ring_len =
 596                     config->rx_cfg[i].num_rxd - 1;
 597                 mac_control->rings[i].nic = nic;
 598                 mac_control->rings[i].ring_no = i;
 599
 600                 blk_cnt = config->rx_cfg[i].num_rxd /
 601                                 (rxd_count[nic->rxd_mode] + 1);
 602                 /*  Allocating all the Rx blocks */
 603                 for (j = 0; j < blk_cnt; j++) {
 604                         rx_block_info_t *rx_blocks;
 605                         int l;
 606
 607                         rx_blocks = &mac_control->rings[i].rx_blocks[j];
 608                         size = SIZE_OF_BLOCK; //size is always page size
 609                         tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
 610                                                           &tmp_p_addr);
 611                         if (tmp_v_addr == NULL) {
 612                                 /*
 613                                  * In case of failure, free_shared_mem()
 614                                  * is called, which should free any
 615                                  * memory that was alloced till the
 616                                  * failure happened.
 617                                  */
 618                                 rx_blocks->block_virt_addr = tmp_v_addr;
 619                                 return -ENOMEM;
 620                         }
 621                         memset(tmp_v_addr, 0, size);
 622                         rx_blocks->block_virt_addr = tmp_v_addr;
 623                         rx_blocks->block_dma_addr = tmp_p_addr;
 624                         rx_blocks->rxds = kmalloc(sizeof(rxd_info_t)*
 625                                                   rxd_count[nic->rxd_mode],
 626                                                   GFP_KERNEL);
 627                         for (l=0; l<rxd_count[nic->rxd_mode];l++) {
 628                                 rx_blocks->rxds[l].virt_addr =
 629                                         rx_blocks->block_virt_addr +
 630                                         (rxd_size[nic->rxd_mode] * l);
 631                                 rx_blocks->rxds[l].dma_addr =
 632                                         rx_blocks->block_dma_addr +
 633                                         (rxd_size[nic->rxd_mode] * l);
 634                         }
 635                 }
 636                 /* Interlinking all Rx Blocks */
 637                 for (j = 0; j < blk_cnt; j++) {
 638                         tmp_v_addr =
 639                                 mac_control->rings[i].rx_blocks[j].block_virt_addr;
 640                         tmp_v_addr_next =
 641                                 mac_control->rings[i].rx_blocks[(j + 1) %
 642                                               blk_cnt].block_virt_addr;
 643                         tmp_p_addr =
 644                                 mac_control->rings[i].rx_blocks[j].block_dma_addr;
 645                         tmp_p_addr_next =
 646                                 mac_control->rings[i].rx_blocks[(j + 1) %
 647                                               blk_cnt].block_dma_addr;
 648
 649                         pre_rxd_blk = (RxD_block_t *) tmp_v_addr;
 650                         pre_rxd_blk->reserved_2_pNext_RxD_block =
 651                             (unsigned long) tmp_v_addr_next;
 652                         pre_rxd_blk->pNext_RxD_Blk_physical =
 653                             (u64) tmp_p_addr_next;
 654                 }
 655         }
 656         if (nic->rxd_mode >= RXD_MODE_3A) {
 657                 /*
 658                  * Allocation of Storages for buffer addresses in 2BUFF mode
 659                  * and the buffers as well.
 660                  */
 661                 for (i = 0; i < config->rx_ring_num; i++) {
 662                         blk_cnt = config->rx_cfg[i].num_rxd /
 663                            (rxd_count[nic->rxd_mode]+ 1);
 664                         mac_control->rings[i].ba =
 665                                 kmalloc((sizeof(buffAdd_t *) * blk_cnt),
 666                                      GFP_KERNEL);
 667                         if (!mac_control->rings[i].ba)
 668                                 return -ENOMEM;
 669                         for (j = 0; j < blk_cnt; j++) {
 670                                 int k = 0;
 671                                 mac_control->rings[i].ba[j] =
 672                                         kmalloc((sizeof(buffAdd_t) *
 673                                                 (rxd_count[nic->rxd_mode] + 1)),
 674                                                 GFP_KERNEL);
 675                                 if (!mac_control->rings[i].ba[j])
 676                                         return -ENOMEM;
 677                                 while (k != rxd_count[nic->rxd_mode]) {
 678                                         ba = &mac_control->rings[i].ba[j][k];
 679
 680                                         ba->ba_0_org = (void *) kmalloc
 681                                             (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL);
 682                                         if (!ba->ba_0_org)
 683                                                 return -ENOMEM;
 684                                         tmp = (unsigned long)ba->ba_0_org;
 685                                         tmp += ALIGN_SIZE;
 686                                         tmp &= ~((unsigned long) ALIGN_SIZE);
 687                                         ba->ba_0 = (void *) tmp;
 688
 689                                         ba->ba_1_org = (void *) kmalloc
 690                                             (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL);
 691                                         if (!ba->ba_1_org)
 692                                                 return -ENOMEM;
 693                                         tmp = (unsigned long) ba->ba_1_org;
 694                                         tmp += ALIGN_SIZE;
 695                                         tmp &= ~((unsigned long) ALIGN_SIZE);
 696                                         ba->ba_1 = (void *) tmp;
 697                                         k++;
 698                                 }
 699                         }
 700                 }
 701         }
 702
 703         /* Allocation and initialization of Statistics block */
 704         size = sizeof(StatInfo_t);
 705         mac_control->stats_mem = pci_alloc_consistent
 706             (nic->pdev, size, &mac_control->stats_mem_phy);
 707
 708         if (!mac_control->stats_mem) {
 709                 /*
 710                  * In case of failure, free_shared_mem() is called, which
 711                  * should free any memory that was alloced till the
 712                  * failure happened.
 713                  */
 714                 return -ENOMEM;
 715         }
 716         mac_control->stats_mem_sz = size;
 717
 718         tmp_v_addr = mac_control->stats_mem;
 719         mac_control->stats_info = (StatInfo_t *) tmp_v_addr;
 720         memset(tmp_v_addr, 0, size);
 721         DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
 722                   (unsigned long long) tmp_p_addr);
 723
 724         return SUCCESS;
 725 }
 726
 727 /**
 728  * free_shared_mem - Free the allocated Memory
 729  * @nic:  Device private variable.
 730  * Description: This function is to free all memory locations allocated by
 731  * the init_shared_mem() function and return it to the kernel.
 732  */
 733
 734 static void free_shared_mem(struct s2io_nic *nic)
 735 {
 736         int i, j, blk_cnt, size;
 737         void *tmp_v_addr;
 738         dma_addr_t tmp_p_addr;
 739         mac_info_t *mac_control;
 740         struct config_param *config;
 741         int lst_size, lst_per_page;
 742         struct net_device *dev = nic->dev;
 743
 744         if (!nic)
 745                 return;
 746
 747         mac_control = &nic->mac_control;
 748         config = &nic->config;
 749
 750         lst_size = (sizeof(TxD_t) * config->max_txds);
 751         lst_per_page = PAGE_SIZE / lst_size;
 752
 753         for (i = 0; i < config->tx_fifo_num; i++) {
 754                 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
 755                                                 lst_per_page);
 756                 for (j = 0; j < page_num; j++) {
 757                         int mem_blks = (j * lst_per_page);
 758                         if (!mac_control->fifos[i].list_info)
 759                                 return;
 760                         if (!mac_control->fifos[i].list_info[mem_blks].
 761                                  list_virt_addr)
 762                                 break;
 763                         pci_free_consistent(nic->pdev, PAGE_SIZE,
 764                                             mac_control->fifos[i].
 765                                             list_info[mem_blks].
 766                                             list_virt_addr,
 767                                             mac_control->fifos[i].
 768                                             list_info[mem_blks].
 769                                             list_phy_addr);
 770                 }
 771                 /* If we got a zero DMA address during allocation,
 772                  * free the page now
 773                  */
 774                 if (mac_control->zerodma_virt_addr) {
 775                         pci_free_consistent(nic->pdev, PAGE_SIZE,
 776                                             mac_control->zerodma_virt_addr,
 777                                             (dma_addr_t)0);
 778                         DBG_PRINT(INIT_DBG,
 779                                 "%s: Freeing TxDL with zero DMA addr. ",
 780                                 dev->name);
 781                         DBG_PRINT(INIT_DBG, "Virtual address %p\n",
 782                                 mac_control->zerodma_virt_addr);
 783                 }
 784                 kfree(mac_control->fifos[i].list_info);
 785         }
 786
 787         size = SIZE_OF_BLOCK;
 788         for (i = 0; i < config->rx_ring_num; i++) {
 789                 blk_cnt = mac_control->rings[i].block_count;
 790                 for (j = 0; j < blk_cnt; j++) {
 791                         tmp_v_addr = mac_control->rings[i].rx_blocks[j].
 792                                 block_virt_addr;
 793                         tmp_p_addr = mac_control->rings[i].rx_blocks[j].
 794                                 block_dma_addr;
 795                         if (tmp_v_addr == NULL)
 796                                 break;
 797                         pci_free_consistent(nic->pdev, size,
 798                                             tmp_v_addr, tmp_p_addr);
 799                         kfree(mac_control->rings[i].rx_blocks[j].rxds);
 800                 }
 801         }
 802
 803         if (nic->rxd_mode >= RXD_MODE_3A) {
 804                 /* Freeing buffer storage addresses in 2BUFF mode. */
 805                 for (i = 0; i < config->rx_ring_num; i++) {
 806                         blk_cnt = config->rx_cfg[i].num_rxd /
 807                             (rxd_count[nic->rxd_mode] + 1);
 808                         for (j = 0; j < blk_cnt; j++) {
 809                                 int k = 0;
 810                                 if (!mac_control->rings[i].ba[j])
 811                                         continue;
 812                                 while (k != rxd_count[nic->rxd_mode]) {
 813                                         buffAdd_t *ba =
 814                                                 &mac_control->rings[i].ba[j][k];
 815                                         kfree(ba->ba_0_org);
 816                                         kfree(ba->ba_1_org);
 817                                         k++;
 818                                 }
 819                                 kfree(mac_control->rings[i].ba[j]);
 820                         }
 821                         kfree(mac_control->rings[i].ba);
 822                 }
 823         }
 824
 825         if (mac_control->stats_mem) {
 826                 pci_free_consistent(nic->pdev,
 827                                     mac_control->stats_mem_sz,
 828                                     mac_control->stats_mem,
 829                                     mac_control->stats_mem_phy);
 830         }
 831         if (nic->ufo_in_band_v)
 832                 kfree(nic->ufo_in_band_v);
 833 }
 834
 835 /**
 836  * s2io_verify_pci_mode -
 837  */
 838
 839 static int s2io_verify_pci_mode(nic_t *nic)
 840 {
 841         XENA_dev_config_t __iomem *bar0 = nic->bar0;
 842         register u64 val64 = 0;
 843         int     mode;
 844
 845         val64 = readq(&bar0->pci_mode);
 846         mode = (u8)GET_PCI_MODE(val64);
 847
 848         if ( val64 & PCI_MODE_UNKNOWN_MODE)
 849                 return -1;      /* Unknown PCI mode */
 850         return mode;
 851 }
 852
 853 #define NEC_VENID   0x1033
 854 #define NEC_DEVID   0x0125
 855 static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
 856 {
 857         struct pci_dev *tdev = NULL;
 858         while ((tdev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
 859                 if ((tdev->vendor == NEC_VENID) && (tdev->device == NEC_DEVID)){
 860                         if (tdev->bus == s2io_pdev->bus->parent)
 861                                 return 1;
 862                 }
 863         }
 864         return 0;
 865 }
 866
 867 static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
 868 /**
 869  * s2io_print_pci_mode -
 870  */
 871 static int s2io_print_pci_mode(nic_t *nic)
 872 {
 873         XENA_dev_config_t __iomem *bar0 = nic->bar0;
 874         register u64 val64 = 0;
 875         int     mode;
 876         struct config_param *config = &nic->config;
 877
 878         val64 = readq(&bar0->pci_mode);
 879         mode = (u8)GET_PCI_MODE(val64);
 880
 881         if ( val64 & PCI_MODE_UNKNOWN_MODE)
 882                 return -1;      /* Unknown PCI mode */
 883
 884         config->bus_speed = bus_speed[mode];
 885
 886         if (s2io_on_nec_bridge(nic->pdev)) {
 887                 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
 888                                                         nic->dev->name);
 889                 return mode;
 890         }
 891
 892         if (val64 & PCI_MODE_32_BITS) {
 893                 DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name);
 894         } else {
 895                 DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name);
 896         }
 897
 898         switch(mode) {
 899                 case PCI_MODE_PCI_33:
 900                         DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
 901                         break;
 902                 case PCI_MODE_PCI_66:
 903                         DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
 904                         break;
 905                 case PCI_MODE_PCIX_M1_66:
 906                         DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
 907                         break;
 908                 case PCI_MODE_PCIX_M1_100:
 909                         DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
 910                         break;
 911                 case PCI_MODE_PCIX_M1_133:
 912                         DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
 913                         break;
 914                 case PCI_MODE_PCIX_M2_66:
 915                         DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
 916                         break;
 917                 case PCI_MODE_PCIX_M2_100:
 918                         DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
 919                         break;
 920                 case PCI_MODE_PCIX_M2_133:
 921                         DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
 922                         break;
 923                 default:
 924                         return -1;      /* Unsupported bus speed */
 925         }
 926
 927         return mode;
 928 }
 929
 930 /**
 931  *  init_nic - Initialization of hardware
 932  *  @nic: device peivate variable
 933  *  Description: The function sequentially configures every block
 934  *  of the H/W from their reset values.
 935  *  Return Value:  SUCCESS on success and
 936  *  '-1' on failure (endian settings incorrect).
 937  */
 938
 939 static int init_nic(struct s2io_nic *nic)
 940 {
 941         XENA_dev_config_t __iomem *bar0 = nic->bar0;
 942         struct net_device *dev = nic->dev;
 943         register u64 val64 = 0;
 944         void __iomem *add;
 945         u32 time;
 946         int i, j;
 947         mac_info_t *mac_control;
 948         struct config_param *config;
 949         int dtx_cnt = 0;
 950         unsigned long long mem_share;
 951         int mem_size;
 952
 953         mac_control = &nic->mac_control;
 954         config = &nic->config;
 955
 956         /* to set the swapper controle on the card */
 957         if(s2io_set_swapper(nic)) {
 958                 DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n");
 959                 return -1;
 960         }
 961
 962         /*
 963          * Herc requires EOI to be removed from reset before XGXS, so..
 964          */
 965         if (nic->device_type & XFRAME_II_DEVICE) {
 966                 val64 = 0xA500000000ULL;
 967                 writeq(val64, &bar0->sw_reset);
 968                 msleep(500);
 969                 val64 = readq(&bar0->sw_reset);
 970         }
 971
 972         /* Remove XGXS from reset state */
 973         val64 = 0;
 974         writeq(val64, &bar0->sw_reset);
 975         msleep(500);
 976         val64 = readq(&bar0->sw_reset);
 977
 978         /*  Enable Receiving broadcasts */
 979         add = &bar0->mac_cfg;
 980         val64 = readq(&bar0->mac_cfg);
 981         val64 |= MAC_RMAC_BCAST_ENABLE;
 982         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
 983         writel((u32) val64, add);
 984         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
 985         writel((u32) (val64 >> 32), (add + 4));
 986
 987         /* Read registers in all blocks */
 988         val64 = readq(&bar0->mac_int_mask);
 989         val64 = readq(&bar0->mc_int_mask);
 990         val64 = readq(&bar0->xgxs_int_mask);
 991
 992         /*  Set MTU */
 993         val64 = dev->mtu;
 994         writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
 995
 996         if (nic->device_type & XFRAME_II_DEVICE) {
 997                 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
 998                         SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
 999                                           &bar0->dtx_control, UF);
1000                         if (dtx_cnt & 0x1)
1001                                 msleep(1); /* Necessary!! */
1002                         dtx_cnt++;
1003                 }
1004         } else {
1005                 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1006                         SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1007                                           &bar0->dtx_control, UF);
1008                         val64 = readq(&bar0->dtx_control);
1009                         dtx_cnt++;
1010                 }
1011         }
1012
1013         /*  Tx DMA Initialization */
1014         val64 = 0;
1015         writeq(val64, &bar0->tx_fifo_partition_0);
1016         writeq(val64, &bar0->tx_fifo_partition_1);
1017         writeq(val64, &bar0->tx_fifo_partition_2);
1018         writeq(val64, &bar0->tx_fifo_partition_3);
1019
1020
1021         for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1022                 val64 |=
1023                     vBIT(config->tx_cfg[i].fifo_len - 1, ((i * 32) + 19),
1024                          13) | vBIT(config->tx_cfg[i].fifo_priority,
1025                                     ((i * 32) + 5), 3);
1026
1027                 if (i == (config->tx_fifo_num - 1)) {
1028                         if (i % 2 == 0)
1029                                 i++;
1030                 }
1031
1032                 switch (i) {
1033                 case 1:
1034                         writeq(val64, &bar0->tx_fifo_partition_0);
1035                         val64 = 0;
1036                         break;
1037                 case 3:
1038                         writeq(val64, &bar0->tx_fifo_partition_1);
1039                         val64 = 0;
1040                         break;
1041                 case 5:
1042                         writeq(val64, &bar0->tx_fifo_partition_2);
1043                         val64 = 0;
1044                         break;
1045                 case 7:
1046                         writeq(val64, &bar0->tx_fifo_partition_3);
1047                         break;
1048                 }
1049         }
1050
1051         /*
1052          * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1053          * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1054          */
1055         if ((nic->device_type == XFRAME_I_DEVICE) &&
1056                 (get_xena_rev_id(nic->pdev) < 4))
1057                 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1058
1059         val64 = readq(&bar0->tx_fifo_partition_0);
1060         DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1061                   &bar0->tx_fifo_partition_0, (unsigned long long) val64);
1062
1063         /*
1064          * Initialization of Tx_PA_CONFIG register to ignore packet
1065          * integrity checking.
1066          */
1067         val64 = readq(&bar0->tx_pa_cfg);
1068         val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI |
1069             TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR;
1070         writeq(val64, &bar0->tx_pa_cfg);
1071
1072         /* Rx DMA intialization. */
1073         val64 = 0;
1074         for (i = 0; i < config->rx_ring_num; i++) {
1075                 val64 |=
1076                     vBIT(config->rx_cfg[i].ring_priority, (5 + (i * 8)),
1077                          3);
1078         }
1079         writeq(val64, &bar0->rx_queue_priority);
1080
1081         /*
1082          * Allocating equal share of memory to all the
1083          * configured Rings.
1084          */
1085         val64 = 0;
1086         if (nic->device_type & XFRAME_II_DEVICE)
1087                 mem_size = 32;
1088         else
1089                 mem_size = 64;
1090
1091         for (i = 0; i < config->rx_ring_num; i++) {
1092                 switch (i) {
1093                 case 0:
1094                         mem_share = (mem_size / config->rx_ring_num +
1095                                      mem_size % config->rx_ring_num);
1096                         val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1097                         continue;
1098                 case 1:
1099                         mem_share = (mem_size / config->rx_ring_num);
1100                         val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1101                         continue;
1102                 case 2:
1103                         mem_share = (mem_size / config->rx_ring_num);
1104                         val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1105                         continue;
1106                 case 3:
1107                         mem_share = (mem_size / config->rx_ring_num);
1108                         val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1109                         continue;
1110                 case 4:
1111                         mem_share = (mem_size / config->rx_ring_num);
1112                         val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1113                         continue;
1114                 case 5:
1115                         mem_share = (mem_size / config->rx_ring_num);
1116                         val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1117                         continue;
1118                 case 6:
1119                         mem_share = (mem_size / config->rx_ring_num);
1120                         val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1121                         continue;
1122                 case 7:
1123                         mem_share = (mem_size / config->rx_ring_num);
1124                         val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1125                         continue;
1126                 }
1127         }
1128         writeq(val64, &bar0->rx_queue_cfg);
1129
1130         /*
1131          * Filling Tx round robin registers
1132          * as per the number of FIFOs
1133          */
1134         switch (config->tx_fifo_num) {
1135         case 1:
1136                 val64 = 0x0000000000000000ULL;
1137                 writeq(val64, &bar0->tx_w_round_robin_0);
1138                 writeq(val64, &bar0->tx_w_round_robin_1);
1139                 writeq(val64, &bar0->tx_w_round_robin_2);
1140                 writeq(val64, &bar0->tx_w_round_robin_3);
1141                 writeq(val64, &bar0->tx_w_round_robin_4);
1142                 break;
1143         case 2:
1144                 val64 = 0x0000010000010000ULL;
1145                 writeq(val64, &bar0->tx_w_round_robin_0);
1146                 val64 = 0x0100000100000100ULL;
1147                 writeq(val64, &bar0->tx_w_round_robin_1);
1148                 val64 = 0x0001000001000001ULL;
1149                 writeq(val64, &bar0->tx_w_round_robin_2);
1150                 val64 = 0x0000010000010000ULL;
1151                 writeq(val64, &bar0->tx_w_round_robin_3);
1152                 val64 = 0x0100000000000000ULL;
1153                 writeq(val64, &bar0->tx_w_round_robin_4);
1154                 break;
1155         case 3:
1156                 val64 = 0x0001000102000001ULL;
1157                 writeq(val64, &bar0->tx_w_round_robin_0);
1158                 val64 = 0x0001020000010001ULL;
1159                 writeq(val64, &bar0->tx_w_round_robin_1);
1160                 val64 = 0x0200000100010200ULL;
1161                 writeq(val64, &bar0->tx_w_round_robin_2);
1162                 val64 = 0x0001000102000001ULL;
1163                 writeq(val64, &bar0->tx_w_round_robin_3);
1164                 val64 = 0x0001020000000000ULL;
1165                 writeq(val64, &bar0->tx_w_round_robin_4);
1166                 break;
1167         case 4:
1168                 val64 = 0x0001020300010200ULL;
1169                 writeq(val64, &bar0->tx_w_round_robin_0);
1170                 val64 = 0x0100000102030001ULL;
1171                 writeq(val64, &bar0->tx_w_round_robin_1);
1172                 val64 = 0x0200010000010203ULL;
1173                 writeq(val64, &bar0->tx_w_round_robin_2);
1174                 val64 = 0x0001020001000001ULL;
1175                 writeq(val64, &bar0->tx_w_round_robin_3);
1176                 val64 = 0x0203000100000000ULL;
1177                 writeq(val64, &bar0->tx_w_round_robin_4);
1178                 break;
1179         case 5:
1180                 val64 = 0x0001000203000102ULL;
1181                 writeq(val64, &bar0->tx_w_round_robin_0);
1182                 val64 = 0x0001020001030004ULL;
1183                 writeq(val64, &bar0->tx_w_round_robin_1);
1184                 val64 = 0x0001000203000102ULL;
1185                 writeq(val64, &bar0->tx_w_round_robin_2);
1186                 val64 = 0x0001020001030004ULL;
1187                 writeq(val64, &bar0->tx_w_round_robin_3);
1188                 val64 = 0x0001000000000000ULL;
1189                 writeq(val64, &bar0->tx_w_round_robin_4);
1190                 break;
1191         case 6:
1192                 val64 = 0x0001020304000102ULL;
1193                 writeq(val64, &bar0->tx_w_round_robin_0);
1194                 val64 = 0x0304050001020001ULL;
1195                 writeq(val64, &bar0->tx_w_round_robin_1);
1196                 val64 = 0x0203000100000102ULL;
1197                 writeq(val64, &bar0->tx_w_round_robin_2);
1198                 val64 = 0x0304000102030405ULL;
1199                 writeq(val64, &bar0->tx_w_round_robin_3);
1200                 val64 = 0x0001000200000000ULL;
1201                 writeq(val64, &bar0->tx_w_round_robin_4);
1202                 break;
1203         case 7:
1204                 val64 = 0x0001020001020300ULL;
1205                 writeq(val64, &bar0->tx_w_round_robin_0);
1206                 val64 = 0x0102030400010203ULL;
1207                 writeq(val64, &bar0->tx_w_round_robin_1);
1208                 val64 = 0x0405060001020001ULL;
1209                 writeq(val64, &bar0->tx_w_round_robin_2);
1210                 val64 = 0x0304050000010200ULL;
1211                 writeq(val64, &bar0->tx_w_round_robin_3);
1212                 val64 = 0x0102030000000000ULL;
1213                 writeq(val64, &bar0->tx_w_round_robin_4);
1214                 break;
1215         case 8:
1216                 val64 = 0x0001020300040105ULL;
1217                 writeq(val64, &bar0->tx_w_round_robin_0);
1218                 val64 = 0x0200030106000204ULL;
1219                 writeq(val64, &bar0->tx_w_round_robin_1);
1220                 val64 = 0x0103000502010007ULL;
1221                 writeq(val64, &bar0->tx_w_round_robin_2);
1222                 val64 = 0x0304010002060500ULL;
1223                 writeq(val64, &bar0->tx_w_round_robin_3);
1224                 val64 = 0x0103020400000000ULL;
1225                 writeq(val64, &bar0->tx_w_round_robin_4);
1226                 break;
1227         }
1228
1229         /* Enable all configured Tx FIFO partitions */
1230         val64 = readq(&bar0->tx_fifo_partition_0);
1231         val64 |= (TX_FIFO_PARTITION_EN);
1232         writeq(val64, &bar0->tx_fifo_partition_0);
1233
1234         /* Filling the Rx round robin registers as per the
1235          * number of Rings and steering based on QoS.
1236          */
1237         switch (config->rx_ring_num) {
1238         case 1:
1239                 val64 = 0x8080808080808080ULL;
1240                 writeq(val64, &bar0->rts_qos_steering);
1241                 break;
1242         case 2:
1243                 val64 = 0x0000010000010000ULL;
1244                 writeq(val64, &bar0->rx_w_round_robin_0);
1245                 val64 = 0x0100000100000100ULL;
1246                 writeq(val64, &bar0->rx_w_round_robin_1);
1247                 val64 = 0x0001000001000001ULL;
1248                 writeq(val64, &bar0->rx_w_round_robin_2);
1249                 val64 = 0x0000010000010000ULL;
1250                 writeq(val64, &bar0->rx_w_round_robin_3);
1251                 val64 = 0x0100000000000000ULL;
1252                 writeq(val64, &bar0->rx_w_round_robin_4);
1253
1254                 val64 = 0x8080808040404040ULL;
1255                 writeq(val64, &bar0->rts_qos_steering);
1256                 break;
1257         case 3:
1258                 val64 = 0x0001000102000001ULL;
1259                 writeq(val64, &bar0->rx_w_round_robin_0);
1260                 val64 = 0x0001020000010001ULL;
1261                 writeq(val64, &bar0->rx_w_round_robin_1);
1262                 val64 = 0x0200000100010200ULL;
1263                 writeq(val64, &bar0->rx_w_round_robin_2);
1264                 val64 = 0x0001000102000001ULL;
1265                 writeq(val64, &bar0->rx_w_round_robin_3);
1266                 val64 = 0x0001020000000000ULL;
1267                 writeq(val64, &bar0->rx_w_round_robin_4);
1268
1269                 val64 = 0x8080804040402020ULL;
1270                 writeq(val64, &bar0->rts_qos_steering);
1271                 break;
1272         case 4:
1273                 val64 = 0x0001020300010200ULL;
1274                 writeq(val64, &bar0->rx_w_round_robin_0);
1275                 val64 = 0x0100000102030001ULL;
1276                 writeq(val64, &bar0->rx_w_round_robin_1);
1277                 val64 = 0x0200010000010203ULL;
1278                 writeq(val64, &bar0->rx_w_round_robin_2);
1279                 val64 = 0x0001020001000001ULL;
1280                 writeq(val64, &bar0->rx_w_round_robin_3);
1281                 val64 = 0x0203000100000000ULL;
1282                 writeq(val64, &bar0->rx_w_round_robin_4);
1283
1284                 val64 = 0x8080404020201010ULL;
1285                 writeq(val64, &bar0->rts_qos_steering);
1286                 break;
1287         case 5:
1288                 val64 = 0x0001000203000102ULL;
1289                 writeq(val64, &bar0->rx_w_round_robin_0);
1290                 val64 = 0x0001020001030004ULL;
1291                 writeq(val64, &bar0->rx_w_round_robin_1);
1292                 val64 = 0x0001000203000102ULL;
1293                 writeq(val64, &bar0->rx_w_round_robin_2);
1294                 val64 = 0x0001020001030004ULL;
1295                 writeq(val64, &bar0->rx_w_round_robin_3);
1296                 val64 = 0x0001000000000000ULL;
1297                 writeq(val64, &bar0->rx_w_round_robin_4);
1298
1299                 val64 = 0x8080404020201008ULL;
1300                 writeq(val64, &bar0->rts_qos_steering);
1301                 break;
1302         case 6:
1303                 val64 = 0x0001020304000102ULL;
1304                 writeq(val64, &bar0->rx_w_round_robin_0);
1305                 val64 = 0x0304050001020001ULL;
1306                 writeq(val64, &bar0->rx_w_round_robin_1);
1307                 val64 = 0x0203000100000102ULL;
1308                 writeq(val64, &bar0->rx_w_round_robin_2);
1309                 val64 = 0x0304000102030405ULL;
1310                 writeq(val64, &bar0->rx_w_round_robin_3);
1311                 val64 = 0x0001000200000000ULL;
1312                 writeq(val64, &bar0->rx_w_round_robin_4);
1313
1314                 val64 = 0x8080404020100804ULL;
1315                 writeq(val64, &bar0->rts_qos_steering);
1316                 break;
1317         case 7:
1318                 val64 = 0x0001020001020300ULL;
1319                 writeq(val64, &bar0->rx_w_round_robin_0);
1320                 val64 = 0x0102030400010203ULL;
1321                 writeq(val64, &bar0->rx_w_round_robin_1);
1322                 val64 = 0x0405060001020001ULL;
1323                 writeq(val64, &bar0->rx_w_round_robin_2);
1324                 val64 = 0x0304050000010200ULL;
1325                 writeq(val64, &bar0->rx_w_round_robin_3);
1326                 val64 = 0x0102030000000000ULL;
1327                 writeq(val64, &bar0->rx_w_round_robin_4);
1328
1329                 val64 = 0x8080402010080402ULL;
1330                 writeq(val64, &bar0->rts_qos_steering);
1331                 break;
1332         case 8:
1333                 val64 = 0x0001020300040105ULL;
1334                 writeq(val64, &bar0->rx_w_round_robin_0);
1335                 val64 = 0x0200030106000204ULL;
1336                 writeq(val64, &bar0->rx_w_round_robin_1);
1337                 val64 = 0x0103000502010007ULL;
1338                 writeq(val64, &bar0->rx_w_round_robin_2);
1339                 val64 = 0x0304010002060500ULL;
1340                 writeq(val64, &bar0->rx_w_round_robin_3);
1341                 val64 = 0x0103020400000000ULL;
1342                 writeq(val64, &bar0->rx_w_round_robin_4);
1343
1344                 val64 = 0x8040201008040201ULL;
1345                 writeq(val64, &bar0->rts_qos_steering);
1346                 break;
1347         }
1348
1349         /* UDP Fix */
1350         val64 = 0;
1351         for (i = 0; i < 8; i++)
1352                 writeq(val64, &bar0->rts_frm_len_n[i]);
1353
1354         /* Set the default rts frame length for the rings configured */
1355         val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1356         for (i = 0 ; i < config->rx_ring_num ; i++)
1357                 writeq(val64, &bar0->rts_frm_len_n[i]);
1358
1359         /* Set the frame length for the configured rings
1360          * desired by the user
1361          */
1362         for (i = 0; i < config->rx_ring_num; i++) {
1363                 /* If rts_frm_len[i] == 0 then it is assumed that user not
1364                  * specified frame length steering.
1365                  * If the user provides the frame length then program
1366                  * the rts_frm_len register for those values or else
1367                  * leave it as it is.
1368                  */
1369                 if (rts_frm_len[i] != 0) {
1370                         writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1371                                 &bar0->rts_frm_len_n[i]);
1372                 }
1373         }
1374
1375         /* Program statistics memory */
1376         writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1377
1378         if (nic->device_type == XFRAME_II_DEVICE) {
1379                 val64 = STAT_BC(0x320);
1380                 writeq(val64, &bar0->stat_byte_cnt);
1381         }
1382
1383         /*
1384          * Initializing the sampling rate for the device to calculate the
1385          * bandwidth utilization.
1386          */
1387         val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1388             MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1389         writeq(val64, &bar0->mac_link_util);
1390
1391
1392         /*
1393          * Initializing the Transmit and Receive Traffic Interrupt
1394          * Scheme.
1395          */
1396         /*
1397          * TTI Initialization. Default Tx timer gets us about
1398          * 250 interrupts per sec. Continuous interrupts are enabled
1399          * by default.
1400          */
1401         if (nic->device_type == XFRAME_II_DEVICE) {
1402                 int count = (nic->config.bus_speed * 125)/2;
1403                 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1404         } else {
1405
1406                 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1407         }
1408         val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1409             TTI_DATA1_MEM_TX_URNG_B(0x10) |
1410             TTI_DATA1_MEM_TX_URNG_C(0x30) | TTI_DATA1_MEM_TX_TIMER_AC_EN;
1411                 if (use_continuous_tx_intrs)
1412                         val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1413         writeq(val64, &bar0->tti_data1_mem);
1414
1415         val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1416             TTI_DATA2_MEM_TX_UFC_B(0x20) |
1417             TTI_DATA2_MEM_TX_UFC_C(0x70) | TTI_DATA2_MEM_TX_UFC_D(0x80);
1418         writeq(val64, &bar0->tti_data2_mem);
1419
1420         val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1421         writeq(val64, &bar0->tti_command_mem);
1422
1423         /*
1424          * Once the operation completes, the Strobe bit of the command
1425          * register will be reset. We poll for this particular condition
1426          * We wait for a maximum of 500ms for the operation to complete,
1427          * if it's not complete by then we return error.
1428          */
1429         time = 0;
1430         while (TRUE) {
1431                 val64 = readq(&bar0->tti_command_mem);
1432                 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1433                         break;
1434                 }
1435                 if (time > 10) {
1436                         DBG_PRINT(ERR_DBG, "%s: TTI init Failed\n",
1437                                   dev->name);
1438                         return -1;
1439                 }
1440                 msleep(50);
1441                 time++;
1442         }
1443
1444         if (nic->config.bimodal) {
1445                 int k = 0;
1446                 for (k = 0; k < config->rx_ring_num; k++) {
1447                         val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1448                         val64 |= TTI_CMD_MEM_OFFSET(0x38+k);
1449                         writeq(val64, &bar0->tti_command_mem);
1450
1451                 /*
1452                  * Once the operation completes, the Strobe bit of the command
1453                  * register will be reset. We poll for this particular condition
1454                  * We wait for a maximum of 500ms for the operation to complete,
1455                  * if it's not complete by then we return error.
1456                 */
1457                         time = 0;
1458                         while (TRUE) {
1459                                 val64 = readq(&bar0->tti_command_mem);
1460                                 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1461                                         break;
1462                                 }
1463                                 if (time > 10) {
1464                                         DBG_PRINT(ERR_DBG,
1465                                                 "%s: TTI init Failed\n",
1466                                         dev->name);
1467                                         return -1;
1468                                 }
1469                                 time++;
1470                                 msleep(50);
1471                         }
1472                 }
1473         } else {
1474
1475                 /* RTI Initialization */
1476                 if (nic->device_type == XFRAME_II_DEVICE) {
1477                         /*
1478                          * Programmed to generate Apprx 500 Intrs per
1479                          * second
1480                          */
1481                         int count = (nic->config.bus_speed * 125)/4;
1482                         val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1483                 } else {
1484                         val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1485                 }
1486                 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1487                     RTI_DATA1_MEM_RX_URNG_B(0x10) |
1488                     RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
1489
1490                 writeq(val64, &bar0->rti_data1_mem);
1491
1492                 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1493                     RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1494                 if (nic->intr_type == MSI_X)
1495                     val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
1496                                 RTI_DATA2_MEM_RX_UFC_D(0x40));
1497                 else
1498                     val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
1499                                 RTI_DATA2_MEM_RX_UFC_D(0x80));
1500                 writeq(val64, &bar0->rti_data2_mem);
1501
1502                 for (i = 0; i < config->rx_ring_num; i++) {
1503                         val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
1504                                         | RTI_CMD_MEM_OFFSET(i);
1505                         writeq(val64, &bar0->rti_command_mem);
1506
1507                         /*
1508                          * Once the operation completes, the Strobe bit of the
1509                          * command register will be reset. We poll for this
1510                          * particular condition. We wait for a maximum of 500ms
1511                          * for the operation to complete, if it's not complete
1512                          * by then we return error.
1513                          */
1514                         time = 0;
1515                         while (TRUE) {
1516                                 val64 = readq(&bar0->rti_command_mem);
1517                                 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD)) {
1518                                         break;
1519                                 }
1520                                 if (time > 10) {
1521                                         DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
1522                                                   dev->name);
1523                                         return -1;
1524                                 }
1525                                 time++;
1526                                 msleep(50);
1527                         }
1528                 }
1529         }
1530
1531         /*
1532          * Initializing proper values as Pause threshold into all
1533          * the 8 Queues on Rx side.
1534          */
1535         writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1536         writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1537
1538         /* Disable RMAC PAD STRIPPING */
1539         add = &bar0->mac_cfg;
1540         val64 = readq(&bar0->mac_cfg);
1541         val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1542         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1543         writel((u32) (val64), add);
1544         writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1545         writel((u32) (val64 >> 32), (add + 4));
1546         val64 = readq(&bar0->mac_cfg);
1547
1548         /* Enable FCS stripping by adapter */
1549         add = &bar0->mac_cfg;
1550         val64 = readq(&bar0->mac_cfg);
1551         val64 |= MAC_CFG_RMAC_STRIP_FCS;
1552         if (nic->device_type == XFRAME_II_DEVICE)
1553                 writeq(val64, &bar0->mac_cfg);
1554         else {
1555                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1556                 writel((u32) (val64), add);
1557                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1558                 writel((u32) (val64 >> 32), (add + 4));
1559         }
1560
1561         /*
1562          * Set the time value to be inserted in the pause frame
1563          * generated by xena.
1564          */
1565         val64 = readq(&bar0->rmac_pause_cfg);
1566         val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1567         val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1568         writeq(val64, &bar0->rmac_pause_cfg);
1569
1570         /*
1571          * Set the Threshold Limit for Generating the pause frame
1572          * If the amount of data in any Queue exceeds ratio of
1573          * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1574          * pause frame is generated
1575          */
1576         val64 = 0;
1577         for (i = 0; i < 4; i++) {
1578                 val64 |=
1579                     (((u64) 0xFF00 | nic->mac_control.
1580                       mc_pause_threshold_q0q3)
1581                      << (i * 2 * 8));
1582         }
1583         writeq(val64, &bar0->mc_pause_thresh_q0q3);
1584
1585         val64 = 0;
1586         for (i = 0; i < 4; i++) {
1587                 val64 |=
1588                     (((u64) 0xFF00 | nic->mac_control.
1589                       mc_pause_threshold_q4q7)
1590                      << (i * 2 * 8));
1591         }
1592         writeq(val64, &bar0->mc_pause_thresh_q4q7);
1593
1594         /*
1595          * TxDMA will stop Read request if the number of read split has
1596          * exceeded the limit pointed by shared_splits
1597          */
1598         val64 = readq(&bar0->pic_control);
1599         val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1600         writeq(val64, &bar0->pic_control);
1601
1602         if (nic->config.bus_speed == 266) {
1603                 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1604                 writeq(0x0, &bar0->read_retry_delay);
1605                 writeq(0x0, &bar0->write_retry_delay);
1606         }
1607
1608         /*
1609          * Programming the Herc to split every write transaction
1610          * that does not start on an ADB to reduce disconnects.
1611          */
1612         if (nic->device_type == XFRAME_II_DEVICE) {
1613                 val64 = EXT_REQ_EN | MISC_LINK_STABILITY_PRD(3);
1614                 writeq(val64, &bar0->misc_control);
1615                 val64 = readq(&bar0->pic_control2);
1616                 val64 &= ~(BIT(13)|BIT(14)|BIT(15));
1617                 writeq(val64, &bar0->pic_control2);
1618         }
1619         if (strstr(nic->product_name, "CX4")) {
1620                 val64 = TMAC_AVG_IPG(0x17);
1621                 writeq(val64, &bar0->tmac_avg_ipg);
1622         }
1623
1624         return SUCCESS;
1625 }
1626 #define LINK_UP_DOWN_INTERRUPT          1
1627 #define MAC_RMAC_ERR_TIMER              2
1628
1629 static int s2io_link_fault_indication(nic_t *nic)
1630 {
1631         if (nic->intr_type != INTA)
1632                 return MAC_RMAC_ERR_TIMER;
1633         if (nic->device_type == XFRAME_II_DEVICE)
1634                 return LINK_UP_DOWN_INTERRUPT;
1635         else
1636                 return MAC_RMAC_ERR_TIMER;
1637 }
1638
1639 /**
1640  *  en_dis_able_nic_intrs - Enable or Disable the interrupts
1641  *  @nic: device private variable,
1642  *  @mask: A mask indicating which Intr block must be modified and,
1643  *  @flag: A flag indicating whether to enable or disable the Intrs.
1644  *  Description: This function will either disable or enable the interrupts
1645  *  depending on the flag argument. The mask argument can be used to
1646  *  enable/disable any Intr block.
1647  *  Return Value: NONE.
1648  */
1649
1650 static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1651 {
1652         XENA_dev_config_t __iomem *bar0 = nic->bar0;
1653         register u64 val64 = 0, temp64 = 0;
1654
1655         /*  Top level interrupt classification */
1656         /*  PIC Interrupts */
1657         if ((mask & (TX_PIC_INTR | RX_PIC_INTR))) {
1658                 /*  Enable PIC Intrs in the general intr mask register */
1659                 val64 = TXPIC_INT_M | PIC_RX_INT_M;
1660                 if (flag == ENABLE_INTRS) {
1661                         temp64 = readq(&bar0->general_int_mask);
1662                         temp64 &= ~((u64) val64);
1663                         writeq(temp64, &bar0->general_int_mask);
1664                         /*
1665                          * If Hercules adapter enable GPIO otherwise
1666                          * disable all PCIX, Flash, MDIO, IIC and GPIO
1667                          * interrupts for now.
1668                          * TODO
1669                          */
1670                         if (s2io_link_fault_indication(nic) ==
1671                                         LINK_UP_DOWN_INTERRUPT ) {
1672                                 temp64 = readq(&bar0->pic_int_mask);
1673                                 temp64 &= ~((u64) PIC_INT_GPIO);
1674                                 writeq(temp64, &bar0->pic_int_mask);
1675                                 temp64 = readq(&bar0->gpio_int_mask);
1676                                 temp64 &= ~((u64) GPIO_INT_MASK_LINK_UP);
1677                                 writeq(temp64, &bar0->gpio_int_mask);
1678                         } else {
1679                                 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1680                         }
1681                         /*
1682                          * No MSI Support is available presently, so TTI and
1683                          * RTI interrupts are also disabled.
1684                          */
1685                 } else if (flag == DISABLE_INTRS) {
1686                         /*
1687                          * Disable PIC Intrs in the general
1688                          * intr mask register
1689                          */
1690                         writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1691                         temp64 = readq(&bar0->general_int_mask);
1692                         val64 |= temp64;
1693                         writeq(val64, &bar0->general_int_mask);
1694                 }
1695         }
1696
1697         /*  DMA Interrupts */
1698         /*  Enabling/Disabling Tx DMA interrupts */
1699         if (mask & TX_DMA_INTR) {
1700                 /* Enable TxDMA Intrs in the general intr mask register */
1701                 val64 = TXDMA_INT_M;
1702                 if (flag == ENABLE_INTRS) {
1703                         temp64 = readq(&bar0->general_int_mask);
1704                         temp64 &= ~((u64) val64);
1705                         writeq(temp64, &bar0->general_int_mask);
1706                         /*
1707                          * Keep all interrupts other than PFC interrupt
1708                          * and PCC interrupt disabled in DMA level.
1709                          */
1710                         val64 = DISABLE_ALL_INTRS & ~(TXDMA_PFC_INT_M |
1711                                                       TXDMA_PCC_INT_M);
1712                         writeq(val64, &bar0->txdma_int_mask);
1713                         /*
1714                          * Enable only the MISC error 1 interrupt in PFC block
1715                          */
1716                         val64 = DISABLE_ALL_INTRS & (~PFC_MISC_ERR_1);
1717                         writeq(val64, &bar0->pfc_err_mask);
1718                         /*
1719                          * Enable only the FB_ECC error interrupt in PCC block
1720                          */
1721                         val64 = DISABLE_ALL_INTRS & (~PCC_FB_ECC_ERR);
1722                         writeq(val64, &bar0->pcc_err_mask);
1723                 } else if (flag == DISABLE_INTRS) {
1724                         /*
1725                          * Disable TxDMA Intrs in the general intr mask
1726                          * register
1727                          */
1728                         writeq(DISABLE_ALL_INTRS, &bar0->txdma_int_mask);
1729                         writeq(DISABLE_ALL_INTRS, &bar0->pfc_err_mask);
1730                         temp64 = readq(&bar0->general_int_mask);
1731                         val64 |= temp64;
1732                         writeq(val64, &bar0->general_int_mask);
1733                 }
1734         }
1735
1736         /*  Enabling/Disabling Rx DMA interrupts */
1737         if (mask & RX_DMA_INTR) {
1738                 /*  Enable RxDMA Intrs in the general intr mask register */
1739                 val64 = RXDMA_INT_M;
1740                 if (flag == ENABLE_INTRS) {
1741                         temp64 = readq(&bar0->general_int_mask);
1742                         temp64 &= ~((u64) val64);
1743                         writeq(temp64, &bar0->general_int_mask);
1744                         /*
1745                          * All RxDMA block interrupts are disabled for now
1746                          * TODO
1747                          */
1748                         writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask);
1749                 } else if (flag == DISABLE_INTRS) {
1750                         /*
1751                          * Disable RxDMA Intrs in the general intr mask
1752                          * register
1753                          */
1754                         writeq(DISABLE_ALL_INTRS, &bar0->rxdma_int_mask);
1755                         temp64 = readq(&bar0->general_int_mask);
1756                         val64 |= temp64;
1757                         writeq(val64, &bar0->general_int_mask);
1758                 }
1759         }
1760
1761         /*  MAC Interrupts */
1762         /*  Enabling/Disabling MAC interrupts */
1763         if (mask & (TX_MAC_INTR | RX_MAC_INTR)) {
1764                 val64 = TXMAC_INT_M | RXMAC_INT_M;
1765                 if (flag == ENABLE_INTRS) {
1766                         temp64 = readq(&bar0->general_int_mask);
1767                         temp64 &= ~((u64) val64);
1768                         writeq(temp64, &bar0->general_int_mask);
1769                         /*
1770                          * All MAC block error interrupts are disabled for now
1771                          * TODO
1772                          */
1773                 } else if (flag == DISABLE_INTRS) {
1774                         /*
1775                          * Disable MAC Intrs in the general intr mask register
1776                          */
1777                         writeq(DISABLE_ALL_INTRS, &bar0->mac_int_mask);
1778                         writeq(DISABLE_ALL_INTRS,
1779                                &bar0->mac_rmac_err_mask);
1780
1781                         temp64 = readq(&bar0->general_int_mask);
1782                         val64 |= temp64;
1783                         writeq(val64, &bar0->general_int_mask);
1784                 }
1785         }
1786
1787         /*  XGXS Interrupts */
1788         if (mask & (TX_XGXS_INTR | RX_XGXS_INTR)) {
1789                 val64 = TXXGXS_INT_M | RXXGXS_INT_M;
1790                 if (flag == ENABLE_INTRS) {
1791                         temp64 = readq(&bar0->general_int_mask);
1792                         temp64 &= ~((u64) val64);
1793                         writeq(temp64, &bar0->general_int_mask);
1794                         /*
1795                          * All XGXS block error interrupts are disabled for now
1796                          * TODO
1797                          */
1798                         writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask);
1799                 } else if (flag == DISABLE_INTRS) {
1800                         /*
1801                          * Disable MC Intrs in the general intr mask register
1802                          */
1803                         writeq(DISABLE_ALL_INTRS, &bar0->xgxs_int_mask);
1804                         temp64 = readq(&bar0->general_int_mask);
1805                         val64 |= temp64;
1806                         writeq(val64, &bar0->general_int_mask);
1807                 }
1808         }
1809
1810         /*  Memory Controller(MC) interrupts */
1811         if (mask & MC_INTR) {
1812                 val64 = MC_INT_M;
1813                 if (flag == ENABLE_INTRS) {
1814                         temp64 = readq(&bar0->general_int_mask);
1815                         temp64 &= ~((u64) val64);
1816                         writeq(temp64, &bar0->general_int_mask);
1817                         /*
1818                          * Enable all MC Intrs.
1819                          */
1820                         writeq(0x0, &bar0->mc_int_mask);
1821                         writeq(0x0, &bar0->mc_err_mask);
1822                 } else if (flag == DISABLE_INTRS) {
1823                         /*
1824                          * Disable MC Intrs in the general intr mask register
1825                          */
1826                         writeq(DISABLE_ALL_INTRS, &bar0->mc_int_mask);
1827                         temp64 = readq(&bar0->general_int_mask);
1828                         val64 |= temp64;
1829                         writeq(val64, &bar0->general_int_mask);
1830                 }
1831         }
1832
1833
1834         /*  Tx traffic interrupts */
1835         if (mask & TX_TRAFFIC_INTR) {
1836                 val64 = TXTRAFFIC_INT_M;
1837                 if (flag == ENABLE_INTRS) {
1838                         temp64 = readq(&bar0->general_int_mask);
1839                         temp64 &= ~((u64) val64);
1840                         writeq(temp64, &bar0->general_int_mask);
1841                         /*
1842                          * Enable all the Tx side interrupts
1843                          * writing 0 Enables all 64 TX interrupt levels
1844                          */
1845                         writeq(0x0, &bar0->tx_traffic_mask);
1846                 } else if (flag == DISABLE_INTRS) {
1847                         /*
1848                          * Disable Tx Traffic Intrs in the general intr mask
1849                          * register.
1850                          */
1851                         writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
1852                         temp64 = readq(&bar0->general_int_mask);
1853                         val64 |= temp64;
1854                         writeq(val64, &bar0->general_int_mask);
1855                 }
1856         }
1857
1858         /*  Rx traffic interrupts */
1859         if (mask & RX_TRAFFIC_INTR) {
1860                 val64 = RXTRAFFIC_INT_M;
1861                 if (flag == ENABLE_INTRS) {
1862                         temp64 = readq(&bar0->general_int_mask);
1863                         temp64 &= ~((u64) val64);
1864                         writeq(temp64, &bar0->general_int_mask);
1865                         /* writing 0 Enables all 8 RX interrupt levels */
1866                         writeq(0x0, &bar0->rx_traffic_mask);
1867                 } else if (flag == DISABLE_INTRS) {
1868                         /*
1869                          * Disable Rx Traffic Intrs in the general intr mask
1870                          * register.
1871                          */
1872                         writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
1873                         temp64 = readq(&bar0->general_int_mask);
1874                         val64 |= temp64;
1875                         writeq(val64, &bar0->general_int_mask);
1876                 }
1877         }
1878 }
1879
1880 static int check_prc_pcc_state(u64 val64, int flag, int rev_id, int herc)
1881 {
1882         int ret = 0;
1883
1884         if (flag == FALSE) {
1885                 if ((!herc && (rev_id >= 4)) || herc) {
1886                         if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) &&
1887                             ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1888                              ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
1889                                 ret = 1;
1890                         }
1891                 }else {
1892                         if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) &&
1893                             ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1894                              ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
1895                                 ret = 1;
1896                         }
1897                 }
1898         } else {
1899                 if ((!herc && (rev_id >= 4)) || herc) {
1900                         if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
1901                              ADAPTER_STATUS_RMAC_PCC_IDLE) &&
1902                             (!(val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ||
1903                              ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1904                               ADAPTER_STATUS_RC_PRC_QUIESCENT))) {
1905                                 ret = 1;
1906                         }
1907                 } else {
1908                         if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
1909                              ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) &&
1910                             (!(val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ||
1911                              ((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1912                               ADAPTER_STATUS_RC_PRC_QUIESCENT))) {
1913                                 ret = 1;
1914                         }
1915                 }
1916         }
1917
1918         return ret;
1919 }
1920 /**
1921  *  verify_xena_quiescence - Checks whether the H/W is ready
1922  *  @val64 :  Value read from adapter status register.
1923  *  @flag : indicates if the adapter enable bit was ever written once
1924  *  before.
1925  *  Description: Returns whether the H/W is ready to go or not. Depending
1926  *  on whether adapter enable bit was written or not the comparison
1927  *  differs and the calling function passes the input argument flag to
1928  *  indicate this.
1929  *  Return: 1 If xena is quiescence
1930  *          0 If Xena is not quiescence
1931  */
1932
1933 static int verify_xena_quiescence(nic_t *sp, u64 val64, int flag)
1934 {
1935         int ret = 0, herc;
1936         u64 tmp64 = ~((u64) val64);
1937         int rev_id = get_xena_rev_id(sp->pdev);
1938
1939         herc = (sp->device_type == XFRAME_II_DEVICE);
1940         if (!
1941             (tmp64 &
1942              (ADAPTER_STATUS_TDMA_READY | ADAPTER_STATUS_RDMA_READY |
1943               ADAPTER_STATUS_PFC_READY | ADAPTER_STATUS_TMAC_BUF_EMPTY |
1944               ADAPTER_STATUS_PIC_QUIESCENT | ADAPTER_STATUS_MC_DRAM_READY |
1945               ADAPTER_STATUS_MC_QUEUES_READY | ADAPTER_STATUS_M_PLL_LOCK |
1946               ADAPTER_STATUS_P_PLL_LOCK))) {
1947                 ret = check_prc_pcc_state(val64, flag, rev_id, herc);
1948         }
1949
1950         return ret;
1951 }
1952
1953 /**
1954  * fix_mac_address -  Fix for Mac addr problem on Alpha platforms
1955  * @sp: Pointer to device specifc structure
1956  * Description :
1957  * New procedure to clear mac address reading  problems on Alpha platforms
1958  *
1959  */
1960
1961 static void fix_mac_address(nic_t * sp)
1962 {
1963         XENA_dev_config_t __iomem *bar0 = sp->bar0;
1964         u64 val64;
1965         int i = 0;
1966
1967         while (fix_mac[i] != END_SIGN) {
1968                 writeq(fix_mac[i++], &bar0->gpio_control);
1969                 udelay(10);
1970                 val64 = readq(&bar0->gpio_control);
1971         }
1972 }
1973
1974 /**
1975  *  start_nic - Turns the device on
1976  *  @nic : device private variable.
1977  *  Description:
1978  *  This function actually turns the device on. Before this  function is
1979  *  called,all Registers are configured from their reset states
1980  *  and shared memory is allocated but the NIC is still quiescent. On
1981  *  calling this function, the device interrupts are cleared and the NIC is
1982  *  literally switched on by writing into the adapter control register.
1983  *  Return Value:
1984  *  SUCCESS on success and -1 on failure.
1985  */
1986
1987 static int start_nic(struct s2io_nic *nic)
1988 {
1989         XENA_dev_config_t __iomem *bar0 = nic->bar0;
1990         struct net_device *dev = nic->dev;
1991         register u64 val64 = 0;
1992         u16 subid, i;
1993         mac_info_t *mac_control;
1994         struct config_param *config;
1995
1996         mac_control = &nic->mac_control;
1997         config = &nic->config;
1998
1999         /*  PRC Initialization and configuration */
2000         for (i = 0; i < config->rx_ring_num; i++) {
2001                 writeq((u64) mac_control->rings[i].rx_blocks[0].block_dma_addr,
2002                        &bar0->prc_rxd0_n[i]);
2003
2004                 val64 = readq(&bar0->prc_ctrl_n[i]);
2005                 if (nic->config.bimodal)
2006                         val64 |= PRC_CTRL_BIMODAL_INTERRUPT;
2007                 if (nic->rxd_mode == RXD_MODE_1)
2008                         val64 |= PRC_CTRL_RC_ENABLED;
2009                 else
2010                         val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
2011                 if (nic->device_type == XFRAME_II_DEVICE)
2012                         val64 |= PRC_CTRL_GROUP_READS;
2013                 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2014                 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
2015                 writeq(val64, &bar0->prc_ctrl_n[i]);
2016         }
2017
2018         if (nic->rxd_mode == RXD_MODE_3B) {
2019                 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2020                 val64 = readq(&bar0->rx_pa_cfg);
2021                 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2022                 writeq(val64, &bar0->rx_pa_cfg);
2023         }
2024
2025         /*
2026          * Enabling MC-RLDRAM. After enabling the device, we timeout
2027          * for around 100ms, which is approximately the time required
2028          * for the device to be ready for operation.
2029          */
2030         val64 = readq(&bar0->mc_rldram_mrs);
2031         val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2032         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2033         val64 = readq(&bar0->mc_rldram_mrs);
2034
2035         msleep(100);    /* Delay by around 100 ms. */
2036
2037         /* Enabling ECC Protection. */
2038         val64 = readq(&bar0->adapter_control);
2039         val64 &= ~ADAPTER_ECC_EN;
2040         writeq(val64, &bar0->adapter_control);
2041
2042         /*
2043          * Clearing any possible Link state change interrupts that
2044          * could have popped up just before Enabling the card.
2045          */
2046         val64 = readq(&bar0->mac_rmac_err_reg);
2047         if (val64)
2048                 writeq(val64, &bar0->mac_rmac_err_reg);
2049
2050         /*
2051          * Verify if the device is ready to be enabled, if so enable
2052          * it.
2053          */
2054         val64 = readq(&bar0->adapter_status);
2055         if (!verify_xena_quiescence(nic, val64, nic->device_enabled_once)) {
2056                 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
2057                 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
2058                           (unsigned long long) val64);
2059                 return FAILURE;
2060         }
2061
2062         /*
2063          * With some switches, link might be already up at this point.
2064          * Because of this weird behavior, when we enable laser,
2065          * we may not get link. We need to handle this. We cannot
2066          * figure out which switch is misbehaving. So we are forced to
2067          * make a global change.
2068          */
2069
2070         /* Enabling Laser. */
2071         val64 = readq(&bar0->adapter_control);
2072         val64 |= ADAPTER_EOI_TX_ON;
2073         writeq(val64, &bar0->adapter_control);
2074
2075         if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2076                 /*
2077                  * Dont see link state interrupts initally on some switches,
2078                  * so directly scheduling the link state task here.
2079                  */
2080                 schedule_work(&nic->set_link_task);
2081         }
2082         /* SXE-002: Initialize link and activity LED */
2083         subid = nic->pdev->subsystem_device;
2084         if (((subid & 0xFF) >= 0x07) &&
2085             (nic->device_type == XFRAME_I_DEVICE)) {
2086                 val64 = readq(&bar0->gpio_control);
2087                 val64 |= 0x0000800000000000ULL;
2088                 writeq(val64, &bar0->gpio_control);
2089                 val64 = 0x0411040400000000ULL;
2090                 writeq(val64, (void __iomem *)bar0 + 0x2700);
2091         }
2092
2093         return SUCCESS;
2094 }
2095 /**
2096  * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2097  */
2098 static struct sk_buff *s2io_txdl_getskb(fifo_info_t *fifo_data, TxD_t *txdlp, int get_off)
2099 {
2100         nic_t *nic = fifo_data->nic;
2101         struct sk_buff *skb;
2102         TxD_t *txds;
2103         u16 j, frg_cnt;
2104
2105         txds = txdlp;
2106         if (txds->Host_Control == (u64)(long)nic->ufo_in_band_v) {
2107                 pci_unmap_single(nic->pdev, (dma_addr_t)
2108                         txds->Buffer_Pointer, sizeof(u64),
2109                         PCI_DMA_TODEVICE);
2110                 txds++;
2111         }
2112
2113         skb = (struct sk_buff *) ((unsigned long)
2114                         txds->Host_Control);
2115         if (!skb) {
2116                 memset(txdlp, 0, (sizeof(TxD_t) * fifo_data->max_txds));
2117                 return NULL;
2118         }
2119         pci_unmap_single(nic->pdev, (dma_addr_t)
2120                          txds->Buffer_Pointer,
2121                          skb->len - skb->data_len,
2122                          PCI_DMA_TODEVICE);
2123         frg_cnt = skb_shinfo(skb)->nr_frags;
2124         if (frg_cnt) {
2125                 txds++;
2126                 for (j = 0; j < frg_cnt; j++, txds++) {
2127                         skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2128                         if (!txds->Buffer_Pointer)
2129                                 break;
2130                         pci_unmap_page(nic->pdev, (dma_addr_t)
2131                                         txds->Buffer_Pointer,
2132                                        frag->size, PCI_DMA_TODEVICE);
2133                 }
2134         }
2135         memset(txdlp,0, (sizeof(TxD_t) * fifo_data->max_txds));
2136         return(skb);
2137 }
2138
2139 /**
2140  *  free_tx_buffers - Free all queued Tx buffers
2141  *  @nic : device private variable.
2142  *  Description:
2143  *  Free all queued Tx buffers.
2144  *  Return Value: void
2145 */
2146
2147 static void free_tx_buffers(struct s2io_nic *nic)
2148 {
2149         struct net_device *dev = nic->dev;
2150         struct sk_buff *skb;
2151         TxD_t *txdp;
2152         int i, j;
2153         mac_info_t *mac_control;
2154         struct config_param *config;
2155         int cnt = 0;
2156
2157         mac_control = &nic->mac_control;
2158         config = &nic->config;
2159
2160         for (i = 0; i < config->tx_fifo_num; i++) {
2161                 for (j = 0; j < config->tx_cfg[i].fifo_len - 1; j++) {
2162                         txdp = (TxD_t *) mac_control->fifos[i].list_info[j].
2163                             list_virt_addr;
2164                         skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2165                         if (skb) {
2166                                 dev_kfree_skb(skb);
2167                                 cnt++;
2168                         }
2169                 }
2170                 DBG_PRINT(INTR_DBG,
2171                           "%s:forcibly freeing %d skbs on FIFO%d\n",
2172                           dev->name, cnt, i);
2173                 mac_control->fifos[i].tx_curr_get_info.offset = 0;
2174                 mac_control->fifos[i].tx_curr_put_info.offset = 0;
2175         }
2176 }
2177
2178 /**
2179  *   stop_nic -  To stop the nic
2180  *   @nic ; device private variable.
2181  *   Description:
2182  *   This function does exactly the opposite of what the start_nic()
2183  *   function does. This function is called to stop the device.
2184  *   Return Value:
2185  *   void.
2186  */
2187
2188 static void stop_nic(struct s2io_nic *nic)
2189 {
2190         XENA_dev_config_t __iomem *bar0 = nic->bar0;
2191         register u64 val64 = 0;
2192         u16 interruptible;
2193         mac_info_t *mac_control;
2194         struct config_param *config;
2195
2196         mac_control = &nic->mac_control;
2197         config = &nic->config;
2198
2199         /*  Disable all interrupts */
2200         interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
2201         interruptible |= TX_PIC_INTR | RX_PIC_INTR;
2202         interruptible |= TX_MAC_INTR | RX_MAC_INTR;
2203         en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2204
2205         /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2206         val64 = readq(&bar0->adapter_control);
2207         val64 &= ~(ADAPTER_CNTL_EN);
2208         writeq(val64, &bar0->adapter_control);
2209 }
2210
2211 static int fill_rxd_3buf(nic_t *nic, RxD_t *rxdp, struct sk_buff *skb)
2212 {
2213         struct net_device *dev = nic->dev;
2214         struct sk_buff *frag_list;
2215         void *tmp;
2216
2217         /* Buffer-1 receives L3/L4 headers */
2218         ((RxD3_t*)rxdp)->Buffer1_ptr = pci_map_single
2219                         (nic->pdev, skb->data, l3l4hdr_size + 4,
2220                         PCI_DMA_FROMDEVICE);
2221
2222         /* skb_shinfo(skb)->frag_list will have L4 data payload */
2223         skb_shinfo(skb)->frag_list = dev_alloc_skb(dev->mtu + ALIGN_SIZE);
2224         if (skb_shinfo(skb)->frag_list == NULL) {
2225                 DBG_PRINT(ERR_DBG, "%s: dev_alloc_skb failed\n ", dev->name);
2226                 return -ENOMEM ;
2227         }
2228         frag_list = skb_shinfo(skb)->frag_list;
2229         frag_list->next = NULL;
2230         tmp = (void *)ALIGN((long)frag_list->data, ALIGN_SIZE + 1);
2231         frag_list->data = tmp;
2232         frag_list->tail = tmp;
2233
2234         /* Buffer-2 receives L4 data payload */
2235         ((RxD3_t*)rxdp)->Buffer2_ptr = pci_map_single(nic->pdev,
2236                                 frag_list->data, dev->mtu,
2237                                 PCI_DMA_FROMDEVICE);
2238         rxdp->Control_2 |= SET_BUFFER1_SIZE_3(l3l4hdr_size + 4);
2239         rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu);
2240
2241         return SUCCESS;
2242 }
2243
2244 /**
2245  *  fill_rx_buffers - Allocates the Rx side skbs
2246  *  @nic:  device private variable
2247  *  @ring_no: ring number
2248  *  Description:
2249  *  The function allocates Rx side skbs and puts the physical
2250  *  address of these buffers into the RxD buffer pointers, so that the NIC
2251  *  can DMA the received frame into these locations.
2252  *  The NIC supports 3 receive modes, viz
2253  *  1. single buffer,
2254  *  2. three buffer and
2255  *  3. Five buffer modes.
2256  *  Each mode defines how many fragments the received frame will be split
2257  *  up into by the NIC. The frame is split into L3 header, L4 Header,
2258  *  L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2259  *  is split into 3 fragments. As of now only single buffer mode is
2260  *  supported.
2261  *   Return Value:
2262  *  SUCCESS on success or an appropriate -ve value on failure.
2263  */
2264
2265 static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
2266 {
2267         struct net_device *dev = nic->dev;
2268         struct sk_buff *skb;
2269         RxD_t *rxdp;
2270         int off, off1, size, block_no, block_no1;
2271         u32 alloc_tab = 0;
2272         u32 alloc_cnt;
2273         mac_info_t *mac_control;
2274         struct config_param *config;
2275         u64 tmp;
2276         buffAdd_t *ba;
2277 #ifndef CONFIG_S2IO_NAPI
2278         unsigned long flags;
2279 #endif
2280         RxD_t *first_rxdp = NULL;
2281
2282         mac_control = &nic->mac_control;
2283         config = &nic->config;
2284         alloc_cnt = mac_control->rings[ring_no].pkt_cnt -
2285             atomic_read(&nic->rx_bufs_left[ring_no]);
2286
2287         block_no1 = mac_control->rings[ring_no].rx_curr_get_info.block_index;
2288         off1 = mac_control->rings[ring_no].rx_curr_get_info.offset;
2289         while (alloc_tab < alloc_cnt) {
2290                 block_no = mac_control->rings[ring_no].rx_curr_put_info.
2291                     block_index;
2292                 off = mac_control->rings[ring_no].rx_curr_put_info.offset;
2293
2294                 rxdp = mac_control->rings[ring_no].
2295                                 rx_blocks[block_no].rxds[off].virt_addr;
2296
2297                 if ((block_no == block_no1) && (off == off1) &&
2298                                         (rxdp->Host_Control)) {
2299                         DBG_PRINT(INTR_DBG, "%s: Get and Put",
2300                                   dev->name);
2301                         DBG_PRINT(INTR_DBG, " info equated\n");
2302                         goto end;
2303                 }
2304                 if (off && (off == rxd_count[nic->rxd_mode])) {
2305                         mac_control->rings[ring_no].rx_curr_put_info.
2306                             block_index++;
2307                         if (mac_control->rings[ring_no].rx_curr_put_info.
2308                             block_index == mac_control->rings[ring_no].
2309                                         block_count)
2310                                 mac_control->rings[ring_no].rx_curr_put_info.
2311                                         block_index = 0;
2312                         block_no = mac_control->rings[ring_no].
2313                                         rx_curr_put_info.block_index;
2314                         if (off == rxd_count[nic->rxd_mode])
2315                                 off = 0;
2316                         mac_control->rings[ring_no].rx_curr_put_info.
2317                                 offset = off;
2318                         rxdp = mac_control->rings[ring_no].
2319                                 rx_blocks[block_no].block_virt_addr;
2320                         DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2321                                   dev->name, rxdp);
2322                 }
2323 #ifndef CONFIG_S2IO_NAPI
2324                 spin_lock_irqsave(&nic->put_lock, flags);
2325                 mac_control->rings[ring_no].put_pos =
2326                     (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2327                 spin_unlock_irqrestore(&nic->put_lock, flags);
2328 #endif
2329                 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
2330                         ((nic->rxd_mode >= RXD_MODE_3A) &&
2331                                 (rxdp->Control_2 & BIT(0)))) {
2332                         mac_control->rings[ring_no].rx_curr_put_info.
2333                                         offset = off;
2334                         goto end;
2335                 }
2336                 /* calculate size of skb based on ring mode */
2337                 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
2338                                 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2339                 if (nic->rxd_mode == RXD_MODE_1)
2340                         size += NET_IP_ALIGN;
2341                 else if (nic->rxd_mode == RXD_MODE_3B)
2342                         size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
2343                 else
2344                         size = l3l4hdr_size + ALIGN_SIZE + BUF0_LEN + 4;
2345
2346                 /* allocate skb */
2347                 skb = dev_alloc_skb(size);
2348                 if(!skb) {
2349                         DBG_PRINT(ERR_DBG, "%s: Out of ", dev->name);
2350                         DBG_PRINT(ERR_DBG, "memory to allocate SKBs\n");
2351                         if (first_rxdp) {
2352                                 wmb();
2353                                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2354                         }
2355                         return -ENOMEM ;
2356                 }
2357                 if (nic->rxd_mode == RXD_MODE_1) {
2358                         /* 1 buffer mode - normal operation mode */
2359                         memset(rxdp, 0, sizeof(RxD1_t));
2360                         skb_reserve(skb, NET_IP_ALIGN);
2361                         ((RxD1_t*)rxdp)->Buffer0_ptr = pci_map_single
2362                             (nic->pdev, skb->data, size - NET_IP_ALIGN,
2363                                 PCI_DMA_FROMDEVICE);
2364                         rxdp->Control_2 = SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
2365
2366                 } else if (nic->rxd_mode >= RXD_MODE_3A) {
2367                         /*
2368                          * 2 or 3 buffer mode -
2369                          * Both 2 buffer mode and 3 buffer mode provides 128
2370                          * byte aligned receive buffers.
2371                          *
2372                          * 3 buffer mode provides header separation where in
2373                          * skb->data will have L3/L4 headers where as
2374                          * skb_shinfo(skb)->frag_list will have the L4 data
2375                          * payload
2376                          */
2377
2378                         memset(rxdp, 0, sizeof(RxD3_t));
2379                         ba = &mac_control->rings[ring_no].ba[block_no][off];
2380                         skb_reserve(skb, BUF0_LEN);
2381                         tmp = (u64)(unsigned long) skb->data;
2382                         tmp += ALIGN_SIZE;
2383                         tmp &= ~ALIGN_SIZE;
2384                         skb->data = (void *) (unsigned long)tmp;
2385                         skb->tail = (void *) (unsigned long)tmp;
2386
2387                         if (!(((RxD3_t*)rxdp)->Buffer0_ptr))
2388                                 ((RxD3_t*)rxdp)->Buffer0_ptr =
2389                                    pci_map_single(nic->pdev, ba->ba_0, BUF0_LEN,
2390                                            PCI_DMA_FROMDEVICE);
2391                         else
2392                                 pci_dma_sync_single_for_device(nic->pdev,
2393                                     (dma_addr_t) ((RxD3_t*)rxdp)->Buffer0_ptr,
2394                                     BUF0_LEN, PCI_DMA_FROMDEVICE);
2395                         rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2396                         if (nic->rxd_mode == RXD_MODE_3B) {
2397                                 /* Two buffer mode */
2398
2399                                 /*
2400                                  * Buffer2 will have L3/L4 header plus
2401                                  * L4 payload
2402                                  */
2403                                 ((RxD3_t*)rxdp)->Buffer2_ptr = pci_map_single
2404                                 (nic->pdev, skb->data, dev->mtu + 4,
2405                                                 PCI_DMA_FROMDEVICE);
2406
2407                                 /* Buffer-1 will be dummy buffer. Not used */
2408                                 if (!(((RxD3_t*)rxdp)->Buffer1_ptr)) {
2409                                         ((RxD3_t*)rxdp)->Buffer1_ptr =
2410                                                 pci_map_single(nic->pdev,
2411                                                 ba->ba_1, BUF1_LEN,
2412                                                 PCI_DMA_FROMDEVICE);
2413                                 }
2414                                 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2415                                 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2416                                                                 (dev->mtu + 4);
2417                         } else {
2418                                 /* 3 buffer mode */
2419                                 if (fill_rxd_3buf(nic, rxdp, skb) == -ENOMEM) {
2420                                         dev_kfree_skb_irq(skb);
2421                                         if (first_rxdp) {
2422                                                 wmb();
2423                                                 first_rxdp->Control_1 |=
2424                                                         RXD_OWN_XENA;
2425                                         }
2426                                         return -ENOMEM ;
2427                                 }
2428                         }
2429                         rxdp->Control_2 |= BIT(0);
2430                 }
2431                 rxdp->Host_Control = (unsigned long) (skb);
2432                 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2433                         rxdp->Control_1 |= RXD_OWN_XENA;
2434                 off++;
2435                 if (off == (rxd_count[nic->rxd_mode] + 1))
2436                         off = 0;
2437                 mac_control->rings[ring_no].rx_curr_put_info.offset = off;
2438
2439                 rxdp->Control_2 |= SET_RXD_MARKER;
2440                 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2441                         if (first_rxdp) {
2442                                 wmb();
2443                                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2444                         }
2445                         first_rxdp = rxdp;
2446                 }
2447                 atomic_inc(&nic->rx_bufs_left[ring_no]);
2448                 alloc_tab++;
2449         }
2450
2451       end:
2452         /* Transfer ownership of first descriptor to adapter just before
2453          * exiting. Before that, use memory barrier so that ownership
2454          * and other fields are seen by adapter correctly.
2455          */
2456         if (first_rxdp) {
2457                 wmb();
2458                 first_rxdp->Control_1 |= RXD_OWN_XENA;
2459         }
2460
2461         return SUCCESS;
2462 }
2463
2464 static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2465 {
2466         struct net_device *dev = sp->dev;
2467         int j;
2468         struct sk_buff *skb;
2469         RxD_t *rxdp;
2470         mac_info_t *mac_control;
2471         buffAdd_t *ba;
2472
2473         mac_control = &sp->mac_control;
2474         for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2475                 rxdp = mac_control->rings[ring_no].
2476                                 rx_blocks[blk].rxds[j].virt_addr;
2477                 skb = (struct sk_buff *)
2478                         ((unsigned long) rxdp->Host_Control);
2479                 if (!skb) {
2480                         continue;
2481                 }
2482                 if (sp->rxd_mode == RXD_MODE_1) {
2483                         pci_unmap_single(sp->pdev, (dma_addr_t)
2484                                  ((RxD1_t*)rxdp)->Buffer0_ptr,
2485                                  dev->mtu +
2486                                  HEADER_ETHERNET_II_802_3_SIZE
2487                                  + HEADER_802_2_SIZE +
2488                                  HEADER_SNAP_SIZE,
2489                                  PCI_DMA_FROMDEVICE);
2490                         memset(rxdp, 0, sizeof(RxD1_t));
2491                 } else if(sp->rxd_mode == RXD_MODE_3B) {
2492                         ba = &mac_control->rings[ring_no].
2493                                 ba[blk][j];
2494                         pci_unmap_single(sp->pdev, (dma_addr_t)
2495                                  ((RxD3_t*)rxdp)->Buffer0_ptr,
2496                                  BUF0_LEN,
2497                                  PCI_DMA_FROMDEVICE);
2498                         pci_unmap_single(sp->pdev, (dma_addr_t)
2499                                  ((RxD3_t*)rxdp)->Buffer1_ptr,
2500                                  BUF1_LEN,
2501                                  PCI_DMA_FROMDEVICE);
2502                         pci_unmap_single(sp->pdev, (dma_addr_t)
2503                                  ((RxD3_t*)rxdp)->Buffer2_ptr,
2504                                  dev->mtu + 4,
2505                                  PCI_DMA_FROMDEVICE);
2506                         memset(rxdp, 0, sizeof(RxD3_t));
2507                 } else {
2508                         pci_unmap_single(sp->pdev, (dma_addr_t)
2509                                 ((RxD3_t*)rxdp)->Buffer0_ptr, BUF0_LEN,
2510                                 PCI_DMA_FROMDEVICE);
2511                         pci_unmap_single(sp->pdev, (dma_addr_t)
2512                                 ((RxD3_t*)rxdp)->Buffer1_ptr,
2513                                 l3l4hdr_size + 4,
2514                                 PCI_DMA_FROMDEVICE);
2515                         pci_unmap_single(sp->pdev, (dma_addr_t)
2516                                 ((RxD3_t*)rxdp)->Buffer2_ptr, dev->mtu,
2517                                 PCI_DMA_FROMDEVICE);
2518                         memset(rxdp, 0, sizeof(RxD3_t));
2519                 }
2520                 dev_kfree_skb(skb);
2521                 atomic_dec(&sp->rx_bufs_left[ring_no]);
2522         }
2523 }
2524
2525 /**
2526  *  free_rx_buffers - Frees all Rx buffers
2527  *  @sp: device private variable.
2528  *  Description:
2529  *  This function will free all Rx buffers allocated by host.
2530  *  Return Value:
2531  *  NONE.
2532  */
2533
2534 static void free_rx_buffers(struct s2io_nic *sp)
2535 {
2536         struct net_device *dev = sp->dev;
2537         int i, blk = 0, buf_cnt = 0;
2538         mac_info_t *mac_control;
2539         struct config_param *config;
2540
2541         mac_control = &sp->mac_control;
2542         config = &sp->config;
2543
2544         for (i = 0; i < config->rx_ring_num; i++) {
2545                 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2546                         free_rxd_blk(sp,i,blk);
2547
2548                 mac_control->rings[i].rx_curr_put_info.block_index = 0;
2549                 mac_control->rings[i].rx_curr_get_info.block_index = 0;
2550                 mac_control->rings[i].rx_curr_put_info.offset = 0;
2551                 mac_control->rings[i].rx_curr_get_info.offset = 0;
2552                 atomic_set(&sp->rx_bufs_left[i], 0);
2553                 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2554                           dev->name, buf_cnt, i);
2555         }
2556 }
2557
2558 /**
2559  * s2io_poll - Rx interrupt handler for NAPI support
2560  * @dev : pointer to the device structure.
2561  * @budget : The number of packets that were budgeted to be processed
2562  * during  one pass through the 'Poll" function.
2563  * Description:
2564  * Comes into picture only if NAPI support has been incorporated. It does
2565  * the same thing that rx_intr_handler does, but not in a interrupt context
2566  * also It will process only a given number of packets.
2567  * Return value:
2568  * 0 on success and 1 if there are No Rx packets to be processed.
2569  */
2570
2571 #if defined(CONFIG_S2IO_NAPI)
2572 static int s2io_poll(struct net_device *dev, int *budget)
2573 {
2574         nic_t *nic = dev->priv;
2575         int pkt_cnt = 0, org_pkts_to_process;
2576         mac_info_t *mac_control;
2577         struct config_param *config;
2578         XENA_dev_config_t __iomem *bar0 = nic->bar0;
2579         u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
2580         int i;
2581
2582         atomic_inc(&nic->isr_cnt);
2583         mac_control = &nic->mac_control;
2584         config = &nic->config;
2585
2586         nic->pkts_to_process = *budget;
2587         if (nic->pkts_to_process > dev->quota)
2588                 nic->pkts_to_process = dev->quota;
2589         org_pkts_to_process = nic->pkts_to_process;
2590
2591         writeq(val64, &bar0->rx_traffic_int);
2592         val64 = readl(&bar0->rx_traffic_int);
2593
2594         for (i = 0; i < config->rx_ring_num; i++) {
2595                 rx_intr_handler(&mac_control->rings[i]);
2596                 pkt_cnt = org_pkts_to_process - nic->pkts_to_process;
2597                 if (!nic->pkts_to_process) {
2598                         /* Quota for the current iteration has been met */
2599                         goto no_rx;
2600                 }
2601         }
2602         if (!pkt_cnt)
2603                 pkt_cnt = 1;
2604
2605         dev->quota -= pkt_cnt;
2606         *budget -= pkt_cnt;
2607         netif_rx_complete(dev);
2608
2609         for (i = 0; i < config->rx_ring_num; i++) {
2610                 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2611                         DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
2612                         DBG_PRINT(ERR_DBG, " in Rx Poll!!\n");
2613                         break;
2614                 }
2615         }
2616         /* Re enable the Rx interrupts. */
2617         writeq(0x0, &bar0->rx_traffic_mask);
2618         val64 = readl(&bar0->rx_traffic_mask);
2619         atomic_dec(&nic->isr_cnt);
2620         return 0;
2621
2622 no_rx:
2623         dev->quota -= pkt_cnt;
2624         *budget -= pkt_cnt;
2625
2626         for (i = 0; i < config->rx_ring_num; i++) {
2627                 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2628                         DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
2629                         DBG_PRINT(ERR_DBG, " in Rx Poll!!\n");
2630                         break;
2631                 }
2632         }
2633         atomic_dec(&nic->isr_cnt);
2634         return 1;
2635 }
2636 #endif
2637
2638 #ifdef CONFIG_NET_POLL_CONTROLLER
2639 /**
2640  * s2io_netpoll - netpoll event handler entry point
2641  * @dev : pointer to the device structure.
2642  * Description:
2643  *      This function will be called by upper layer to check for events on the
2644  * interface in situations where interrupts are disabled. It is used for
2645  * specific in-kernel networking tasks, such as remote consoles and kernel
2646  * debugging over the network (example netdump in RedHat).
2647  */
2648 static void s2io_netpoll(struct net_device *dev)
2649 {
2650         nic_t *nic = dev->priv;
2651         mac_info_t *mac_control;
2652         struct config_param *config;
2653         XENA_dev_config_t __iomem *bar0 = nic->bar0;
2654         u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
2655         int i;
2656
2657         disable_irq(dev->irq);
2658
2659         atomic_inc(&nic->isr_cnt);
2660         mac_control = &nic->mac_control;
2661         config = &nic->config;
2662
2663         writeq(val64, &bar0->rx_traffic_int);
2664         writeq(val64, &bar0->tx_traffic_int);
2665
2666         /* we need to free up the transmitted skbufs or else netpoll will
2667          * run out of skbs and will fail and eventually netpoll application such
2668          * as netdump will fail.
2669          */
2670         for (i = 0; i < config->tx_fifo_num; i++)
2671                 tx_intr_handler(&mac_control->fifos[i]);
2672
2673         /* check for received packet and indicate up to network */
2674         for (i = 0; i < config->rx_ring_num; i++)
2675                 rx_intr_handler(&mac_control->rings[i]);
2676
2677         for (i = 0; i < config->rx_ring_num; i++) {
2678                 if (fill_rx_buffers(nic, i) == -ENOMEM) {
2679                         DBG_PRINT(ERR_DBG, "%s:Out of memory", dev->name);
2680                         DBG_PRINT(ERR_DBG, " in Rx Netpoll!!\n");
2681                         break;
2682                 }
2683         }
2684         atomic_dec(&nic->isr_cnt);
2685         enable_irq(dev->irq);
2686         return;
2687 }
2688 #endif
2689
2690 /**
2691  *  rx_intr_handler - Rx interrupt handler
2692  *  @nic: device private variable.
2693  *  Description:
2694  *  If the interrupt is because of a received frame or if the
2695  *  receive ring contains fresh as yet un-processed frames,this function is
2696  *  called. It picks out the RxD at which place the last Rx processing had
2697  *  stopped and sends the skb to the OSM's Rx handler and then increments
2698  *  the offset.
2699  *  Return Value:
2700  *  NONE.
2701  */
2702 static void rx_intr_handler(ring_info_t *ring_data)
2703 {
2704         nic_t *nic = ring_data->nic;
2705         struct net_device *dev = (struct net_device *) nic->dev;
2706         int get_block, put_block, put_offset;
2707         rx_curr_get_info_t get_info, put_info;
2708         RxD_t *rxdp;
2709         struct sk_buff *skb;
2710 #ifndef CONFIG_S2IO_NAPI
2711         int pkt_cnt = 0;
2712 #endif
2713         int i;
2714
2715         spin_lock(&nic->rx_lock);
2716         if (atomic_read(&nic->card_state) == CARD_DOWN) {
2717                 DBG_PRINT(INTR_DBG, "%s: %s going down for reset\n",
2718                           __FUNCTION__, dev->name);
2719                 spin_unlock(&nic->rx_lock);
2720                 return;
2721         }
2722
2723         get_info = ring_data->rx_curr_get_info;
2724         get_block = get_info.block_index;
2725         put_info = ring_data->rx_curr_put_info;
2726         put_block = put_info.block_index;
2727         rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
2728 #ifndef CONFIG_S2IO_NAPI
2729         spin_lock(&nic->put_lock);
2730         put_offset = ring_data->put_pos;
2731         spin_unlock(&nic->put_lock);
2732 #else
2733         put_offset = (put_block * (rxd_count[nic->rxd_mode] + 1)) +
2734                 put_info.offset;
2735 #endif
2736         while (RXD_IS_UP2DT(rxdp)) {
2737                 /* If your are next to put index then it's FIFO full condition */
2738                 if ((get_block == put_block) &&
2739                     (get_info.offset + 1) == put_info.offset) {
2740                         DBG_PRINT(INTR_DBG, "%s: Ring Full\n",dev->name);
2741                         break;
2742                 }
2743                 skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control);
2744                 if (skb == NULL) {
2745                         DBG_PRINT(ERR_DBG, "%s: The skb is ",
2746                                   dev->name);
2747                         DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
2748                         spin_unlock(&nic->rx_lock);
2749                         return;
2750                 }
2751                 if (nic->rxd_mode == RXD_MODE_1) {
2752                         pci_unmap_single(nic->pdev, (dma_addr_t)
2753                                  ((RxD1_t*)rxdp)->Buffer0_ptr,
2754                                  dev->mtu +
2755                                  HEADER_ETHERNET_II_802_3_SIZE +
2756                                  HEADER_802_2_SIZE +
2757                                  HEADER_SNAP_SIZE,
2758                                  PCI_DMA_FROMDEVICE);
2759                 } else if (nic->rxd_mode == RXD_MODE_3B) {
2760                         pci_dma_sync_single_for_cpu(nic->pdev, (dma_addr_t)
2761                                  ((RxD3_t*)rxdp)->Buffer0_ptr,
2762                                  BUF0_LEN, PCI_DMA_FROMDEVICE);
2763                         pci_unmap_single(nic->pdev, (dma_addr_t)
2764                                  ((RxD3_t*)rxdp)->Buffer2_ptr,
2765                                  dev->mtu + 4,
2766                                  PCI_DMA_FROMDEVICE);
2767                 } else {
2768                         pci_dma_sync_single_for_cpu(nic->pdev, (dma_addr_t)
2769                                          ((RxD3_t*)rxdp)->Buffer0_ptr, BUF0_LEN,
2770                                          PCI_DMA_FROMDEVICE);
2771                         pci_unmap_single(nic->pdev, (dma_addr_t)
2772                                          ((RxD3_t*)rxdp)->Buffer1_ptr,
2773                                          l3l4hdr_size + 4,
2774                                          PCI_DMA_FROMDEVICE);
2775                         pci_unmap_single(nic->pdev, (dma_addr_t)
2776                                          ((RxD3_t*)rxdp)->Buffer2_ptr,
2777                                          dev->mtu, PCI_DMA_FROMDEVICE);
2778                 }
2779                 prefetch(skb->data);
2780                 rx_osm_handler(ring_data, rxdp);
2781                 get_info.offset++;
2782                 ring_data->rx_curr_get_info.offset = get_info.offset;
2783                 rxdp = ring_data->rx_blocks[get_block].
2784                                 rxds[get_info.offset].virt_addr;
2785                 if (get_info.offset == rxd_count[nic->rxd_mode]) {
2786                         get_info.offset = 0;
2787                         ring_data->rx_curr_get_info.offset = get_info.offset;
2788                         get_block++;
2789                         if (get_block == ring_data->block_count)
2790                                 get_block = 0;
2791                         ring_data->rx_curr_get_info.block_index = get_block;
2792                         rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
2793                 }
2794
2795 #ifdef CONFIG_S2IO_NAPI
2796                 nic->pkts_to_process -= 1;
2797                 if (!nic->pkts_to_process)
2798                         break;
2799 #else
2800                 pkt_cnt++;
2801                 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
2802                         break;
2803 #endif
2804         }
2805         if (nic->lro) {
2806                 /* Clear all LRO sessions before exiting */
2807                 for (i=0; i<MAX_LRO_SESSIONS; i++) {
2808                         lro_t *lro = &nic->lro0_n[i];
2809                         if (lro->in_use) {
2810                                 update_L3L4_header(nic, lro);
2811                                 queue_rx_frame(lro->parent);
2812                                 clear_lro_session(lro);
2813                         }
2814                 }
2815         }
2816
2817         spin_unlock(&nic->rx_lock);
2818 }
2819
2820 /**
2821  *  tx_intr_handler - Transmit interrupt handler
2822  *  @nic : device private variable
2823  *  Description:
2824  *  If an interrupt was raised to indicate DMA complete of the
2825  *  Tx packet, this function is called. It identifies the last TxD
2826  *  whose buffer was freed and frees all skbs whose data have already
2827  *  DMA'ed into the NICs internal memory.
2828  *  Return Value:
2829  *  NONE
2830  */
2831
2832 static void tx_intr_handler(fifo_info_t *fifo_data)
2833 {
2834         nic_t *nic = fifo_data->nic;
2835         struct net_device *dev = (struct net_device *) nic->dev;
2836         tx_curr_get_info_t get_info, put_info;
2837         struct sk_buff *skb;
2838         TxD_t *txdlp;
2839
2840         get_info = fifo_data->tx_curr_get_info;
2841         put_info = fifo_data->tx_curr_put_info;
2842         txdlp = (TxD_t *) fifo_data->list_info[get_info.offset].
2843             list_virt_addr;
2844         while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
2845                (get_info.offset != put_info.offset) &&
2846                (txdlp->Host_Control)) {
2847                 /* Check for TxD errors */
2848                 if (txdlp->Control_1 & TXD_T_CODE) {
2849                         unsigned long long err;
2850                         err = txdlp->Control_1 & TXD_T_CODE;
2851                         if (err & 0x1) {
2852                                 nic->mac_control.stats_info->sw_stat.
2853                                                 parity_err_cnt++;
2854                         }
2855                         if ((err >> 48) == 0xA) {
2856                                 DBG_PRINT(TX_DBG, "TxD returned due \
2857 to loss of link\n");
2858                         }
2859                         else {
2860                                 DBG_PRINT(ERR_DBG, "***TxD error \
2861 %llx\n", err);
2862                         }
2863                 }
2864
2865                 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
2866                 if (skb == NULL) {
2867                         DBG_PRINT(ERR_DBG, "%s: Null skb ",
2868                         __FUNCTION__);
2869                         DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
2870                         return;
2871                 }
2872
2873                 /* Updating the statistics block */
2874                 nic->stats.tx_bytes += skb->len;
2875                 dev_kfree_skb_irq(skb);
2876
2877                 get_info.offset++;
2878                 if (get_info.offset == get_info.fifo_len + 1)
2879                         get_info.offset = 0;
2880                 txdlp = (TxD_t *) fifo_data->list_info
2881                     [get_info.offset].list_virt_addr;
2882                 fifo_data->tx_curr_get_info.offset =
2883                     get_info.offset;
2884         }
2885
2886         spin_lock(&nic->tx_lock);
2887         if (netif_queue_stopped(dev))
2888                 netif_wake_queue(dev);
2889         spin_unlock(&nic->tx_lock);
2890 }
2891
2892 /**
2893  *  s2io_mdio_write - Function to write in to MDIO registers
2894  *  @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
2895  *  @addr     : address value
2896  *  @value    : data value
2897  *  @dev      : pointer to net_device structure
2898  *  Description:
2899  *  This function is used to write values to the MDIO registers
2900  *  NONE
2901  */
2902 static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value, struct net_device *dev)
2903 {
2904         u64 val64 = 0x0;
2905         nic_t *sp = dev->priv;
2906         XENA_dev_config_t *bar0 = (XENA_dev_config_t *)sp->bar0;
2907
2908         //address transaction
2909         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2910                         | MDIO_MMD_DEV_ADDR(mmd_type)
2911                         | MDIO_MMS_PRT_ADDR(0x0);
2912         writeq(val64, &bar0->mdio_control);
2913         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2914         writeq(val64, &bar0->mdio_control);
2915         udelay(100);
2916
2917         //Data transaction
2918         val64 = 0x0;
2919         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2920                         | MDIO_MMD_DEV_ADDR(mmd_type)
2921                         | MDIO_MMS_PRT_ADDR(0x0)
2922                         | MDIO_MDIO_DATA(value)
2923                         | MDIO_OP(MDIO_OP_WRITE_TRANS);
2924         writeq(val64, &bar0->mdio_control);
2925         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2926         writeq(val64, &bar0->mdio_control);
2927         udelay(100);
2928
2929         val64 = 0x0;
2930         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2931         | MDIO_MMD_DEV_ADDR(mmd_type)
2932         | MDIO_MMS_PRT_ADDR(0x0)
2933         | MDIO_OP(MDIO_OP_READ_TRANS);
2934         writeq(val64, &bar0->mdio_control);
2935         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2936         writeq(val64, &bar0->mdio_control);
2937         udelay(100);
2938
2939 }
2940
2941 /**
2942  *  s2io_mdio_read - Function to write in to MDIO registers
2943  *  @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
2944  *  @addr     : address value
2945  *  @dev      : pointer to net_device structure
2946  *  Description:
2947  *  This function is used to read values to the MDIO registers
2948  *  NONE
2949  */
2950 static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
2951 {
2952         u64 val64 = 0x0;
2953         u64 rval64 = 0x0;
2954         nic_t *sp = dev->priv;
2955         XENA_dev_config_t *bar0 = (XENA_dev_config_t *)sp->bar0;
2956
2957         /* address transaction */
2958         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2959                         | MDIO_MMD_DEV_ADDR(mmd_type)
2960                         | MDIO_MMS_PRT_ADDR(0x0);
2961         writeq(val64, &bar0->mdio_control);
2962         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2963         writeq(val64, &bar0->mdio_control);
2964         udelay(100);
2965
2966         /* Data transaction */
2967         val64 = 0x0;
2968         val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2969                         | MDIO_MMD_DEV_ADDR(mmd_type)
2970                         | MDIO_MMS_PRT_ADDR(0x0)
2971                         | MDIO_OP(MDIO_OP_READ_TRANS);
2972         writeq(val64, &bar0->mdio_control);
2973         val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2974         writeq(val64, &bar0->mdio_control);
2975         udelay(100);
2976
2977         /* Read the value from regs */
2978         rval64 = readq(&bar0->mdio_control);
2979         rval64 = rval64 & 0xFFFF0000;
2980         rval64 = rval64 >> 16;
2981         return rval64;
2982 }
2983 /**
2984  *  s2io_chk_xpak_counter - Function to check the status of the xpak counters
2985  *  @counter      : couter value to be updated
2986  *  @flag         : flag to indicate the status
2987  *  @type         : counter type
2988  *  Description:
2989  *  This function is to check the status of the xpak counters value
2990  *  NONE
2991  */
2992
2993 static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index, u16 flag, u16 type)
2994 {
2995         u64 mask = 0x3;
2996         u64 val64;
2997         int i;
2998         for(i = 0; i <index; i++)
2999                 mask = mask << 0x2;
3000
3001         if(flag > 0)
3002         {
3003                 *counter = *counter + 1;
3004                 val64 = *regs_stat & mask;
3005                 val64 = val64 >> (index * 0x2);
3006                 val64 = val64 + 1;
3007                 if(val64 == 3)
3008                 {
3009                         switch(type)
3010                         {
3011                         case 1:
3012                                 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3013                                           "service. Excessive temperatures may "
3014                                           "result in premature transceiver "
3015                                           "failure \n");
3016                         break;
3017                         case 2:
3018                                 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3019                                           "service Excessive bias currents may "
3020                                           "indicate imminent laser diode "
3021                                           "failure \n");
3022                         break;
3023                         case 3:
3024                                 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3025                                           "service Excessive laser output "
3026                                           "power may saturate far-end "
3027                                           "receiver\n");
3028                         break;
3029                         default:
3030                                 DBG_PRINT(ERR_DBG, "Incorrect XPAK Alarm "
3031                                           "type \n");
3032                         }
3033                         val64 = 0x0;
3034                 }
3035                 val64 = val64 << (index * 0x2);
3036                 *regs_stat = (*regs_stat & (~mask)) | (val64);
3037
3038         } else {
3039                 *regs_stat = *regs_stat & (~mask);
3040         }
3041 }
3042
3043 /**
3044  *  s2io_updt_xpak_counter - Function to update the xpak counters
3045  *  @dev         : pointer to net_device struct
3046  *  Description:
3047  *  This function is to upate the status of the xpak counters value
3048  *  NONE
3049  */
3050 static void s2io_updt_xpak_counter(struct net_device *dev)
3051 {
3052         u16 flag  = 0x0;
3053         u16 type  = 0x0;
3054         u16 val16 = 0x0;
3055         u64 val64 = 0x0;
3056         u64 addr  = 0x0;
3057
3058         nic_t *sp = dev->priv;
3059         StatInfo_t *stat_info = sp->mac_control.stats_info;
3060
3061         /* Check the communication with the MDIO slave */
3062         addr = 0x0000;
3063         val64 = 0x0;
3064         val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3065         if((val64 == 0xFFFF) || (val64 == 0x0000))
3066         {
3067                 DBG_PRINT(ERR_DBG, "ERR: MDIO slave access failed - "
3068                           "Returned %llx\n", (unsigned long long)val64);
3069                 return;
3070         }
3071
3072         /* Check for the expecte value of 2040 at PMA address 0x0000 */
3073         if(val64 != 0x2040)
3074         {
3075                 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - ");
3076                 DBG_PRINT(ERR_DBG, "Returned: %llx- Expected: 0x2040\n",
3077                           (unsigned long long)val64);
3078                 return;
3079         }
3080
3081         /* Loading the DOM register to MDIO register */
3082         addr = 0xA100;
3083         s2io_mdio_write(MDIO_MMD_PMA_DEV_ADDR, addr, val16, dev);
3084         val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3085
3086         /* Reading the Alarm flags */
3087         addr = 0xA070;
3088         val64 = 0x0;
3089         val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3090
3091         flag = CHECKBIT(val64, 0x7);
3092         type = 1;
3093         s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_transceiver_temp_high,
3094                                 &stat_info->xpak_stat.xpak_regs_stat,
3095                                 0x0, flag, type);
3096
3097         if(CHECKBIT(val64, 0x6))
3098                 stat_info->xpak_stat.alarm_transceiver_temp_low++;
3099
3100         flag = CHECKBIT(val64, 0x3);
3101         type = 2;
3102         s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_bias_current_high,
3103                                 &stat_info->xpak_stat.xpak_regs_stat,
3104                                 0x2, flag, type);
3105
3106         if(CHECKBIT(val64, 0x2))
3107                 stat_info->xpak_stat.alarm_laser_bias_current_low++;
3108
3109         flag = CHECKBIT(val64, 0x1);
3110         type = 3;
3111         s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_output_power_high,
3112                                 &stat_info->xpak_stat.xpak_regs_stat,
3113                                 0x4, flag, type);
3114
3115         if(CHECKBIT(val64, 0x0))
3116                 stat_info->xpak_stat.alarm_laser_output_power_low++;
3117
3118         /* Reading the Warning flags */
3119         addr = 0xA074;
3120         val64 = 0x0;
3121         val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3122
3123         if(CHECKBIT(val64, 0x7))
3124                 stat_info->xpak_stat.warn_transceiver_temp_high++;
3125
3126         if(CHECKBIT(val64, 0x6))
3127                 stat_info->xpak_stat.warn_transceiver_temp_low++;
3128
3129         if(CHECKBIT(val64, 0x3))
3130                 stat_info->xpak_stat.warn_laser_bias_current_high++;
3131
3132         if(CHECKBIT(val64, 0x2))
3133                 stat_info->xpak_stat.warn_laser_bias_current_low++;
3134
3135         if(CHECKBIT(val64, 0x1))
3136                 stat_info->xpak_stat.warn_laser_output_power_high++;
3137
3138         if(CHECKBIT(val64, 0x0))
3139                 stat_info->xpak_stat.warn_laser_output_power_low++;
3140 }
3141
3142 /**
3143  *  alarm_intr_handler - Alarm Interrrupt handler
3144  *  @nic: device private variable
3145  *  Description: If the interrupt was neither because of Rx packet or Tx
3146  *  complete, this function is called. If the interrupt was to indicate
3147  *  a loss of link, the OSM link status handler is invoked for any other
3148  *  alarm interrupt the block that raised the interrupt is displayed
3149  *  and a H/W reset is issued.
3150  *  Return Value:
3151  *  NONE
3152 */
3153
3154 static void alarm_intr_handler(struct s2io_nic *nic)
3155 {
3156         struct net_device *dev = (struct net_device *) nic->dev;
3157         XENA_dev_config_t __iomem *bar0 = nic->bar0;
3158         register u64 val64 = 0, err_reg = 0;
3159         u64 cnt;
3160         int i;
3161         nic->mac_control.stats_info->sw_stat.ring_full_cnt = 0;
3162         /* Handling the XPAK counters update */
3163         if(nic->mac_control.stats_info->xpak_stat.xpak_timer_count < 72000) {
3164                 /* waiting for an hour */
3165                 nic->mac_control.stats_info->xpak_stat.xpak_timer_count++;
3166         } else {
3167                 s2io_updt_xpak_counter(dev);
3168                 /* reset the count to zero */
3169                 nic->mac_control.stats_info->xpak_stat.xpak_timer_count = 0;
3170         }
3171
3172         /* Handling link status change error Intr */
3173         if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
3174                 err_reg = readq(&bar0->mac_rmac_err_reg);
3175                 writeq(err_reg, &bar0->mac_rmac_err_reg);
3176                 if (err_reg & RMAC_LINK_STATE_CHANGE_INT) {
3177                         schedule_work(&nic->set_link_task);
3178                 }
3179         }
3180
3181         /* Handling Ecc errors */
3182         val64 = readq(&bar0->mc_err_reg);
3183         writeq(val64, &bar0->mc_err_reg);
3184         if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
3185                 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
3186                         nic->mac_control.stats_info->sw_stat.
3187                                 double_ecc_errs++;
3188                         DBG_PRINT(INIT_DBG, "%s: Device indicates ",
3189                                   dev->name);
3190                         DBG_PRINT(INIT_DBG, "double ECC error!!\n");
3191                         if (nic->device_type != XFRAME_II_DEVICE) {
3192                                 /* Reset XframeI only if critical error */
3193                                 if (val64 & (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
3194                                              MC_ERR_REG_MIRI_ECC_DB_ERR_1)) {
3195                                         netif_stop_queue(dev);
3196                                         schedule_work(&nic->rst_timer_task);
3197                                         nic->mac_control.stats_info->sw_stat.
3198                                                         soft_reset_cnt++;
3199                                 }
3200                         }
3201                 } else {
3202                         nic->mac_control.stats_info->sw_stat.
3203                                 single_ecc_errs++;
3204                 }
3205         }
3206
3207         /* In case of a serious error, the device will be Reset. */
3208         val64 = readq(&bar0->serr_source);
3209         if (val64 & SERR_SOURCE_ANY) {
3210                 nic->mac_control.stats_info->sw_stat.serious_err_cnt++;
3211                 DBG_PRINT(ERR_DBG, "%s: Device indicates ", dev->name);
3212                 DBG_PRINT(ERR_DBG, "serious error %llx!!\n",
3213                           (unsigned long long)val64);
3214                 netif_stop_queue(dev);
3215                 schedule_work(&nic->rst_timer_task);
3216                 nic->mac_control.stats_info->sw_stat.soft_reset_cnt++;
3217         }
3218
3219         /*
3220          * Also as mentioned in the latest Errata sheets if the PCC_FB_ECC
3221          * Error occurs, the adapter will be recycled by disabling the
3222          * adapter enable bit and enabling it again after the device
3223          * becomes Quiescent.
3224          */
3225         val64 = readq(&bar0->pcc_err_reg);
3226         writeq(val64, &bar0->pcc_err_reg);
3227         if (val64 & PCC_FB_ECC_DB_ERR) {
3228                 u64 ac = readq(&bar0->adapter_control);
3229                 ac &= ~(ADAPTER_CNTL_EN);
3230                 writeq(ac, &bar0->adapter_control);
3231                 ac = readq(&bar0->adapter_control);
3232                 schedule_work(&nic->set_link_task);
3233         }
3234         /* Check for data parity error */
3235         val64 = readq(&bar0->pic_int_status);
3236         if (val64 & PIC_INT_GPIO) {
3237                 val64 = readq(&bar0->gpio_int_reg);
3238                 if (val64 & GPIO_INT_REG_DP_ERR_INT) {
3239                         nic->mac_control.stats_info->sw_stat.parity_err_cnt++;
3240                         schedule_work(&nic->rst_timer_task);
3241                         nic->mac_control.stats_info->sw_stat.soft_reset_cnt++;
3242                 }
3243         }
3244
3245         /* Check for ring full counter */
3246         if (nic->device_type & XFRAME_II_DEVICE) {
3247                 val64 = readq(&bar0->ring_bump_counter1);
3248                 for (i=0; i<4; i++) {
3249                         cnt = ( val64 & vBIT(0xFFFF,(i*16),16));
3250                         cnt >>= 64 - ((i+1)*16);
3251                         nic->mac_control.stats_info->sw_stat.ring_full_cnt
3252                                 += cnt;
3253                 }
3254
3255                 val64 = readq(&bar0->ring_bump_counter2);
3256                 for (i=0; i<4; i++) {
3257                         cnt = ( val64 & vBIT(0xFFFF,(i*16),16));
3258                         cnt >>= 64 - ((i+1)*16);
3259                         nic->mac_control.stats_info->sw_stat.ring_full_cnt
3260                                 += cnt;
3261                 }
3262         }
3263
3264         /* Other type of interrupts are not being handled now,  TODO */
3265 }
3266
3267 /**
3268  *  wait_for_cmd_complete - waits for a command to complete.
3269  *  @sp : private member of the device structure, which is a pointer to the
3270  *  s2io_nic structure.
3271  *  Description: Function that waits for a command to Write into RMAC
3272  *  ADDR DATA registers to be completed and returns either success or
3273  *  error depending on whether the command was complete or not.
3274  *  Return value:
3275  *   SUCCESS on success and FAILURE on failure.
3276  */
3277
3278 static int wait_for_cmd_complete(void *addr, u64 busy_bit)
3279 {
3280         int ret = FAILURE, cnt = 0;
3281         u64 val64;
3282
3283         while (TRUE) {
3284                 val64 = readq(addr);
3285                 if (!(val64 & busy_bit)) {
3286                         ret = SUCCESS;
3287                         break;
3288                 }
3289
3290                 if(in_interrupt())
3291                         mdelay(50);
3292                 else
3293                         msleep(50);
3294
3295                 if (cnt++ > 10)
3296                         break;
3297         }
3298         return ret;
3299 }
3300
3301 /**
3302  *  s2io_reset - Resets the card.
3303  *  @sp : private member of the device structure.
3304  *  Description: Function to Reset the card. This function then also
3305  *  restores the previously saved PCI configuration space registers as
3306  *  the card reset also resets the configuration space.
3307  *  Return value:
3308  *  void.
3309  */
3310
3311 static void s2io_reset(nic_t * sp)
3312 {
3313         XENA_dev_config_t __iomem *bar0 = sp->bar0;
3314         u64 val64;
3315         u16 subid, pci_cmd;
3316
3317         /* Back up  the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
3318         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
3319
3320         val64 = SW_RESET_ALL;
3321         writeq(val64, &bar0->sw_reset);
3322
3323         /*
3324          * At this stage, if the PCI write is indeed completed, the
3325          * card is reset and so is the PCI Config space of the device.
3326          * So a read cannot be issued at this stage on any of the
3327          * registers to ensure the write into "sw_reset" register
3328          * has gone through.
3329          * Question: Is there any system call that will explicitly force
3330          * all the write commands still pending on the bus to be pushed
3331          * through?
3332          * As of now I'am just giving a 250ms delay and hoping that the
3333          * PCI write to sw_reset register is done by this time.
3334          */
3335         msleep(250);
3336         if (strstr(sp->product_name, "CX4")) {
3337                 msleep(750);
3338         }
3339
3340         /* Restore the PCI state saved during initialization. */
3341         pci_restore_state(sp->pdev);
3342         pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
3343                                      pci_cmd);
3344         s2io_init_pci(sp);
3345
3346         msleep(250);
3347
3348         /* Set swapper to enable I/O register access */
3349         s2io_set_swapper(sp);
3350
3351         /* Restore the MSIX table entries from local variables */
3352         restore_xmsi_data(sp);
3353
3354         /* Clear certain PCI/PCI-X fields after reset */
3355         if (sp->device_type == XFRAME_II_DEVICE) {
3356                 /* Clear "detected parity error" bit */
3357                 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
3358
3359                 /* Clearing PCIX Ecc status register */
3360                 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
3361
3362                 /* Clearing PCI_STATUS error reflected here */
3363                 writeq(BIT(62), &bar0->txpic_int_reg);
3364         }
3365
3366         /* Reset device statistics maintained by OS */
3367         memset(&sp->stats, 0, sizeof (struct net_device_stats));
3368
3369         /* SXE-002: Configure link and activity LED to turn it off */
3370         subid = sp->pdev->subsystem_device;
3371         if (((subid & 0xFF) >= 0x07) &&
3372             (sp->device_type == XFRAME_I_DEVICE)) {
3373                 val64 = readq(&bar0->gpio_control);
3374                 val64 |= 0x0000800000000000ULL;
3375                 writeq(val64, &bar0->gpio_control);
3376                 val64 = 0x0411040400000000ULL;
3377                 writeq(val64, (void __iomem *)bar0 + 0x2700);
3378         }
3379
3380         /*
3381          * Clear spurious ECC interrupts that would have occured on
3382          * XFRAME II cards after reset.
3383          */
3384         if (sp->device_type == XFRAME_II_DEVICE) {
3385                 val64 = readq(&bar0->pcc_err_reg);
3386                 writeq(val64, &bar0->pcc_err_reg);
3387         }
3388
3389         sp->device_enabled_once = FALSE;
3390 }
3391
3392 /**
3393  *  s2io_set_swapper - to set the swapper controle on the card
3394  *  @sp : private member of the device structure,
3395  *  pointer to the s2io_nic structure.
3396  *  Description: Function to set the swapper control on the card
3397  *  correctly depending on the 'endianness' of the system.
3398  *  Return value:
3399  *  SUCCESS on success and FAILURE on failure.
3400  */
3401
3402 static int s2io_set_swapper(nic_t * sp)
3403 {
3404         struct net_device *dev = sp->dev;
3405         XENA_dev_config_t __iomem *bar0 = sp->bar0;
3406         u64 val64, valt, valr;
3407
3408         /*
3409          * Set proper endian settings and verify the same by reading
3410          * the PIF Feed-back register.
3411          */
3412
3413         val64 = readq(&bar0->pif_rd_swapper_fb);
3414         if (val64 != 0x0123456789ABCDEFULL) {
3415                 int i = 0;
3416                 u64 value[] = { 0xC30000C3C30000C3ULL,   /* FE=1, SE=1 */
3417                                 0x8100008181000081ULL,  /* FE=1, SE=0 */
3418                                 0x4200004242000042ULL,  /* FE=0, SE=1 */
3419                                 0};                     /* FE=0, SE=0 */
3420
3421                 while(i<4) {
3422                         writeq(value[i], &bar0->swapper_ctrl);
3423                         val64 = readq(&bar0->pif_rd_swapper_fb);
3424                         if (val64 == 0x0123456789ABCDEFULL)
3425                                 break;
3426                         i++;
3427                 }
3428                 if (i == 4) {
3429                         DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3430                                 dev->name);
3431                         DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3432                                 (unsigned long long) val64);
3433                         return FAILURE;
3434                 }
3435                 valr = value[i];
3436         } else {
3437                 valr = readq(&bar0->swapper_ctrl);
3438         }
3439
3440         valt = 0x0123456789ABCDEFULL;
3441         writeq(valt, &bar0->xmsi_address);
3442         val64 = readq(&bar0->xmsi_address);
3443
3444         if(val64 != valt) {
3445                 int i = 0;
3446                 u64 value[] = { 0x00C3C30000C3C300ULL,  /* FE=1, SE=1 */
3447                                 0x0081810000818100ULL,  /* FE=1, SE=0 */
3448                                 0x0042420000424200ULL,  /* FE=0, SE=1 */
3449                                 0};                     /* FE=0, SE=0 */
3450
3451                 while(i<4) {
3452                         writeq((value[i] | valr), &bar0->swapper_ctrl);
3453                         writeq(valt, &bar0->xmsi_address);
3454                         val64 = readq(&bar0->xmsi_address);
3455                         if(val64 == valt)
3456                                 break;
3457                         i++;
3458                 }
3459                 if(i == 4) {
3460                         unsigned long long x = val64;
3461                         DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr ");
3462                         DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x);
3463                         return FAILURE;
3464                 }
3465         }
3466         val64 = readq(&bar0->swapper_ctrl);
3467         val64 &= 0xFFFF000000000000ULL;
3468
3469 #ifdef  __BIG_ENDIAN
3470         /*
3471          * The device by default set to a big endian format, so a
3472          * big endian driver need not set anything.
3473          */
3474         val64 |= (SWAPPER_CTRL_TXP_FE |
3475                  SWAPPER_CTRL_TXP_SE |
3476                  SWAPPER_CTRL_TXD_R_FE |
3477                  SWAPPER_CTRL_TXD_W_FE |
3478                  SWAPPER_CTRL_TXF_R_FE |
3479                  SWAPPER_CTRL_RXD_R_FE |
3480                  SWAPPER_CTRL_RXD_W_FE |
3481                  SWAPPER_CTRL_RXF_W_FE |
3482                  SWAPPER_CTRL_XMSI_FE |
3483                  SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
3484         if (sp->intr_type == INTA)
3485                 val64 |= SWAPPER_CTRL_XMSI_SE;
3486         writeq(val64, &bar0->swapper_ctrl);
3487 #else
3488         /*
3489          * Initially we enable all bits to make it accessible by the
3490          * driver, then we selectively enable only those bits that
3491          * we want to set.
3492          */
3493         val64 |= (SWAPPER_CTRL_TXP_FE |
3494                  SWAPPER_CTRL_TXP_SE |
3495                  SWAPPER_CTRL_TXD_R_FE |
3496                  SWAPPER_CTRL_TXD_R_SE |
3497                  SWAPPER_CTRL_TXD_W_FE |
3498                  SWAPPER_CTRL_TXD_W_SE |
3499                  SWAPPER_CTRL_TXF_R_FE |
3500                  SWAPPER_CTRL_RXD_R_FE |
3501                  SWAPPER_CTRL_RXD_R_SE |
3502                  SWAPPER_CTRL_RXD_W_FE |
3503                  SWAPPER_CTRL_RXD_W_SE |
3504                  SWAPPER_CTRL_RXF_W_FE |
3505                  SWAPPER_CTRL_XMSI_FE |
3506                  SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
3507         if (sp->intr_type == INTA)
3508                 val64 |= SWAPPER_CTRL_XMSI_SE;
3509         writeq(val64, &bar0->swapper_ctrl);
3510 #endif
3511         val64 = readq(&bar0->swapper_ctrl);
3512
3513         /*
3514          * Verifying if endian settings are accurate by reading a
3515          * feedback register.
3516          */
3517         val64 = readq(&bar0->pif_rd_swapper_fb);
3518         if (val64 != 0x0123456789ABCDEFULL) {
3519                 /* Endian settings are incorrect, calls for another dekko. */
3520                 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3521                           dev->name);
3522                 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3523                           (unsigned long long) val64);
3524                 return FAILURE;
3525         }
3526
3527         return SUCCESS;
3528 }
3529
3530 static int wait_for_msix_trans(nic_t *nic, int i)
3531 {
3532         XENA_dev_config_t __iomem *bar0 = nic->bar0;
3533         u64 val64;
3534         int ret = 0, cnt = 0;
3535
3536         do {
3537                 val64 = readq(&bar0->xmsi_access);
3538                 if (!(val64 & BIT(15)))
3539                         break;
3540                 mdelay(1);
3541                 cnt++;
3542         } while(cnt < 5);
3543         if (cnt == 5) {
3544                 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3545                 ret = 1;
3546         }
3547
3548         return ret;
3549 }
3550
3551 static void restore_xmsi_data(nic_t *nic)
3552 {
3553         XENA_dev_config_t __iomem *bar0 = nic->bar0;
3554         u64 val64;
3555         int i;
3556
3557         for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
3558                 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3559                 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3560                 val64 = (BIT(7) | BIT(15) | vBIT(i, 26, 6));
3561                 writeq(val64, &bar0->xmsi_access);
3562                 if (wait_for_msix_trans(nic, i)) {
3563                         DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3564                         continue;
3565                 }
3566         }
3567 }
3568
3569 static void store_xmsi_data(nic_t *nic)
3570 {
3571         XENA_dev_config_t __iomem *bar0 = nic->bar0;
3572         u64 val64, addr, data;
3573         int i;
3574
3575         /* Store and display */
3576         for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
3577                 val64 = (BIT(15) | vBIT(i, 26, 6));
3578                 writeq(val64, &bar0->xmsi_access);
3579                 if (wait_for_msix_trans(nic, i)) {
3580                         DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3581                         continue;
3582                 }
3583                 addr = readq(&bar0->xmsi_address);
3584                 data = readq(&bar0->xmsi_data);
3585                 if (addr && data) {
3586                         nic->msix_info[i].addr = addr;
3587                         nic->msix_info[i].data = data;
3588                 }
3589         }
3590 }
3591
3592 int s2io_enable_msi(nic_t *nic)
3593 {
3594         XENA_dev_config_t __iomem *bar0 = nic->bar0;
3595         u16 msi_ctrl, msg_val;
3596         struct config_param *config = &nic->config;
3597         struct net_device *dev = nic->dev;
3598         u64 val64, tx_mat, rx_mat;
3599         int i, err;
3600
3601         val64 = readq(&bar0->pic_control);
3602         val64 &= ~BIT(1);
3603         writeq(val64, &bar0->pic_control);
3604
3605         err = pci_enable_msi(nic->pdev);
3606         if (err) {
3607                 DBG_PRINT(ERR_DBG, "%s: enabling MSI failed\n",
3608                           nic->dev->name);
3609                 return err;
3610         }
3611
3612         /*
3613          * Enable MSI and use MSI-1 in stead of the standard MSI-0
3614          * for interrupt handling.
3615          */
3616         pci_read_config_word(nic->pdev, 0x4c, &msg_val);
3617         msg_val ^= 0x1;
3618         pci_write_config_word(nic->pdev, 0x4c, msg_val);
3619         pci_read_config_word(nic->pdev, 0x4c, &msg_val);
3620
3621         pci_read_config_word(nic->pdev, 0x42, &msi_ctrl);
3622         msi_ctrl |= 0x10;
3623         pci_write_config_word(nic->pdev, 0x42, msi_ctrl);
3624
3625         /* program MSI-1 into all usable Tx_Mat and Rx_Mat fields */
3626         tx_mat = readq(&bar0->tx_mat0_n[0]);
3627         for (i=0; i<config->tx_fifo_num; i++) {
3628                 tx_mat |= TX_MAT_SET(i, 1);
3629         }
3630         writeq(tx_mat, &bar0->tx_mat0_n[0]);
3631
3632         rx_mat = readq(&bar0->rx_mat);
3633         for (i=0; i<config->rx_ring_num; i++) {
3634                 rx_mat |= RX_MAT_SET(i, 1);
3635         }
3636         writeq(rx_mat, &bar0->rx_mat);
3637
3638         dev->irq = nic->pdev->irq;
3639         return 0;
3640 }
3641
3642 static int s2io_enable_msi_x(nic_t *nic)
3643 {
3644         XENA_dev_config_t __iomem *bar0 = nic->bar0;
3645         u64 tx_mat, rx_mat;
3646         u16 msi_control; /* Temp variable */
3647         int ret, i, j, msix_indx = 1;
3648
3649         nic->entries = kmalloc(MAX_REQUESTED_MSI_X * sizeof(struct msix_entry),
3650                                GFP_KERNEL);
3651         if (nic->entries == NULL) {
3652                 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", __FUNCTION__);
3653                 return -ENOMEM;
3654         }
3655         memset(nic->entries, 0, MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3656
3657         nic->s2io_entries =
3658                 kmalloc(MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry),
3659                                    GFP_KERNEL);
3660         if (nic->s2io_entries == NULL) {
3661                 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", __FUNCTION__);
3662                 kfree(nic->entries);
3663                 return -ENOMEM;
3664         }
3665         memset(nic->s2io_entries, 0,
3666                MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
3667
3668         for (i=0; i< MAX_REQUESTED_MSI_X; i++) {
3669                 nic->entries[i].entry = i;
3670                 nic->s2io_entries[i].entry = i;
3671                 nic->s2io_entries[i].arg = NULL;
3672                 nic->s2io_entries[i].in_use = 0;
3673         }
3674
3675         tx_mat = readq(&bar0->tx_mat0_n[0]);
3676         for (i=0; i<nic->config.tx_fifo_num; i++, msix_indx++) {
3677                 tx_mat |= TX_MAT_SET(i, msix_indx);
3678                 nic->s2io_entries[msix_indx].arg = &nic->mac_control.fifos[i];
3679                 nic->s2io_entries[msix_indx].type = MSIX_FIFO_TYPE;
3680                 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3681         }
3682         writeq(tx_mat, &bar0->tx_mat0_n[0]);
3683
3684         if (!nic->config.bimodal) {
3685                 rx_mat = readq(&bar0->rx_mat);
3686                 for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) {
3687                         rx_mat |= RX_MAT_SET(j, msix_indx);
3688                         nic->s2io_entries[msix_indx].arg = &nic->mac_control.rings[j];
3689                         nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
3690                         nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3691                 }
3692                 writeq(rx_mat, &bar0->rx_mat);
3693         } else {
3694                 tx_mat = readq(&bar0->tx_mat0_n[7]);
3695                 for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) {
3696                         tx_mat |= TX_MAT_SET(i, msix_indx);
3697                         nic->s2io_entries[msix_indx].arg = &nic->mac_control.rings[j];
3698                         nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
3699                         nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3700                 }
3701                 writeq(tx_mat, &bar0->tx_mat0_n[7]);
3702         }
3703
3704         nic->avail_msix_vectors = 0;
3705         ret = pci_enable_msix(nic->pdev, nic->entries, MAX_REQUESTED_MSI_X);
3706         /* We fail init if error or we get less vectors than min required */
3707         if (ret >= (nic->config.tx_fifo_num + nic->config.rx_ring_num + 1)) {
3708                 nic->avail_msix_vectors = ret;
3709                 ret = pci_enable_msix(nic->pdev, nic->entries, ret);
3710         }
3711         if (ret) {
3712                 DBG_PRINT(ERR_DBG, "%s: Enabling MSIX failed\n", nic->dev->name);
3713                 kfree(nic->entries);
3714                 kfree(nic->s2io_entries);
3715                 nic->entries = NULL;
3716                 nic->s2io_entries = NULL;
3717                 nic->avail_msix_vectors = 0;
3718                 return -ENOMEM;
3719         }
3720         if (!nic->avail_msix_vectors)
3721                 nic->avail_msix_vectors = MAX_REQUESTED_MSI_X;
3722
3723         /*
3724          * To enable MSI-X, MSI also needs to be enabled, due to a bug
3725          * in the herc NIC. (Temp change, needs to be removed later)
3726          */
3727         pci_read_config_word(nic->pdev, 0x42, &msi_control);
3728         msi_control |= 0x1; /* Enable MSI */
3729         pci_write_config_word(nic->pdev, 0x42, msi_control);
3730
3731         return 0;
3732 }
3733
3734 /* ********************************************************* *
3735  * Functions defined below concern the OS part of the driver *
3736  * ********************************************************* */
3737
3738 /**
3739  *  s2io_open - open entry point of the driver
3740  *  @dev : pointer to the device structure.
3741  *  Description:
3742  *  This function is the open entry point of the driver. It mainly calls a
3743  *  function to allocate Rx buffers and inserts them into the buffer
3744  *  descriptors and then enables the Rx part of the NIC.
3745  *  Return value:
3746  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3747  *   file on failure.
3748  */
3749
3750 static int s2io_open(struct net_device *dev)
3751 {
3752         nic_t *sp = dev->priv;
3753         int err = 0;
3754
3755         /*
3756          * Make sure you have link off by default every time
3757          * Nic is initialized
3758          */
3759         netif_carrier_off(dev);
3760         sp->last_link_state = 0;
3761
3762         /* Initialize H/W and enable interrupts */
3763         err = s2io_card_up(sp);
3764         if (err) {
3765                 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
3766                           dev->name);
3767                 goto hw_init_failed;
3768         }
3769
3770         if (s2io_set_mac_addr(dev, dev->dev_addr) == FAILURE) {
3771                 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
3772                 s2io_card_down(sp);
3773                 err = -ENODEV;
3774                 goto hw_init_failed;
3775         }
3776
3777         netif_start_queue(dev);
3778         return 0;
3779
3780 hw_init_failed:
3781         if (sp->intr_type == MSI_X) {
3782                 if (sp->entries)
3783                         kfree(sp->entries);
3784                 if (sp->s2io_entries)
3785                         kfree(sp->s2io_entries);
3786         }
3787         return err;
3788 }
3789
3790 /**
3791  *  s2io_close -close entry point of the driver
3792  *  @dev : device pointer.
3793  *  Description:
3794  *  This is the stop entry point of the driver. It needs to undo exactly
3795  *  whatever was done by the open entry point,thus it's usually referred to
3796  *  as the close function.Among other things this function mainly stops the
3797  *  Rx side of the NIC and frees all the Rx buffers in the Rx rings.
3798  *  Return value:
3799  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3800  *  file on failure.
3801  */
3802
3803 static int s2io_close(struct net_device *dev)
3804 {
3805         nic_t *sp = dev->priv;
3806
3807         flush_scheduled_work();
3808         netif_stop_queue(dev);
3809         /* Reset card, kill tasklet and free Tx and Rx buffers. */
3810         s2io_card_down(sp);
3811
3812         sp->device_close_flag = TRUE;   /* Device is shut down. */
3813         return 0;
3814 }
3815
3816 /**
3817  *  s2io_xmit - Tx entry point of te driver
3818  *  @skb : the socket buffer containing the Tx data.
3819  *  @dev : device pointer.
3820  *  Description :
3821  *  This function is the Tx entry point of the driver. S2IO NIC supports
3822  *  certain protocol assist features on Tx side, namely  CSO, S/G, LSO.
3823  *  NOTE: when device cant queue the pkt,just the trans_start variable will
3824  *  not be upadted.
3825  *  Return value:
3826  *  0 on success & 1 on failure.
3827  */
3828
3829 static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
3830 {
3831         nic_t *sp = dev->priv;
3832         u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
3833         register u64 val64;
3834         TxD_t *txdp;
3835         TxFIFO_element_t __iomem *tx_fifo;
3836         unsigned long flags;
3837         u16 vlan_tag = 0;
3838         int vlan_priority = 0;
3839         mac_info_t *mac_control;
3840         struct config_param *config;
3841         int offload_type;
3842
3843         mac_control = &sp->mac_control;
3844         config = &sp->config;
3845
3846         DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
3847         spin_lock_irqsave(&sp->tx_lock, flags);
3848         if (atomic_read(&sp->card_state) == CARD_DOWN) {
3849                 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
3850                           dev->name);
3851                 spin_unlock_irqrestore(&sp->tx_lock, flags);
3852                 dev_kfree_skb(skb);
3853                 return 0;
3854         }
3855
3856         queue = 0;
3857
3858         /* Get Fifo number to Transmit based on vlan priority */
3859         if (sp->vlgrp && vlan_tx_tag_present(skb)) {
3860                 vlan_tag = vlan_tx_tag_get(skb);
3861                 vlan_priority = vlan_tag >> 13;
3862                 queue = config->fifo_mapping[vlan_priority];
3863         }
3864
3865         put_off = (u16) mac_control->fifos[queue].tx_curr_put_info.offset;
3866         get_off = (u16) mac_control->fifos[queue].tx_curr_get_info.offset;
3867         txdp = (TxD_t *) mac_control->fifos[queue].list_info[put_off].
3868                 list_virt_addr;
3869
3870         queue_len = mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1;
3871         /* Avoid "put" pointer going beyond "get" pointer */
3872         if (txdp->Host_Control ||
3873                    ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
3874                 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
3875                 netif_stop_queue(dev);
3876                 dev_kfree_skb(skb);
3877                 spin_unlock_irqrestore(&sp->tx_lock, flags);
3878                 return 0;
3879         }
3880
3881         /* A buffer with no data will be dropped */
3882         if (!skb->len) {
3883                 DBG_PRINT(TX_DBG, "%s:Buffer has no data..\n", dev->name);
3884                 dev_kfree_skb(skb);
3885                 spin_unlock_irqrestore(&sp->tx_lock, flags);
3886                 return 0;
3887         }
3888
3889         offload_type = s2io_offload_type(skb);
3890 #ifdef NETIF_F_TSO
3891         if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
3892                 txdp->Control_1 |= TXD_TCP_LSO_EN;
3893                 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
3894         }
3895 #endif
3896         if (skb->ip_summed == CHECKSUM_HW) {
3897                 txdp->Control_2 |=
3898                     (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN |
3899                      TXD_TX_CKO_UDP_EN);
3900         }
3901         txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
3902         txdp->Control_1 |= TXD_LIST_OWN_XENA;
3903         txdp->Control_2 |= config->tx_intr_type;
3904
3905         if (sp->vlgrp && vlan_tx_tag_present(skb)) {
3906                 txdp->Control_2 |= TXD_VLAN_ENABLE;
3907                 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
3908         }
3909
3910         frg_len = skb->len - skb->data_len;
3911         if (offload_type == SKB_GSO_UDP) {
3912                 int ufo_size;
3913
3914                 ufo_size = s2io_udp_mss(skb);
3915                 ufo_size &= ~7;
3916                 txdp->Control_1 |= TXD_UFO_EN;
3917                 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
3918                 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
3919 #ifdef __BIG_ENDIAN
3920                 sp->ufo_in_band_v[put_off] =
3921                                 (u64)skb_shinfo(skb)->ip6_frag_id;
3922 #else
3923                 sp->ufo_in_band_v[put_off] =
3924                                 (u64)skb_shinfo(skb)->ip6_frag_id << 32;
3925 #endif
3926                 txdp->Host_Control = (unsigned long)sp->ufo_in_band_v;
3927                 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
3928                                         sp->ufo_in_band_v,
3929                                         sizeof(u64), PCI_DMA_TODEVICE);
3930                 txdp++;
3931         }
3932
3933         txdp->Buffer_Pointer = pci_map_single
3934             (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE);
3935         txdp->Host_Control = (unsigned long) skb;
3936         txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
3937         if (offload_type == SKB_GSO_UDP)
3938                 txdp->Control_1 |= TXD_UFO_EN;
3939
3940         frg_cnt = skb_shinfo(skb)->nr_frags;
3941         /* For fragmented SKB. */
3942         for (i = 0; i < frg_cnt; i++) {
3943                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3944                 /* A '0' length fragment will be ignored */
3945                 if (!frag->size)
3946                         continue;
3947                 txdp++;
3948                 txdp->Buffer_Pointer = (u64) pci_map_page
3949                     (sp->pdev, frag->page, frag->page_offset,
3950                      frag->size, PCI_DMA_TODEVICE);
3951                 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
3952                 if (offload_type == SKB_GSO_UDP)
3953                         txdp->Control_1 |= TXD_UFO_EN;
3954         }
3955         txdp->Control_1 |= TXD_GATHER_CODE_LAST;
3956
3957         if (offload_type == SKB_GSO_UDP)
3958                 frg_cnt++; /* as Txd0 was used for inband header */
3959
3960         tx_fifo = mac_control->tx_FIFO_start[queue];
3961         val64 = mac_control->fifos[queue].list_info[put_off].list_phy_addr;
3962         writeq(val64, &tx_fifo->TxDL_Pointer);
3963
3964         val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
3965                  TX_FIFO_LAST_LIST);
3966         if (offload_type)
3967                 val64 |= TX_FIFO_SPECIAL_FUNC;
3968
3969         writeq(val64, &tx_fifo->List_Control);
3970
3971         mmiowb();
3972
3973         put_off++;
3974         if (put_off == mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1)
3975                 put_off = 0;
3976         mac_control->fifos[queue].tx_curr_put_info.offset = put_off;
3977
3978         /* Avoid "put" pointer going beyond "get" pointer */
3979         if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
3980                 sp->mac_control.stats_info->sw_stat.fifo_full_cnt++;
3981                 DBG_PRINT(TX_DBG,
3982                           "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
3983                           put_off, get_off);
3984                 netif_stop_queue(dev);
3985         }
3986
3987         dev->trans_start = jiffies;
3988         spin_unlock_irqrestore(&sp->tx_lock, flags);
3989
3990         return 0;
3991 }
3992
3993 static void
3994 s2io_alarm_handle(unsigned long data)
3995 {
3996         nic_t *sp = (nic_t *)data;
3997
3998         alarm_intr_handler(sp);
3999         mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4000 }
4001
4002 static int s2io_chk_rx_buffers(nic_t *sp, int rng_n)
4003 {
4004         int rxb_size, level;
4005
4006         if (!sp->lro) {
4007                 rxb_size = atomic_read(&sp->rx_bufs_left[rng_n]);
4008                 level = rx_buffer_level(sp, rxb_size, rng_n);
4009
4010                 if ((level == PANIC) && (!TASKLET_IN_USE)) {
4011                         int ret;
4012                         DBG_PRINT(INTR_DBG, "%s: Rx BD hit ", __FUNCTION__);
4013                         DBG_PRINT(INTR_DBG, "PANIC levels\n");
4014                         if ((ret = fill_rx_buffers(sp, rng_n)) == -ENOMEM) {
4015                                 DBG_PRINT(ERR_DBG, "Out of memory in %s",
4016                                           __FUNCTION__);
4017                                 clear_bit(0, (&sp->tasklet_status));
4018                                 return -1;
4019                         }
4020                         clear_bit(0, (&sp->tasklet_status));
4021                 } else if (level == LOW)
4022                         tasklet_schedule(&sp->task);
4023
4024         } else if (fill_rx_buffers(sp, rng_n) == -ENOMEM) {
4025                         DBG_PRINT(ERR_DBG, "%s:Out of memory", sp->dev->name);
4026                         DBG_PRINT(ERR_DBG, " in Rx Intr!!\n");
4027         }
4028         return 0;
4029 }
4030
4031 static irqreturn_t
4032 s2io_msi_handle(int irq, void *dev_id, struct pt_regs *regs)
4033 {
4034         struct net_device *dev = (struct net_device *) dev_id;
4035         nic_t *sp = dev->priv;
4036         int i;
4037         mac_info_t *mac_control;
4038         struct config_param *config;
4039
4040         atomic_inc(&sp->isr_cnt);
4041         mac_control = &sp->mac_control;
4042         config = &sp->config;
4043         DBG_PRINT(INTR_DBG, "%s: MSI handler\n", __FUNCTION__);
4044
4045         /* If Intr is because of Rx Traffic */
4046         for (i = 0; i < config->rx_ring_num; i++)
4047                 rx_intr_handler(&mac_control->rings[i]);
4048
4049         /* If Intr is because of Tx Traffic */
4050         for (i = 0; i < config->tx_fifo_num; i++)
4051                 tx_intr_handler(&mac_control->fifos[i]);
4052
4053         /*
4054          * If the Rx buffer count is below the panic threshold then
4055          * reallocate the buffers from the interrupt handler itself,
4056          * else schedule a tasklet to reallocate the buffers.
4057          */
4058         for (i = 0; i < config->rx_ring_num; i++)
4059                 s2io_chk_rx_buffers(sp, i);
4060
4061         atomic_dec(&sp->isr_cnt);
4062         return IRQ_HANDLED;
4063 }
4064
4065 static irqreturn_t
4066 s2io_msix_ring_handle(int irq, void *dev_id, struct pt_regs *regs)
4067 {
4068         ring_info_t *ring = (ring_info_t *)dev_id;
4069         nic_t *sp = ring->nic;
4070
4071         atomic_inc(&sp->isr_cnt);
4072
4073         rx_intr_handler(ring);
4074         s2io_chk_rx_buffers(sp, ring->ring_no);
4075
4076         atomic_dec(&sp->isr_cnt);
4077         return IRQ_HANDLED;
4078 }
4079
4080 static irqreturn_t
4081 s2io_msix_fifo_handle(int irq, void *dev_id, struct pt_regs *regs)
4082 {
4083         fifo_info_t *fifo = (fifo_info_t *)dev_id;
4084         nic_t *sp = fifo->nic;
4085
4086         atomic_inc(&sp->isr_cnt);
4087         tx_intr_handler(fifo);
4088         atomic_dec(&sp->isr_cnt);
4089         return IRQ_HANDLED;
4090 }
4091 static void s2io_txpic_intr_handle(nic_t *sp)
4092 {
4093         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4094         u64 val64;
4095
4096         val64 = readq(&bar0->pic_int_status);
4097         if (val64 & PIC_INT_GPIO) {
4098                 val64 = readq(&bar0->gpio_int_reg);
4099                 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4100                     (val64 & GPIO_INT_REG_LINK_UP)) {
4101                         /*
4102                          * This is unstable state so clear both up/down
4103                          * interrupt and adapter to re-evaluate the link state.
4104                          */
4105                         val64 |=  GPIO_INT_REG_LINK_DOWN;
4106                         val64 |= GPIO_INT_REG_LINK_UP;
4107                         writeq(val64, &bar0->gpio_int_reg);
4108                         val64 = readq(&bar0->gpio_int_mask);
4109                         val64 &= ~(GPIO_INT_MASK_LINK_UP |
4110                                    GPIO_INT_MASK_LINK_DOWN);
4111                         writeq(val64, &bar0->gpio_int_mask);
4112                 }
4113                 else if (val64 & GPIO_INT_REG_LINK_UP) {
4114                         val64 = readq(&bar0->adapter_status);
4115                         if (verify_xena_quiescence(sp, val64,
4116                                                    sp->device_enabled_once)) {
4117                                 /* Enable Adapter */
4118                                 val64 = readq(&bar0->adapter_control);
4119                                 val64 |= ADAPTER_CNTL_EN;
4120                                 writeq(val64, &bar0->adapter_control);
4121                                 val64 |= ADAPTER_LED_ON;
4122                                 writeq(val64, &bar0->adapter_control);
4123                                 if (!sp->device_enabled_once)
4124                                         sp->device_enabled_once = 1;
4125
4126                                 s2io_link(sp, LINK_UP);
4127                                 /*
4128                                  * unmask link down interrupt and mask link-up
4129                                  * intr
4130                                  */
4131                                 val64 = readq(&bar0->gpio_int_mask);
4132                                 val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4133                                 val64 |= GPIO_INT_MASK_LINK_UP;
4134                                 writeq(val64, &bar0->gpio_int_mask);
4135
4136                         }
4137                 }else if (val64 & GPIO_INT_REG_LINK_DOWN) {
4138                         val64 = readq(&bar0->adapter_status);
4139                         if (verify_xena_quiescence(sp, val64,
4140                                                    sp->device_enabled_once)) {
4141                                 s2io_link(sp, LINK_DOWN);
4142                                 /* Link is down so unmaks link up interrupt */
4143                                 val64 = readq(&bar0->gpio_int_mask);
4144                                 val64 &= ~GPIO_INT_MASK_LINK_UP;
4145                                 val64 |= GPIO_INT_MASK_LINK_DOWN;
4146                                 writeq(val64, &bar0->gpio_int_mask);
4147                         }
4148                 }
4149         }
4150         val64 = readq(&bar0->gpio_int_mask);
4151 }
4152
4153 /**
4154  *  s2io_isr - ISR handler of the device .
4155  *  @irq: the irq of the device.
4156  *  @dev_id: a void pointer to the dev structure of the NIC.
4157  *  @pt_regs: pointer to the registers pushed on the stack.
4158  *  Description:  This function is the ISR handler of the device. It
4159  *  identifies the reason for the interrupt and calls the relevant
4160  *  service routines. As a contongency measure, this ISR allocates the
4161  *  recv buffers, if their numbers are below the panic value which is
4162  *  presently set to 25% of the original number of rcv buffers allocated.
4163  *  Return value:
4164  *   IRQ_HANDLED: will be returned if IRQ was handled by this routine
4165  *   IRQ_NONE: will be returned if interrupt is not from our device
4166  */
4167 static irqreturn_t s2io_isr(int irq, void *dev_id, struct pt_regs *regs)
4168 {
4169         struct net_device *dev = (struct net_device *) dev_id;
4170         nic_t *sp = dev->priv;
4171         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4172         int i;
4173         u64 reason = 0, val64, org_mask;
4174         mac_info_t *mac_control;
4175         struct config_param *config;
4176
4177         atomic_inc(&sp->isr_cnt);
4178         mac_control = &sp->mac_control;
4179         config = &sp->config;
4180
4181         /*
4182          * Identify the cause for interrupt and call the appropriate
4183          * interrupt handler. Causes for the interrupt could be;
4184          * 1. Rx of packet.
4185          * 2. Tx complete.
4186          * 3. Link down.
4187          * 4. Error in any functional blocks of the NIC.
4188          */
4189         reason = readq(&bar0->general_int_status);
4190
4191         if (!reason) {
4192                 /* The interrupt was not raised by Xena. */
4193                 atomic_dec(&sp->isr_cnt);
4194                 return IRQ_NONE;
4195         }
4196
4197         val64 = 0xFFFFFFFFFFFFFFFFULL;
4198         /* Store current mask before masking all interrupts */
4199         org_mask = readq(&bar0->general_int_mask);
4200         writeq(val64, &bar0->general_int_mask);
4201
4202 #ifdef CONFIG_S2IO_NAPI
4203         if (reason & GEN_INTR_RXTRAFFIC) {
4204                 if (netif_rx_schedule_prep(dev)) {
4205                         writeq(val64, &bar0->rx_traffic_mask);
4206                         __netif_rx_schedule(dev);
4207                 }
4208         }
4209 #else
4210         /*
4211          * Rx handler is called by default, without checking for the
4212          * cause of interrupt.
4213          * rx_traffic_int reg is an R1 register, writing all 1's
4214          * will ensure that the actual interrupt causing bit get's
4215          * cleared and hence a read can be avoided.
4216          */
4217         writeq(val64, &bar0->rx_traffic_int);
4218         for (i = 0; i < config->rx_ring_num; i++) {
4219                 rx_intr_handler(&mac_control->rings[i]);
4220         }
4221 #endif
4222
4223         /*
4224          * tx_traffic_int reg is an R1 register, writing all 1's
4225          * will ensure that the actual interrupt causing bit get's
4226          * cleared and hence a read can be avoided.
4227          */
4228         writeq(val64, &bar0->tx_traffic_int);
4229
4230         for (i = 0; i < config->tx_fifo_num; i++)
4231                 tx_intr_handler(&mac_control->fifos[i]);
4232
4233         if (reason & GEN_INTR_TXPIC)
4234                 s2io_txpic_intr_handle(sp);
4235         /*
4236          * If the Rx buffer count is below the panic threshold then
4237          * reallocate the buffers from the interrupt handler itself,
4238          * else schedule a tasklet to reallocate the buffers.
4239          */
4240 #ifndef CONFIG_S2IO_NAPI
4241         for (i = 0; i < config->rx_ring_num; i++)
4242                 s2io_chk_rx_buffers(sp, i);
4243 #endif
4244         writeq(org_mask, &bar0->general_int_mask);
4245         atomic_dec(&sp->isr_cnt);
4246         return IRQ_HANDLED;
4247 }
4248
4249 /**
4250  * s2io_updt_stats -
4251  */
4252 static void s2io_updt_stats(nic_t *sp)
4253 {
4254         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4255         u64 val64;
4256         int cnt = 0;
4257
4258         if (atomic_read(&sp->card_state) == CARD_UP) {
4259                 /* Apprx 30us on a 133 MHz bus */
4260                 val64 = SET_UPDT_CLICKS(10) |
4261                         STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4262                 writeq(val64, &bar0->stat_cfg);
4263                 do {
4264                         udelay(100);
4265                         val64 = readq(&bar0->stat_cfg);
4266                         if (!(val64 & BIT(0)))
4267                                 break;
4268                         cnt++;
4269                         if (cnt == 5)
4270                                 break; /* Updt failed */
4271                 } while(1);
4272         } else {
4273                 memset(sp->mac_control.stats_info, 0, sizeof(StatInfo_t));
4274         }
4275 }
4276
4277 /**
4278  *  s2io_get_stats - Updates the device statistics structure.
4279  *  @dev : pointer to the device structure.
4280  *  Description:
4281  *  This function updates the device statistics structure in the s2io_nic
4282  *  structure and returns a pointer to the same.
4283  *  Return value:
4284  *  pointer to the updated net_device_stats structure.
4285  */
4286
4287 static struct net_device_stats *s2io_get_stats(struct net_device *dev)
4288 {
4289         nic_t *sp = dev->priv;
4290         mac_info_t *mac_control;
4291         struct config_param *config;
4292
4293
4294         mac_control = &sp->mac_control;
4295         config = &sp->config;
4296
4297         /* Configure Stats for immediate updt */
4298         s2io_updt_stats(sp);
4299
4300         sp->stats.tx_packets =
4301                 le32_to_cpu(mac_control->stats_info->tmac_frms);
4302         sp->stats.tx_errors =
4303                 le32_to_cpu(mac_control->stats_info->tmac_any_err_frms);
4304         sp->stats.rx_errors =
4305                 le32_to_cpu(mac_control->stats_info->rmac_drop_frms);
4306         sp->stats.multicast =
4307                 le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms);
4308         sp->stats.rx_length_errors =
4309                 le32_to_cpu(mac_control->stats_info->rmac_long_frms);
4310
4311         return (&sp->stats);
4312 }
4313
4314 /**
4315  *  s2io_set_multicast - entry point for multicast address enable/disable.
4316  *  @dev : pointer to the device structure
4317  *  Description:
4318  *  This function is a driver entry point which gets called by the kernel
4319  *  whenever multicast addresses must be enabled/disabled. This also gets
4320  *  called to set/reset promiscuous mode. Depending on the deivce flag, we
4321  *  determine, if multicast address must be enabled or if promiscuous mode
4322  *  is to be disabled etc.
4323  *  Return value:
4324  *  void.
4325  */
4326
4327 static void s2io_set_multicast(struct net_device *dev)
4328 {
4329         int i, j, prev_cnt;
4330         struct dev_mc_list *mclist;
4331         nic_t *sp = dev->priv;
4332         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4333         u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
4334             0xfeffffffffffULL;
4335         u64 dis_addr = 0xffffffffffffULL, mac_addr = 0;
4336         void __iomem *add;
4337
4338         if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
4339                 /*  Enable all Multicast addresses */
4340                 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
4341                        &bar0->rmac_addr_data0_mem);
4342                 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
4343                        &bar0->rmac_addr_data1_mem);
4344                 val64 = RMAC_ADDR_CMD_MEM_WE |
4345                     RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4346                     RMAC_ADDR_CMD_MEM_OFFSET(MAC_MC_ALL_MC_ADDR_OFFSET);
4347                 writeq(val64, &bar0->rmac_addr_cmd_mem);
4348                 /* Wait till command completes */
4349                 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4350                                       RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING);
4351
4352                 sp->m_cast_flg = 1;
4353                 sp->all_multi_pos = MAC_MC_ALL_MC_ADDR_OFFSET;
4354         } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
4355                 /*  Disable all Multicast addresses */
4356                 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4357                        &bar0->rmac_addr_data0_mem);
4358                 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4359                        &bar0->rmac_addr_data1_mem);
4360                 val64 = RMAC_ADDR_CMD_MEM_WE |
4361                     RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4362                     RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
4363                 writeq(val64, &bar0->rmac_addr_cmd_mem);
4364                 /* Wait till command completes */
4365                 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4366                                       RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING);
4367
4368                 sp->m_cast_flg = 0;
4369                 sp->all_multi_pos = 0;
4370         }
4371
4372         if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
4373                 /*  Put the NIC into promiscuous mode */
4374                 add = &bar0->mac_cfg;
4375                 val64 = readq(&bar0->mac_cfg);
4376                 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
4377
4378                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4379                 writel((u32) val64, add);
4380                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4381                 writel((u32) (val64 >> 32), (add + 4));
4382
4383                 val64 = readq(&bar0->mac_cfg);
4384                 sp->promisc_flg = 1;
4385                 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
4386                           dev->name);
4387         } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
4388                 /*  Remove the NIC from promiscuous mode */
4389                 add = &bar0->mac_cfg;
4390                 val64 = readq(&bar0->mac_cfg);
4391                 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
4392
4393                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4394                 writel((u32) val64, add);
4395                 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4396                 writel((u32) (val64 >> 32), (add + 4));
4397
4398                 val64 = readq(&bar0->mac_cfg);
4399                 sp->promisc_flg = 0;
4400                 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n",
4401                           dev->name);
4402         }
4403
4404         /*  Update individual M_CAST address list */
4405         if ((!sp->m_cast_flg) && dev->mc_count) {
4406                 if (dev->mc_count >
4407                     (MAX_ADDRS_SUPPORTED - MAC_MC_ADDR_START_OFFSET - 1)) {
4408                         DBG_PRINT(ERR_DBG, "%s: No more Rx filters ",
4409                                   dev->name);
4410                         DBG_PRINT(ERR_DBG, "can be added, please enable ");
4411                         DBG_PRINT(ERR_DBG, "ALL_MULTI instead\n");
4412                         return;
4413                 }
4414
4415                 prev_cnt = sp->mc_addr_count;
4416                 sp->mc_addr_count = dev->mc_count;
4417
4418                 /* Clear out the previous list of Mc in the H/W. */
4419                 for (i = 0; i < prev_cnt; i++) {
4420                         writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4421                                &bar0->rmac_addr_data0_mem);
4422                         writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
4423                                 &bar0->rmac_addr_data1_mem);
4424                         val64 = RMAC_ADDR_CMD_MEM_WE |
4425                             RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4426                             RMAC_ADDR_CMD_MEM_OFFSET
4427                             (MAC_MC_ADDR_START_OFFSET + i);
4428                         writeq(val64, &bar0->rmac_addr_cmd_mem);
4429
4430                         /* Wait for command completes */
4431                         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4432                                       RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING)) {
4433                                 DBG_PRINT(ERR_DBG, "%s: Adding ",
4434                                           dev->name);
4435                                 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
4436                                 return;
4437                         }
4438                 }
4439
4440                 /* Create the new Rx filter list and update the same in H/W. */
4441                 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
4442                      i++, mclist = mclist->next) {
4443                         memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr,
4444                                ETH_ALEN);
4445                         mac_addr = 0;
4446                         for (j = 0; j < ETH_ALEN; j++) {
4447                                 mac_addr |= mclist->dmi_addr[j];
4448                                 mac_addr <<= 8;
4449                         }
4450                         mac_addr >>= 8;
4451                         writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
4452                                &bar0->rmac_addr_data0_mem);
4453                         writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
4454                                 &bar0->rmac_addr_data1_mem);
4455                         val64 = RMAC_ADDR_CMD_MEM_WE |
4456                             RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4457                             RMAC_ADDR_CMD_MEM_OFFSET
4458                             (i + MAC_MC_ADDR_START_OFFSET);
4459                         writeq(val64, &bar0->rmac_addr_cmd_mem);
4460
4461                         /* Wait for command completes */
4462                         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4463                                       RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING)) {
4464                                 DBG_PRINT(ERR_DBG, "%s: Adding ",
4465                                           dev->name);
4466                                 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
4467                                 return;
4468                         }
4469                 }
4470         }
4471 }
4472
4473 /**
4474  *  s2io_set_mac_addr - Programs the Xframe mac address
4475  *  @dev : pointer to the device structure.
4476  *  @addr: a uchar pointer to the new mac address which is to be set.
4477  *  Description : This procedure will program the Xframe to receive
4478  *  frames with new Mac Address
4479  *  Return value: SUCCESS on success and an appropriate (-)ve integer
4480  *  as defined in errno.h file on failure.
4481  */
4482
4483 static int s2io_set_mac_addr(struct net_device *dev, u8 * addr)
4484 {
4485         nic_t *sp = dev->priv;
4486         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4487         register u64 val64, mac_addr = 0;
4488         int i;
4489
4490         /*
4491          * Set the new MAC address as the new unicast filter and reflect this
4492          * change on the device address registered with the OS. It will be
4493          * at offset 0.
4494          */
4495         for (i = 0; i < ETH_ALEN; i++) {
4496                 mac_addr <<= 8;
4497                 mac_addr |= addr[i];
4498         }
4499
4500         writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
4501                &bar0->rmac_addr_data0_mem);
4502
4503         val64 =
4504             RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4505             RMAC_ADDR_CMD_MEM_OFFSET(0);
4506         writeq(val64, &bar0->rmac_addr_cmd_mem);
4507         /* Wait till command completes */
4508         if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4509                       RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING)) {
4510                 DBG_PRINT(ERR_DBG, "%s: set_mac_addr failed\n", dev->name);
4511                 return FAILURE;
4512         }
4513
4514         return SUCCESS;
4515 }
4516
4517 /**
4518  * s2io_ethtool_sset - Sets different link parameters.
4519  * @sp : private member of the device structure, which is a pointer to the  * s2io_nic structure.
4520  * @info: pointer to the structure with parameters given by ethtool to set
4521  * link information.
4522  * Description:
4523  * The function sets different link parameters provided by the user onto
4524  * the NIC.
4525  * Return value:
4526  * 0 on success.
4527 */
4528
4529 static int s2io_ethtool_sset(struct net_device *dev,
4530                              struct ethtool_cmd *info)
4531 {
4532         nic_t *sp = dev->priv;
4533         if ((info->autoneg == AUTONEG_ENABLE) ||
4534             (info->speed != SPEED_10000) || (info->duplex != DUPLEX_FULL))
4535                 return -EINVAL;
4536         else {
4537                 s2io_close(sp->dev);
4538                 s2io_open(sp->dev);
4539         }
4540
4541         return 0;
4542 }
4543
4544 /**
4545  * s2io_ethtol_gset - Return link specific information.
4546  * @sp : private member of the device structure, pointer to the
4547  *      s2io_nic structure.
4548  * @info : pointer to the structure with parameters given by ethtool
4549  * to return link information.
4550  * Description:
4551  * Returns link specific information like speed, duplex etc.. to ethtool.
4552  * Return value :
4553  * return 0 on success.
4554  */
4555
4556 static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
4557 {
4558         nic_t *sp = dev->priv;
4559         info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
4560         info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
4561         info->port = PORT_FIBRE;
4562         /* info->transceiver?? TODO */
4563
4564         if (netif_carrier_ok(sp->dev)) {
4565                 info->speed = 10000;
4566                 info->duplex = DUPLEX_FULL;
4567         } else {
4568                 info->speed = -1;
4569                 info->duplex = -1;
4570         }
4571
4572         info->autoneg = AUTONEG_DISABLE;
4573         return 0;
4574 }
4575
4576 /**
4577  * s2io_ethtool_gdrvinfo - Returns driver specific information.
4578  * @sp : private member of the device structure, which is a pointer to the
4579  * s2io_nic structure.
4580  * @info : pointer to the structure with parameters given by ethtool to
4581  * return driver information.
4582  * Description:
4583  * Returns driver specefic information like name, version etc.. to ethtool.
4584  * Return value:
4585  *  void
4586  */
4587
4588 static void s2io_ethtool_gdrvinfo(struct net_device *dev,
4589                                   struct ethtool_drvinfo *info)
4590 {
4591         nic_t *sp = dev->priv;
4592
4593         strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
4594         strncpy(info->version, s2io_driver_version, sizeof(info->version));
4595         strncpy(info->fw_version, "", sizeof(info->fw_version));
4596         strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
4597         info->regdump_len = XENA_REG_SPACE;
4598         info->eedump_len = XENA_EEPROM_SPACE;
4599         info->testinfo_len = S2IO_TEST_LEN;
4600         info->n_stats = S2IO_STAT_LEN;
4601 }
4602
4603 /**
4604  *  s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
4605  *  @sp: private member of the device structure, which is a pointer to the
4606  *  s2io_nic structure.
4607  *  @regs : pointer to the structure with parameters given by ethtool for
4608  *  dumping the registers.
4609  *  @reg_space: The input argumnet into which all the registers are dumped.
4610  *  Description:
4611  *  Dumps the entire register space of xFrame NIC into the user given
4612  *  buffer area.
4613  * Return value :
4614  * void .
4615 */
4616
4617 static void s2io_ethtool_gregs(struct net_device *dev,
4618                                struct ethtool_regs *regs, void *space)
4619 {
4620         int i;
4621         u64 reg;
4622         u8 *reg_space = (u8 *) space;
4623         nic_t *sp = dev->priv;
4624
4625         regs->len = XENA_REG_SPACE;
4626         regs->version = sp->pdev->subsystem_device;
4627
4628         for (i = 0; i < regs->len; i += 8) {
4629                 reg = readq(sp->bar0 + i);
4630                 memcpy((reg_space + i), &reg, 8);
4631         }
4632 }
4633
4634 /**
4635  *  s2io_phy_id  - timer function that alternates adapter LED.
4636  *  @data : address of the private member of the device structure, which
4637  *  is a pointer to the s2io_nic structure, provided as an u32.
4638  * Description: This is actually the timer function that alternates the
4639  * adapter LED bit of the adapter control bit to set/reset every time on
4640  * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
4641  *  once every second.
4642 */
4643 static void s2io_phy_id(unsigned long data)
4644 {
4645         nic_t *sp = (nic_t *) data;
4646         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4647         u64 val64 = 0;
4648         u16 subid;
4649
4650         subid = sp->pdev->subsystem_device;
4651         if ((sp->device_type == XFRAME_II_DEVICE) ||
4652                    ((subid & 0xFF) >= 0x07)) {
4653                 val64 = readq(&bar0->gpio_control);
4654                 val64 ^= GPIO_CTRL_GPIO_0;
4655                 writeq(val64, &bar0->gpio_control);
4656         } else {
4657                 val64 = readq(&bar0->adapter_control);
4658                 val64 ^= ADAPTER_LED_ON;
4659                 writeq(val64, &bar0->adapter_control);
4660         }
4661
4662         mod_timer(&sp->id_timer, jiffies + HZ / 2);
4663 }
4664
4665 /**
4666  * s2io_ethtool_idnic - To physically identify the nic on the system.
4667  * @sp : private member of the device structure, which is a pointer to the
4668  * s2io_nic structure.
4669  * @id : pointer to the structure with identification parameters given by
4670  * ethtool.
4671  * Description: Used to physically identify the NIC on the system.
4672  * The Link LED will blink for a time specified by the user for
4673  * identification.
4674  * NOTE: The Link has to be Up to be able to blink the LED. Hence
4675  * identification is possible only if it's link is up.
4676  * Return value:
4677  * int , returns 0 on success
4678  */
4679
4680 static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
4681 {
4682         u64 val64 = 0, last_gpio_ctrl_val;
4683         nic_t *sp = dev->priv;
4684         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4685         u16 subid;
4686
4687         subid = sp->pdev->subsystem_device;
4688         last_gpio_ctrl_val = readq(&bar0->gpio_control);
4689         if ((sp->device_type == XFRAME_I_DEVICE) &&
4690                 ((subid & 0xFF) < 0x07)) {
4691                 val64 = readq(&bar0->adapter_control);
4692                 if (!(val64 & ADAPTER_CNTL_EN)) {
4693                         printk(KERN_ERR
4694                                "Adapter Link down, cannot blink LED\n");
4695                         return -EFAULT;
4696                 }
4697         }
4698         if (sp->id_timer.function == NULL) {
4699                 init_timer(&sp->id_timer);
4700                 sp->id_timer.function = s2io_phy_id;
4701                 sp->id_timer.data = (unsigned long) sp;
4702         }
4703         mod_timer(&sp->id_timer, jiffies);
4704         if (data)
4705                 msleep_interruptible(data * HZ);
4706         else
4707                 msleep_interruptible(MAX_FLICKER_TIME);
4708         del_timer_sync(&sp->id_timer);
4709
4710         if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
4711                 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
4712                 last_gpio_ctrl_val = readq(&bar0->gpio_control);
4713         }
4714
4715         return 0;
4716 }
4717
4718 /**
4719  * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
4720  * @sp : private member of the device structure, which is a pointer to the
4721  *      s2io_nic structure.
4722  * @ep : pointer to the structure with pause parameters given by ethtool.
4723  * Description:
4724  * Returns the Pause frame generation and reception capability of the NIC.
4725  * Return value:
4726  *  void
4727  */
4728 static void s2io_ethtool_getpause_data(struct net_device *dev,
4729                                        struct ethtool_pauseparam *ep)
4730 {
4731         u64 val64;
4732         nic_t *sp = dev->priv;
4733         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4734
4735         val64 = readq(&bar0->rmac_pause_cfg);
4736         if (val64 & RMAC_PAUSE_GEN_ENABLE)
4737                 ep->tx_pause = TRUE;
4738         if (val64 & RMAC_PAUSE_RX_ENABLE)
4739                 ep->rx_pause = TRUE;
4740         ep->autoneg = FALSE;
4741 }
4742
4743 /**
4744  * s2io_ethtool_setpause_data -  set/reset pause frame generation.
4745  * @sp : private member of the device structure, which is a pointer to the
4746  *      s2io_nic structure.
4747  * @ep : pointer to the structure with pause parameters given by ethtool.
4748  * Description:
4749  * It can be used to set or reset Pause frame generation or reception
4750  * support of the NIC.
4751  * Return value:
4752  * int, returns 0 on Success
4753  */
4754
4755 static int s2io_ethtool_setpause_data(struct net_device *dev,
4756                                struct ethtool_pauseparam *ep)
4757 {
4758         u64 val64;
4759         nic_t *sp = dev->priv;
4760         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4761
4762         val64 = readq(&bar0->rmac_pause_cfg);
4763         if (ep->tx_pause)
4764                 val64 |= RMAC_PAUSE_GEN_ENABLE;
4765         else
4766                 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
4767         if (ep->rx_pause)
4768                 val64 |= RMAC_PAUSE_RX_ENABLE;
4769         else
4770                 val64 &= ~RMAC_PAUSE_RX_ENABLE;
4771         writeq(val64, &bar0->rmac_pause_cfg);
4772         return 0;
4773 }
4774
4775 /**
4776  * read_eeprom - reads 4 bytes of data from user given offset.
4777  * @sp : private member of the device structure, which is a pointer to the
4778  *      s2io_nic structure.
4779  * @off : offset at which the data must be written
4780  * @data : Its an output parameter where the data read at the given
4781  *      offset is stored.
4782  * Description:
4783  * Will read 4 bytes of data from the user given offset and return the
4784  * read data.
4785  * NOTE: Will allow to read only part of the EEPROM visible through the
4786  *   I2C bus.
4787  * Return value:
4788  *  -1 on failure and 0 on success.
4789  */
4790
4791 #define S2IO_DEV_ID             5
4792 static int read_eeprom(nic_t * sp, int off, u64 * data)
4793 {
4794         int ret = -1;
4795         u32 exit_cnt = 0;
4796         u64 val64;
4797         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4798
4799         if (sp->device_type == XFRAME_I_DEVICE) {
4800                 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
4801                     I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ |
4802                     I2C_CONTROL_CNTL_START;
4803                 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
4804
4805                 while (exit_cnt < 5) {
4806                         val64 = readq(&bar0->i2c_control);
4807                         if (I2C_CONTROL_CNTL_END(val64)) {
4808                                 *data = I2C_CONTROL_GET_DATA(val64);
4809                                 ret = 0;
4810                                 break;
4811                         }
4812                         msleep(50);
4813                         exit_cnt++;
4814                 }
4815         }
4816
4817         if (sp->device_type == XFRAME_II_DEVICE) {
4818                 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
4819                         SPI_CONTROL_BYTECNT(0x3) |
4820                         SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
4821                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4822                 val64 |= SPI_CONTROL_REQ;
4823                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4824                 while (exit_cnt < 5) {
4825                         val64 = readq(&bar0->spi_control);
4826                         if (val64 & SPI_CONTROL_NACK) {
4827                                 ret = 1;
4828                                 break;
4829                         } else if (val64 & SPI_CONTROL_DONE) {
4830                                 *data = readq(&bar0->spi_data);
4831                                 *data &= 0xffffff;
4832                                 ret = 0;
4833                                 break;
4834                         }
4835                         msleep(50);
4836                         exit_cnt++;
4837                 }
4838         }
4839         return ret;
4840 }
4841
4842 /**
4843  *  write_eeprom - actually writes the relevant part of the data value.
4844  *  @sp : private member of the device structure, which is a pointer to the
4845  *       s2io_nic structure.
4846  *  @off : offset at which the data must be written
4847  *  @data : The data that is to be written
4848  *  @cnt : Number of bytes of the data that are actually to be written into
4849  *  the Eeprom. (max of 3)
4850  * Description:
4851  *  Actually writes the relevant part of the data value into the Eeprom
4852  *  through the I2C bus.
4853  * Return value:
4854  *  0 on success, -1 on failure.
4855  */
4856
4857 static int write_eeprom(nic_t * sp, int off, u64 data, int cnt)
4858 {
4859         int exit_cnt = 0, ret = -1;
4860         u64 val64;
4861         XENA_dev_config_t __iomem *bar0 = sp->bar0;
4862
4863         if (sp->device_type == XFRAME_I_DEVICE) {
4864                 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
4865                     I2C_CONTROL_BYTE_CNT(cnt) | I2C_CONTROL_SET_DATA((u32)data) |
4866                     I2C_CONTROL_CNTL_START;
4867                 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
4868
4869                 while (exit_cnt < 5) {
4870                         val64 = readq(&bar0->i2c_control);
4871                         if (I2C_CONTROL_CNTL_END(val64)) {
4872                                 if (!(val64 & I2C_CONTROL_NACK))
4873                                         ret = 0;
4874                                 break;
4875                         }
4876                         msleep(50);
4877                         exit_cnt++;
4878                 }
4879         }
4880
4881         if (sp->device_type == XFRAME_II_DEVICE) {
4882                 int write_cnt = (cnt == 8) ? 0 : cnt;
4883                 writeq(SPI_DATA_WRITE(data,(cnt<<3)), &bar0->spi_data);
4884
4885                 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
4886                         SPI_CONTROL_BYTECNT(write_cnt) |
4887                         SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
4888                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4889                 val64 |= SPI_CONTROL_REQ;
4890                 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4891                 while (exit_cnt < 5) {
4892                         val64 = readq(&bar0->spi_control);
4893                         if (val64 & SPI_CONTROL_NACK) {
4894                                 ret = 1;
4895                                 break;
4896                         } else if (val64 & SPI_CONTROL_DONE) {
4897                                 ret = 0;
4898                                 break;
4899                         }
4900                         msleep(50);
4901                         exit_cnt++;
4902                 }
4903         }
4904         return ret;
4905 }
4906 static void s2io_vpd_read(nic_t *nic)
4907 {
4908         u8 *vpd_data;
4909         u8 data;
4910         int i=0, cnt, fail = 0;
4911         int vpd_addr = 0x80;
4912
4913         if (nic->device_type == XFRAME_II_DEVICE) {
4914                 strcpy(nic->product_name, "Xframe II 10GbE network adapter");
4915                 vpd_addr = 0x80;
4916         }
4917         else {
4918                 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
4919                 vpd_addr = 0x50;
4920         }
4921
4922         vpd_data = kmalloc(256, GFP_KERNEL);
4923         if (!vpd_data)
4924                 return;
4925
4926         for (i = 0; i < 256; i +=4 ) {
4927                 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
4928                 pci_read_config_byte(nic->pdev,  (vpd_addr + 2), &data);
4929                 pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
4930                 for (cnt = 0; cnt <5; cnt++) {
4931                         msleep(2);
4932                         pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
4933                         if (data == 0x80)
4934                                 break;
4935                 }
4936                 if (cnt >= 5) {
4937                         DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
4938                         fail = 1;
4939                         break;
4940                 }
4941                 pci_read_config_dword(nic->pdev,  (vpd_addr + 4),
4942                                       (u32 *)&vpd_data[i]);
4943         }
4944         if ((!fail) && (vpd_data[1] < VPD_PRODUCT_NAME_LEN)) {
4945                 memset(nic->product_name, 0, vpd_data[1]);
4946                 memcpy(nic->product_name, &vpd_data[3], vpd_data[1]);
4947         }
4948         kfree(vpd_data);
4949 }
4950
4951 /**
4952  *  s2io_ethtool_geeprom  - reads the value stored in the Eeprom.
4953  *  @sp : private member of the device structure, which is a pointer to the *       s2io_nic structure.
4954  *  @eeprom : pointer to the user level structure provided by ethtool,
4955  *  containing all relevant information.
4956  *  @data_buf : user defined value to be written into Eeprom.
4957  *  Description: Reads the values stored in the Eeprom at given offset
4958  *  for a given length. Stores these values int the input argument data
4959  *  buffer 'data_buf' and returns these to the caller (ethtool.)
4960  *  Return value:
4961  *  int  0 on success
4962  */
4963
4964 static int s2io_ethtool_geeprom(struct net_device *dev,
4965                          struct ethtool_eeprom *eeprom, u8 * data_buf)
4966 {
4967         u32 i, valid;
4968         u64 data;
4969         nic_t *sp = dev->priv;
4970
4971         eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
4972
4973         if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
4974                 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
4975
4976         for (i = 0; i < eeprom->len; i += 4) {
4977                 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
4978                         DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
4979                         return -EFAULT;
4980                 }
4981                 valid = INV(data);
4982                 memcpy((data_buf + i), &valid, 4);
4983         }
4984         return 0;
4985 }
4986
4987 /**
4988  *  s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
4989  *  @sp : private member of the device structure, which is a pointer to the
4990  *  s2io_nic structure.
4991  *  @eeprom : pointer to the user level structure provided by ethtool,
4992  *  containing all relevant information.
4993  *  @data_buf ; user defined value to be written into Eeprom.
4994  *  Description:
4995  *  Tries to write the user provided value in the Eeprom, at the offset
4996  *  given by the user.
4997  *  Return value:
4998  *  0 on success, -EFAULT on failure.
4999  */
5000
5001 static int s2io_ethtool_seeprom(struct net_device *dev,
5002                                 struct ethtool_eeprom *eeprom,
5003                                 u8 * data_buf)
5004 {
5005         int len = eeprom->len, cnt = 0;
5006         u64 valid = 0, data;
5007         nic_t *sp = dev->priv;
5008
5009         if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5010                 DBG_PRINT(ERR_DBG,
5011                           "ETHTOOL_WRITE_EEPROM Err: Magic value ");
5012                 DBG_PRINT(ERR_DBG, "is wrong, Its not 0x%x\n",
5013                           eeprom->magic);
5014                 return -EFAULT;
5015         }
5016
5017         while (len) {
5018                 data = (u32) data_buf[cnt] & 0x000000FF;
5019                 if (data) {
5020                         valid = (u32) (data << 24);
5021                 } else
5022                         valid = data;
5023
5024                 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
5025                         DBG_PRINT(ERR_DBG,
5026                                   "ETHTOOL_WRITE_EEPROM Err: Cannot ");
5027                         DBG_PRINT(ERR_DBG,
5028                                   "write into the specified offset\n");
5029                         return -EFAULT;
5030                 }
5031                 cnt++;
5032                 len--;
5033         }
5034
5035         return 0;
5036 }
5037
5038 /**
5039  * s2io_register_test - reads and writes into all clock domains.
5040  * @sp : private member of the device structure, which is a pointer to the
5041  * s2io_nic structure.
5042  * @data : variable that returns the result of each of the test conducted b
5043  * by the driver.
5044  * Description:
5045  * Read and write into all clock domains. The NIC has 3 clock domains,
5046  * see that registers in all the three regions are accessible.
5047  * Return value:
5048  * 0 on success.
5049  */
5050
5051 static int s2io_register_test(nic_t * sp, uint64_t * data)
5052 {
5053         XENA_dev_config_t __iomem *bar0 = sp->bar0;
5054         u64 val64 = 0, exp_val;
5055         int fail = 0;
5056
5057         val64 = readq(&bar0->pif_rd_swapper_fb);
5058         if (val64 != 0x123456789abcdefULL) {
5059                 fail = 1;
5060                 DBG_PRINT(INFO_DBG, "Read Test level 1 fails\n");
5061         }
5062
5063         val64 = readq(&bar0->rmac_pause_cfg);
5064         if (val64 != 0xc000ffff00000000ULL) {
5065                 fail = 1;
5066                 DBG_PRINT(INFO_DBG, "Read Test level 2 fails\n");
5067         }
5068
5069         val64 = readq(&bar0->rx_queue_cfg);
5070         if (sp->device_type == XFRAME_II_DEVICE)
5071                 exp_val = 0x0404040404040404ULL;
5072         else
5073                 exp_val = 0x0808080808080808ULL;
5074         if (val64 != exp_val) {
5075                 fail = 1;
5076                 DBG_PRINT(INFO_DBG, "Read Test level 3 fails\n");
5077         }
5078
5079         val64 = readq(&bar0->xgxs_efifo_cfg);
5080         if (val64 != 0x000000001923141EULL) {
5081                 fail = 1;
5082                 DBG_PRINT(INFO_DBG, "Read Test level 4 fails\n");
5083         }
5084
5085         val64 = 0x5A5A5A5A5A5A5A5AULL;
5086         writeq(val64, &bar0->xmsi_data);
5087         val64 = readq(&bar0->xmsi_data);
5088         if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
5089                 fail = 1;
5090                 DBG_PRINT(ERR_DBG, "Write Test level 1 fails\n");
5091         }
5092
5093         val64 = 0xA5A5A5A5A5A5A5A5ULL;
5094         writeq(val64, &bar0->xmsi_data);
5095         val64 = readq(&bar0->xmsi_data);
5096         if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
5097                 fail = 1;
5098                 DBG_PRINT(ERR_DBG, "Write Test level 2 fails\n");
5099         }
5100
5101         *data = fail;
5102         return fail;
5103 }
5104
5105 /**
5106  * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
5107  * @sp : private member of the device structure, which is a pointer to the
5108  * s2io_nic structure.
5109  * @data:variable that returns the result of each of the test conducted by
5110  * the driver.
5111  * Description:
5112  * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
5113  * register.
5114  * Return value:
5115  * 0 on success.
5116  */
5117
5118 static int s2io_eeprom_test(nic_t * sp, uint64_t * data)
5119 {
5120         int fail = 0;
5121         u64 ret_data, org_4F0, org_7F0;
5122         u8 saved_4F0 = 0, saved_7F0 = 0;
5123         struct net_device *dev = sp->dev;
5124
5125         /* Test Write Error at offset 0 */
5126         /* Note that SPI interface allows write access to all areas
5127          * of EEPROM. Hence doing all negative testing only for Xframe I.
5128          */
5129         if (sp->device_type == XFRAME_I_DEVICE)
5130                 if (!write_eeprom(sp, 0, 0, 3))
5131                         fail = 1;
5132
5133         /* Save current values at offsets 0x4F0 and 0x7F0 */
5134         if (!read_eeprom(sp, 0x4F0, &org_4F0))
5135                 saved_4F0 = 1;
5136         if (!read_eeprom(sp, 0x7F0, &org_7F0))
5137                 saved_7F0 = 1;
5138
5139         /* Test Write at offset 4f0 */
5140         if (write_eeprom(sp, 0x4F0, 0x012345, 3))
5141                 fail = 1;
5142         if (read_eeprom(sp, 0x4F0, &ret_data))
5143                 fail = 1;
5144
5145         if (ret_data != 0x012345) {
5146                 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
5147                         "Data written %llx Data read %llx\n",
5148                         dev->name, (unsigned long long)0x12345,
5149                         (unsigned long long)ret_data);
5150                 fail = 1;
5151         }
5152
5153         /* Reset the EEPROM data go FFFF */
5154         write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
5155
5156         /* Test Write Request Error at offset 0x7c */
5157         if (sp->device_type == XFRAME_I_DEVICE)
5158                 if (!write_eeprom(sp, 0x07C, 0, 3))
5159                         fail = 1;
5160
5161         /* Test Write Request at offset 0x7f0 */
5162         if (write_eeprom(sp, 0x7F0, 0x012345, 3))
5163                 fail = 1;
5164         if (read_eeprom(sp, 0x7F0, &ret_data))
5165                 fail = 1;
5166
5167         if (ret_data != 0x012345) {
5168                 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
5169                         "Data written %llx Data read %llx\n",
5170                         dev->name, (unsigned long long)0x12345,
5171                         (unsigned long long)ret_data);
5172                 fail = 1;
5173         }
5174
5175         /* Reset the EEPROM data go FFFF */
5176         write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
5177
5178         if (sp->device_type == XFRAME_I_DEVICE) {
5179                 /* Test Write Error at offset 0x80 */
5180                 if (!write_eeprom(sp, 0x080, 0, 3))
5181                         fail = 1;
5182
5183                 /* Test Write Error at offset 0xfc */
5184                 if (!write_eeprom(sp, 0x0FC, 0, 3))
5185                         fail = 1;
5186
5187                 /* Test Write Error at offset 0x100 */
5188                 if (!write_eeprom(sp, 0x100, 0, 3))
5189                         fail = 1;
5190
5191                 /* Test Write Error at offset 4ec */
5192                 if (!write_eeprom(sp, 0x4EC, 0, 3))
5193                         fail = 1;
5194         }
5195
5196         /* Restore values at offsets 0x4F0 and 0x7F0 */
5197         if (saved_4F0)
5198                 write_eeprom(sp, 0x4F0, org_4F0, 3);
5199         if (saved_7F0)
5200                 write_eeprom(sp, 0x7F0, org_7F0, 3);
5201
5202         *data = fail;
5203         return fail;
5204 }
5205
5206 /**
5207  * s2io_bist_test - invokes the MemBist test of the card .
5208  * @sp : private member of the device structure, which is a pointer to the
5209  * s2io_nic structure.
5210  * @data:variable that returns the result of each of the test conducted by
5211  * the driver.
5212  * Description:
5213  * This invokes the MemBist test of the card. We give around
5214  * 2 secs time for the Test to complete. If it's still not complete
5215  * within this peiod, we consider that the test failed.
5216  * Return value:
5217  * 0 on success and -1 on failure.
5218  */
5219
5220 static int s2io_bist_test(nic_t * sp, uint64_t * data)
5221 {
5222         u8 bist = 0;
5223         int cnt = 0, ret = -1;
5224
5225         pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
5226         bist |= PCI_BIST_START;
5227         pci_write_config_word(sp->pdev, PCI_BIST, bist);
5228
5229         while (cnt < 20) {
5230                 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
5231                 if (!(bist & PCI_BIST_START)) {
5232                         *data = (bist & PCI_BIST_CODE_MASK);
5233                         ret = 0;
5234                         break;
5235                 }
5236                 msleep(100);
5237                 cnt++;
5238         }
5239
5240         return ret;
5241 }
5242
5243 /**
5244  * s2io-link_test - verifies the link state of the nic
5245  * @sp ; private member of the device structure, which is a pointer to the
5246  * s2io_nic structure.
5247  * @data: variable that returns the result of each of the test conducted by
5248  * the driver.
5249  * Description:
5250  * The function verifies the link state of the NIC and updates the input
5251  * argument 'data' appropriately.
5252  * Return value:
5253  * 0 on success.
5254  */
5255
5256 static int s2io_link_test(nic_t * sp, uint64_t * data)
5257 {
5258         XENA_dev_config_t __iomem *bar0 = sp->bar0;
5259         u64 val64;
5260
5261         val64 = readq(&bar0->adapter_status);
5262         if(!(LINK_IS_UP(val64)))
5263                 *data = 1;
5264         else
5265                 *data = 0;
5266
5267         return *data;
5268 }
5269
5270 /**
5271  * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
5272  * @sp - private member of the device structure, which is a pointer to the
5273  * s2io_nic structure.
5274  * @data - variable that returns the result of each of the test
5275  * conducted by the driver.
5276  * Description:
5277  *  This is one of the offline test that tests the read and write
5278  *  access to the RldRam chip on the NIC.
5279  * Return value:
5280  *  0 on success.
5281  */
5282
5283 static int s2io_rldram_test(nic_t * sp, uint64_t * data)
5284 {
5285         XENA_dev_config_t __iomem *bar0 = sp->bar0;
5286         u64 val64;
5287         int cnt, iteration = 0, test_fail = 0;
5288
5289         val64 = readq(&bar0->adapter_control);
5290         val64 &= ~ADAPTER_ECC_EN;
5291         writeq(val64, &bar0->adapter_control);
5292
5293         val64 = readq(&bar0->mc_rldram_test_ctrl);
5294         val64 |= MC_RLDRAM_TEST_MODE;
5295         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
5296
5297         val64 = readq(&bar0->mc_rldram_mrs);
5298         val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
5299         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
5300
5301         val64 |= MC_RLDRAM_MRS_ENABLE;
5302         SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
5303
5304         while (iteration < 2) {
5305                 val64 = 0x55555555aaaa0000ULL;
5306                 if (iteration == 1) {
5307                         val64 ^= 0xFFFFFFFFFFFF0000ULL;
5308                 }
5309                 writeq(val64, &bar0->mc_rldram_test_d0);
5310
5311                 val64 = 0xaaaa5a5555550000ULL;
5312                 if (iteration == 1) {
5313                         val64 ^= 0xFFFFFFFFFFFF0000ULL;
5314                 }
5315                 writeq(val64, &bar0->mc_rldram_test_d1);
5316
5317                 val64 = 0x55aaaaaaaa5a0000ULL;
5318                 if (iteration == 1) {
5319                         val64 ^= 0xFFFFFFFFFFFF0000ULL;
5320                 }
5321                 writeq(val64, &bar0->mc_rldram_test_d2);
5322
5323                 val64 = (u64) (0x0000003ffffe0100ULL);
5324                 writeq(val64, &bar0->mc_rldram_test_add);
5325
5326                 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_WRITE |
5327                         MC_RLDRAM_TEST_GO;
5328                 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
5329
5330                 for (cnt = 0; cnt < 5; cnt++) {
5331                         val64 = readq(&bar0->mc_rldram_test_ctrl);
5332                         if (val64 & MC_RLDRAM_TEST_DONE)
5333                                 break;
5334                         msleep(200);
5335                 }
5336
5337                 if (cnt == 5)
5338                         break;
5339
5340                 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
5341                 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
5342
5343                 for (cnt = 0; cnt < 5; cnt++) {
5344                         val64 = readq(&bar0->mc_rldram_test_ctrl);
5345                         if (val64 & MC_RLDRAM_TEST_DONE)
5346                                 break;
5347                         msleep(500);
5348                 }
5349
5350                 if (cnt == 5)
5351                         break;
5352
5353                 val64 = readq(&bar0->mc_rldram_test_ctrl);
5354                 if (!(val64 & MC_RLDRAM_TEST_PASS))
5355                         test_fail = 1;
5356
5357                 iteration++;
5358         }
5359
5360         *data = test_fail;
5361
5362         /* Bring the adapter out of test mode */
5363         SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
5364
5365         return test_fail;
5366 }
5367
5368 /**
5369  *  s2io_ethtool_test - conducts 6 tsets to determine the health of card.
5370  *  @sp : private member of the device structure, which is a pointer to the
5371  *  s2io_nic structure.
5372  *  @ethtest : pointer to a ethtool command specific structure that will be
5373  *  returned to the user.
5374  *  @data : variable that returns the result of each of the test
5375  * conducted by the driver.
5376  * Description:
5377  *  This function conducts 6 tests ( 4 offline and 2 online) to determine
5378  *  the health of the card.
5379  * Return value:
5380  *  void
5381  */
5382
5383 static void s2io_ethtool_test(struct net_device *dev,
5384                               struct ethtool_test *ethtest,
5385                               uint64_t * data)
5386 {
5387         nic_t *sp = dev->priv;
5388         int orig_state = netif_running(sp->dev);
5389
5390         if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
5391                 /* Offline Tests. */
5392                 if (orig_state)
5393                         s2io_close(sp->dev);
5394
5395                 if (s2io_register_test(sp, &data[0]))
5396                         ethtest->flags |= ETH_TEST_FL_FAILED;
5397
5398                 s2io_reset(sp);
5399
5400                 if (s2io_rldram_test(sp, &data[3]))
5401                         ethtest->flags |= ETH_TEST_FL_FAILED;
5402
5403                 s2io_reset(sp);
5404
5405                 if (s2io_eeprom_test(sp, &data[1]))
5406                         ethtest->flags |= ETH_TEST_FL_FAILED;
5407
5408                 if (s2io_bist_test(sp, &data[4]))
5409                         ethtest->flags |= ETH_TEST_FL_FAILED;
5410
5411                 if (orig_state)
5412                         s2io_open(sp->dev);
5413
5414                 data[2] = 0;
5415         } else {
5416                 /* Online Tests. */
5417                 if (!orig_state) {
5418                         DBG_PRINT(ERR_DBG,
5419                                   "%s: is not up, cannot run test\n",
5420                                   dev->name);
5421                         data[0] = -1;
5422                         data[1] = -1;
5423                         data[2] = -1;
5424                         data[3] = -1;
5425                         data[4] = -1;
5426                 }
5427
5428                 if (s2io_link_test(sp, &data[2]))
5429                         ethtest->flags |= ETH_TEST_FL_FAILED;
5430
5431                 data[0] = 0;
5432                 data[1] = 0;
5433                 data[3] = 0;
5434                 data[4] = 0;
5435         }
5436 }
5437
5438 static void s2io_get_ethtool_stats(struct net_device *dev,
5439                                    struct ethtool_stats *estats,
5440                                    u64 * tmp_stats)
5441 {
5442         int i = 0;
5443         nic_t *sp = dev->priv;
5444         StatInfo_t *stat_info = sp->mac_control.stats_info;
5445
5446         s2io_updt_stats(sp);
5447         tmp_stats[i++] =
5448                 (u64)le32_to_cpu(stat_info->tmac_frms_oflow) << 32  |
5449                 le32_to_cpu(stat_info->tmac_frms);
5450         tmp_stats[i++] =
5451                 (u64)le32_to_cpu(stat_info->tmac_data_octets_oflow) << 32 |
5452                 le32_to_cpu(stat_info->tmac_data_octets);
5453         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_drop_frms);
5454         tmp_stats[i++] =
5455                 (u64)le32_to_cpu(stat_info->tmac_mcst_frms_oflow) << 32 |
5456                 le32_to_cpu(stat_info->tmac_mcst_frms);
5457         tmp_stats[i++] =
5458                 (u64)le32_to_cpu(stat_info->tmac_bcst_frms_oflow) << 32 |
5459                 le32_to_cpu(stat_info->tmac_bcst_frms);
5460         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_pause_ctrl_frms);
5461         tmp_stats[i++] =
5462                 (u64)le32_to_cpu(stat_info->tmac_ttl_octets_oflow) << 32 |
5463                 le32_to_cpu(stat_info->tmac_ttl_octets);
5464         tmp_stats[i++] =
5465                 (u64)le32_to_cpu(stat_info->tmac_ucst_frms_oflow) << 32 |
5466                 le32_to_cpu(stat_info->tmac_ucst_frms);
5467         tmp_stats[i++] =
5468                 (u64)le32_to_cpu(stat_info->tmac_nucst_frms_oflow) << 32 |
5469                 le32_to_cpu(stat_info->tmac_nucst_frms);
5470         tmp_stats[i++] =
5471                 (u64)le32_to_cpu(stat_info->tmac_any_err_frms_oflow) << 32 |
5472                 le32_to_cpu(stat_info->tmac_any_err_frms);
5473         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_ttl_less_fb_octets);
5474         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_vld_ip_octets);
5475         tmp_stats[i++] =
5476                 (u64)le32_to_cpu(stat_info->tmac_vld_ip_oflow) << 32 |
5477                 le32_to_cpu(stat_info->tmac_vld_ip);
5478         tmp_stats[i++] =
5479                 (u64)le32_to_cpu(stat_info->tmac_drop_ip_oflow) << 32 |
5480                 le32_to_cpu(stat_info->tmac_drop_ip);
5481         tmp_stats[i++] =
5482                 (u64)le32_to_cpu(stat_info->tmac_icmp_oflow) << 32 |
5483                 le32_to_cpu(stat_info->tmac_icmp);
5484         tmp_stats[i++] =
5485                 (u64)le32_to_cpu(stat_info->tmac_rst_tcp_oflow) << 32 |
5486                 le32_to_cpu(stat_info->tmac_rst_tcp);
5487         tmp_stats[i++] = le64_to_cpu(stat_info->tmac_tcp);
5488         tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_udp_oflow) << 32 |
5489                 le32_to_cpu(stat_info->tmac_udp);
5490         tmp_stats[i++] =
5491                 (u64)le32_to_cpu(stat_info->rmac_vld_frms_oflow) << 32 |
5492                 le32_to_cpu(stat_info->rmac_vld_frms);
5493         tmp_stats[i++] =
5494                 (u64)le32_to_cpu(stat_info->rmac_data_octets_oflow) << 32 |
5495                 le32_to_cpu(stat_info->rmac_data_octets);
5496         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_fcs_err_frms);
5497         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_drop_frms);
5498         tmp_stats[i++] =
5499                 (u64)le32_to_cpu(stat_info->rmac_vld_mcst_frms_oflow) << 32 |
5500                 le32_to_cpu(stat_info->rmac_vld_mcst_frms);
5501         tmp_stats[i++] =
5502                 (u64)le32_to_cpu(stat_info->rmac_vld_bcst_frms_oflow) << 32 |
5503                 le32_to_cpu(stat_info->rmac_vld_bcst_frms);
5504         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_in_rng_len_err_frms);
5505         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_out_rng_len_err_frms);
5506         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_long_frms);
5507         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_pause_ctrl_frms);
5508         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_unsup_ctrl_frms);
5509         tmp_stats[i++] =
5510                 (u64)le32_to_cpu(stat_info->rmac_ttl_octets_oflow) << 32 |
5511                 le32_to_cpu(stat_info->rmac_ttl_octets);
5512         tmp_stats[i++] =
5513                 (u64)le32_to_cpu(stat_info->rmac_accepted_ucst_frms_oflow)
5514                 << 32 | le32_to_cpu(stat_info->rmac_accepted_ucst_frms);
5515         tmp_stats[i++] =
5516                 (u64)le32_to_cpu(stat_info->rmac_accepted_nucst_frms_oflow)
5517                  << 32 | le32_to_cpu(stat_info->rmac_accepted_nucst_frms);
5518         tmp_stats[i++] =
5519                 (u64)le32_to_cpu(stat_info->rmac_discarded_frms_oflow) << 32 |
5520                 le32_to_cpu(stat_info->rmac_discarded_frms);
5521         tmp_stats[i++] =
5522                 (u64)le32_to_cpu(stat_info->rmac_drop_events_oflow)
5523                  << 32 | le32_to_cpu(stat_info->rmac_drop_events);
5524         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_less_fb_octets);
5525         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_frms);
5526         tmp_stats[i++] =
5527                 (u64)le32_to_cpu(stat_info->rmac_usized_frms_oflow) << 32 |
5528                 le32_to_cpu(stat_info->rmac_usized_frms);
5529         tmp_stats[i++] =
5530                 (u64)le32_to_cpu(stat_info->rmac_osized_frms_oflow) << 32 |
5531                 le32_to_cpu(stat_info->rmac_osized_frms);
5532         tmp_stats[i++] =
5533                 (u64)le32_to_cpu(stat_info->rmac_frag_frms_oflow) << 32 |
5534                 le32_to_cpu(stat_info->rmac_frag_frms);
5535         tmp_stats[i++] =
5536                 (u64)le32_to_cpu(stat_info->rmac_jabber_frms_oflow) << 32 |
5537                 le32_to_cpu(stat_info->rmac_jabber_frms);
5538         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_64_frms);
5539         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_65_127_frms);
5540         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_128_255_frms);
5541         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_256_511_frms);
5542         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_512_1023_frms);
5543         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_1024_1518_frms);
5544         tmp_stats[i++] =
5545                 (u64)le32_to_cpu(stat_info->rmac_ip_oflow) << 32 |
5546                 le32_to_cpu(stat_info->rmac_ip);
5547         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ip_octets);
5548         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_hdr_err_ip);
5549         tmp_stats[i++] =
5550                 (u64)le32_to_cpu(stat_info->rmac_drop_ip_oflow) << 32 |
5551                 le32_to_cpu(stat_info->rmac_drop_ip);
5552         tmp_stats[i++] =
5553                 (u64)le32_to_cpu(stat_info->rmac_icmp_oflow) << 32 |
5554                 le32_to_cpu(stat_info->rmac_icmp);
5555         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_tcp);
5556         tmp_stats[i++] =
5557                 (u64)le32_to_cpu(stat_info->rmac_udp_oflow) << 32 |
5558                 le32_to_cpu(stat_info->rmac_udp);
5559         tmp_stats[i++] =
5560                 (u64)le32_to_cpu(stat_info->rmac_err_drp_udp_oflow) << 32 |
5561                 le32_to_cpu(stat_info->rmac_err_drp_udp);
5562         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_err_sym);
5563         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q0);
5564         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q1);
5565         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q2);
5566         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q3);
5567         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q4);
5568         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q5);
5569         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q6);
5570         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q7);
5571         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q0);
5572         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q1);
5573         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q2);
5574         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q3);
5575         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q4);
5576         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q5);
5577         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q6);
5578         tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q7);
5579         tmp_stats[i++] =
5580                 (u64)le32_to_cpu(stat_info->rmac_pause_cnt_oflow) << 32 |
5581                 le32_to_cpu(stat_info->rmac_pause_cnt);
5582         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_data_err_cnt);
5583         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_ctrl_err_cnt);
5584         tmp_stats[i++] =
5585                 (u64)le32_to_cpu(stat_info->rmac_accepted_ip_oflow) << 32 |
5586                 le32_to_cpu(stat_info->rmac_accepted_ip);
5587         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_err_tcp);
5588         tmp_stats[i++] = le32_to_cpu(stat_info->rd_req_cnt);
5589         tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_cnt);
5590         tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_rtry_cnt);
5591         tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_cnt);
5592         tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_rd_ack_cnt);
5593         tmp_stats[i++] = le32_to_cpu(stat_info->wr_req_cnt);
5594         tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_cnt);
5595         tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_rtry_cnt);
5596         tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_cnt);
5597         tmp_stats[i++] = le32_to_cpu(stat_info->wr_disc_cnt);
5598         tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_wr_ack_cnt);
5599         tmp_stats[i++] = le32_to_cpu(stat_info->txp_wr_cnt);
5600         tmp_stats[i++] = le32_to_cpu(stat_info->txd_rd_cnt);
5601         tmp_stats[i++] = le32_to_cpu(stat_info->txd_wr_cnt);
5602         tmp_stats[i++] = le32_to_cpu(stat_info->rxd_rd_cnt);
5603         tmp_stats[i++] = le32_to_cpu(stat_info->rxd_wr_cnt);
5604         tmp_stats[i++] = le32_to_cpu(stat_info->txf_rd_cnt);
5605         tmp_stats[i++] = le32_to_cpu(stat_info->rxf_wr_cnt);
5606         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_1519_4095_frms);
5607         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_4096_8191_frms);
5608         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_8192_max_frms);
5609         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_gt_max_frms);
5610         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_osized_alt_frms);
5611         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_jabber_alt_frms);
5612         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_gt_max_alt_frms);
5613         tmp_stats[i++] = le64_to_cpu(stat_info->rmac_vlan_frms);
5614         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_len_discard);
5615         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_fcs_discard);
5616         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_pf_discard);
5617         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_da_discard);
5618         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_red_discard);
5619         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_rts_discard);
5620         tmp_stats[i++] = le32_to_cpu(stat_info->rmac_ingm_full_discard);
5621         tmp_stats[i++] = le32_to_cpu(stat_info->link_fault_cnt);
5622         tmp_stats[i++] = 0;
5623         tmp_stats[i++] = stat_info->sw_stat.single_ecc_errs;
5624         tmp_stats[i++] = stat_info->sw_stat.double_ecc_errs;
5625         tmp_stats[i++] = stat_info->sw_stat.parity_err_cnt;
5626         tmp_stats[i++] = stat_info->sw_stat.serious_err_cnt;
5627         tmp_stats[i++] = stat_info->sw_stat.soft_reset_cnt;
5628         tmp_stats[i++] = stat_info->sw_stat.fifo_full_cnt;
5629         tmp_stats[i++] = stat_info->sw_stat.ring_full_cnt;
5630         tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_high;
5631         tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_low;
5632         tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_high;
5633         tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_low;
5634         tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_high;
5635         tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_low;
5636         tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_high;
5637         tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_low;
5638         tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_high;
5639         tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_low;
5640         tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_high;
5641         tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_low;
5642         tmp_stats[i++] = stat_info->sw_stat.clubbed_frms_cnt;
5643         tmp_stats[i++] = stat_info->sw_stat.sending_both;
5644         tmp_stats[i++] = stat_info->sw_stat.outof_sequence_pkts;
5645         tmp_stats[i++] = stat_info->sw_stat.flush_max_pkts;
5646         if (stat_info->sw_stat.num_aggregations) {
5647                 u64 tmp = stat_info->sw_stat.sum_avg_pkts_aggregated;
5648                 int count = 0;
5649                 /*
5650                  * Since 64-bit divide does not work on all platforms,
5651                  * do repeated subtraction.
5652                  */
5653                 while (tmp >= stat_info->sw_stat.num_aggregations) {
5654                         tmp -= stat_info->sw_stat.num_aggregations;
5655                         count++;
5656                 }
5657                 tmp_stats[i++] = count;
5658         }
5659         else
5660                 tmp_stats[i++] = 0;
5661 }
5662
5663 static int s2io_ethtool_get_regs_len(struct net_device *dev)
5664 {
5665         return (XENA_REG_SPACE);
5666 }
5667
5668
5669 static u32 s2io_ethtool_get_rx_csum(struct net_device * dev)
5670 {
5671         nic_t *sp = dev->priv;
5672
5673         return (sp->rx_csum);
5674 }
5675
5676 static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
5677 {
5678         nic_t *sp = dev->priv;
5679
5680         if (data)
5681                 sp->rx_csum = 1;
5682         else
5683                 sp->rx_csum = 0;
5684
5685         return 0;
5686 }
5687
5688 static int s2io_get_eeprom_len(struct net_device *dev)
5689 {
5690         return (XENA_EEPROM_SPACE);
5691 }
5692
5693 static int s2io_ethtool_self_test_count(struct net_device *dev)
5694 {
5695         return (S2IO_TEST_LEN);
5696 }
5697
5698 static void s2io_ethtool_get_strings(struct net_device *dev,
5699                                      u32 stringset, u8 * data)
5700 {
5701         switch (stringset) {
5702         case ETH_SS_TEST:
5703                 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
5704                 break;
5705         case ETH_SS_STATS:
5706                 memcpy(data, &ethtool_stats_keys,
5707                        sizeof(ethtool_stats_keys));
5708         }
5709 }
5710 static int s2io_ethtool_get_stats_count(struct net_device *dev)
5711 {
5712         return (S2IO_STAT_LEN);
5713 }
5714
5715 static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
5716 {
5717         if (data)
5718                 dev->features |= NETIF_F_IP_CSUM;
5719         else
5720                 dev->features &= ~NETIF_F_IP_CSUM;
5721
5722         return 0;
5723 }
5724
5725 static u32 s2io_ethtool_op_get_tso(struct net_device *dev)
5726 {
5727         return (dev->features & NETIF_F_TSO) != 0;
5728 }
5729 static int s2io_ethtool_op_set_tso(struct net_device *dev, u32 data)
5730 {
5731         if (data)
5732                 dev->features |= (NETIF_F_TSO | NETIF_F_TSO6);
5733         else
5734                 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
5735
5736         return 0;
5737 }
5738
5739 static struct ethtool_ops netdev_ethtool_ops = {
5740         .get_settings = s2io_ethtool_gset,
5741         .set_settings = s2io_ethtool_sset,
5742         .get_drvinfo = s2io_ethtool_gdrvinfo,
5743         .get_regs_len = s2io_ethtool_get_regs_len,
5744         .get_regs = s2io_ethtool_gregs,
5745         .get_link = ethtool_op_get_link,
5746         .get_eeprom_len = s2io_get_eeprom_len,
5747         .get_eeprom = s2io_ethtool_geeprom,
5748         .set_eeprom = s2io_ethtool_seeprom,
5749         .get_pauseparam = s2io_ethtool_getpause_data,
5750         .set_pauseparam = s2io_ethtool_setpause_data,
5751         .get_rx_csum = s2io_ethtool_get_rx_csum,
5752         .set_rx_csum = s2io_ethtool_set_rx_csum,
5753         .get_tx_csum = ethtool_op_get_tx_csum,
5754         .set_tx_csum = s2io_ethtool_op_set_tx_csum,
5755         .get_sg = ethtool_op_get_sg,
5756         .set_sg = ethtool_op_set_sg,
5757 #ifdef NETIF_F_TSO
5758         .get_tso = s2io_ethtool_op_get_tso,
5759         .set_tso = s2io_ethtool_op_set_tso,
5760 #endif
5761         .get_ufo = ethtool_op_get_ufo,
5762         .set_ufo = ethtool_op_set_ufo,
5763         .self_test_count = s2io_ethtool_self_test_count,
5764         .self_test = s2io_ethtool_test,
5765         .get_strings = s2io_ethtool_get_strings,
5766         .phys_id = s2io_ethtool_idnic,
5767         .get_stats_count = s2io_ethtool_get_stats_count,
5768         .get_ethtool_stats = s2io_get_ethtool_stats
5769 };
5770
5771 /**
5772  *  s2io_ioctl - Entry point for the Ioctl
5773  *  @dev :  Device pointer.
5774  *  @ifr :  An IOCTL specefic structure, that can contain a pointer to
5775  *  a proprietary structure used to pass information to the driver.
5776  *  @cmd :  This is used to distinguish between the different commands that
5777  *  can be passed to the IOCTL functions.
5778  *  Description:
5779  *  Currently there are no special functionality supported in IOCTL, hence
5780  *  function always return EOPNOTSUPPORTED
5781  */
5782
5783 static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
5784 {
5785         return -EOPNOTSUPP;
5786 }
5787
5788 /**
5789  *  s2io_change_mtu - entry point to change MTU size for the device.
5790  *   @dev : device pointer.
5791  *   @new_mtu : the new MTU size for the device.
5792  *   Description: A driver entry point to change MTU size for the device.
5793  *   Before changing the MTU the device must be stopped.
5794  *  Return value:
5795  *   0 on success and an appropriate (-)ve integer as defined in errno.h
5796  *   file on failure.
5797  */
5798
5799 static int s2io_change_mtu(struct net_device *dev, int new_mtu)
5800 {
5801         nic_t *sp = dev->priv;
5802
5803         if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
5804                 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n",
5805                           dev->name);
5806                 return -EPERM;
5807         }
5808
5809         dev->mtu = new_mtu;
5810         if (netif_running(dev)) {
5811                 s2io_card_down(sp);
5812                 netif_stop_queue(dev);
5813                 if (s2io_card_up(sp)) {
5814                         DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
5815                                   __FUNCTION__);
5816                 }
5817                 if (netif_queue_stopped(dev))
5818                         netif_wake_queue(dev);
5819         } else { /* Device is down */
5820                 XENA_dev_config_t __iomem *bar0 = sp->bar0;
5821                 u64 val64 = new_mtu;
5822
5823                 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
5824         }
5825
5826         return 0;
5827 }
5828
5829 /**
5830  *  s2io_tasklet - Bottom half of the ISR.
5831  *  @dev_adr : address of the device structure in dma_addr_t format.
5832  *  Description:
5833  *  This is the tasklet or the bottom half of the ISR. This is
5834  *  an extension of the ISR which is scheduled by the scheduler to be run
5835  *  when the load on the CPU is low. All low priority tasks of the ISR can
5836  *  be pushed into the tasklet. For now the tasklet is used only to
5837  *  replenish the Rx buffers in the Rx buffer descriptors.
5838  *  Return value:
5839  *  void.
5840  */
5841
5842 static void s2io_tasklet(unsigned long dev_addr)
5843 {
5844         struct net_device *dev = (struct net_device *) dev_addr;
5845         nic_t *sp = dev->priv;
5846         int i, ret;
5847         mac_info_t *mac_control;
5848         struct config_param *config;
5849
5850         mac_control = &sp->mac_control;
5851         config = &sp->config;
5852
5853         if (!TASKLET_IN_USE) {
5854                 for (i = 0; i < config->rx_ring_num; i++) {
5855                         ret = fill_rx_buffers(sp, i);
5856                         if (ret == -ENOMEM) {
5857                                 DBG_PRINT(ERR_DBG, "%s: Out of ",
5858                                           dev->name);
5859                                 DBG_PRINT(ERR_DBG, "memory in tasklet\n");
5860                                 break;
5861                         } else if (ret == -EFILL) {
5862                                 DBG_PRINT(ERR_DBG,
5863                                           "%s: Rx Ring %d is full\n",
5864                                           dev->name, i);
5865                                 break;
5866                         }
5867                 }
5868                 clear_bit(0, (&sp->tasklet_status));
5869         }
5870 }
5871
5872 /**
5873  * s2io_set_link - Set the LInk status
5874  * @data: long pointer to device private structue
5875  * Description: Sets the link status for the adapter
5876  */
5877
5878 static void s2io_set_link(unsigned long data)
5879 {
5880         nic_t *nic = (nic_t *) data;
5881         struct net_device *dev = nic->dev;
5882         XENA_dev_config_t __iomem *bar0 = nic->bar0;
5883         register u64 val64;
5884         u16 subid;
5885
5886         if (test_and_set_bit(0, &(nic->link_state))) {
5887                 /* The card is being reset, no point doing anything */
5888                 return;
5889         }
5890
5891         subid = nic->pdev->subsystem_device;
5892         if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
5893                 /*
5894                  * Allow a small delay for the NICs self initiated
5895                  * cleanup to complete.
5896                  */
5897                 msleep(100);
5898         }
5899
5900         val64 = readq(&bar0->adapter_status);
5901         if (verify_xena_quiescence(nic, val64, nic->device_enabled_once)) {
5902                 if (LINK_IS_UP(val64)) {
5903                         val64 = readq(&bar0->adapter_control);
5904                         val64 |= ADAPTER_CNTL_EN;
5905                         writeq(val64, &bar0->adapter_control);
5906                         if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
5907                                                              subid)) {
5908                                 val64 = readq(&bar0->gpio_control);
5909                                 val64 |= GPIO_CTRL_GPIO_0;
5910                                 writeq(val64, &bar0->gpio_control);
5911                                 val64 = readq(&bar0->gpio_control);
5912                         } else {
5913                                 val64 |= ADAPTER_LED_ON;
5914                                 writeq(val64, &bar0->adapter_control);
5915                         }
5916                         if (s2io_link_fault_indication(nic) ==
5917                                                 MAC_RMAC_ERR_TIMER) {
5918                                 val64 = readq(&bar0->adapter_status);
5919                                 if (!LINK_IS_UP(val64)) {
5920                                         DBG_PRINT(ERR_DBG, "%s:", dev->name);
5921                                         DBG_PRINT(ERR_DBG, " Link down");
5922                                         DBG_PRINT(ERR_DBG, "after ");
5923                                         DBG_PRINT(ERR_DBG, "enabling ");
5924                                         DBG_PRINT(ERR_DBG, "device \n");
5925                                 }
5926                         }
5927                         if (nic->device_enabled_once == FALSE) {
5928                                 nic->device_enabled_once = TRUE;
5929                         }
5930                         s2io_link(nic, LINK_UP);
5931                 } else {
5932                         if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
5933                                                               subid)) {
5934                                 val64 = readq(&bar0->gpio_control);
5935                                 val64 &= ~GPIO_CTRL_GPIO_0;
5936                                 writeq(val64, &bar0->gpio_control);
5937                                 val64 = readq(&bar0->gpio_control);
5938                         }
5939                         s2io_link(nic, LINK_DOWN);
5940                 }
5941         } else {                /* NIC is not Quiescent. */
5942                 DBG_PRINT(ERR_DBG, "%s: Error: ", dev->name);
5943                 DBG_PRINT(ERR_DBG, "device is not Quiescent\n");
5944                 netif_stop_queue(dev);
5945         }
5946         clear_bit(0, &(nic->link_state));
5947 }
5948
5949 static int set_rxd_buffer_pointer(nic_t *sp, RxD_t *rxdp, buffAdd_t *ba,
5950                            struct sk_buff **skb, u64 *temp0, u64 *temp1,
5951                            u64 *temp2, int size)
5952 {
5953         struct net_device *dev = sp->dev;
5954         struct sk_buff *frag_list;
5955
5956         if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
5957                 /* allocate skb */
5958                 if (*skb) {
5959                         DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
5960                         /*
5961                          * As Rx frame are not going to be processed,
5962                          * using same mapped address for the Rxd
5963                          * buffer pointer
5964                          */
5965                         ((RxD1_t*)rxdp)->Buffer0_ptr = *temp0;
5966                 } else {
5967                         *skb = dev_alloc_skb(size);
5968                         if (!(*skb)) {
5969                                 DBG_PRINT(ERR_DBG, "%s: Out of ", dev->name);
5970                                 DBG_PRINT(ERR_DBG, "memory to allocate SKBs\n");
5971                                 return -ENOMEM ;
5972                         }
5973                         /* storing the mapped addr in a temp variable
5974                          * such it will be used for next rxd whose
5975                          * Host Control is NULL
5976                          */
5977                         ((RxD1_t*)rxdp)->Buffer0_ptr = *temp0 =
5978                                 pci_map_single( sp->pdev, (*skb)->data,
5979                                         size - NET_IP_ALIGN,
5980                                         PCI_DMA_FROMDEVICE);
5981                         rxdp->Host_Control = (unsigned long) (*skb);
5982                 }
5983         } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
5984                 /* Two buffer Mode */
5985                 if (*skb) {
5986                         ((RxD3_t*)rxdp)->Buffer2_ptr = *temp2;
5987                         ((RxD3_t*)rxdp)->Buffer0_ptr = *temp0;
5988                         ((RxD3_t*)rxdp)->Buffer1_ptr = *temp1;
5989                 } else {
5990                         *skb = dev_alloc_skb(size);
5991                         ((RxD3_t*)rxdp)->Buffer2_ptr = *temp2 =
5992                                 pci_map_single(sp->pdev, (*skb)->data,
5993                                                dev->mtu + 4,
5994                                                PCI_DMA_FROMDEVICE);
5995                         ((RxD3_t*)rxdp)->Buffer0_ptr = *temp0 =
5996                                 pci_map_single( sp->pdev, ba->ba_0, BUF0_LEN,
5997                                                 PCI_DMA_FROMDEVICE);
5998                         rxdp->Host_Control = (unsigned long) (*skb);
5999
6000                         /* Buffer-1 will be dummy buffer not used */
6001                         ((RxD3_t*)rxdp)->Buffer1_ptr = *temp1 =
6002                                 pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
6003                                                PCI_DMA_FROMDEVICE);
6004                 }
6005         } else if ((rxdp->Host_Control == 0)) {
6006                 /* Three buffer mode */
6007                 if (*skb) {
6008                         ((RxD3_t*)rxdp)->Buffer0_ptr = *temp0;
6009                         ((RxD3_t*)rxdp)->Buffer1_ptr = *temp1;
6010                         ((RxD3_t*)rxdp)->Buffer2_ptr = *temp2;
6011                 } else {
6012                         *skb = dev_alloc_skb(size);
6013
6014                         ((RxD3_t*)rxdp)->Buffer0_ptr = *temp0 =
6015                                 pci_map_single(sp->pdev, ba->ba_0, BUF0_LEN,
6016                                                PCI_DMA_FROMDEVICE);
6017                         /* Buffer-1 receives L3/L4 headers */
6018                         ((RxD3_t*)rxdp)->Buffer1_ptr = *temp1 =
6019                                 pci_map_single( sp->pdev, (*skb)->data,
6020                                                 l3l4hdr_size + 4,
6021                                                 PCI_DMA_FROMDEVICE);
6022                         /*
6023                          * skb_shinfo(skb)->frag_list will have L4
6024                          * data payload
6025                          */
6026                         skb_shinfo(*skb)->frag_list = dev_alloc_skb(dev->mtu +
6027                                                                    ALIGN_SIZE);
6028                         if (skb_shinfo(*skb)->frag_list == NULL) {
6029                                 DBG_PRINT(ERR_DBG, "%s: dev_alloc_skb \
6030                                           failed\n ", dev->name);
6031                                 return -ENOMEM ;
6032                         }
6033                         frag_list = skb_shinfo(*skb)->frag_list;
6034                         frag_list->next = NULL;
6035                         /*
6036                          * Buffer-2 receives L4 data payload
6037                          */
6038                         ((RxD3_t*)rxdp)->Buffer2_ptr = *temp2 =
6039                                 pci_map_single( sp->pdev, frag_list->data,
6040                                                 dev->mtu, PCI_DMA_FROMDEVICE);
6041                 }
6042         }
6043         return 0;
6044 }
6045 static void set_rxd_buffer_size(nic_t *sp, RxD_t *rxdp, int size)
6046 {
6047         struct net_device *dev = sp->dev;
6048         if (sp->rxd_mode == RXD_MODE_1) {
6049                 rxdp->Control_2 = SET_BUFFER0_SIZE_1( size - NET_IP_ALIGN);
6050         } else if (sp->rxd_mode == RXD_MODE_3B) {
6051                 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6052                 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
6053                 rxdp->Control_2 |= SET_BUFFER2_SIZE_3( dev->mtu + 4);
6054         } else {
6055                 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6056                 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(l3l4hdr_size + 4);
6057                 rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu);
6058         }
6059 }
6060
6061 static  int rxd_owner_bit_reset(nic_t *sp)
6062 {
6063         int i, j, k, blk_cnt = 0, size;
6064         mac_info_t * mac_control = &sp->mac_control;
6065         struct config_param *config = &sp->config;
6066         struct net_device *dev = sp->dev;
6067         RxD_t *rxdp = NULL;
6068         struct sk_buff *skb = NULL;
6069         buffAdd_t *ba = NULL;
6070         u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
6071
6072         /* Calculate the size based on ring mode */
6073         size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
6074                 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
6075         if (sp->rxd_mode == RXD_MODE_1)
6076                 size += NET_IP_ALIGN;
6077         else if (sp->rxd_mode == RXD_MODE_3B)
6078                 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
6079         else
6080                 size = l3l4hdr_size + ALIGN_SIZE + BUF0_LEN + 4;
6081
6082         for (i = 0; i < config->rx_ring_num; i++) {
6083                 blk_cnt = config->rx_cfg[i].num_rxd /
6084                         (rxd_count[sp->rxd_mode] +1);
6085
6086                 for (j = 0; j < blk_cnt; j++) {
6087                         for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
6088                                 rxdp = mac_control->rings[i].
6089                                         rx_blocks[j].rxds[k].virt_addr;
6090                                 if(sp->rxd_mode >= RXD_MODE_3A)
6091                                         ba = &mac_control->rings[i].ba[j][k];
6092                                 set_rxd_buffer_pointer(sp, rxdp, ba,
6093                                                        &skb,(u64 *)&temp0_64,
6094                                                        (u64 *)&temp1_64,
6095                                                        (u64 *)&temp2_64, size);
6096
6097                                 set_rxd_buffer_size(sp, rxdp, size);
6098                                 wmb();
6099                                 /* flip the Ownership bit to Hardware */
6100                                 rxdp->Control_1 |= RXD_OWN_XENA;
6101                         }
6102                 }
6103         }
6104         return 0;
6105
6106 }
6107
6108 static int s2io_add_isr(nic_t * sp)
6109 {
6110         int ret = 0;
6111         struct net_device *dev = sp->dev;
6112         int err = 0;
6113
6114         if (sp->intr_type == MSI)
6115                 ret = s2io_enable_msi(sp);
6116         else if (sp->intr_type == MSI_X)
6117                 ret = s2io_enable_msi_x(sp);
6118         if (ret) {
6119                 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
6120                 sp->intr_type = INTA;
6121         }
6122
6123         /* Store the values of the MSIX table in the nic_t structure */
6124         store_xmsi_data(sp);
6125
6126         /* After proper initialization of H/W, register ISR */
6127         if (sp->intr_type == MSI) {
6128                 err = request_irq((int) sp->pdev->irq, s2io_msi_handle,
6129                         IRQF_SHARED, sp->name, dev);
6130                 if (err) {
6131                         pci_disable_msi(sp->pdev);
6132                         DBG_PRINT(ERR_DBG, "%s: MSI registration failed\n",
6133                                   dev->name);
6134                         return -1;
6135                 }
6136         }
6137         if (sp->intr_type == MSI_X) {
6138                 int i;
6139
6140                 for (i=1; (sp->s2io_entries[i].in_use == MSIX_FLG); i++) {
6141                         if (sp->s2io_entries[i].type == MSIX_FIFO_TYPE) {
6142                                 sprintf(sp->desc[i], "%s:MSI-X-%d-TX",
6143                                         dev->name, i);
6144                                 err = request_irq(sp->entries[i].vector,
6145                                           s2io_msix_fifo_handle, 0, sp->desc[i],
6146                                                   sp->s2io_entries[i].arg);
6147                                 DBG_PRINT(ERR_DBG, "%s @ 0x%llx\n", sp->desc[i],
6148                                 (unsigned long long)sp->msix_info[i].addr);
6149                         } else {
6150                                 sprintf(sp->desc[i], "%s:MSI-X-%d-RX",
6151                                         dev->name, i);
6152                                 err = request_irq(sp->entries[i].vector,
6153                                           s2io_msix_ring_handle, 0, sp->desc[i],
6154                                                   sp->s2io_entries[i].arg);
6155                                 DBG_PRINT(ERR_DBG, "%s @ 0x%llx\n", sp->desc[i],
6156                                 (unsigned long long)sp->msix_info[i].addr);
6157                         }
6158                         if (err) {
6159                                 DBG_PRINT(ERR_DBG,"%s:MSI-X-%d registration "
6160                                           "failed\n", dev->name, i);
6161                                 DBG_PRINT(ERR_DBG, "Returned: %d\n", err);
6162                                 return -1;
6163                         }
6164                         sp->s2io_entries[i].in_use = MSIX_REGISTERED_SUCCESS;
6165                 }
6166         }
6167         if (sp->intr_type == INTA) {
6168                 err = request_irq((int) sp->pdev->irq, s2io_isr, IRQF_SHARED,
6169                                 sp->name, dev);
6170                 if (err) {
6171                         DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
6172                                   dev->name);
6173                         return -1;
6174                 }
6175         }
6176         return 0;
6177 }
6178 static void s2io_rem_isr(nic_t * sp)
6179 {
6180         int cnt = 0;
6181         struct net_device *dev = sp->dev;
6182
6183         if (sp->intr_type == MSI_X) {
6184                 int i;
6185                 u16 msi_control;
6186
6187                 for (i=1; (sp->s2io_entries[i].in_use ==
6188                         MSIX_REGISTERED_SUCCESS); i++) {
6189                         int vector = sp->entries[i].vector;
6190                         void *arg = sp->s2io_entries[i].arg;
6191
6192                         free_irq(vector, arg);
6193                 }
6194                 pci_read_config_word(sp->pdev, 0x42, &msi_control);
6195                 msi_control &= 0xFFFE; /* Disable MSI */
6196                 pci_write_config_word(sp->pdev, 0x42, msi_control);
6197
6198                 pci_disable_msix(sp->pdev);
6199         } else {
6200                 free_irq(sp->pdev->irq, dev);
6201                 if (sp->intr_type == MSI) {
6202                         u16 val;
6203
6204                         pci_disable_msi(sp->pdev);
6205                         pci_read_config_word(sp->pdev, 0x4c, &val);
6206                         val ^= 0x1;
6207                         pci_write_config_word(sp->pdev, 0x4c, val);
6208                 }
6209         }
6210         /* Waiting till all Interrupt handlers are complete */
6211         cnt = 0;
6212         do {
6213                 msleep(10);
6214                 if (!atomic_read(&sp->isr_cnt))
6215                         break;
6216                 cnt++;
6217         } while(cnt < 5);
6218 }
6219
6220 static void s2io_card_down(nic_t * sp)
6221 {
6222         int cnt = 0;
6223         XENA_dev_config_t __iomem *bar0 = sp->bar0;
6224         unsigned long flags;
6225         register u64 val64 = 0;
6226
6227         del_timer_sync(&sp->alarm_timer);
6228         /* If s2io_set_link task is executing, wait till it completes. */
6229         while (test_and_set_bit(0, &(sp->link_state))) {
6230                 msleep(50);
6231         }
6232         atomic_set(&sp->card_state, CARD_DOWN);
6233
6234         /* disable Tx and Rx traffic on the NIC */
6235         stop_nic(sp);
6236
6237         s2io_rem_isr(sp);
6238
6239         /* Kill tasklet. */
6240         tasklet_kill(&sp->task);
6241
6242         /* Check if the device is Quiescent and then Reset the NIC */
6243         do {
6244                 /* As per the HW requirement we need to replenish the
6245                  * receive buffer to avoid the ring bump. Since there is
6246                  * no intention of processing the Rx frame at this pointwe are
6247                  * just settting the ownership bit of rxd in Each Rx
6248                  * ring to HW and set the appropriate buffer size
6249                  * based on the ring mode
6250                  */
6251                 rxd_owner_bit_reset(sp);
6252
6253                 val64 = readq(&bar0->adapter_status);
6254                 if (verify_xena_quiescence(sp, val64, sp->device_enabled_once)) {
6255                         break;
6256                 }
6257
6258                 msleep(50);
6259                 cnt++;
6260                 if (cnt == 10) {
6261                         DBG_PRINT(ERR_DBG,
6262                                   "s2io_close:Device not Quiescent ");
6263                         DBG_PRINT(ERR_DBG, "adaper status reads 0x%llx\n",
6264                                   (unsigned long long) val64);
6265                         break;
6266                 }
6267         } while (1);
6268         s2io_reset(sp);
6269
6270         spin_lock_irqsave(&sp->tx_lock, flags);
6271         /* Free all Tx buffers */
6272         free_tx_buffers(sp);
6273         spin_unlock_irqrestore(&sp->tx_lock, flags);
6274
6275         /* Free all Rx buffers */
6276         spin_lock_irqsave(&sp->rx_lock, flags);
6277         free_rx_buffers(sp);
6278         spin_unlock_irqrestore(&sp->rx_lock, flags);
6279
6280         clear_bit(0, &(sp->link_state));
6281 }
6282
6283 static int s2io_card_up(nic_t * sp)
6284 {
6285         int i, ret = 0;
6286         mac_info_t *mac_control;
6287         struct config_param *config;
6288         struct net_device *dev = (struct net_device *) sp->dev;
6289         u16 interruptible;
6290
6291         /* Initialize the H/W I/O registers */
6292         if (init_nic(sp) != 0) {
6293                 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
6294                           dev->name);
6295                 s2io_reset(sp);
6296                 return -ENODEV;
6297         }
6298
6299         /*
6300          * Initializing the Rx buffers. For now we are considering only 1
6301          * Rx ring and initializing buffers into 30 Rx blocks
6302          */
6303         mac_control = &sp->mac_control;
6304         config = &sp->config;
6305
6306         for (i = 0; i < config->rx_ring_num; i++) {
6307                 if ((ret = fill_rx_buffers(sp, i))) {
6308                         DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
6309                                   dev->name);
6310                         s2io_reset(sp);
6311                         free_rx_buffers(sp);
6312                         return -ENOMEM;
6313                 }
6314                 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
6315                           atomic_read(&sp->rx_bufs_left[i]));
6316         }
6317
6318         /* Setting its receive mode */
6319         s2io_set_multicast(dev);
6320
6321         if (sp->lro) {
6322                 /* Initialize max aggregatable pkts per session based on MTU */
6323                 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
6324                 /* Check if we can use(if specified) user provided value */
6325                 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
6326                         sp->lro_max_aggr_per_sess = lro_max_pkts;
6327         }
6328
6329         /* Enable Rx Traffic and interrupts on the NIC */
6330         if (start_nic(sp)) {
6331                 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
6332                 s2io_reset(sp);
6333                 free_rx_buffers(sp);
6334                 return -ENODEV;
6335         }
6336
6337         /* Add interrupt service routine */
6338         if (s2io_add_isr(sp) != 0) {
6339                 if (sp->intr_type == MSI_X)
6340                         s2io_rem_isr(sp);
6341                 s2io_reset(sp);
6342                 free_rx_buffers(sp);
6343                 return -ENODEV;
6344         }
6345
6346         S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
6347
6348         /* Enable tasklet for the device */
6349         tasklet_init(&sp->task, s2io_tasklet, (unsigned long) dev);
6350
6351         /*  Enable select interrupts */
6352         if (sp->intr_type != INTA)
6353                 en_dis_able_nic_intrs(sp, ENA_ALL_INTRS, DISABLE_INTRS);
6354         else {
6355                 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
6356                 interruptible |= TX_PIC_INTR | RX_PIC_INTR;
6357                 interruptible |= TX_MAC_INTR | RX_MAC_INTR;
6358                 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
6359         }
6360
6361
6362         atomic_set(&sp->card_state, CARD_UP);
6363         return 0;
6364 }
6365
6366 /**
6367  * s2io_restart_nic - Resets the NIC.
6368  * @data : long pointer to the device private structure
6369  * Description:
6370  * This function is scheduled to be run by the s2io_tx_watchdog
6371  * function after 0.5 secs to reset the NIC. The idea is to reduce
6372  * the run time of the watch dog routine which is run holding a
6373  * spin lock.
6374  */
6375
6376 static void s2io_restart_nic(unsigned long data)
6377 {
6378         struct net_device *dev = (struct net_device *) data;
6379         nic_t *sp = dev->priv;
6380
6381         s2io_card_down(sp);
6382         if (s2io_card_up(sp)) {
6383                 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
6384                           dev->name);
6385         }
6386         netif_wake_queue(dev);
6387         DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n",
6388                   dev->name);
6389
6390 }
6391
6392 /**
6393  *  s2io_tx_watchdog - Watchdog for transmit side.
6394  *  @dev : Pointer to net device structure
6395  *  Description:
6396  *  This function is triggered if the Tx Queue is stopped
6397  *  for a pre-defined amount of time when the Interface is still up.
6398  *  If the Interface is jammed in such a situation, the hardware is
6399  *  reset (by s2io_close) and restarted again (by s2io_open) to
6400  *  overcome any problem that might have been caused in the hardware.
6401  *  Return value:
6402  *  void
6403  */
6404
6405 static void s2io_tx_watchdog(struct net_device *dev)
6406 {
6407         nic_t *sp = dev->priv;
6408
6409         if (netif_carrier_ok(dev)) {
6410                 schedule_work(&sp->rst_timer_task);
6411                 sp->mac_control.stats_info->sw_stat.soft_reset_cnt++;
6412         }
6413 }
6414
6415 /**
6416  *   rx_osm_handler - To perform some OS related operations on SKB.
6417  *   @sp: private member of the device structure,pointer to s2io_nic structure.
6418  *   @skb : the socket buffer pointer.
6419  *   @len : length of the packet
6420  *   @cksum : FCS checksum of the frame.
6421  *   @ring_no : the ring from which this RxD was extracted.
6422  *   Description:
6423  *   This function is called by the Rx interrupt serivce routine to perform
6424  *   some OS related operations on the SKB before passing it to the upper
6425  *   layers. It mainly checks if the checksum is OK, if so adds it to the
6426  *   SKBs cksum variable, increments the Rx packet count and passes the SKB
6427  *   to the upper layer. If the checksum is wrong, it increments the Rx
6428  *   packet error count, frees the SKB and returns error.
6429  *   Return value:
6430  *   SUCCESS on success and -1 on failure.
6431  */
6432 static int rx_osm_handler(ring_info_t *ring_data, RxD_t * rxdp)
6433 {
6434         nic_t *sp = ring_data->nic;
6435         struct net_device *dev = (struct net_device *) sp->dev;
6436         struct sk_buff *skb = (struct sk_buff *)
6437                 ((unsigned long) rxdp->Host_Control);
6438         int ring_no = ring_data->ring_no;
6439         u16 l3_csum, l4_csum;
6440         unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
6441         lro_t *lro;
6442
6443         skb->dev = dev;
6444
6445         if (err) {
6446                 /* Check for parity error */
6447                 if (err & 0x1) {
6448                         sp->mac_control.stats_info->sw_stat.parity_err_cnt++;
6449                 }
6450
6451                 /*
6452                 * Drop the packet if bad transfer code. Exception being
6453                 * 0x5, which could be due to unsupported IPv6 extension header.
6454                 * In this case, we let stack handle the packet.
6455                 * Note that in this case, since checksum will be incorrect,
6456                 * stack will validate the same.
6457                 */
6458                 if (err && ((err >> 48) != 0x5)) {
6459                         DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%llx\n",
6460                                 dev->name, err);
6461                         sp->stats.rx_crc_errors++;
6462                         dev_kfree_skb(skb);
6463                         atomic_dec(&sp->rx_bufs_left[ring_no]);
6464                         rxdp->Host_Control = 0;
6465                         return 0;
6466                 }
6467         }
6468
6469         /* Updating statistics */
6470         rxdp->Host_Control = 0;
6471         sp->rx_pkt_count++;
6472         sp->stats.rx_packets++;
6473         if (sp->rxd_mode == RXD_MODE_1) {
6474                 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
6475
6476                 sp->stats.rx_bytes += len;
6477                 skb_put(skb, len);
6478
6479         } else if (sp->rxd_mode >= RXD_MODE_3A) {
6480                 int get_block = ring_data->rx_curr_get_info.block_index;
6481                 int get_off = ring_data->rx_curr_get_info.offset;
6482                 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
6483                 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
6484                 unsigned char *buff = skb_push(skb, buf0_len);
6485
6486                 buffAdd_t *ba = &ring_data->ba[get_block][get_off];
6487                 sp->stats.rx_bytes += buf0_len + buf2_len;
6488                 memcpy(buff, ba->ba_0, buf0_len);
6489
6490                 if (sp->rxd_mode == RXD_MODE_3A) {
6491                         int buf1_len = RXD_GET_BUFFER1_SIZE_3(rxdp->Control_2);
6492
6493                         skb_put(skb, buf1_len);
6494                         skb->len += buf2_len;
6495                         skb->data_len += buf2_len;
6496                         skb->truesize += buf2_len;
6497                         skb_put(skb_shinfo(skb)->frag_list, buf2_len);
6498                         sp->stats.rx_bytes += buf1_len;
6499
6500                 } else
6501                         skb_put(skb, buf2_len);
6502         }
6503
6504         if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) && ((!sp->lro) ||
6505             (sp->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) &&
6506             (sp->rx_csum)) {
6507                 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
6508                 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
6509                 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
6510                         /*
6511                          * NIC verifies if the Checksum of the received
6512                          * frame is Ok or not and accordingly returns
6513                          * a flag in the RxD.
6514                          */
6515                         skb->ip_summed = CHECKSUM_UNNECESSARY;
6516                         if (sp->lro) {
6517                                 u32 tcp_len;
6518                                 u8 *tcp;
6519                                 int ret = 0;
6520
6521                                 ret = s2io_club_tcp_session(skb->data, &tcp,
6522                                                 &tcp_len, &lro, rxdp, sp);
6523                                 switch (ret) {
6524                                         case 3: /* Begin anew */
6525                                                 lro->parent = skb;
6526                                                 goto aggregate;
6527                                         case 1: /* Aggregate */
6528                                         {
6529                                                 lro_append_pkt(sp, lro,
6530                                                         skb, tcp_len);
6531                                                 goto aggregate;
6532                                         }
6533                                         case 4: /* Flush session */
6534                                         {
6535                                                 lro_append_pkt(sp, lro,
6536                                                         skb, tcp_len);
6537                                                 queue_rx_frame(lro->parent);
6538                                                 clear_lro_session(lro);
6539                                                 sp->mac_control.stats_info->
6540                                                     sw_stat.flush_max_pkts++;
6541                                                 goto aggregate;
6542                                         }
6543                                         case 2: /* Flush both */
6544                                                 lro->parent->data_len =
6545                                                         lro->frags_len;
6546                                                 sp->mac_control.stats_info->
6547                                                      sw_stat.sending_both++;
6548                                                 queue_rx_frame(lro->parent);
6549                                                 clear_lro_session(lro);
6550                                                 goto send_up;
6551                                         case 0: /* sessions exceeded */
6552                                         case -1: /* non-TCP or not
6553                                                   * L2 aggregatable
6554                                                   */
6555                                         case 5: /*
6556                                                  * First pkt in session not
6557                                                  * L3/L4 aggregatable
6558                                                  */
6559                                                 break;
6560                                         default:
6561                                                 DBG_PRINT(ERR_DBG,
6562                                                         "%s: Samadhana!!\n",
6563                                                          __FUNCTION__);
6564                                                 BUG();
6565                                 }
6566                         }
6567                 } else {
6568                         /*
6569                          * Packet with erroneous checksum, let the
6570                          * upper layers deal with it.
6571                          */
6572                         skb->ip_summed = CHECKSUM_NONE;
6573                 }
6574         } else {
6575                 skb->ip_summed = CHECKSUM_NONE;
6576         }
6577
6578         if (!sp->lro) {
6579                 skb->protocol = eth_type_trans(skb, dev);
6580 #ifdef CONFIG_S2IO_NAPI
6581                 if (sp->vlgrp && RXD_GET_VLAN_TAG(rxdp->Control_2)) {
6582                         /* Queueing the vlan frame to the upper layer */
6583                         vlan_hwaccel_receive_skb(skb, sp->vlgrp,
6584                                 RXD_GET_VLAN_TAG(rxdp->Control_2));
6585                 } else {
6586                         netif_receive_skb(skb);
6587                 }
6588 #else
6589                 if (sp->vlgrp && RXD_GET_VLAN_TAG(rxdp->Control_2)) {
6590                         /* Queueing the vlan frame to the upper layer */
6591                         vlan_hwaccel_rx(skb, sp->vlgrp,
6592                                 RXD_GET_VLAN_TAG(rxdp->Control_2));
6593                 } else {
6594                         netif_rx(skb);
6595                 }
6596 #endif
6597         } else {
6598 send_up:
6599                 queue_rx_frame(skb);
6600         }
6601         dev->last_rx = jiffies;
6602 aggregate:
6603         atomic_dec(&sp->rx_bufs_left[ring_no]);
6604         return SUCCESS;
6605 }
6606
6607 /**
6608  *  s2io_link - stops/starts the Tx queue.
6609  *  @sp : private member of the device structure, which is a pointer to the
6610  *  s2io_nic structure.
6611  *  @link : inidicates whether link is UP/DOWN.
6612  *  Description:
6613  *  This function stops/starts the Tx queue depending on whether the link
6614  *  status of the NIC is is down or up. This is called by the Alarm
6615  *  interrupt handler whenever a link change interrupt comes up.
6616  *  Return value:
6617  *  void.
6618  */
6619
6620 static void s2io_link(nic_t * sp, int link)
6621 {
6622         struct net_device *dev = (struct net_device *) sp->dev;
6623
6624         if (link != sp->last_link_state) {
6625                 if (link == LINK_DOWN) {
6626                         DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
6627                         netif_carrier_off(dev);
6628                 } else {
6629                         DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
6630                         netif_carrier_on(dev);
6631                 }
6632         }
6633         sp->last_link_state = link;
6634 }
6635
6636 /**
6637  *  get_xena_rev_id - to identify revision ID of xena.
6638  *  @pdev : PCI Dev structure
6639  *  Description:
6640  *  Function to identify the Revision ID of xena.
6641  *  Return value:
6642  *  returns the revision ID of the device.
6643  */
6644
6645 static int get_xena_rev_id(struct pci_dev *pdev)
6646 {
6647         u8 id = 0;
6648         int ret;
6649         ret = pci_read_config_byte(pdev, PCI_REVISION_ID, (u8 *) & id);
6650         return id;
6651 }
6652
6653 /**
6654  *  s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
6655  *  @sp : private member of the device structure, which is a pointer to the
6656  *  s2io_nic structure.
6657  *  Description:
6658  *  This function initializes a few of the PCI and PCI-X configuration registers
6659  *  with recommended values.
6660  *  Return value:
6661  *  void
6662  */
6663
6664 static void s2io_init_pci(nic_t * sp)
6665 {
6666         u16 pci_cmd = 0, pcix_cmd = 0;
6667
6668         /* Enable Data Parity Error Recovery in PCI-X command register. */
6669         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
6670                              &(pcix_cmd));
6671         pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
6672                               (pcix_cmd | 1));
6673         pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
6674                              &(pcix_cmd));
6675
6676         /* Set the PErr Response bit in PCI command register. */
6677         pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
6678         pci_write_config_word(sp->pdev, PCI_COMMAND,
6679                               (pci_cmd | PCI_COMMAND_PARITY));
6680         pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
6681 }
6682
6683 static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type)
6684 {
6685         if ( tx_fifo_num > 8) {
6686                 DBG_PRINT(ERR_DBG, "s2io: Requested number of Tx fifos not "
6687                          "supported\n");
6688                 DBG_PRINT(ERR_DBG, "s2io: Default to 8 Tx fifos\n");
6689                 tx_fifo_num = 8;
6690         }
6691         if ( rx_ring_num > 8) {
6692                 DBG_PRINT(ERR_DBG, "s2io: Requested number of Rx rings not "
6693                          "supported\n");
6694                 DBG_PRINT(ERR_DBG, "s2io: Default to 8 Rx rings\n");
6695                 rx_ring_num = 8;
6696         }
6697 #ifdef CONFIG_S2IO_NAPI
6698         if (*dev_intr_type != INTA) {
6699                 DBG_PRINT(ERR_DBG, "s2io: NAPI cannot be enabled when "
6700                           "MSI/MSI-X is enabled. Defaulting to INTA\n");
6701                 *dev_intr_type = INTA;
6702         }
6703 #endif
6704 #ifndef CONFIG_PCI_MSI
6705         if (*dev_intr_type != INTA) {
6706                 DBG_PRINT(ERR_DBG, "s2io: This kernel does not support"
6707                           "MSI/MSI-X. Defaulting to INTA\n");
6708                 *dev_intr_type = INTA;
6709         }
6710 #else
6711         if (*dev_intr_type > MSI_X) {
6712                 DBG_PRINT(ERR_DBG, "s2io: Wrong intr_type requested. "
6713                           "Defaulting to INTA\n");
6714                 *dev_intr_type = INTA;
6715         }
6716 #endif
6717         if ((*dev_intr_type == MSI_X) &&
6718                         ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
6719                         (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
6720                 DBG_PRINT(ERR_DBG, "s2io: Xframe I does not support MSI_X. "
6721                                         "Defaulting to INTA\n");
6722                 *dev_intr_type = INTA;
6723         }
6724         if (rx_ring_mode > 3) {
6725                 DBG_PRINT(ERR_DBG, "s2io: Requested ring mode not supported\n");
6726                 DBG_PRINT(ERR_DBG, "s2io: Defaulting to 3-buffer mode\n");
6727                 rx_ring_mode = 3;
6728         }
6729         return SUCCESS;
6730 }
6731
6732 /**
6733  *  s2io_init_nic - Initialization of the adapter .
6734  *  @pdev : structure containing the PCI related information of the device.
6735  *  @pre: List of PCI devices supported by the driver listed in s2io_tbl.
6736  *  Description:
6737  *  The function initializes an adapter identified by the pci_dec structure.
6738  *  All OS related initialization including memory and device structure and
6739  *  initlaization of the device private variable is done. Also the swapper
6740  *  control register is initialized to enable read and write into the I/O
6741  *  registers of the device.
6742  *  Return value:
6743  *  returns 0 on success and negative on failure.
6744  */
6745
6746 static int __devinit
6747 s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
6748 {
6749         nic_t *sp;
6750         struct net_device *dev;
6751         int i, j, ret;
6752         int dma_flag = FALSE;
6753         u32 mac_up, mac_down;
6754         u64 val64 = 0, tmp64 = 0;
6755         XENA_dev_config_t __iomem *bar0 = NULL;
6756         u16 subid;
6757         mac_info_t *mac_control;
6758         struct config_param *config;
6759         int mode;
6760         u8 dev_intr_type = intr_type;
6761
6762         if ((ret = s2io_verify_parm(pdev, &dev_intr_type)))
6763                 return ret;
6764
6765         if ((ret = pci_enable_device(pdev))) {
6766                 DBG_PRINT(ERR_DBG,
6767                           "s2io_init_nic: pci_enable_device failed\n");
6768                 return ret;
6769         }
6770
6771         if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
6772                 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 64bit DMA\n");
6773                 dma_flag = TRUE;
6774                 if (pci_set_consistent_dma_mask
6775                     (pdev, DMA_64BIT_MASK)) {
6776                         DBG_PRINT(ERR_DBG,
6777                                   "Unable to obtain 64bit DMA for \
6778                                         consistent allocations\n");
6779                         pci_disable_device(pdev);
6780                         return -ENOMEM;
6781                 }
6782         } else if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
6783                 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 32bit DMA\n");
6784         } else {
6785                 pci_disable_device(pdev);
6786                 return -ENOMEM;
6787         }
6788         if (dev_intr_type != MSI_X) {
6789                 if (pci_request_regions(pdev, s2io_driver_name)) {
6790                         DBG_PRINT(ERR_DBG, "Request Regions failed\n");
6791                         pci_disable_device(pdev);
6792                         return -ENODEV;
6793                 }
6794         }
6795         else {
6796                 if (!(request_mem_region(pci_resource_start(pdev, 0),
6797                          pci_resource_len(pdev, 0), s2io_driver_name))) {
6798                         DBG_PRINT(ERR_DBG, "bar0 Request Regions failed\n");
6799                         pci_disable_device(pdev);
6800                         return -ENODEV;
6801                 }
6802                 if (!(request_mem_region(pci_resource_start(pdev, 2),
6803                          pci_resource_len(pdev, 2), s2io_driver_name))) {
6804                         DBG_PRINT(ERR_DBG, "bar1 Request Regions failed\n");
6805                         release_mem_region(pci_resource_start(pdev, 0),
6806                                    pci_resource_len(pdev, 0));
6807                         pci_disable_device(pdev);
6808                         return -ENODEV;
6809                 }
6810         }
6811
6812         dev = alloc_etherdev(sizeof(nic_t));
6813         if (dev == NULL) {
6814                 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
6815                 pci_disable_device(pdev);
6816                 pci_release_regions(pdev);
6817                 return -ENODEV;
6818         }
6819
6820         pci_set_master(pdev);
6821         pci_set_drvdata(pdev, dev);
6822         SET_MODULE_OWNER(dev);
6823         SET_NETDEV_DEV(dev, &pdev->dev);
6824
6825         /*  Private member variable initialized to s2io NIC structure */
6826         sp = dev->priv;
6827         memset(sp, 0, sizeof(nic_t));
6828         sp->dev = dev;
6829         sp->pdev = pdev;
6830         sp->high_dma_flag = dma_flag;
6831         sp->device_enabled_once = FALSE;
6832         if (rx_ring_mode == 1)
6833                 sp->rxd_mode = RXD_MODE_1;
6834         if (rx_ring_mode == 2)
6835                 sp->rxd_mode = RXD_MODE_3B;
6836         if (rx_ring_mode == 3)
6837                 sp->rxd_mode = RXD_MODE_3A;
6838
6839         sp->intr_type = dev_intr_type;
6840
6841         if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
6842                 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
6843                 sp->device_type = XFRAME_II_DEVICE;
6844         else
6845                 sp->device_type = XFRAME_I_DEVICE;
6846
6847         sp->lro = lro;
6848
6849         /* Initialize some PCI/PCI-X fields of the NIC. */
6850         s2io_init_pci(sp);
6851
6852         /*
6853          * Setting the device configuration parameters.
6854          * Most of these parameters can be specified by the user during
6855          * module insertion as they are module loadable parameters. If
6856          * these parameters are not not specified during load time, they
6857          * are initialized with default values.
6858          */
6859         mac_control = &sp->mac_control;
6860         config = &sp->config;
6861
6862         /* Tx side parameters. */
6863         config->tx_fifo_num = tx_fifo_num;
6864         for (i = 0; i < MAX_TX_FIFOS; i++) {
6865                 config->tx_cfg[i].fifo_len = tx_fifo_len[i];
6866                 config->tx_cfg[i].fifo_priority = i;
6867         }
6868
6869         /* mapping the QoS priority to the configured fifos */
6870         for (i = 0; i < MAX_TX_FIFOS; i++)
6871                 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num][i];
6872
6873         config->tx_intr_type = TXD_INT_TYPE_UTILZ;
6874         for (i = 0; i < config->tx_fifo_num; i++) {
6875                 config->tx_cfg[i].f_no_snoop =
6876                     (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
6877                 if (config->tx_cfg[i].fifo_len < 65) {
6878                         config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
6879                         break;
6880                 }
6881         }
6882         /* + 2 because one Txd for skb->data and one Txd for UFO */
6883         config->max_txds = MAX_SKB_FRAGS + 2;
6884
6885         /* Rx side parameters. */
6886         config->rx_ring_num = rx_ring_num;
6887         for (i = 0; i < MAX_RX_RINGS; i++) {
6888                 config->rx_cfg[i].num_rxd = rx_ring_sz[i] *
6889                     (rxd_count[sp->rxd_mode] + 1);
6890                 config->rx_cfg[i].ring_priority = i;
6891         }
6892
6893         for (i = 0; i < rx_ring_num; i++) {
6894                 config->rx_cfg[i].ring_org = RING_ORG_BUFF1;
6895                 config->rx_cfg[i].f_no_snoop =
6896                     (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
6897         }
6898
6899         /*  Setting Mac Control parameters */
6900         mac_control->rmac_pause_time = rmac_pause_time;
6901         mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
6902         mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
6903
6904
6905         /* Initialize Ring buffer parameters. */
6906         for (i = 0; i < config->rx_ring_num; i++)
6907                 atomic_set(&sp->rx_bufs_left[i], 0);
6908
6909         /* Initialize the number of ISRs currently running */
6910         atomic_set(&sp->isr_cnt, 0);
6911
6912         /*  initialize the shared memory used by the NIC and the host */
6913         if (init_shared_mem(sp)) {
6914                 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n",
6915                           dev->name);
6916                 ret = -ENOMEM;
6917                 goto mem_alloc_failed;
6918         }
6919
6920         sp->bar0 = ioremap(pci_resource_start(pdev, 0),
6921                                      pci_resource_len(pdev, 0));
6922         if (!sp->bar0) {
6923                 DBG_PRINT(ERR_DBG, "%s: S2IO: cannot remap io mem1\n",
6924                           dev->name);
6925                 ret = -ENOMEM;
6926                 goto bar0_remap_failed;
6927         }
6928
6929         sp->bar1 = ioremap(pci_resource_start(pdev, 2),
6930                                      pci_resource_len(pdev, 2));
6931         if (!sp->bar1) {
6932                 DBG_PRINT(ERR_DBG, "%s: S2IO: cannot remap io mem2\n",
6933                           dev->name);
6934                 ret = -ENOMEM;
6935                 goto bar1_remap_failed;
6936         }
6937
6938         dev->irq = pdev->irq;
6939         dev->base_addr = (unsigned long) sp->bar0;
6940
6941         /* Initializing the BAR1 address as the start of the FIFO pointer. */
6942         for (j = 0; j < MAX_TX_FIFOS; j++) {
6943                 mac_control->tx_FIFO_start[j] = (TxFIFO_element_t __iomem *)
6944                     (sp->bar1 + (j * 0x00020000));
6945         }
6946
6947         /*  Driver entry points */
6948         dev->open = &s2io_open;
6949         dev->stop = &s2io_close;
6950         dev->hard_start_xmit = &s2io_xmit;
6951         dev->get_stats = &s2io_get_stats;
6952         dev->set_multicast_list = &s2io_set_multicast;
6953         dev->do_ioctl = &s2io_ioctl;
6954         dev->change_mtu = &s2io_change_mtu;
6955         SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
6956         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6957         dev->vlan_rx_register = s2io_vlan_rx_register;
6958         dev->vlan_rx_kill_vid = (void *)s2io_vlan_rx_kill_vid;
6959
6960         /*
6961          * will use eth_mac_addr() for  dev->set_mac_address
6962          * mac address will be set every time dev->open() is called
6963          */
6964 #if defined(CONFIG_S2IO_NAPI)
6965         dev->poll = s2io_poll;
6966         dev->weight = 32;
6967 #endif
6968
6969 #ifdef CONFIG_NET_POLL_CONTROLLER
6970         dev->poll_controller = s2io_netpoll;
6971 #endif
6972
6973         dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
6974         if (sp->high_dma_flag == TRUE)
6975                 dev->features |= NETIF_F_HIGHDMA;
6976 #ifdef NETIF_F_TSO
6977         dev->features |= NETIF_F_TSO;
6978 #endif
6979 #ifdef NETIF_F_TSO6
6980         dev->features |= NETIF_F_TSO6;
6981 #endif
6982         if (sp->device_type & XFRAME_II_DEVICE) {
6983                 dev->features |= NETIF_F_UFO;
6984                 dev->features |= NETIF_F_HW_CSUM;
6985         }
6986
6987         dev->tx_timeout = &s2io_tx_watchdog;
6988         dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
6989         INIT_WORK(&sp->rst_timer_task,
6990                   (void (*)(void *)) s2io_restart_nic, dev);
6991         INIT_WORK(&sp->set_link_task,
6992                   (void (*)(void *)) s2io_set_link, sp);
6993
6994         pci_save_state(sp->pdev);
6995
6996         /* Setting swapper control on the NIC, for proper reset operation */
6997         if (s2io_set_swapper(sp)) {
6998                 DBG_PRINT(ERR_DBG, "%s:swapper settings are wrong\n",
6999                           dev->name);
7000                 ret = -EAGAIN;
7001                 goto set_swap_failed;
7002         }
7003
7004         /* Verify if the Herc works on the slot its placed into */
7005         if (sp->device_type & XFRAME_II_DEVICE) {
7006                 mode = s2io_verify_pci_mode(sp);
7007                 if (mode < 0) {
7008                         DBG_PRINT(ERR_DBG, "%s: ", __FUNCTION__);
7009                         DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
7010                         ret = -EBADSLT;
7011                         goto set_swap_failed;
7012                 }
7013         }
7014
7015         /* Not needed for Herc */
7016         if (sp->device_type & XFRAME_I_DEVICE) {
7017                 /*
7018                  * Fix for all "FFs" MAC address problems observed on
7019                  * Alpha platforms
7020                  */
7021                 fix_mac_address(sp);
7022                 s2io_reset(sp);
7023         }
7024
7025         /*
7026          * MAC address initialization.
7027          * For now only one mac address will be read and used.
7028          */
7029         bar0 = sp->bar0;
7030         val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
7031             RMAC_ADDR_CMD_MEM_OFFSET(0 + MAC_MAC_ADDR_START_OFFSET);
7032         writeq(val64, &bar0->rmac_addr_cmd_mem);
7033         wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
7034                       RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING);
7035         tmp64 = readq(&bar0->rmac_addr_data0_mem);
7036         mac_down = (u32) tmp64;
7037         mac_up = (u32) (tmp64 >> 32);
7038
7039         memset(sp->def_mac_addr[0].mac_addr, 0, sizeof(ETH_ALEN));
7040
7041         sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
7042         sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
7043         sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
7044         sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
7045         sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
7046         sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
7047
7048         /*  Set the factory defined MAC address initially   */
7049         dev->addr_len = ETH_ALEN;
7050         memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
7051
7052         /* reset Nic and bring it to known state */
7053         s2io_reset(sp);
7054
7055         /*
7056          * Initialize the tasklet status and link state flags
7057          * and the card state parameter
7058          */
7059         atomic_set(&(sp->card_state), 0);
7060         sp->tasklet_status = 0;
7061         sp->link_state = 0;
7062
7063         /* Initialize spinlocks */
7064         spin_lock_init(&sp->tx_lock);
7065 #ifndef CONFIG_S2IO_NAPI
7066         spin_lock_init(&sp->put_lock);
7067 #endif
7068         spin_lock_init(&sp->rx_lock);
7069
7070         /*
7071          * SXE-002: Configure link and activity LED to init state
7072          * on driver load.
7073          */
7074         subid = sp->pdev->subsystem_device;
7075         if ((subid & 0xFF) >= 0x07) {
7076                 val64 = readq(&bar0->gpio_control);
7077                 val64 |= 0x0000800000000000ULL;
7078                 writeq(val64, &bar0->gpio_control);
7079                 val64 = 0x0411040400000000ULL;
7080                 writeq(val64, (void __iomem *) bar0 + 0x2700);
7081                 val64 = readq(&bar0->gpio_control);
7082         }
7083
7084         sp->rx_csum = 1;        /* Rx chksum verify enabled by default */
7085
7086         if (register_netdev(dev)) {
7087                 DBG_PRINT(ERR_DBG, "Device registration failed\n");
7088                 ret = -ENODEV;
7089                 goto register_failed;
7090         }
7091         s2io_vpd_read(sp);
7092         DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2005 Neterion Inc.\n");
7093         DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n",dev->name,
7094                   sp->product_name, get_xena_rev_id(sp->pdev));
7095         DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
7096                   s2io_driver_version);
7097         DBG_PRINT(ERR_DBG, "%s: MAC ADDR: "
7098                           "%02x:%02x:%02x:%02x:%02x:%02x\n", dev->name,
7099                           sp->def_mac_addr[0].mac_addr[0],
7100                           sp->def_mac_addr[0].mac_addr[1],
7101                           sp->def_mac_addr[0].mac_addr[2],
7102                           sp->def_mac_addr[0].mac_addr[3],
7103                           sp->def_mac_addr[0].mac_addr[4],
7104                           sp->def_mac_addr[0].mac_addr[5]);
7105         if (sp->device_type & XFRAME_II_DEVICE) {
7106                 mode = s2io_print_pci_mode(sp);
7107                 if (mode < 0) {
7108                         DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
7109                         ret = -EBADSLT;
7110                         unregister_netdev(dev);
7111                         goto set_swap_failed;
7112                 }
7113         }
7114         switch(sp->rxd_mode) {
7115                 case RXD_MODE_1:
7116                     DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
7117                                                 dev->name);
7118                     break;
7119                 case RXD_MODE_3B:
7120                     DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
7121                                                 dev->name);
7122                     break;
7123                 case RXD_MODE_3A:
7124                     DBG_PRINT(ERR_DBG, "%s: 3-Buffer receive mode enabled\n",
7125                                                 dev->name);
7126                     break;
7127         }
7128 #ifdef CONFIG_S2IO_NAPI
7129         DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
7130 #endif
7131         switch(sp->intr_type) {
7132                 case INTA:
7133                     DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
7134                     break;
7135                 case MSI:
7136                     DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI\n", dev->name);
7137                     break;
7138                 case MSI_X:
7139                     DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
7140                     break;
7141         }
7142         if (sp->lro)
7143                 DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
7144                           dev->name);
7145
7146         /* Initialize device name */
7147         sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
7148
7149         /* Initialize bimodal Interrupts */
7150         sp->config.bimodal = bimodal;
7151         if (!(sp->device_type & XFRAME_II_DEVICE) && bimodal) {
7152                 sp->config.bimodal = 0;
7153                 DBG_PRINT(ERR_DBG,"%s:Bimodal intr not supported by Xframe I\n",
7154                         dev->name);
7155         }
7156
7157         /*
7158          * Make Link state as off at this point, when the Link change
7159          * interrupt comes the state will be automatically changed to
7160          * the right state.
7161          */
7162         netif_carrier_off(dev);
7163
7164         return 0;
7165
7166       register_failed:
7167       set_swap_failed:
7168         iounmap(sp->bar1);
7169       bar1_remap_failed:
7170         iounmap(sp->bar0);
7171       bar0_remap_failed:
7172       mem_alloc_failed:
7173         free_shared_mem(sp);
7174         pci_disable_device(pdev);
7175         if (dev_intr_type != MSI_X)
7176                 pci_release_regions(pdev);
7177         else {
7178                 release_mem_region(pci_resource_start(pdev, 0),
7179                         pci_resource_len(pdev, 0));
7180                 release_mem_region(pci_resource_start(pdev, 2),
7181                         pci_resource_len(pdev, 2));
7182         }
7183         pci_set_drvdata(pdev, NULL);
7184         free_netdev(dev);
7185
7186         return ret;
7187 }
7188
7189 /**
7190  * s2io_rem_nic - Free the PCI device
7191  * @pdev: structure containing the PCI related information of the device.
7192  * Description: This function is called by the Pci subsystem to release a
7193  * PCI device and free up all resource held up by the device. This could
7194  * be in response to a Hot plug event or when the driver is to be removed
7195  * from memory.
7196  */
7197
7198 static void __devexit s2io_rem_nic(struct pci_dev *pdev)
7199 {
7200         struct net_device *dev =
7201             (struct net_device *) pci_get_drvdata(pdev);
7202         nic_t *sp;
7203
7204         if (dev == NULL) {
7205                 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
7206                 return;
7207         }
7208
7209         sp = dev->priv;
7210         unregister_netdev(dev);
7211
7212         free_shared_mem(sp);
7213         iounmap(sp->bar0);
7214         iounmap(sp->bar1);
7215         pci_disable_device(pdev);
7216         if (sp->intr_type != MSI_X)
7217                 pci_release_regions(pdev);
7218         else {
7219                 release_mem_region(pci_resource_start(pdev, 0),
7220                         pci_resource_len(pdev, 0));
7221                 release_mem_region(pci_resource_start(pdev, 2),
7222                         pci_resource_len(pdev, 2));
7223         }
7224         pci_set_drvdata(pdev, NULL);
7225         free_netdev(dev);
7226 }
7227
7228 /**
7229  * s2io_starter - Entry point for the driver
7230  * Description: This function is the entry point for the driver. It verifies
7231  * the module loadable parameters and initializes PCI configuration space.
7232  */
7233
7234 int __init s2io_starter(void)
7235 {
7236         return pci_module_init(&s2io_driver);
7237 }
7238
7239 /**
7240  * s2io_closer - Cleanup routine for the driver
7241  * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
7242  */
7243
7244 static void s2io_closer(void)
7245 {
7246         pci_unregister_driver(&s2io_driver);
7247         DBG_PRINT(INIT_DBG, "cleanup done\n");
7248 }
7249
7250 module_init(s2io_starter);
7251 module_exit(s2io_closer);
7252
7253 static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
7254                 struct tcphdr **tcp, RxD_t *rxdp)
7255 {
7256         int ip_off;
7257         u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
7258
7259         if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
7260                 DBG_PRINT(INIT_DBG,"%s: Non-TCP frames not supported for LRO\n",
7261                           __FUNCTION__);
7262                 return -1;
7263         }
7264
7265         /* TODO:
7266          * By default the VLAN field in the MAC is stripped by the card, if this
7267          * feature is turned off in rx_pa_cfg register, then the ip_off field
7268          * has to be shifted by a further 2 bytes
7269          */
7270         switch (l2_type) {
7271                 case 0: /* DIX type */
7272                 case 4: /* DIX type with VLAN */
7273                         ip_off = HEADER_ETHERNET_II_802_3_SIZE;
7274                         break;
7275                 /* LLC, SNAP etc are considered non-mergeable */
7276                 default:
7277                         return -1;
7278         }
7279
7280         *ip = (struct iphdr *)((u8 *)buffer + ip_off);
7281         ip_len = (u8)((*ip)->ihl);
7282         ip_len <<= 2;
7283         *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
7284
7285         return 0;
7286 }
7287
7288 static int check_for_socket_match(lro_t *lro, struct iphdr *ip,
7289                                   struct tcphdr *tcp)
7290 {
7291         DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7292         if ((lro->iph->saddr != ip->saddr) || (lro->iph->daddr != ip->daddr) ||
7293            (lro->tcph->source != tcp->source) || (lro->tcph->dest != tcp->dest))
7294                 return -1;
7295         return 0;
7296 }
7297
7298 static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
7299 {
7300         return(ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2));
7301 }
7302
7303 static void initiate_new_session(lro_t *lro, u8 *l2h,
7304                      struct iphdr *ip, struct tcphdr *tcp, u32 tcp_pyld_len)
7305 {
7306         DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7307         lro->l2h = l2h;
7308         lro->iph = ip;
7309         lro->tcph = tcp;
7310         lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
7311         lro->tcp_ack = ntohl(tcp->ack_seq);
7312         lro->sg_num = 1;
7313         lro->total_len = ntohs(ip->tot_len);
7314         lro->frags_len = 0;
7315         /*
7316          * check if we saw TCP timestamp. Other consistency checks have
7317          * already been done.
7318          */
7319         if (tcp->doff == 8) {
7320                 u32 *ptr;
7321                 ptr = (u32 *)(tcp+1);
7322                 lro->saw_ts = 1;
7323                 lro->cur_tsval = *(ptr+1);
7324                 lro->cur_tsecr = *(ptr+2);
7325         }
7326         lro->in_use = 1;
7327 }
7328
7329 static void update_L3L4_header(nic_t *sp, lro_t *lro)
7330 {
7331         struct iphdr *ip = lro->iph;
7332         struct tcphdr *tcp = lro->tcph;
7333         u16 nchk;
7334         StatInfo_t *statinfo = sp->mac_control.stats_info;
7335         DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7336
7337         /* Update L3 header */
7338         ip->tot_len = htons(lro->total_len);
7339         ip->check = 0;
7340         nchk = ip_fast_csum((u8 *)lro->iph, ip->ihl);
7341         ip->check = nchk;
7342
7343         /* Update L4 header */
7344         tcp->ack_seq = lro->tcp_ack;
7345         tcp->window = lro->window;
7346
7347         /* Update tsecr field if this session has timestamps enabled */
7348         if (lro->saw_ts) {
7349                 u32 *ptr = (u32 *)(tcp + 1);
7350                 *(ptr+2) = lro->cur_tsecr;
7351         }
7352
7353         /* Update counters required for calculation of
7354          * average no. of packets aggregated.
7355          */
7356         statinfo->sw_stat.sum_avg_pkts_aggregated += lro->sg_num;
7357         statinfo->sw_stat.num_aggregations++;
7358 }
7359
7360 static void aggregate_new_rx(lro_t *lro, struct iphdr *ip,
7361                 struct tcphdr *tcp, u32 l4_pyld)
7362 {
7363         DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7364         lro->total_len += l4_pyld;
7365         lro->frags_len += l4_pyld;
7366         lro->tcp_next_seq += l4_pyld;
7367         lro->sg_num++;
7368
7369         /* Update ack seq no. and window ad(from this pkt) in LRO object */
7370         lro->tcp_ack = tcp->ack_seq;
7371         lro->window = tcp->window;
7372
7373         if (lro->saw_ts) {
7374                 u32 *ptr;
7375                 /* Update tsecr and tsval from this packet */
7376                 ptr = (u32 *) (tcp + 1);
7377                 lro->cur_tsval = *(ptr + 1);
7378                 lro->cur_tsecr = *(ptr + 2);
7379         }
7380 }
7381
7382 static int verify_l3_l4_lro_capable(lro_t *l_lro, struct iphdr *ip,
7383                                     struct tcphdr *tcp, u32 tcp_pyld_len)
7384 {
7385         u8 *ptr;
7386
7387         DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7388
7389         if (!tcp_pyld_len) {
7390                 /* Runt frame or a pure ack */
7391                 return -1;
7392         }
7393
7394         if (ip->ihl != 5) /* IP has options */
7395                 return -1;
7396
7397         /* If we see CE codepoint in IP header, packet is not mergeable */
7398         if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
7399                 return -1;
7400
7401         /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
7402         if (tcp->urg || tcp->psh || tcp->rst || tcp->syn || tcp->fin ||
7403                                     tcp->ece || tcp->cwr || !tcp->ack) {
7404                 /*
7405                  * Currently recognize only the ack control word and
7406                  * any other control field being set would result in
7407                  * flushing the LRO session
7408                  */
7409                 return -1;
7410         }
7411
7412         /*
7413          * Allow only one TCP timestamp option. Don't aggregate if
7414          * any other options are detected.
7415          */
7416         if (tcp->doff != 5 && tcp->doff != 8)
7417                 return -1;
7418
7419         if (tcp->doff == 8) {
7420                 ptr = (u8 *)(tcp + 1);
7421                 while (*ptr == TCPOPT_NOP)
7422                         ptr++;
7423                 if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
7424                         return -1;
7425
7426                 /* Ensure timestamp value increases monotonically */
7427                 if (l_lro)
7428                         if (l_lro->cur_tsval > *((u32 *)(ptr+2)))
7429                                 return -1;
7430
7431                 /* timestamp echo reply should be non-zero */
7432                 if (*((u32 *)(ptr+6)) == 0)
7433                         return -1;
7434         }
7435
7436         return 0;
7437 }
7438
7439 static int
7440 s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, lro_t **lro,
7441                       RxD_t *rxdp, nic_t *sp)
7442 {
7443         struct iphdr *ip;
7444         struct tcphdr *tcph;
7445         int ret = 0, i;
7446
7447         if (!(ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
7448                                          rxdp))) {
7449                 DBG_PRINT(INFO_DBG,"IP Saddr: %x Daddr: %x\n",
7450                           ip->saddr, ip->daddr);
7451         } else {
7452                 return ret;
7453         }
7454
7455         tcph = (struct tcphdr *)*tcp;
7456         *tcp_len = get_l4_pyld_length(ip, tcph);
7457         for (i=0; i<MAX_LRO_SESSIONS; i++) {
7458                 lro_t *l_lro = &sp->lro0_n[i];
7459                 if (l_lro->in_use) {
7460                         if (check_for_socket_match(l_lro, ip, tcph))
7461                                 continue;
7462                         /* Sock pair matched */
7463                         *lro = l_lro;
7464
7465                         if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
7466                                 DBG_PRINT(INFO_DBG, "%s:Out of order. expected "
7467                                           "0x%x, actual 0x%x\n", __FUNCTION__,
7468                                           (*lro)->tcp_next_seq,
7469                                           ntohl(tcph->seq));
7470
7471                                 sp->mac_control.stats_info->
7472                                    sw_stat.outof_sequence_pkts++;
7473                                 ret = 2;
7474                                 break;
7475                         }
7476
7477                         if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,*tcp_len))
7478                                 ret = 1; /* Aggregate */
7479                         else
7480                                 ret = 2; /* Flush both */
7481                         break;
7482                 }
7483         }
7484
7485         if (ret == 0) {
7486                 /* Before searching for available LRO objects,
7487                  * check if the pkt is L3/L4 aggregatable. If not
7488                  * don't create new LRO session. Just send this
7489                  * packet up.
7490                  */
7491                 if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len)) {
7492                         return 5;
7493                 }
7494
7495                 for (i=0; i<MAX_LRO_SESSIONS; i++) {
7496                         lro_t *l_lro = &sp->lro0_n[i];
7497                         if (!(l_lro->in_use)) {
7498                                 *lro = l_lro;
7499                                 ret = 3; /* Begin anew */
7500                                 break;
7501                         }
7502                 }
7503         }
7504
7505         if (ret == 0) { /* sessions exceeded */
7506                 DBG_PRINT(INFO_DBG,"%s:All LRO sessions already in use\n",
7507                           __FUNCTION__);
7508                 *lro = NULL;
7509                 return ret;
7510         }
7511
7512         switch (ret) {
7513                 case 3:
7514                         initiate_new_session(*lro, buffer, ip, tcph, *tcp_len);
7515                         break;
7516                 case 2:
7517                         update_L3L4_header(sp, *lro);
7518                         break;
7519                 case 1:
7520                         aggregate_new_rx(*lro, ip, tcph, *tcp_len);
7521                         if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
7522                                 update_L3L4_header(sp, *lro);
7523                                 ret = 4; /* Flush the LRO */
7524                         }
7525                         break;
7526                 default:
7527                         DBG_PRINT(ERR_DBG,"%s:Dont know, can't say!!\n",
7528                                 __FUNCTION__);
7529                         break;
7530         }
7531
7532         return ret;
7533 }
7534
7535 static void clear_lro_session(lro_t *lro)
7536 {
7537         static u16 lro_struct_size = sizeof(lro_t);
7538
7539         memset(lro, 0, lro_struct_size);
7540 }
7541
7542 static void queue_rx_frame(struct sk_buff *skb)
7543 {
7544         struct net_device *dev = skb->dev;
7545
7546         skb->protocol = eth_type_trans(skb, dev);
7547 #ifdef CONFIG_S2IO_NAPI
7548         netif_receive_skb(skb);
7549 #else
7550         netif_rx(skb);
7551 #endif
7552 }
7553
7554 static void lro_append_pkt(nic_t *sp, lro_t *lro, struct sk_buff *skb,
7555                            u32 tcp_len)
7556 {
7557         struct sk_buff *first = lro->parent;
7558
7559         first->len += tcp_len;
7560         first->data_len = lro->frags_len;
7561         skb_pull(skb, (skb->len - tcp_len));
7562         if (skb_shinfo(first)->frag_list)
7563                 lro->last_frag->next = skb;
7564         else
7565                 skb_shinfo(first)->frag_list = skb;
7566         lro->last_frag = skb;
7567         sp->mac_control.stats_info->sw_stat.clubbed_frms_cnt++;
7568         return;
7569 }