git.oblomov.eu Git - linux-2.6/blob - arch/mips/au1000/common/irq.c

   1 /*
   2  * BRIEF MODULE DESCRIPTION
   3  *      Au1000 interrupt routines.
   4  *
   5  * Copyright 2001 MontaVista Software Inc.
   6  * Author: MontaVista Software, Inc.
   7  *              ppopov@mvista.com or source@mvista.com
   8  *
   9  *  This program is free software; you can redistribute  it and/or modify it
  10  *  under  the terms of  the GNU General  Public License as published by the
  11  *  Free Software Foundation;  either version 2 of the  License, or (at your
  12  *  option) any later version.
  13  *
  14  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  15  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  16  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  17  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  18  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  19  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  20  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  21  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  22  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  23  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  24  *
  25  *  You should have received a copy of the  GNU General Public License along
  26  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  27  *  675 Mass Ave, Cambridge, MA 02139, USA.
  28  */
  29 #include <linux/config.h>
  30 #include <linux/errno.h>
  31 #include <linux/init.h>
  32 #include <linux/irq.h>
  33 #include <linux/kernel_stat.h>
  34 #include <linux/module.h>
  35 #include <linux/signal.h>
  36 #include <linux/sched.h>
  37 #include <linux/types.h>
  38 #include <linux/interrupt.h>
  39 #include <linux/ioport.h>
  40 #include <linux/timex.h>
  41 #include <linux/slab.h>
  42 #include <linux/random.h>
  43 #include <linux/delay.h>
  44 #include <linux/bitops.h>
  45
  46 #include <asm/bootinfo.h>
  47 #include <asm/io.h>
  48 #include <asm/mipsregs.h>
  49 #include <asm/system.h>
  50 #include <asm/mach-au1x00/au1000.h>
  51 #ifdef CONFIG_MIPS_PB1000
  52 #include <asm/mach-pb1x00/pb1000.h>
  53 #endif
  54
  55 #undef DEBUG_IRQ
  56 #ifdef DEBUG_IRQ
  57 /* note: prints function name for you */
  58 #define DPRINTK(fmt, args...) printk("%s: " fmt, __FUNCTION__ , ## args)
  59 #else
  60 #define DPRINTK(fmt, args...)
  61 #endif
  62
  63 #define EXT_INTC0_REQ0 2 /* IP 2 */
  64 #define EXT_INTC0_REQ1 3 /* IP 3 */
  65 #define EXT_INTC1_REQ0 4 /* IP 4 */
  66 #define EXT_INTC1_REQ1 5 /* IP 5 */
  67 #define MIPS_TIMER_IP  7 /* IP 7 */
  68
  69 extern void set_debug_traps(void);
  70 extern irq_cpustat_t irq_stat [NR_CPUS];
  71
  72 static void setup_local_irq(unsigned int irq, int type, int int_req);
  73 static unsigned int startup_irq(unsigned int irq);
  74 static void end_irq(unsigned int irq_nr);
  75 static inline void mask_and_ack_level_irq(unsigned int irq_nr);
  76 static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr);
  77 static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr);
  78 static inline void mask_and_ack_either_edge_irq(unsigned int irq_nr);
  79 inline void local_enable_irq(unsigned int irq_nr);
  80 inline void local_disable_irq(unsigned int irq_nr);
  81
  82 void    (*board_init_irq)(void);
  83
  84 #ifdef CONFIG_PM
  85 extern irqreturn_t counter0_irq(int irq, void *dev_id, struct pt_regs *regs);
  86 #endif
  87
  88 static DEFINE_SPINLOCK(irq_lock);
  89
  90
  91 static unsigned int startup_irq(unsigned int irq_nr)
  92 {
  93         local_enable_irq(irq_nr);
  94         return 0;
  95 }
  96
  97
  98 static void shutdown_irq(unsigned int irq_nr)
  99 {
 100         local_disable_irq(irq_nr);
 101         return;
 102 }
 103
 104
 105 inline void local_enable_irq(unsigned int irq_nr)
 106 {
 107         if (irq_nr > AU1000_LAST_INTC0_INT) {
 108                 au_writel(1<<(irq_nr-32), IC1_MASKSET);
 109                 au_writel(1<<(irq_nr-32), IC1_WAKESET);
 110         }
 111         else {
 112                 au_writel(1<<irq_nr, IC0_MASKSET);
 113                 au_writel(1<<irq_nr, IC0_WAKESET);
 114         }
 115         au_sync();
 116 }
 117
 118
 119 inline void local_disable_irq(unsigned int irq_nr)
 120 {
 121         if (irq_nr > AU1000_LAST_INTC0_INT) {
 122                 au_writel(1<<(irq_nr-32), IC1_MASKCLR);
 123                 au_writel(1<<(irq_nr-32), IC1_WAKECLR);
 124         }
 125         else {
 126                 au_writel(1<<irq_nr, IC0_MASKCLR);
 127                 au_writel(1<<irq_nr, IC0_WAKECLR);
 128         }
 129         au_sync();
 130 }
 131
 132
 133 static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr)
 134 {
 135         if (irq_nr > AU1000_LAST_INTC0_INT) {
 136                 au_writel(1<<(irq_nr-32), IC1_RISINGCLR);
 137                 au_writel(1<<(irq_nr-32), IC1_MASKCLR);
 138         }
 139         else {
 140                 au_writel(1<<irq_nr, IC0_RISINGCLR);
 141                 au_writel(1<<irq_nr, IC0_MASKCLR);
 142         }
 143         au_sync();
 144 }
 145
 146
 147 static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr)
 148 {
 149         if (irq_nr > AU1000_LAST_INTC0_INT) {
 150                 au_writel(1<<(irq_nr-32), IC1_FALLINGCLR);
 151                 au_writel(1<<(irq_nr-32), IC1_MASKCLR);
 152         }
 153         else {
 154                 au_writel(1<<irq_nr, IC0_FALLINGCLR);
 155                 au_writel(1<<irq_nr, IC0_MASKCLR);
 156         }
 157         au_sync();
 158 }
 159
 160
 161 static inline void mask_and_ack_either_edge_irq(unsigned int irq_nr)
 162 {
 163         /* This may assume that we don't get interrupts from
 164          * both edges at once, or if we do, that we don't care.
 165          */
 166         if (irq_nr > AU1000_LAST_INTC0_INT) {
 167                 au_writel(1<<(irq_nr-32), IC1_FALLINGCLR);
 168                 au_writel(1<<(irq_nr-32), IC1_RISINGCLR);
 169                 au_writel(1<<(irq_nr-32), IC1_MASKCLR);
 170         }
 171         else {
 172                 au_writel(1<<irq_nr, IC0_FALLINGCLR);
 173                 au_writel(1<<irq_nr, IC0_RISINGCLR);
 174                 au_writel(1<<irq_nr, IC0_MASKCLR);
 175         }
 176         au_sync();
 177 }
 178
 179
 180 static inline void mask_and_ack_level_irq(unsigned int irq_nr)
 181 {
 182
 183         local_disable_irq(irq_nr);
 184         au_sync();
 185 #if defined(CONFIG_MIPS_PB1000)
 186         if (irq_nr == AU1000_GPIO_15) {
 187                 au_writel(0x8000, PB1000_MDR); /* ack int */
 188                 au_sync();
 189         }
 190 #endif
 191         return;
 192 }
 193
 194
 195 static void end_irq(unsigned int irq_nr)
 196 {
 197         if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
 198                 local_enable_irq(irq_nr);
 199         }
 200 #if defined(CONFIG_MIPS_PB1000)
 201         if (irq_nr == AU1000_GPIO_15) {
 202                 au_writel(0x4000, PB1000_MDR); /* enable int */
 203                 au_sync();
 204         }
 205 #endif
 206 }
 207
 208 unsigned long save_local_and_disable(int controller)
 209 {
 210         int i;
 211         unsigned long flags, mask;
 212
 213         spin_lock_irqsave(&irq_lock, flags);
 214         if (controller) {
 215                 mask = au_readl(IC1_MASKSET);
 216                 for (i=32; i<64; i++) {
 217                         local_disable_irq(i);
 218                 }
 219         }
 220         else {
 221                 mask = au_readl(IC0_MASKSET);
 222                 for (i=0; i<32; i++) {
 223                         local_disable_irq(i);
 224                 }
 225         }
 226         spin_unlock_irqrestore(&irq_lock, flags);
 227
 228         return mask;
 229 }
 230
 231 void restore_local_and_enable(int controller, unsigned long mask)
 232 {
 233         int i;
 234         unsigned long flags, new_mask;
 235
 236         spin_lock_irqsave(&irq_lock, flags);
 237         for (i=0; i<32; i++) {
 238                 if (mask & (1<<i)) {
 239                         if (controller)
 240                                 local_enable_irq(i+32);
 241                         else
 242                                 local_enable_irq(i);
 243                 }
 244         }
 245         if (controller)
 246                 new_mask = au_readl(IC1_MASKSET);
 247         else
 248                 new_mask = au_readl(IC0_MASKSET);
 249
 250         spin_unlock_irqrestore(&irq_lock, flags);
 251 }
 252
 253
 254 static struct hw_interrupt_type rise_edge_irq_type = {
 255         .typename = "Au1000 Rise Edge",
 256         .startup = startup_irq,
 257         .shutdown = shutdown_irq,
 258         .enable = local_enable_irq,
 259         .disable = local_disable_irq,
 260         .ack = mask_and_ack_rise_edge_irq,
 261         .end = end_irq,
 262 };
 263
 264 static struct hw_interrupt_type fall_edge_irq_type = {
 265         .typename = "Au1000 Fall Edge",
 266         .startup = startup_irq,
 267         .shutdown = shutdown_irq,
 268         .enable = local_enable_irq,
 269         .disable = local_disable_irq,
 270         .ack = mask_and_ack_fall_edge_irq,
 271         .end = end_irq,
 272 };
 273
 274 static struct hw_interrupt_type either_edge_irq_type = {
 275         .typename = "Au1000 Rise or Fall Edge",
 276         .startup = startup_irq,
 277         .shutdown = shutdown_irq,
 278         .enable = local_enable_irq,
 279         .disable = local_disable_irq,
 280         .ack = mask_and_ack_either_edge_irq,
 281         .end = end_irq,
 282 };
 283
 284 static struct hw_interrupt_type level_irq_type = {
 285         .typename = "Au1000 Level",
 286         .startup = startup_irq,
 287         .shutdown = shutdown_irq,
 288         .enable = local_enable_irq,
 289         .disable = local_disable_irq,
 290         .ack = mask_and_ack_level_irq,
 291         .end = end_irq,
 292 };
 293
 294 #ifdef CONFIG_PM
 295 void startup_match20_interrupt(irqreturn_t (*handler)(int, void *, struct pt_regs *))
 296 {
 297         struct irq_desc *desc = &irq_desc[AU1000_TOY_MATCH2_INT];
 298
 299         static struct irqaction action;
 300         memset(&action, 0, sizeof(struct irqaction));
 301
 302         /* This is a big problem.... since we didn't use request_irq
 303          * when kernel/irq.c calls probe_irq_xxx this interrupt will
 304          * be probed for usage. This will end up disabling the device :(
 305          * Give it a bogus "action" pointer -- this will keep it from
 306          * getting auto-probed!
 307          *
 308          * By setting the status to match that of request_irq() we
 309          * can avoid it.  --cgray
 310         */
 311         action.dev_id = handler;
 312         action.flags = SA_INTERRUPT;
 313         cpus_clear(action.mask);
 314         action.name = "Au1xxx TOY";
 315         action.handler = handler;
 316         action.next = NULL;
 317
 318         desc->action = &action;
 319         desc->status &= ~(IRQ_DISABLED | IRQ_AUTODETECT | IRQ_WAITING | IRQ_INPROGRESS);
 320
 321         local_enable_irq(AU1000_TOY_MATCH2_INT);
 322 }
 323 #endif
 324
 325 static void setup_local_irq(unsigned int irq_nr, int type, int int_req)
 326 {
 327         if (irq_nr > AU1000_MAX_INTR) return;
 328         /* Config2[n], Config1[n], Config0[n] */
 329         if (irq_nr > AU1000_LAST_INTC0_INT) {
 330                 switch (type) {
 331                         case INTC_INT_RISE_EDGE: /* 0:0:1 */
 332                                 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
 333                                 au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
 334                                 au_writel(1<<(irq_nr-32), IC1_CFG0SET);
 335                                 irq_desc[irq_nr].handler = &rise_edge_irq_type;
 336                                 break;
 337                         case INTC_INT_FALL_EDGE: /* 0:1:0 */
 338                                 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
 339                                 au_writel(1<<(irq_nr-32), IC1_CFG1SET);
 340                                 au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
 341                                 irq_desc[irq_nr].handler = &fall_edge_irq_type;
 342                                 break;
 343                         case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */
 344                                 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
 345                                 au_writel(1<<(irq_nr-32), IC1_CFG1SET);
 346                                 au_writel(1<<(irq_nr-32), IC1_CFG0SET);
 347                                 irq_desc[irq_nr].handler = &either_edge_irq_type;
 348                                 break;
 349                         case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
 350                                 au_writel(1<<(irq_nr-32), IC1_CFG2SET);
 351                                 au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
 352                                 au_writel(1<<(irq_nr-32), IC1_CFG0SET);
 353                                 irq_desc[irq_nr].handler = &level_irq_type;
 354                                 break;
 355                         case INTC_INT_LOW_LEVEL: /* 1:1:0 */
 356                                 au_writel(1<<(irq_nr-32), IC1_CFG2SET);
 357                                 au_writel(1<<(irq_nr-32), IC1_CFG1SET);
 358                                 au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
 359                                 irq_desc[irq_nr].handler = &level_irq_type;
 360                                 break;
 361                         case INTC_INT_DISABLED: /* 0:0:0 */
 362                                 au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
 363                                 au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
 364                                 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
 365                                 break;
 366                         default: /* disable the interrupt */
 367                                 printk("unexpected int type %d (irq %d)\n", type, irq_nr);
 368                                 au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
 369                                 au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
 370                                 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
 371                                 return;
 372                 }
 373                 if (int_req) /* assign to interrupt request 1 */
 374                         au_writel(1<<(irq_nr-32), IC1_ASSIGNCLR);
 375                 else         /* assign to interrupt request 0 */
 376                         au_writel(1<<(irq_nr-32), IC1_ASSIGNSET);
 377                 au_writel(1<<(irq_nr-32), IC1_SRCSET);
 378                 au_writel(1<<(irq_nr-32), IC1_MASKCLR);
 379                 au_writel(1<<(irq_nr-32), IC1_WAKECLR);
 380         }
 381         else {
 382                 switch (type) {
 383                         case INTC_INT_RISE_EDGE: /* 0:0:1 */
 384                                 au_writel(1<<irq_nr, IC0_CFG2CLR);
 385                                 au_writel(1<<irq_nr, IC0_CFG1CLR);
 386                                 au_writel(1<<irq_nr, IC0_CFG0SET);
 387                                 irq_desc[irq_nr].handler = &rise_edge_irq_type;
 388                                 break;
 389                         case INTC_INT_FALL_EDGE: /* 0:1:0 */
 390                                 au_writel(1<<irq_nr, IC0_CFG2CLR);
 391                                 au_writel(1<<irq_nr, IC0_CFG1SET);
 392                                 au_writel(1<<irq_nr, IC0_CFG0CLR);
 393                                 irq_desc[irq_nr].handler = &fall_edge_irq_type;
 394                                 break;
 395                         case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */
 396                                 au_writel(1<<irq_nr, IC0_CFG2CLR);
 397                                 au_writel(1<<irq_nr, IC0_CFG1SET);
 398                                 au_writel(1<<irq_nr, IC0_CFG0SET);
 399                                 irq_desc[irq_nr].handler = &either_edge_irq_type;
 400                                 break;
 401                         case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
 402                                 au_writel(1<<irq_nr, IC0_CFG2SET);
 403                                 au_writel(1<<irq_nr, IC0_CFG1CLR);
 404                                 au_writel(1<<irq_nr, IC0_CFG0SET);
 405                                 irq_desc[irq_nr].handler = &level_irq_type;
 406                                 break;
 407                         case INTC_INT_LOW_LEVEL: /* 1:1:0 */
 408                                 au_writel(1<<irq_nr, IC0_CFG2SET);
 409                                 au_writel(1<<irq_nr, IC0_CFG1SET);
 410                                 au_writel(1<<irq_nr, IC0_CFG0CLR);
 411                                 irq_desc[irq_nr].handler = &level_irq_type;
 412                                 break;
 413                         case INTC_INT_DISABLED: /* 0:0:0 */
 414                                 au_writel(1<<irq_nr, IC0_CFG0CLR);
 415                                 au_writel(1<<irq_nr, IC0_CFG1CLR);
 416                                 au_writel(1<<irq_nr, IC0_CFG2CLR);
 417                                 break;
 418                         default: /* disable the interrupt */
 419                                 printk("unexpected int type %d (irq %d)\n", type, irq_nr);
 420                                 au_writel(1<<irq_nr, IC0_CFG0CLR);
 421                                 au_writel(1<<irq_nr, IC0_CFG1CLR);
 422                                 au_writel(1<<irq_nr, IC0_CFG2CLR);
 423                                 return;
 424                 }
 425                 if (int_req) /* assign to interrupt request 1 */
 426                         au_writel(1<<irq_nr, IC0_ASSIGNCLR);
 427                 else         /* assign to interrupt request 0 */
 428                         au_writel(1<<irq_nr, IC0_ASSIGNSET);
 429                 au_writel(1<<irq_nr, IC0_SRCSET);
 430                 au_writel(1<<irq_nr, IC0_MASKCLR);
 431                 au_writel(1<<irq_nr, IC0_WAKECLR);
 432         }
 433         au_sync();
 434 }
 435
 436
 437 void __init arch_init_irq(void)
 438 {
 439         int i;
 440         unsigned long cp0_status;
 441         au1xxx_irq_map_t *imp;
 442         extern au1xxx_irq_map_t au1xxx_irq_map[];
 443         extern au1xxx_irq_map_t au1xxx_ic0_map[];
 444         extern int au1xxx_nr_irqs;
 445         extern int au1xxx_ic0_nr_irqs;
 446
 447         cp0_status = read_c0_status();
 448
 449         /* Initialize interrupt controllers to a safe state.
 450         */
 451         au_writel(0xffffffff, IC0_CFG0CLR);
 452         au_writel(0xffffffff, IC0_CFG1CLR);
 453         au_writel(0xffffffff, IC0_CFG2CLR);
 454         au_writel(0xffffffff, IC0_MASKCLR);
 455         au_writel(0xffffffff, IC0_ASSIGNSET);
 456         au_writel(0xffffffff, IC0_WAKECLR);
 457         au_writel(0xffffffff, IC0_SRCSET);
 458         au_writel(0xffffffff, IC0_FALLINGCLR);
 459         au_writel(0xffffffff, IC0_RISINGCLR);
 460         au_writel(0x00000000, IC0_TESTBIT);
 461
 462         au_writel(0xffffffff, IC1_CFG0CLR);
 463         au_writel(0xffffffff, IC1_CFG1CLR);
 464         au_writel(0xffffffff, IC1_CFG2CLR);
 465         au_writel(0xffffffff, IC1_MASKCLR);
 466         au_writel(0xffffffff, IC1_ASSIGNSET);
 467         au_writel(0xffffffff, IC1_WAKECLR);
 468         au_writel(0xffffffff, IC1_SRCSET);
 469         au_writel(0xffffffff, IC1_FALLINGCLR);
 470         au_writel(0xffffffff, IC1_RISINGCLR);
 471         au_writel(0x00000000, IC1_TESTBIT);
 472
 473         /* Initialize IC0, which is fixed per processor.
 474         */
 475         imp = au1xxx_ic0_map;
 476         for (i=0; i<au1xxx_ic0_nr_irqs; i++) {
 477                 setup_local_irq(imp->im_irq, imp->im_type, imp->im_request);
 478                 imp++;
 479         }
 480
 481         /* Now set up the irq mapping for the board.
 482         */
 483         imp = au1xxx_irq_map;
 484         for (i=0; i<au1xxx_nr_irqs; i++) {
 485                 setup_local_irq(imp->im_irq, imp->im_type, imp->im_request);
 486                 imp++;
 487         }
 488
 489         set_c0_status(ALLINTS);
 490
 491         /* Board specific IRQ initialization.
 492         */
 493         if (board_init_irq)
 494                 (*board_init_irq)();
 495 }
 496
 497
 498 /*
 499  * Interrupts are nested. Even if an interrupt handler is registered
 500  * as "fast", we might get another interrupt before we return from
 501  * intcX_reqX_irqdispatch().
 502  */
 503
 504 void intc0_req0_irqdispatch(struct pt_regs *regs)
 505 {
 506         int irq = 0;
 507         static unsigned long intc0_req0 = 0;
 508
 509         intc0_req0 |= au_readl(IC0_REQ0INT);
 510
 511         if (!intc0_req0) return;
 512 #ifdef AU1000_USB_DEV_REQ_INT
 513         /*
 514          * Because of the tight timing of SETUP token to reply
 515          * transactions, the USB devices-side packet complete
 516          * interrupt needs the highest priority.
 517          */
 518         if ((intc0_req0 & (1<<AU1000_USB_DEV_REQ_INT))) {
 519                 intc0_req0 &= ~(1<<AU1000_USB_DEV_REQ_INT);
 520                 do_IRQ(AU1000_USB_DEV_REQ_INT, regs);
 521                 return;
 522         }
 523 #endif
 524         irq = au_ffs(intc0_req0) - 1;
 525         intc0_req0 &= ~(1<<irq);
 526         do_IRQ(irq, regs);
 527 }
 528
 529
 530 void intc0_req1_irqdispatch(struct pt_regs *regs)
 531 {
 532         int irq = 0;
 533         static unsigned long intc0_req1 = 0;
 534
 535         intc0_req1 |= au_readl(IC0_REQ1INT);
 536
 537         if (!intc0_req1) return;
 538
 539         irq = au_ffs(intc0_req1) - 1;
 540         intc0_req1 &= ~(1<<irq);
 541         do_IRQ(irq, regs);
 542 }
 543
 544
 545 /*
 546  * Interrupt Controller 1:
 547  * interrupts 32 - 63
 548  */
 549 void intc1_req0_irqdispatch(struct pt_regs *regs)
 550 {
 551         int irq = 0;
 552         static unsigned long intc1_req0 = 0;
 553
 554         intc1_req0 |= au_readl(IC1_REQ0INT);
 555
 556         if (!intc1_req0) return;
 557
 558         irq = au_ffs(intc1_req0) - 1;
 559         intc1_req0 &= ~(1<<irq);
 560         irq += 32;
 561         do_IRQ(irq, regs);
 562 }
 563
 564
 565 void intc1_req1_irqdispatch(struct pt_regs *regs)
 566 {
 567         int irq = 0;
 568         static unsigned long intc1_req1 = 0;
 569
 570         intc1_req1 |= au_readl(IC1_REQ1INT);
 571
 572         if (!intc1_req1) return;
 573
 574         irq = au_ffs(intc1_req1) - 1;
 575         intc1_req1 &= ~(1<<irq);
 576         irq += 32;
 577         do_IRQ(irq, regs);
 578 }
 579
 580 #ifdef CONFIG_PM
 581
 582 /* Save/restore the interrupt controller state.
 583  * Called from the save/restore core registers as part of the
 584  * au_sleep function in power.c.....maybe I should just pm_register()
 585  * them instead?
 586  */
 587 static uint     sleep_intctl_config0[2];
 588 static uint     sleep_intctl_config1[2];
 589 static uint     sleep_intctl_config2[2];
 590 static uint     sleep_intctl_src[2];
 591 static uint     sleep_intctl_assign[2];
 592 static uint     sleep_intctl_wake[2];
 593 static uint     sleep_intctl_mask[2];
 594
 595 void
 596 save_au1xxx_intctl(void)
 597 {
 598         sleep_intctl_config0[0] = au_readl(IC0_CFG0RD);
 599         sleep_intctl_config1[0] = au_readl(IC0_CFG1RD);
 600         sleep_intctl_config2[0] = au_readl(IC0_CFG2RD);
 601         sleep_intctl_src[0] = au_readl(IC0_SRCRD);
 602         sleep_intctl_assign[0] = au_readl(IC0_ASSIGNRD);
 603         sleep_intctl_wake[0] = au_readl(IC0_WAKERD);
 604         sleep_intctl_mask[0] = au_readl(IC0_MASKRD);
 605
 606         sleep_intctl_config0[1] = au_readl(IC1_CFG0RD);
 607         sleep_intctl_config1[1] = au_readl(IC1_CFG1RD);
 608         sleep_intctl_config2[1] = au_readl(IC1_CFG2RD);
 609         sleep_intctl_src[1] = au_readl(IC1_SRCRD);
 610         sleep_intctl_assign[1] = au_readl(IC1_ASSIGNRD);
 611         sleep_intctl_wake[1] = au_readl(IC1_WAKERD);
 612         sleep_intctl_mask[1] = au_readl(IC1_MASKRD);
 613 }
 614
 615 /* For most restore operations, we clear the entire register and
 616  * then set the bits we found during the save.
 617  */
 618 void
 619 restore_au1xxx_intctl(void)
 620 {
 621         au_writel(0xffffffff, IC0_MASKCLR); au_sync();
 622
 623         au_writel(0xffffffff, IC0_CFG0CLR); au_sync();
 624         au_writel(sleep_intctl_config0[0], IC0_CFG0SET); au_sync();
 625         au_writel(0xffffffff, IC0_CFG1CLR); au_sync();
 626         au_writel(sleep_intctl_config1[0], IC0_CFG1SET); au_sync();
 627         au_writel(0xffffffff, IC0_CFG2CLR); au_sync();
 628         au_writel(sleep_intctl_config2[0], IC0_CFG2SET); au_sync();
 629         au_writel(0xffffffff, IC0_SRCCLR); au_sync();
 630         au_writel(sleep_intctl_src[0], IC0_SRCSET); au_sync();
 631         au_writel(0xffffffff, IC0_ASSIGNCLR); au_sync();
 632         au_writel(sleep_intctl_assign[0], IC0_ASSIGNSET); au_sync();
 633         au_writel(0xffffffff, IC0_WAKECLR); au_sync();
 634         au_writel(sleep_intctl_wake[0], IC0_WAKESET); au_sync();
 635         au_writel(0xffffffff, IC0_RISINGCLR); au_sync();
 636         au_writel(0xffffffff, IC0_FALLINGCLR); au_sync();
 637         au_writel(0x00000000, IC0_TESTBIT); au_sync();
 638
 639         au_writel(0xffffffff, IC1_MASKCLR); au_sync();
 640
 641         au_writel(0xffffffff, IC1_CFG0CLR); au_sync();
 642         au_writel(sleep_intctl_config0[1], IC1_CFG0SET); au_sync();
 643         au_writel(0xffffffff, IC1_CFG1CLR); au_sync();
 644         au_writel(sleep_intctl_config1[1], IC1_CFG1SET); au_sync();
 645         au_writel(0xffffffff, IC1_CFG2CLR); au_sync();
 646         au_writel(sleep_intctl_config2[1], IC1_CFG2SET); au_sync();
 647         au_writel(0xffffffff, IC1_SRCCLR); au_sync();
 648         au_writel(sleep_intctl_src[1], IC1_SRCSET); au_sync();
 649         au_writel(0xffffffff, IC1_ASSIGNCLR); au_sync();
 650         au_writel(sleep_intctl_assign[1], IC1_ASSIGNSET); au_sync();
 651         au_writel(0xffffffff, IC1_WAKECLR); au_sync();
 652         au_writel(sleep_intctl_wake[1], IC1_WAKESET); au_sync();
 653         au_writel(0xffffffff, IC1_RISINGCLR); au_sync();
 654         au_writel(0xffffffff, IC1_FALLINGCLR); au_sync();
 655         au_writel(0x00000000, IC1_TESTBIT); au_sync();
 656
 657         au_writel(sleep_intctl_mask[1], IC1_MASKSET); au_sync();
 658
 659         au_writel(sleep_intctl_mask[0], IC0_MASKSET); au_sync();
 660 }
 661 #endif /* CONFIG_PM */
 662
 663 asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
 664 {
 665         unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
 666
 667         if (pending & CAUSEF_IP7)
 668                 mips_timer_interrupt(regs);
 669         else if (pending & CAUSEF_IP2)
 670                 intc0_req0_irqdispatch(regs);
 671         else if (pending & CAUSEF_IP3)
 672                 intc0_req1_irqdispatch(regs);
 673         else if (pending & CAUSEF_IP4)
 674                 intc1_req0_irqdispatch(regs);
 675         else if (pending  & CAUSEF_IP5)
 676                 intc1_req1_irqdispatch(regs);
 677         else
 678                 spurious_interrupt(regs);
 679 }