1 /******************************************************************************
3 * Copyright(c) 2007-2008 Intel Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *****************************************************************************/
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/init.h>
29 #include <linux/pci.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/delay.h>
32 #include <linux/skbuff.h>
33 #include <linux/netdevice.h>
34 #include <linux/wireless.h>
35 #include <net/mac80211.h>
36 #include <linux/etherdevice.h>
37 #include <asm/unaligned.h>
39 #include "iwl-eeprom.h"
44 #include "iwl-helpers.h"
45 #include "iwl-5000-hw.h"
47 #define IWL5000_UCODE_API "-1"
49 static const u16 iwl5000_default_queue_to_tx_fifo[] = {
59 /* FIXME: same implementation as 4965 */
60 static int iwl5000_apm_stop_master(struct iwl_priv *priv)
65 spin_lock_irqsave(&priv->lock, flags);
67 /* set stop master bit */
68 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
70 ret = iwl_poll_bit(priv, CSR_RESET,
71 CSR_RESET_REG_FLAG_MASTER_DISABLED,
72 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
77 spin_unlock_irqrestore(&priv->lock, flags);
78 IWL_DEBUG_INFO("stop master\n");
84 static int iwl5000_apm_init(struct iwl_priv *priv)
88 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
89 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
91 /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
92 iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
93 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
95 /* Set FH wait treshold to maximum (HW error during stress W/A) */
96 iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
98 /* enable HAP INTA to move device L1a -> L0s */
99 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
100 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
102 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
104 /* set "initialization complete" bit to move adapter
105 * D0U* --> D0A* state */
106 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
108 /* wait for clock stabilization */
109 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
110 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
111 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
113 IWL_DEBUG_INFO("Failed to init the card\n");
117 ret = iwl_grab_nic_access(priv);
122 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
126 /* disable L1-Active */
127 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
128 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
130 iwl_release_nic_access(priv);
135 /* FIXME: this is indentical to 4965 */
136 static void iwl5000_apm_stop(struct iwl_priv *priv)
140 iwl5000_apm_stop_master(priv);
142 spin_lock_irqsave(&priv->lock, flags);
144 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
148 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
150 spin_unlock_irqrestore(&priv->lock, flags);
154 static int iwl5000_apm_reset(struct iwl_priv *priv)
159 iwl5000_apm_stop_master(priv);
161 spin_lock_irqsave(&priv->lock, flags);
163 iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
168 /* FIXME: put here L1A -L0S w/a */
170 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
172 /* set "initialization complete" bit to move adapter
173 * D0U* --> D0A* state */
174 iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
176 /* wait for clock stabilization */
177 ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
178 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
179 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
181 IWL_DEBUG_INFO("Failed to init the card\n");
185 ret = iwl_grab_nic_access(priv);
190 iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
194 /* disable L1-Active */
195 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
196 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
198 iwl_release_nic_access(priv);
201 spin_unlock_irqrestore(&priv->lock, flags);
207 static void iwl5000_nic_config(struct iwl_priv *priv)
213 spin_lock_irqsave(&priv->lock, flags);
215 pci_read_config_byte(priv->pci_dev, PCI_LINK_CTRL, &val_link);
217 /* L1 is enabled by BIOS */
218 if ((val_link & PCI_LINK_VAL_L1_EN) == PCI_LINK_VAL_L1_EN)
219 /* diable L0S disabled L1A enabled */
220 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
222 /* L0S enabled L1A disabled */
223 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
225 radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
227 /* write radio config values to register */
228 if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_5000_RF_CFG_TYPE_MAX)
229 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
230 EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
231 EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
232 EEPROM_RF_CFG_DASH_MSK(radio_cfg));
234 /* set CSR_HW_CONFIG_REG for uCode use */
235 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
236 CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
237 CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
239 /* W/A : NIC is stuck in a reset state after Early PCIe power off
240 * (PCIe power is lost before PERST# is asserted),
241 * causing ME FW to lose ownership and not being able to obtain it back.
243 iwl_grab_nic_access(priv);
244 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
245 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
246 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);
247 iwl_release_nic_access(priv);
249 spin_unlock_irqrestore(&priv->lock, flags);
257 static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
261 if ((address & INDIRECT_ADDRESS) == 0)
264 switch (address & INDIRECT_TYPE_MSK) {
266 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
268 case INDIRECT_GENERAL:
269 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
271 case INDIRECT_REGULATORY:
272 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
274 case INDIRECT_CALIBRATION:
275 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
277 case INDIRECT_PROCESS_ADJST:
278 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
280 case INDIRECT_OTHERS:
281 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
284 IWL_ERROR("illegal indirect type: 0x%X\n",
285 address & INDIRECT_TYPE_MSK);
289 /* translate the offset from words to byte */
290 return (address & ADDRESS_MSK) + (offset << 1);
293 static int iwl5000_eeprom_check_version(struct iwl_priv *priv)
296 struct iwl_eeprom_calib_hdr {
302 eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
304 hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
305 EEPROM_5000_CALIB_ALL);
307 if (eeprom_ver < EEPROM_5000_EEPROM_VERSION ||
308 hdr->version < EEPROM_5000_TX_POWER_VERSION)
313 IWL_ERROR("Unsuported EEPROM VER=0x%x < 0x%x CALIB=0x%x < 0x%x\n",
314 eeprom_ver, EEPROM_5000_EEPROM_VERSION,
315 hdr->version, EEPROM_5000_TX_POWER_VERSION);
320 static void iwl5000_gain_computation(struct iwl_priv *priv,
321 u32 average_noise[NUM_RX_CHAINS],
322 u16 min_average_noise_antenna_i,
323 u32 min_average_noise)
327 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
329 /* Find Gain Code for the antennas B and C */
330 for (i = 1; i < NUM_RX_CHAINS; i++) {
331 if ((data->disconn_array[i])) {
332 data->delta_gain_code[i] = 0;
335 delta_g = (1000 * ((s32)average_noise[0] -
336 (s32)average_noise[i])) / 1500;
337 /* bound gain by 2 bits value max, 3rd bit is sign */
338 data->delta_gain_code[i] =
339 min(abs(delta_g), CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
342 /* set negative sign */
343 data->delta_gain_code[i] |= (1 << 2);
346 IWL_DEBUG_CALIB("Delta gains: ANT_B = %d ANT_C = %d\n",
347 data->delta_gain_code[1], data->delta_gain_code[2]);
349 if (!data->radio_write) {
350 struct iwl5000_calibration_chain_noise_gain_cmd cmd;
351 memset(&cmd, 0, sizeof(cmd));
353 cmd.op_code = IWL5000_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD;
354 cmd.delta_gain_1 = data->delta_gain_code[1];
355 cmd.delta_gain_2 = data->delta_gain_code[2];
356 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD,
357 sizeof(cmd), &cmd, NULL);
359 data->radio_write = 1;
360 data->state = IWL_CHAIN_NOISE_CALIBRATED;
363 data->chain_noise_a = 0;
364 data->chain_noise_b = 0;
365 data->chain_noise_c = 0;
366 data->chain_signal_a = 0;
367 data->chain_signal_b = 0;
368 data->chain_signal_c = 0;
369 data->beacon_count = 0;
372 static void iwl5000_chain_noise_reset(struct iwl_priv *priv)
374 struct iwl_chain_noise_data *data = &priv->chain_noise_data;
376 if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
377 struct iwl5000_calibration_chain_noise_reset_cmd cmd;
379 memset(&cmd, 0, sizeof(cmd));
380 cmd.op_code = IWL5000_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD;
381 if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
383 IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n");
384 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
385 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
389 static void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
392 if ((info->flags & IEEE80211_TX_CTL_USE_RTS_CTS) ||
393 (info->flags & IEEE80211_TX_CTL_USE_CTS_PROTECT))
394 *tx_flags |= TX_CMD_FLG_RTS_CTS_MSK;
396 *tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK;
399 static struct iwl_sensitivity_ranges iwl5000_sensitivity = {
402 .auto_corr_min_ofdm = 90,
403 .auto_corr_min_ofdm_mrc = 170,
404 .auto_corr_min_ofdm_x1 = 120,
405 .auto_corr_min_ofdm_mrc_x1 = 240,
407 .auto_corr_max_ofdm = 120,
408 .auto_corr_max_ofdm_mrc = 210,
409 .auto_corr_max_ofdm_x1 = 155,
410 .auto_corr_max_ofdm_mrc_x1 = 290,
412 .auto_corr_min_cck = 125,
413 .auto_corr_max_cck = 200,
414 .auto_corr_min_cck_mrc = 170,
415 .auto_corr_max_cck_mrc = 400,
420 static const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv,
423 u32 address = eeprom_indirect_address(priv, offset);
424 BUG_ON(address >= priv->cfg->eeprom_size);
425 return &priv->eeprom[address];
431 static int iwl5000_send_Xtal_calib(struct iwl_priv *priv)
433 u16 *xtal_calib = (u16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL);
435 struct iwl5000_calibration cal_cmd = {
436 .op_code = IWL5000_PHY_CALIBRATE_CRYSTAL_FRQ_CMD,
443 return iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
444 sizeof(cal_cmd), &cal_cmd);
447 static int iwl5000_send_calib_results(struct iwl_priv *priv)
451 struct iwl_host_cmd hcmd = {
452 .id = REPLY_PHY_CALIBRATION_CMD,
453 .meta.flags = CMD_SIZE_HUGE,
456 if (priv->calib_results.lo_res) {
457 hcmd.len = priv->calib_results.lo_res_len;
458 hcmd.data = priv->calib_results.lo_res;
459 ret = iwl_send_cmd_sync(priv, &hcmd);
465 if (priv->calib_results.tx_iq_res) {
466 hcmd.len = priv->calib_results.tx_iq_res_len;
467 hcmd.data = priv->calib_results.tx_iq_res;
468 ret = iwl_send_cmd_sync(priv, &hcmd);
474 if (priv->calib_results.tx_iq_perd_res) {
475 hcmd.len = priv->calib_results.tx_iq_perd_res_len;
476 hcmd.data = priv->calib_results.tx_iq_perd_res;
477 ret = iwl_send_cmd_sync(priv, &hcmd);
485 IWL_ERROR("Error %d\n", ret);
489 static int iwl5000_send_calib_cfg(struct iwl_priv *priv)
491 struct iwl5000_calib_cfg_cmd calib_cfg_cmd;
492 struct iwl_host_cmd cmd = {
493 .id = CALIBRATION_CFG_CMD,
494 .len = sizeof(struct iwl5000_calib_cfg_cmd),
495 .data = &calib_cfg_cmd,
498 memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
499 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
500 calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
501 calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
502 calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
504 return iwl_send_cmd(priv, &cmd);
507 static void iwl5000_rx_calib_result(struct iwl_priv *priv,
508 struct iwl_rx_mem_buffer *rxb)
510 struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
511 struct iwl5000_calib_hdr *hdr = (struct iwl5000_calib_hdr *)pkt->u.raw;
512 int len = le32_to_cpu(pkt->len) & FH_RSCSR_FRAME_SIZE_MSK;
514 iwl_free_calib_results(priv);
516 /* reduce the size of the length field itself */
519 switch (hdr->op_code) {
520 case IWL5000_PHY_CALIBRATE_LO_CMD:
521 priv->calib_results.lo_res = kzalloc(len, GFP_ATOMIC);
522 priv->calib_results.lo_res_len = len;
523 memcpy(priv->calib_results.lo_res, pkt->u.raw, len);
525 case IWL5000_PHY_CALIBRATE_TX_IQ_CMD:
526 priv->calib_results.tx_iq_res = kzalloc(len, GFP_ATOMIC);
527 priv->calib_results.tx_iq_res_len = len;
528 memcpy(priv->calib_results.tx_iq_res, pkt->u.raw, len);
530 case IWL5000_PHY_CALIBRATE_TX_IQ_PERD_CMD:
531 priv->calib_results.tx_iq_perd_res = kzalloc(len, GFP_ATOMIC);
532 priv->calib_results.tx_iq_perd_res_len = len;
533 memcpy(priv->calib_results.tx_iq_perd_res, pkt->u.raw, len);
536 IWL_ERROR("Unknown calibration notification %d\n",
542 static void iwl5000_rx_calib_complete(struct iwl_priv *priv,
543 struct iwl_rx_mem_buffer *rxb)
545 IWL_DEBUG_INFO("Init. calibration is completed, restarting fw.\n");
546 queue_work(priv->workqueue, &priv->restart);
552 static int iwl5000_load_section(struct iwl_priv *priv,
553 struct fw_desc *image,
559 dma_addr_t phy_addr = image->p_addr;
560 u32 byte_cnt = image->len;
562 spin_lock_irqsave(&priv->lock, flags);
563 ret = iwl_grab_nic_access(priv);
565 spin_unlock_irqrestore(&priv->lock, flags);
569 iwl_write_direct32(priv,
570 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
571 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
573 iwl_write_direct32(priv,
574 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
576 iwl_write_direct32(priv,
577 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
578 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
580 /* FIME: write the MSB of the phy_addr in CTRL1
581 * iwl_write_direct32(priv,
582 IWL_FH_TFDIB_CTRL1_REG(IWL_FH_SRVC_CHNL),
583 ((phy_addr & MSB_MSK)
584 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_count);
586 iwl_write_direct32(priv,
587 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), byte_cnt);
588 iwl_write_direct32(priv,
589 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
590 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
591 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
592 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
594 iwl_write_direct32(priv,
595 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
596 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
597 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL |
598 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
600 iwl_release_nic_access(priv);
601 spin_unlock_irqrestore(&priv->lock, flags);
605 static int iwl5000_load_given_ucode(struct iwl_priv *priv,
606 struct fw_desc *inst_image,
607 struct fw_desc *data_image)
611 ret = iwl5000_load_section(
612 priv, inst_image, RTC_INST_LOWER_BOUND);
616 IWL_DEBUG_INFO("INST uCode section being loaded...\n");
617 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
618 priv->ucode_write_complete, 5 * HZ);
619 if (ret == -ERESTARTSYS) {
620 IWL_ERROR("Could not load the INST uCode section due "
625 IWL_ERROR("Could not load the INST uCode section\n");
629 priv->ucode_write_complete = 0;
631 ret = iwl5000_load_section(
632 priv, data_image, RTC_DATA_LOWER_BOUND);
636 IWL_DEBUG_INFO("DATA uCode section being loaded...\n");
638 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
639 priv->ucode_write_complete, 5 * HZ);
640 if (ret == -ERESTARTSYS) {
641 IWL_ERROR("Could not load the INST uCode section due "
645 IWL_ERROR("Could not load the DATA uCode section\n");
650 priv->ucode_write_complete = 0;
655 static int iwl5000_load_ucode(struct iwl_priv *priv)
659 /* check whether init ucode should be loaded, or rather runtime ucode */
660 if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) {
661 IWL_DEBUG_INFO("Init ucode found. Loading init ucode...\n");
662 ret = iwl5000_load_given_ucode(priv,
663 &priv->ucode_init, &priv->ucode_init_data);
665 IWL_DEBUG_INFO("Init ucode load complete.\n");
666 priv->ucode_type = UCODE_INIT;
669 IWL_DEBUG_INFO("Init ucode not found, or already loaded. "
670 "Loading runtime ucode...\n");
671 ret = iwl5000_load_given_ucode(priv,
672 &priv->ucode_code, &priv->ucode_data);
674 IWL_DEBUG_INFO("Runtime ucode load complete.\n");
675 priv->ucode_type = UCODE_RT;
682 static void iwl5000_init_alive_start(struct iwl_priv *priv)
686 /* Check alive response for "valid" sign from uCode */
687 if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
688 /* We had an error bringing up the hardware, so take it
689 * all the way back down so we can try again */
690 IWL_DEBUG_INFO("Initialize Alive failed.\n");
694 /* initialize uCode was loaded... verify inst image.
695 * This is a paranoid check, because we would not have gotten the
696 * "initialize" alive if code weren't properly loaded. */
697 if (iwl_verify_ucode(priv)) {
698 /* Runtime instruction load was bad;
699 * take it all the way back down so we can try again */
700 IWL_DEBUG_INFO("Bad \"initialize\" uCode load.\n");
704 iwl_clear_stations_table(priv);
705 ret = priv->cfg->ops->lib->alive_notify(priv);
707 IWL_WARNING("Could not complete ALIVE transition: %d\n", ret);
711 iwl5000_send_calib_cfg(priv);
715 /* real restart (first load init_ucode) */
716 queue_work(priv->workqueue, &priv->restart);
719 static void iwl5000_set_wr_ptrs(struct iwl_priv *priv,
720 int txq_id, u32 index)
722 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
723 (index & 0xff) | (txq_id << 8));
724 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index);
727 static void iwl5000_tx_queue_set_status(struct iwl_priv *priv,
728 struct iwl_tx_queue *txq,
729 int tx_fifo_id, int scd_retry)
731 int txq_id = txq->q.id;
732 int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;
734 iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
735 (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
736 (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) |
737 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) |
738 IWL50_SCD_QUEUE_STTS_REG_MSK);
740 txq->sched_retry = scd_retry;
742 IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
743 active ? "Activate" : "Deactivate",
744 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
747 static int iwl5000_send_wimax_coex(struct iwl_priv *priv)
749 struct iwl_wimax_coex_cmd coex_cmd;
751 memset(&coex_cmd, 0, sizeof(coex_cmd));
753 return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD,
754 sizeof(coex_cmd), &coex_cmd);
757 static int iwl5000_alive_notify(struct iwl_priv *priv)
764 spin_lock_irqsave(&priv->lock, flags);
766 ret = iwl_grab_nic_access(priv);
768 spin_unlock_irqrestore(&priv->lock, flags);
772 priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR);
773 a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET;
774 for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET;
776 iwl_write_targ_mem(priv, a, 0);
777 for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET;
779 iwl_write_targ_mem(priv, a, 0);
780 for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
781 iwl_write_targ_mem(priv, a, 0);
783 iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
785 offsetof(struct iwl5000_shared, queues_byte_cnt_tbls)) >> 10);
786 iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
787 IWL50_SCD_QUEUECHAIN_SEL_ALL(
788 priv->hw_params.max_txq_num));
789 iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
791 /* initiate the queues */
792 for (i = 0; i < priv->hw_params.max_txq_num; i++) {
793 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0);
794 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
795 iwl_write_targ_mem(priv, priv->scd_base_addr +
796 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
797 iwl_write_targ_mem(priv, priv->scd_base_addr +
798 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) +
801 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
802 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
804 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
805 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
808 iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK,
809 IWL_MASK(0, priv->hw_params.max_txq_num));
811 /* Activate all Tx DMA/FIFO channels */
812 priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
814 iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
815 /* map qos queues to fifos one-to-one */
816 for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) {
817 int ac = iwl5000_default_queue_to_tx_fifo[i];
818 iwl_txq_ctx_activate(priv, i);
819 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
821 /* TODO - need to initialize those FIFOs inside the loop above,
822 * not only mark them as active */
823 iwl_txq_ctx_activate(priv, 4);
824 iwl_txq_ctx_activate(priv, 7);
825 iwl_txq_ctx_activate(priv, 8);
826 iwl_txq_ctx_activate(priv, 9);
828 iwl_release_nic_access(priv);
829 spin_unlock_irqrestore(&priv->lock, flags);
832 iwl5000_send_wimax_coex(priv);
834 iwl5000_send_Xtal_calib(priv);
836 if (priv->ucode_type == UCODE_RT)
837 iwl5000_send_calib_results(priv);
842 static int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
844 if ((priv->cfg->mod_params->num_of_queues > IWL50_NUM_QUEUES) ||
845 (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
846 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
847 IWL_MIN_NUM_QUEUES, IWL50_NUM_QUEUES);
851 priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
852 priv->hw_params.first_ampdu_q = IWL50_FIRST_AMPDU_QUEUE;
853 priv->hw_params.max_stations = IWL5000_STATION_COUNT;
854 priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID;
855 priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE;
856 priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE;
857 priv->hw_params.max_bsm_size = 0;
858 priv->hw_params.fat_channel = BIT(IEEE80211_BAND_2GHZ) |
859 BIT(IEEE80211_BAND_5GHZ);
860 priv->hw_params.sens = &iwl5000_sensitivity;
862 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
863 case CSR_HW_REV_TYPE_5100:
864 case CSR_HW_REV_TYPE_5150:
865 priv->hw_params.tx_chains_num = 1;
866 priv->hw_params.rx_chains_num = 2;
867 /* FIXME: move to ANT_A, ANT_B, ANT_C enum */
868 priv->hw_params.valid_tx_ant = ANT_A;
869 priv->hw_params.valid_rx_ant = ANT_AB;
871 case CSR_HW_REV_TYPE_5300:
872 case CSR_HW_REV_TYPE_5350:
873 priv->hw_params.tx_chains_num = 3;
874 priv->hw_params.rx_chains_num = 3;
875 priv->hw_params.valid_tx_ant = ANT_ABC;
876 priv->hw_params.valid_rx_ant = ANT_ABC;
880 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
881 case CSR_HW_REV_TYPE_5100:
882 case CSR_HW_REV_TYPE_5300:
883 /* 5X00 wants in Celsius */
884 priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD;
886 case CSR_HW_REV_TYPE_5150:
887 case CSR_HW_REV_TYPE_5350:
888 /* 5X50 wants in Kelvin */
889 priv->hw_params.ct_kill_threshold =
890 CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD);
897 static int iwl5000_alloc_shared_mem(struct iwl_priv *priv)
899 priv->shared_virt = pci_alloc_consistent(priv->pci_dev,
900 sizeof(struct iwl5000_shared),
902 if (!priv->shared_virt)
905 memset(priv->shared_virt, 0, sizeof(struct iwl5000_shared));
907 priv->rb_closed_offset = offsetof(struct iwl5000_shared, rb_closed);
912 static void iwl5000_free_shared_mem(struct iwl_priv *priv)
914 if (priv->shared_virt)
915 pci_free_consistent(priv->pci_dev,
916 sizeof(struct iwl5000_shared),
921 static int iwl5000_shared_mem_rx_idx(struct iwl_priv *priv)
923 struct iwl5000_shared *s = priv->shared_virt;
924 return le32_to_cpu(s->rb_closed) & 0xFFF;
928 * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
930 static void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
931 struct iwl_tx_queue *txq,
934 struct iwl5000_shared *shared_data = priv->shared_virt;
935 int txq_id = txq->q.id;
940 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
942 if (txq_id != IWL_CMD_QUEUE_NUM) {
943 sta = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
944 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
946 switch (sec_ctl & TX_CMD_SEC_MSK) {
950 case TX_CMD_SEC_TKIP:
954 len += WEP_IV_LEN + WEP_ICV_LEN;
959 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
960 tfd_offset[txq->q.write_ptr], byte_cnt, len);
962 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
963 tfd_offset[txq->q.write_ptr], sta_id, sta);
965 if (txq->q.write_ptr < IWL50_MAX_WIN_SIZE) {
966 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
967 tfd_offset[IWL50_QUEUE_SIZE + txq->q.write_ptr],
969 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
970 tfd_offset[IWL50_QUEUE_SIZE + txq->q.write_ptr],
975 static void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
976 struct iwl_tx_queue *txq)
978 int txq_id = txq->q.id;
979 struct iwl5000_shared *shared_data = priv->shared_virt;
982 if (txq_id != IWL_CMD_QUEUE_NUM)
983 sta = txq->cmd[txq->q.read_ptr]->cmd.tx.sta_id;
985 shared_data->queues_byte_cnt_tbls[txq_id].tfd_offset[txq->q.read_ptr].
986 val = cpu_to_le16(1 | (sta << 12));
988 if (txq->q.write_ptr < IWL50_MAX_WIN_SIZE) {
989 shared_data->queues_byte_cnt_tbls[txq_id].
990 tfd_offset[IWL50_QUEUE_SIZE + txq->q.read_ptr].
991 val = cpu_to_le16(1 | (sta << 12));
995 static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
1002 scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
1004 tbl_dw_addr = priv->scd_base_addr +
1005 IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
1007 tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
1010 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
1012 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
1014 iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
1018 static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
1020 /* Simply stop the queue, but don't change any configuration;
1021 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
1022 iwl_write_prph(priv,
1023 IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
1024 (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
1025 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
1028 static int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id,
1029 int tx_fifo, int sta_id, int tid, u16 ssn_idx)
1031 unsigned long flags;
1035 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
1036 (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
1037 IWL_WARNING("queue number out of range: %d, must be %d to %d\n",
1038 txq_id, IWL50_FIRST_AMPDU_QUEUE,
1039 IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1);
1043 ra_tid = BUILD_RAxTID(sta_id, tid);
1045 /* Modify device's station table to Tx this TID */
1046 iwl_sta_modify_enable_tid_tx(priv, sta_id, tid);
1048 spin_lock_irqsave(&priv->lock, flags);
1049 ret = iwl_grab_nic_access(priv);
1051 spin_unlock_irqrestore(&priv->lock, flags);
1055 /* Stop this Tx queue before configuring it */
1056 iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1058 /* Map receiver-address / traffic-ID to this queue */
1059 iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
1061 /* Set this queue as a chain-building queue */
1062 iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id));
1064 /* enable aggregations for the queue */
1065 iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id));
1067 /* Place first TFD at index corresponding to start sequence number.
1068 * Assumes that ssn_idx is valid (!= 0xFFF) */
1069 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1070 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1071 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1073 /* Set up Tx window size and frame limit for this queue */
1074 iwl_write_targ_mem(priv, priv->scd_base_addr +
1075 IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
1078 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1079 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1080 ((SCD_FRAME_LIMIT <<
1081 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1082 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1084 iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1086 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
1087 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
1089 iwl_release_nic_access(priv);
1090 spin_unlock_irqrestore(&priv->lock, flags);
1095 static int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
1096 u16 ssn_idx, u8 tx_fifo)
1100 if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
1101 (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
1102 IWL_WARNING("queue number out of range: %d, must be %d to %d\n",
1103 txq_id, IWL50_FIRST_AMPDU_QUEUE,
1104 IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1);
1108 ret = iwl_grab_nic_access(priv);
1112 iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1114 iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id));
1116 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1117 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1118 /* supposes that ssn_idx is valid (!= 0xFFF) */
1119 iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1121 iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1122 iwl_txq_ctx_deactivate(priv, txq_id);
1123 iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
1125 iwl_release_nic_access(priv);
1130 static u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
1132 u16 size = (u16)sizeof(struct iwl_addsta_cmd);
1133 memcpy(data, cmd, size);
1139 * Activate/Deactivat Tx DMA/FIFO channels according tx fifos mask
1140 * must be called under priv->lock and mac access
1142 static void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask)
1144 iwl_write_prph(priv, IWL50_SCD_TXFACT, mask);
1148 static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp)
1150 return le32_to_cpup((__le32 *)&tx_resp->status +
1151 tx_resp->frame_count) & MAX_SN;
1154 static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv,
1155 struct iwl_ht_agg *agg,
1156 struct iwl5000_tx_resp *tx_resp,
1157 int txq_id, u16 start_idx)
1160 struct agg_tx_status *frame_status = &tx_resp->status;
1161 struct ieee80211_tx_info *info = NULL;
1162 struct ieee80211_hdr *hdr = NULL;
1163 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
1167 if (agg->wait_for_ba)
1168 IWL_DEBUG_TX_REPLY("got tx response w/o block-ack\n");
1170 agg->frame_count = tx_resp->frame_count;
1171 agg->start_idx = start_idx;
1172 agg->rate_n_flags = rate_n_flags;
1175 /* # frames attempted by Tx command */
1176 if (agg->frame_count == 1) {
1177 /* Only one frame was attempted; no block-ack will arrive */
1178 status = le16_to_cpu(frame_status[0].status);
1181 /* FIXME: code repetition */
1182 IWL_DEBUG_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n",
1183 agg->frame_count, agg->start_idx, idx);
1185 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
1186 info->status.retry_count = tx_resp->failure_frame;
1187 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
1188 info->flags |= iwl_is_tx_success(status)?
1189 IEEE80211_TX_STAT_ACK : 0;
1190 iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
1192 /* FIXME: code repetition end */
1194 IWL_DEBUG_TX_REPLY("1 Frame 0x%x failure :%d\n",
1195 status & 0xff, tx_resp->failure_frame);
1196 IWL_DEBUG_TX_REPLY("Rate Info rate_n_flags=%x\n", rate_n_flags);
1198 agg->wait_for_ba = 0;
1200 /* Two or more frames were attempted; expect block-ack */
1202 int start = agg->start_idx;
1204 /* Construct bit-map of pending frames within Tx window */
1205 for (i = 0; i < agg->frame_count; i++) {
1207 status = le16_to_cpu(frame_status[i].status);
1208 seq = le16_to_cpu(frame_status[i].sequence);
1209 idx = SEQ_TO_INDEX(seq);
1210 txq_id = SEQ_TO_QUEUE(seq);
1212 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
1213 AGG_TX_STATE_ABORT_MSK))
1216 IWL_DEBUG_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n",
1217 agg->frame_count, txq_id, idx);
1219 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
1221 sc = le16_to_cpu(hdr->seq_ctrl);
1222 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
1223 IWL_ERROR("BUG_ON idx doesn't match seq control"
1224 " idx=%d, seq_idx=%d, seq=%d\n",
1230 IWL_DEBUG_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n",
1231 i, idx, SEQ_TO_SN(sc));
1235 sh = (start - idx) + 0xff;
1236 bitmap = bitmap << sh;
1239 } else if (sh < -64)
1240 sh = 0xff - (start - idx);
1244 bitmap = bitmap << sh;
1247 bitmap |= 1ULL << sh;
1248 IWL_DEBUG_TX_REPLY("start=%d bitmap=0x%llx\n",
1249 start, (unsigned long long)bitmap);
1252 agg->bitmap = bitmap;
1253 agg->start_idx = start;
1254 IWL_DEBUG_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n",
1255 agg->frame_count, agg->start_idx,
1256 (unsigned long long)agg->bitmap);
1259 agg->wait_for_ba = 1;
1264 static void iwl5000_rx_reply_tx(struct iwl_priv *priv,
1265 struct iwl_rx_mem_buffer *rxb)
1267 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1268 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1269 int txq_id = SEQ_TO_QUEUE(sequence);
1270 int index = SEQ_TO_INDEX(sequence);
1271 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1272 struct ieee80211_tx_info *info;
1273 struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
1274 u32 status = le16_to_cpu(tx_resp->status.status);
1275 int tid = MAX_TID_COUNT, sta_id = IWL_INVALID_STATION;
1276 struct ieee80211_hdr *hdr;
1279 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
1280 IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
1281 "is out of range [0-%d] %d %d\n", txq_id,
1282 index, txq->q.n_bd, txq->q.write_ptr,
1287 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
1288 memset(&info->status, 0, sizeof(info->status));
1290 hdr = iwl_tx_queue_get_hdr(priv, txq_id, index);
1291 if (ieee80211_is_data_qos(hdr->frame_control)) {
1292 qc = ieee80211_get_qos_ctl(hdr);
1296 sta_id = iwl_get_ra_sta_id(priv, hdr);
1297 if (txq->sched_retry && unlikely(sta_id == IWL_INVALID_STATION)) {
1298 IWL_ERROR("Station not known\n");
1302 if (txq->sched_retry) {
1303 const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp);
1304 struct iwl_ht_agg *agg = NULL;
1309 agg = &priv->stations[sta_id].tid[tid].agg;
1311 iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
1313 /* check if BAR is needed */
1314 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
1315 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1317 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
1319 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
1320 IWL_DEBUG_TX_REPLY("Retry scheduler reclaim scd_ssn "
1321 "%d index %d\n", scd_ssn , index);
1322 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1323 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1325 if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
1326 txq_id >= 0 && priv->mac80211_registered &&
1327 agg->state != IWL_EMPTYING_HW_QUEUE_DELBA) {
1328 /* calculate mac80211 ampdu sw queue to wake */
1329 ampdu_q = txq_id - IWL50_FIRST_AMPDU_QUEUE +
1331 if (agg->state == IWL_AGG_OFF)
1332 ieee80211_wake_queue(priv->hw, txq_id);
1334 ieee80211_wake_queue(priv->hw, ampdu_q);
1336 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
1339 info->status.retry_count = tx_resp->failure_frame;
1341 iwl_is_tx_success(status) ? IEEE80211_TX_STAT_ACK : 0;
1342 iwl_hwrate_to_tx_control(priv,
1343 le32_to_cpu(tx_resp->rate_n_flags),
1346 IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) rate_n_flags "
1347 "0x%x retries %d\n", txq_id,
1348 iwl_get_tx_fail_reason(status),
1349 status, le32_to_cpu(tx_resp->rate_n_flags),
1350 tx_resp->failure_frame);
1352 IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
1354 int freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1355 if (tid != MAX_TID_COUNT)
1356 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1357 if (iwl_queue_space(&txq->q) > txq->q.low_mark &&
1358 (txq_id >= 0) && priv->mac80211_registered)
1359 ieee80211_wake_queue(priv->hw, txq_id);
1360 if (tid != MAX_TID_COUNT)
1361 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
1365 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
1366 IWL_ERROR("TODO: Implement Tx ABORT REQUIRED!!!\n");
1369 /* Currently 5000 is the supperset of everything */
1370 static u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len)
1375 static void iwl5000_setup_deferred_work(struct iwl_priv *priv)
1377 /* in 5000 the tx power calibration is done in uCode */
1378 priv->disable_tx_power_cal = 1;
1381 static void iwl5000_rx_handler_setup(struct iwl_priv *priv)
1383 /* init calibration handlers */
1384 priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
1385 iwl5000_rx_calib_result;
1386 priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
1387 iwl5000_rx_calib_complete;
1388 priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx;
1392 static int iwl5000_hw_valid_rtc_data_addr(u32 addr)
1394 return (addr >= RTC_DATA_LOWER_BOUND) &&
1395 (addr < IWL50_RTC_DATA_UPPER_BOUND);
1398 static int iwl5000_send_rxon_assoc(struct iwl_priv *priv)
1401 struct iwl5000_rxon_assoc_cmd rxon_assoc;
1402 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1403 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1405 if ((rxon1->flags == rxon2->flags) &&
1406 (rxon1->filter_flags == rxon2->filter_flags) &&
1407 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1408 (rxon1->ofdm_ht_single_stream_basic_rates ==
1409 rxon2->ofdm_ht_single_stream_basic_rates) &&
1410 (rxon1->ofdm_ht_dual_stream_basic_rates ==
1411 rxon2->ofdm_ht_dual_stream_basic_rates) &&
1412 (rxon1->ofdm_ht_triple_stream_basic_rates ==
1413 rxon2->ofdm_ht_triple_stream_basic_rates) &&
1414 (rxon1->acquisition_data == rxon2->acquisition_data) &&
1415 (rxon1->rx_chain == rxon2->rx_chain) &&
1416 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1417 IWL_DEBUG_INFO("Using current RXON_ASSOC. Not resending.\n");
1421 rxon_assoc.flags = priv->staging_rxon.flags;
1422 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1423 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1424 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1425 rxon_assoc.reserved1 = 0;
1426 rxon_assoc.reserved2 = 0;
1427 rxon_assoc.reserved3 = 0;
1428 rxon_assoc.ofdm_ht_single_stream_basic_rates =
1429 priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1430 rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1431 priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1432 rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1433 rxon_assoc.ofdm_ht_triple_stream_basic_rates =
1434 priv->staging_rxon.ofdm_ht_triple_stream_basic_rates;
1435 rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data;
1437 ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1438 sizeof(rxon_assoc), &rxon_assoc, NULL);
1444 static int iwl5000_send_tx_power(struct iwl_priv *priv)
1446 struct iwl5000_tx_power_dbm_cmd tx_power_cmd;
1448 /* half dBm need to multiply */
1449 tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
1450 tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED;
1451 tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO;
1452 return iwl_send_cmd_pdu_async(priv, REPLY_TX_POWER_DBM_CMD,
1453 sizeof(tx_power_cmd), &tx_power_cmd,
1457 static void iwl5000_temperature(struct iwl_priv *priv)
1459 /* store temperature from statistics (in Celsius) */
1460 priv->temperature = le32_to_cpu(priv->statistics.general.temperature);
1463 /* Calc max signal level (dBm) among 3 possible receivers */
1464 static int iwl5000_calc_rssi(struct iwl_priv *priv,
1465 struct iwl_rx_phy_res *rx_resp)
1467 /* data from PHY/DSP regarding signal strength, etc.,
1468 * contents are always there, not configurable by host
1470 struct iwl5000_non_cfg_phy *ncphy =
1471 (struct iwl5000_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
1472 u32 val, rssi_a, rssi_b, rssi_c, max_rssi;
1475 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_AGC_IDX]);
1476 agc = (val & IWL50_OFDM_AGC_MSK) >> IWL50_OFDM_AGC_BIT_POS;
1478 /* Find max rssi among 3 possible receivers.
1479 * These values are measured by the digital signal processor (DSP).
1480 * They should stay fairly constant even as the signal strength varies,
1481 * if the radio's automatic gain control (AGC) is working right.
1482 * AGC value (see below) will provide the "interesting" info.
1484 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_AB_IDX]);
1485 rssi_a = (val & IWL50_OFDM_RSSI_A_MSK) >> IWL50_OFDM_RSSI_A_BIT_POS;
1486 rssi_b = (val & IWL50_OFDM_RSSI_B_MSK) >> IWL50_OFDM_RSSI_B_BIT_POS;
1487 val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_C_IDX]);
1488 rssi_c = (val & IWL50_OFDM_RSSI_C_MSK) >> IWL50_OFDM_RSSI_C_BIT_POS;
1490 max_rssi = max_t(u32, rssi_a, rssi_b);
1491 max_rssi = max_t(u32, max_rssi, rssi_c);
1493 IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
1494 rssi_a, rssi_b, rssi_c, max_rssi, agc);
1496 /* dBm = max_rssi dB - agc dB - constant.
1497 * Higher AGC (higher radio gain) means lower signal. */
1498 return max_rssi - agc - IWL_RSSI_OFFSET;
1501 static struct iwl_hcmd_ops iwl5000_hcmd = {
1502 .rxon_assoc = iwl5000_send_rxon_assoc,
1505 static struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = {
1506 .get_hcmd_size = iwl5000_get_hcmd_size,
1507 .build_addsta_hcmd = iwl5000_build_addsta_hcmd,
1508 .gain_computation = iwl5000_gain_computation,
1509 .chain_noise_reset = iwl5000_chain_noise_reset,
1510 .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag,
1511 .calc_rssi = iwl5000_calc_rssi,
1514 static struct iwl_lib_ops iwl5000_lib = {
1515 .set_hw_params = iwl5000_hw_set_hw_params,
1516 .alloc_shared_mem = iwl5000_alloc_shared_mem,
1517 .free_shared_mem = iwl5000_free_shared_mem,
1518 .shared_mem_rx_idx = iwl5000_shared_mem_rx_idx,
1519 .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1520 .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1521 .txq_set_sched = iwl5000_txq_set_sched,
1522 .txq_agg_enable = iwl5000_txq_agg_enable,
1523 .txq_agg_disable = iwl5000_txq_agg_disable,
1524 .rx_handler_setup = iwl5000_rx_handler_setup,
1525 .setup_deferred_work = iwl5000_setup_deferred_work,
1526 .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
1527 .load_ucode = iwl5000_load_ucode,
1528 .init_alive_start = iwl5000_init_alive_start,
1529 .alive_notify = iwl5000_alive_notify,
1530 .send_tx_power = iwl5000_send_tx_power,
1531 .temperature = iwl5000_temperature,
1532 .update_chain_flags = iwl4965_update_chain_flags,
1534 .init = iwl5000_apm_init,
1535 .reset = iwl5000_apm_reset,
1536 .stop = iwl5000_apm_stop,
1537 .config = iwl5000_nic_config,
1538 .set_pwr_src = iwl4965_set_pwr_src,
1541 .regulatory_bands = {
1542 EEPROM_5000_REG_BAND_1_CHANNELS,
1543 EEPROM_5000_REG_BAND_2_CHANNELS,
1544 EEPROM_5000_REG_BAND_3_CHANNELS,
1545 EEPROM_5000_REG_BAND_4_CHANNELS,
1546 EEPROM_5000_REG_BAND_5_CHANNELS,
1547 EEPROM_5000_REG_BAND_24_FAT_CHANNELS,
1548 EEPROM_5000_REG_BAND_52_FAT_CHANNELS
1550 .verify_signature = iwlcore_eeprom_verify_signature,
1551 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1552 .release_semaphore = iwlcore_eeprom_release_semaphore,
1553 .check_version = iwl5000_eeprom_check_version,
1554 .query_addr = iwl5000_eeprom_query_addr,
1558 static struct iwl_ops iwl5000_ops = {
1559 .lib = &iwl5000_lib,
1560 .hcmd = &iwl5000_hcmd,
1561 .utils = &iwl5000_hcmd_utils,
1564 static struct iwl_mod_params iwl50_mod_params = {
1565 .num_of_queues = IWL50_NUM_QUEUES,
1566 .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1570 /* the rest are 0 by default */
1574 struct iwl_cfg iwl5300_agn_cfg = {
1576 .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
1577 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1578 .ops = &iwl5000_ops,
1579 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1580 .mod_params = &iwl50_mod_params,
1583 struct iwl_cfg iwl5100_bg_cfg = {
1585 .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
1587 .ops = &iwl5000_ops,
1588 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1589 .mod_params = &iwl50_mod_params,
1592 struct iwl_cfg iwl5100_abg_cfg = {
1594 .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
1595 .sku = IWL_SKU_A|IWL_SKU_G,
1596 .ops = &iwl5000_ops,
1597 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1598 .mod_params = &iwl50_mod_params,
1601 struct iwl_cfg iwl5100_agn_cfg = {
1603 .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
1604 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1605 .ops = &iwl5000_ops,
1606 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1607 .mod_params = &iwl50_mod_params,
1610 struct iwl_cfg iwl5350_agn_cfg = {
1612 .fw_name = "iwlwifi-5000" IWL5000_UCODE_API ".ucode",
1613 .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1614 .ops = &iwl5000_ops,
1615 .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1616 .mod_params = &iwl50_mod_params,
1619 module_param_named(disable50, iwl50_mod_params.disable, int, 0444);
1620 MODULE_PARM_DESC(disable50,
1621 "manually disable the 50XX radio (default 0 [radio on])");
1622 module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, 0444);
1623 MODULE_PARM_DESC(swcrypto50,
1624 "using software crypto engine (default 0 [hardware])\n");
1625 module_param_named(debug50, iwl50_mod_params.debug, int, 0444);
1626 MODULE_PARM_DESC(debug50, "50XX debug output mask");
1627 module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, 0444);
1628 MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series");
1629 module_param_named(qos_enable50, iwl50_mod_params.enable_qos, int, 0444);
1630 MODULE_PARM_DESC(qos_enable50, "enable all 50XX QoS functionality");
1631 module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, 0444);
1632 MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality");
1633 module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K, int, 0444);
1634 MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series");
1635 module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, 0444);
1636 MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error");