git.oblomov.eu Git - linux-2.6/blob - drivers/infiniband/hw/mthca/mthca_cq.c

   1 /*
   2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
   4  * Copyright (c) 2005 Cisco Systems, Inc. All rights reserved.
   5  * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
   6  * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
   7  *
   8  * This software is available to you under a choice of one of two
   9  * licenses.  You may choose to be licensed under the terms of the GNU
  10  * General Public License (GPL) Version 2, available from the file
  11  * COPYING in the main directory of this source tree, or the
  12  * OpenIB.org BSD license below:
  13  *
  14  *     Redistribution and use in source and binary forms, with or
  15  *     without modification, are permitted provided that the following
  16  *     conditions are met:
  17  *
  18  *      - Redistributions of source code must retain the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer.
  21  *
  22  *      - Redistributions in binary form must reproduce the above
  23  *        copyright notice, this list of conditions and the following
  24  *        disclaimer in the documentation and/or other materials
  25  *        provided with the distribution.
  26  *
  27  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  28  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  29  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  30  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  31  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  32  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  33  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  34  * SOFTWARE.
  35  *
  36  * $Id: mthca_cq.c 1369 2004-12-20 16:17:07Z roland $
  37  */
  38
  39 #include <linux/init.h>
  40 #include <linux/hardirq.h>
  41
  42 #include <rdma/ib_pack.h>
  43
  44 #include "mthca_dev.h"
  45 #include "mthca_cmd.h"
  46 #include "mthca_memfree.h"
  47
  48 enum {
  49         MTHCA_MAX_DIRECT_CQ_SIZE = 4 * PAGE_SIZE
  50 };
  51
  52 enum {
  53         MTHCA_CQ_ENTRY_SIZE = 0x20
  54 };
  55
  56 /*
  57  * Must be packed because start is 64 bits but only aligned to 32 bits.
  58  */
  59 struct mthca_cq_context {
  60         __be32 flags;
  61         __be64 start;
  62         __be32 logsize_usrpage;
  63         __be32 error_eqn;       /* Tavor only */
  64         __be32 comp_eqn;
  65         __be32 pd;
  66         __be32 lkey;
  67         __be32 last_notified_index;
  68         __be32 solicit_producer_index;
  69         __be32 consumer_index;
  70         __be32 producer_index;
  71         __be32 cqn;
  72         __be32 ci_db;           /* Arbel only */
  73         __be32 state_db;        /* Arbel only */
  74         u32    reserved;
  75 } __attribute__((packed));
  76
  77 #define MTHCA_CQ_STATUS_OK          ( 0 << 28)
  78 #define MTHCA_CQ_STATUS_OVERFLOW    ( 9 << 28)
  79 #define MTHCA_CQ_STATUS_WRITE_FAIL  (10 << 28)
  80 #define MTHCA_CQ_FLAG_TR            ( 1 << 18)
  81 #define MTHCA_CQ_FLAG_OI            ( 1 << 17)
  82 #define MTHCA_CQ_STATE_DISARMED     ( 0 <<  8)
  83 #define MTHCA_CQ_STATE_ARMED        ( 1 <<  8)
  84 #define MTHCA_CQ_STATE_ARMED_SOL    ( 4 <<  8)
  85 #define MTHCA_EQ_STATE_FIRED        (10 <<  8)
  86
  87 enum {
  88         MTHCA_ERROR_CQE_OPCODE_MASK = 0xfe
  89 };
  90
  91 enum {
  92         SYNDROME_LOCAL_LENGTH_ERR        = 0x01,
  93         SYNDROME_LOCAL_QP_OP_ERR         = 0x02,
  94         SYNDROME_LOCAL_EEC_OP_ERR        = 0x03,
  95         SYNDROME_LOCAL_PROT_ERR          = 0x04,
  96         SYNDROME_WR_FLUSH_ERR            = 0x05,
  97         SYNDROME_MW_BIND_ERR             = 0x06,
  98         SYNDROME_BAD_RESP_ERR            = 0x10,
  99         SYNDROME_LOCAL_ACCESS_ERR        = 0x11,
 100         SYNDROME_REMOTE_INVAL_REQ_ERR    = 0x12,
 101         SYNDROME_REMOTE_ACCESS_ERR       = 0x13,
 102         SYNDROME_REMOTE_OP_ERR           = 0x14,
 103         SYNDROME_RETRY_EXC_ERR           = 0x15,
 104         SYNDROME_RNR_RETRY_EXC_ERR       = 0x16,
 105         SYNDROME_LOCAL_RDD_VIOL_ERR      = 0x20,
 106         SYNDROME_REMOTE_INVAL_RD_REQ_ERR = 0x21,
 107         SYNDROME_REMOTE_ABORTED_ERR      = 0x22,
 108         SYNDROME_INVAL_EECN_ERR          = 0x23,
 109         SYNDROME_INVAL_EEC_STATE_ERR     = 0x24
 110 };
 111
 112 struct mthca_cqe {
 113         __be32 my_qpn;
 114         __be32 my_ee;
 115         __be32 rqpn;
 116         __be16 sl_g_mlpath;
 117         __be16 rlid;
 118         __be32 imm_etype_pkey_eec;
 119         __be32 byte_cnt;
 120         __be32 wqe;
 121         u8     opcode;
 122         u8     is_send;
 123         u8     reserved;
 124         u8     owner;
 125 };
 126
 127 struct mthca_err_cqe {
 128         __be32 my_qpn;
 129         u32    reserved1[3];
 130         u8     syndrome;
 131         u8     reserved2;
 132         __be16 db_cnt;
 133         u32    reserved3;
 134         __be32 wqe;
 135         u8     opcode;
 136         u8     reserved4[2];
 137         u8     owner;
 138 };
 139
 140 #define MTHCA_CQ_ENTRY_OWNER_SW      (0 << 7)
 141 #define MTHCA_CQ_ENTRY_OWNER_HW      (1 << 7)
 142
 143 #define MTHCA_TAVOR_CQ_DB_INC_CI       (1 << 24)
 144 #define MTHCA_TAVOR_CQ_DB_REQ_NOT      (2 << 24)
 145 #define MTHCA_TAVOR_CQ_DB_REQ_NOT_SOL  (3 << 24)
 146 #define MTHCA_TAVOR_CQ_DB_SET_CI       (4 << 24)
 147 #define MTHCA_TAVOR_CQ_DB_REQ_NOT_MULT (5 << 24)
 148
 149 #define MTHCA_ARBEL_CQ_DB_REQ_NOT_SOL  (1 << 24)
 150 #define MTHCA_ARBEL_CQ_DB_REQ_NOT      (2 << 24)
 151 #define MTHCA_ARBEL_CQ_DB_REQ_NOT_MULT (3 << 24)
 152
 153 static inline struct mthca_cqe *get_cqe(struct mthca_cq *cq, int entry)
 154 {
 155         if (cq->is_direct)
 156                 return cq->queue.direct.buf + (entry * MTHCA_CQ_ENTRY_SIZE);
 157         else
 158                 return cq->queue.page_list[entry * MTHCA_CQ_ENTRY_SIZE / PAGE_SIZE].buf
 159                         + (entry * MTHCA_CQ_ENTRY_SIZE) % PAGE_SIZE;
 160 }
 161
 162 static inline struct mthca_cqe *cqe_sw(struct mthca_cq *cq, int i)
 163 {
 164         struct mthca_cqe *cqe = get_cqe(cq, i);
 165         return MTHCA_CQ_ENTRY_OWNER_HW & cqe->owner ? NULL : cqe;
 166 }
 167
 168 static inline struct mthca_cqe *next_cqe_sw(struct mthca_cq *cq)
 169 {
 170         return cqe_sw(cq, cq->cons_index & cq->ibcq.cqe);
 171 }
 172
 173 static inline void set_cqe_hw(struct mthca_cqe *cqe)
 174 {
 175         cqe->owner = MTHCA_CQ_ENTRY_OWNER_HW;
 176 }
 177
 178 static void dump_cqe(struct mthca_dev *dev, void *cqe_ptr)
 179 {
 180         __be32 *cqe = cqe_ptr;
 181
 182         (void) cqe;     /* avoid warning if mthca_dbg compiled away... */
 183         mthca_dbg(dev, "CQE contents %08x %08x %08x %08x %08x %08x %08x %08x\n",
 184                   be32_to_cpu(cqe[0]), be32_to_cpu(cqe[1]), be32_to_cpu(cqe[2]),
 185                   be32_to_cpu(cqe[3]), be32_to_cpu(cqe[4]), be32_to_cpu(cqe[5]),
 186                   be32_to_cpu(cqe[6]), be32_to_cpu(cqe[7]));
 187 }
 188
 189 /*
 190  * incr is ignored in native Arbel (mem-free) mode, so cq->cons_index
 191  * should be correct before calling update_cons_index().
 192  */
 193 static inline void update_cons_index(struct mthca_dev *dev, struct mthca_cq *cq,
 194                                      int incr)
 195 {
 196         __be32 doorbell[2];
 197
 198         if (mthca_is_memfree(dev)) {
 199                 *cq->set_ci_db = cpu_to_be32(cq->cons_index);
 200                 wmb();
 201         } else {
 202                 doorbell[0] = cpu_to_be32(MTHCA_TAVOR_CQ_DB_INC_CI | cq->cqn);
 203                 doorbell[1] = cpu_to_be32(incr - 1);
 204
 205                 mthca_write64(doorbell,
 206                               dev->kar + MTHCA_CQ_DOORBELL,
 207                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
 208         }
 209 }
 210
 211 void mthca_cq_completion(struct mthca_dev *dev, u32 cqn)
 212 {
 213         struct mthca_cq *cq;
 214
 215         cq = mthca_array_get(&dev->cq_table.cq, cqn & (dev->limits.num_cqs - 1));
 216
 217         if (!cq) {
 218                 mthca_warn(dev, "Completion event for bogus CQ %08x\n", cqn);
 219                 return;
 220         }
 221
 222         ++cq->arm_sn;
 223
 224         cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context);
 225 }
 226
 227 void mthca_cq_event(struct mthca_dev *dev, u32 cqn,
 228                     enum ib_event_type event_type)
 229 {
 230         struct mthca_cq *cq;
 231         struct ib_event event;
 232
 233         spin_lock(&dev->cq_table.lock);
 234
 235         cq = mthca_array_get(&dev->cq_table.cq, cqn & (dev->limits.num_cqs - 1));
 236
 237         if (cq)
 238                 atomic_inc(&cq->refcount);
 239         spin_unlock(&dev->cq_table.lock);
 240
 241         if (!cq) {
 242                 mthca_warn(dev, "Async event for bogus CQ %08x\n", cqn);
 243                 return;
 244         }
 245
 246         event.device      = &dev->ib_dev;
 247         event.event       = event_type;
 248         event.element.cq  = &cq->ibcq;
 249         if (cq->ibcq.event_handler)
 250                 cq->ibcq.event_handler(&event, cq->ibcq.cq_context);
 251
 252         if (atomic_dec_and_test(&cq->refcount))
 253                 wake_up(&cq->wait);
 254 }
 255
 256 void mthca_cq_clean(struct mthca_dev *dev, u32 cqn, u32 qpn,
 257                     struct mthca_srq *srq)
 258 {
 259         struct mthca_cq *cq;
 260         struct mthca_cqe *cqe;
 261         int prod_index;
 262         int nfreed = 0;
 263
 264         spin_lock_irq(&dev->cq_table.lock);
 265         cq = mthca_array_get(&dev->cq_table.cq, cqn & (dev->limits.num_cqs - 1));
 266         if (cq)
 267                 atomic_inc(&cq->refcount);
 268         spin_unlock_irq(&dev->cq_table.lock);
 269
 270         if (!cq)
 271                 return;
 272
 273         spin_lock_irq(&cq->lock);
 274
 275         /*
 276          * First we need to find the current producer index, so we
 277          * know where to start cleaning from.  It doesn't matter if HW
 278          * adds new entries after this loop -- the QP we're worried
 279          * about is already in RESET, so the new entries won't come
 280          * from our QP and therefore don't need to be checked.
 281          */
 282         for (prod_index = cq->cons_index;
 283              cqe_sw(cq, prod_index & cq->ibcq.cqe);
 284              ++prod_index)
 285                 if (prod_index == cq->cons_index + cq->ibcq.cqe)
 286                         break;
 287
 288         if (0)
 289                 mthca_dbg(dev, "Cleaning QPN %06x from CQN %06x; ci %d, pi %d\n",
 290                           qpn, cqn, cq->cons_index, prod_index);
 291
 292         /*
 293          * Now sweep backwards through the CQ, removing CQ entries
 294          * that match our QP by copying older entries on top of them.
 295          */
 296         while (prod_index > cq->cons_index) {
 297                 cqe = get_cqe(cq, (prod_index - 1) & cq->ibcq.cqe);
 298                 if (cqe->my_qpn == cpu_to_be32(qpn)) {
 299                         if (srq)
 300                                 mthca_free_srq_wqe(srq, be32_to_cpu(cqe->wqe));
 301                         ++nfreed;
 302                 }
 303                 else if (nfreed)
 304                         memcpy(get_cqe(cq, (prod_index - 1 + nfreed) &
 305                                        cq->ibcq.cqe),
 306                                cqe,
 307                                MTHCA_CQ_ENTRY_SIZE);
 308                 --prod_index;
 309         }
 310
 311         if (nfreed) {
 312                 wmb();
 313                 cq->cons_index += nfreed;
 314                 update_cons_index(dev, cq, nfreed);
 315         }
 316
 317         spin_unlock_irq(&cq->lock);
 318         if (atomic_dec_and_test(&cq->refcount))
 319                 wake_up(&cq->wait);
 320 }
 321
 322 static int handle_error_cqe(struct mthca_dev *dev, struct mthca_cq *cq,
 323                             struct mthca_qp *qp, int wqe_index, int is_send,
 324                             struct mthca_err_cqe *cqe,
 325                             struct ib_wc *entry, int *free_cqe)
 326 {
 327         int err;
 328         int dbd;
 329         __be32 new_wqe;
 330
 331         if (cqe->syndrome == SYNDROME_LOCAL_QP_OP_ERR) {
 332                 mthca_dbg(dev, "local QP operation err "
 333                           "(QPN %06x, WQE @ %08x, CQN %06x, index %d)\n",
 334                           be32_to_cpu(cqe->my_qpn), be32_to_cpu(cqe->wqe),
 335                           cq->cqn, cq->cons_index);
 336                 dump_cqe(dev, cqe);
 337         }
 338
 339         /*
 340          * For completions in error, only work request ID, status (and
 341          * freed resource count for RD) have to be set.
 342          */
 343         switch (cqe->syndrome) {
 344         case SYNDROME_LOCAL_LENGTH_ERR:
 345                 entry->status = IB_WC_LOC_LEN_ERR;
 346                 break;
 347         case SYNDROME_LOCAL_QP_OP_ERR:
 348                 entry->status = IB_WC_LOC_QP_OP_ERR;
 349                 break;
 350         case SYNDROME_LOCAL_EEC_OP_ERR:
 351                 entry->status = IB_WC_LOC_EEC_OP_ERR;
 352                 break;
 353         case SYNDROME_LOCAL_PROT_ERR:
 354                 entry->status = IB_WC_LOC_PROT_ERR;
 355                 break;
 356         case SYNDROME_WR_FLUSH_ERR:
 357                 entry->status = IB_WC_WR_FLUSH_ERR;
 358                 break;
 359         case SYNDROME_MW_BIND_ERR:
 360                 entry->status = IB_WC_MW_BIND_ERR;
 361                 break;
 362         case SYNDROME_BAD_RESP_ERR:
 363                 entry->status = IB_WC_BAD_RESP_ERR;
 364                 break;
 365         case SYNDROME_LOCAL_ACCESS_ERR:
 366                 entry->status = IB_WC_LOC_ACCESS_ERR;
 367                 break;
 368         case SYNDROME_REMOTE_INVAL_REQ_ERR:
 369                 entry->status = IB_WC_REM_INV_REQ_ERR;
 370                 break;
 371         case SYNDROME_REMOTE_ACCESS_ERR:
 372                 entry->status = IB_WC_REM_ACCESS_ERR;
 373                 break;
 374         case SYNDROME_REMOTE_OP_ERR:
 375                 entry->status = IB_WC_REM_OP_ERR;
 376                 break;
 377         case SYNDROME_RETRY_EXC_ERR:
 378                 entry->status = IB_WC_RETRY_EXC_ERR;
 379                 break;
 380         case SYNDROME_RNR_RETRY_EXC_ERR:
 381                 entry->status = IB_WC_RNR_RETRY_EXC_ERR;
 382                 break;
 383         case SYNDROME_LOCAL_RDD_VIOL_ERR:
 384                 entry->status = IB_WC_LOC_RDD_VIOL_ERR;
 385                 break;
 386         case SYNDROME_REMOTE_INVAL_RD_REQ_ERR:
 387                 entry->status = IB_WC_REM_INV_RD_REQ_ERR;
 388                 break;
 389         case SYNDROME_REMOTE_ABORTED_ERR:
 390                 entry->status = IB_WC_REM_ABORT_ERR;
 391                 break;
 392         case SYNDROME_INVAL_EECN_ERR:
 393                 entry->status = IB_WC_INV_EECN_ERR;
 394                 break;
 395         case SYNDROME_INVAL_EEC_STATE_ERR:
 396                 entry->status = IB_WC_INV_EEC_STATE_ERR;
 397                 break;
 398         default:
 399                 entry->status = IB_WC_GENERAL_ERR;
 400                 break;
 401         }
 402
 403         /*
 404          * Mem-free HCAs always generate one CQE per WQE, even in the
 405          * error case, so we don't have to check the doorbell count, etc.
 406          */
 407         if (mthca_is_memfree(dev))
 408                 return 0;
 409
 410         err = mthca_free_err_wqe(dev, qp, is_send, wqe_index, &dbd, &new_wqe);
 411         if (err)
 412                 return err;
 413
 414         /*
 415          * If we're at the end of the WQE chain, or we've used up our
 416          * doorbell count, free the CQE.  Otherwise just update it for
 417          * the next poll operation.
 418          */
 419         if (!(new_wqe & cpu_to_be32(0x3f)) || (!cqe->db_cnt && dbd))
 420                 return 0;
 421
 422         cqe->db_cnt   = cpu_to_be16(be16_to_cpu(cqe->db_cnt) - dbd);
 423         cqe->wqe      = new_wqe;
 424         cqe->syndrome = SYNDROME_WR_FLUSH_ERR;
 425
 426         *free_cqe = 0;
 427
 428         return 0;
 429 }
 430
 431 static inline int mthca_poll_one(struct mthca_dev *dev,
 432                                  struct mthca_cq *cq,
 433                                  struct mthca_qp **cur_qp,
 434                                  int *freed,
 435                                  struct ib_wc *entry)
 436 {
 437         struct mthca_wq *wq;
 438         struct mthca_cqe *cqe;
 439         int wqe_index;
 440         int is_error;
 441         int is_send;
 442         int free_cqe = 1;
 443         int err = 0;
 444
 445         cqe = next_cqe_sw(cq);
 446         if (!cqe)
 447                 return -EAGAIN;
 448
 449         /*
 450          * Make sure we read CQ entry contents after we've checked the
 451          * ownership bit.
 452          */
 453         rmb();
 454
 455         if (0) {
 456                 mthca_dbg(dev, "%x/%d: CQE -> QPN %06x, WQE @ %08x\n",
 457                           cq->cqn, cq->cons_index, be32_to_cpu(cqe->my_qpn),
 458                           be32_to_cpu(cqe->wqe));
 459                 dump_cqe(dev, cqe);
 460         }
 461
 462         is_error = (cqe->opcode & MTHCA_ERROR_CQE_OPCODE_MASK) ==
 463                 MTHCA_ERROR_CQE_OPCODE_MASK;
 464         is_send  = is_error ? cqe->opcode & 0x01 : cqe->is_send & 0x80;
 465
 466         if (!*cur_qp || be32_to_cpu(cqe->my_qpn) != (*cur_qp)->qpn) {
 467                 /*
 468                  * We do not have to take the QP table lock here,
 469                  * because CQs will be locked while QPs are removed
 470                  * from the table.
 471                  */
 472                 *cur_qp = mthca_array_get(&dev->qp_table.qp,
 473                                           be32_to_cpu(cqe->my_qpn) &
 474                                           (dev->limits.num_qps - 1));
 475                 if (!*cur_qp) {
 476                         mthca_warn(dev, "CQ entry for unknown QP %06x\n",
 477                                    be32_to_cpu(cqe->my_qpn) & 0xffffff);
 478                         err = -EINVAL;
 479                         goto out;
 480                 }
 481         }
 482
 483         entry->qp_num = (*cur_qp)->qpn;
 484
 485         if (is_send) {
 486                 wq = &(*cur_qp)->sq;
 487                 wqe_index = ((be32_to_cpu(cqe->wqe) - (*cur_qp)->send_wqe_offset)
 488                              >> wq->wqe_shift);
 489                 entry->wr_id = (*cur_qp)->wrid[wqe_index +
 490                                                (*cur_qp)->rq.max];
 491         } else if ((*cur_qp)->ibqp.srq) {
 492                 struct mthca_srq *srq = to_msrq((*cur_qp)->ibqp.srq);
 493                 u32 wqe = be32_to_cpu(cqe->wqe);
 494                 wq = NULL;
 495                 wqe_index = wqe >> srq->wqe_shift;
 496                 entry->wr_id = srq->wrid[wqe_index];
 497                 mthca_free_srq_wqe(srq, wqe);
 498         } else {
 499                 wq = &(*cur_qp)->rq;
 500                 wqe_index = be32_to_cpu(cqe->wqe) >> wq->wqe_shift;
 501                 entry->wr_id = (*cur_qp)->wrid[wqe_index];
 502         }
 503
 504         if (wq) {
 505                 if (wq->last_comp < wqe_index)
 506                         wq->tail += wqe_index - wq->last_comp;
 507                 else
 508                         wq->tail += wqe_index + wq->max - wq->last_comp;
 509
 510                 wq->last_comp = wqe_index;
 511         }
 512
 513         if (is_error) {
 514                 err = handle_error_cqe(dev, cq, *cur_qp, wqe_index, is_send,
 515                                        (struct mthca_err_cqe *) cqe,
 516                                        entry, &free_cqe);
 517                 goto out;
 518         }
 519
 520         if (is_send) {
 521                 entry->wc_flags = 0;
 522                 switch (cqe->opcode) {
 523                 case MTHCA_OPCODE_RDMA_WRITE:
 524                         entry->opcode    = IB_WC_RDMA_WRITE;
 525                         break;
 526                 case MTHCA_OPCODE_RDMA_WRITE_IMM:
 527                         entry->opcode    = IB_WC_RDMA_WRITE;
 528                         entry->wc_flags |= IB_WC_WITH_IMM;
 529                         break;
 530                 case MTHCA_OPCODE_SEND:
 531                         entry->opcode    = IB_WC_SEND;
 532                         break;
 533                 case MTHCA_OPCODE_SEND_IMM:
 534                         entry->opcode    = IB_WC_SEND;
 535                         entry->wc_flags |= IB_WC_WITH_IMM;
 536                         break;
 537                 case MTHCA_OPCODE_RDMA_READ:
 538                         entry->opcode    = IB_WC_RDMA_READ;
 539                         entry->byte_len  = be32_to_cpu(cqe->byte_cnt);
 540                         break;
 541                 case MTHCA_OPCODE_ATOMIC_CS:
 542                         entry->opcode    = IB_WC_COMP_SWAP;
 543                         entry->byte_len  = be32_to_cpu(cqe->byte_cnt);
 544                         break;
 545                 case MTHCA_OPCODE_ATOMIC_FA:
 546                         entry->opcode    = IB_WC_FETCH_ADD;
 547                         entry->byte_len  = be32_to_cpu(cqe->byte_cnt);
 548                         break;
 549                 case MTHCA_OPCODE_BIND_MW:
 550                         entry->opcode    = IB_WC_BIND_MW;
 551                         break;
 552                 default:
 553                         entry->opcode    = MTHCA_OPCODE_INVALID;
 554                         break;
 555                 }
 556         } else {
 557                 entry->byte_len = be32_to_cpu(cqe->byte_cnt);
 558                 switch (cqe->opcode & 0x1f) {
 559                 case IB_OPCODE_SEND_LAST_WITH_IMMEDIATE:
 560                 case IB_OPCODE_SEND_ONLY_WITH_IMMEDIATE:
 561                         entry->wc_flags = IB_WC_WITH_IMM;
 562                         entry->imm_data = cqe->imm_etype_pkey_eec;
 563                         entry->opcode = IB_WC_RECV;
 564                         break;
 565                 case IB_OPCODE_RDMA_WRITE_LAST_WITH_IMMEDIATE:
 566                 case IB_OPCODE_RDMA_WRITE_ONLY_WITH_IMMEDIATE:
 567                         entry->wc_flags = IB_WC_WITH_IMM;
 568                         entry->imm_data = cqe->imm_etype_pkey_eec;
 569                         entry->opcode = IB_WC_RECV_RDMA_WITH_IMM;
 570                         break;
 571                 default:
 572                         entry->wc_flags = 0;
 573                         entry->opcode = IB_WC_RECV;
 574                         break;
 575                 }
 576                 entry->slid        = be16_to_cpu(cqe->rlid);
 577                 entry->sl          = be16_to_cpu(cqe->sl_g_mlpath) >> 12;
 578                 entry->src_qp      = be32_to_cpu(cqe->rqpn) & 0xffffff;
 579                 entry->dlid_path_bits = be16_to_cpu(cqe->sl_g_mlpath) & 0x7f;
 580                 entry->pkey_index  = be32_to_cpu(cqe->imm_etype_pkey_eec) >> 16;
 581                 entry->wc_flags   |= be16_to_cpu(cqe->sl_g_mlpath) & 0x80 ?
 582                                         IB_WC_GRH : 0;
 583         }
 584
 585         entry->status = IB_WC_SUCCESS;
 586
 587  out:
 588         if (likely(free_cqe)) {
 589                 set_cqe_hw(cqe);
 590                 ++(*freed);
 591                 ++cq->cons_index;
 592         }
 593
 594         return err;
 595 }
 596
 597 int mthca_poll_cq(struct ib_cq *ibcq, int num_entries,
 598                   struct ib_wc *entry)
 599 {
 600         struct mthca_dev *dev = to_mdev(ibcq->device);
 601         struct mthca_cq *cq = to_mcq(ibcq);
 602         struct mthca_qp *qp = NULL;
 603         unsigned long flags;
 604         int err = 0;
 605         int freed = 0;
 606         int npolled;
 607
 608         spin_lock_irqsave(&cq->lock, flags);
 609
 610         for (npolled = 0; npolled < num_entries; ++npolled) {
 611                 err = mthca_poll_one(dev, cq, &qp,
 612                                      &freed, entry + npolled);
 613                 if (err)
 614                         break;
 615         }
 616
 617         if (freed) {
 618                 wmb();
 619                 update_cons_index(dev, cq, freed);
 620         }
 621
 622         spin_unlock_irqrestore(&cq->lock, flags);
 623
 624         return err == 0 || err == -EAGAIN ? npolled : err;
 625 }
 626
 627 int mthca_tavor_arm_cq(struct ib_cq *cq, enum ib_cq_notify notify)
 628 {
 629         __be32 doorbell[2];
 630
 631         doorbell[0] = cpu_to_be32((notify == IB_CQ_SOLICITED ?
 632                                    MTHCA_TAVOR_CQ_DB_REQ_NOT_SOL :
 633                                    MTHCA_TAVOR_CQ_DB_REQ_NOT)      |
 634                                   to_mcq(cq)->cqn);
 635         doorbell[1] = (__force __be32) 0xffffffff;
 636
 637         mthca_write64(doorbell,
 638                       to_mdev(cq->device)->kar + MTHCA_CQ_DOORBELL,
 639                       MTHCA_GET_DOORBELL_LOCK(&to_mdev(cq->device)->doorbell_lock));
 640
 641         return 0;
 642 }
 643
 644 int mthca_arbel_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify notify)
 645 {
 646         struct mthca_cq *cq = to_mcq(ibcq);
 647         __be32 doorbell[2];
 648         u32 sn;
 649         __be32 ci;
 650
 651         sn = cq->arm_sn & 3;
 652         ci = cpu_to_be32(cq->cons_index);
 653
 654         doorbell[0] = ci;
 655         doorbell[1] = cpu_to_be32((cq->cqn << 8) | (2 << 5) | (sn << 3) |
 656                                   (notify == IB_CQ_SOLICITED ? 1 : 2));
 657
 658         mthca_write_db_rec(doorbell, cq->arm_db);
 659
 660         /*
 661          * Make sure that the doorbell record in host memory is
 662          * written before ringing the doorbell via PCI MMIO.
 663          */
 664         wmb();
 665
 666         doorbell[0] = cpu_to_be32((sn << 28)                       |
 667                                   (notify == IB_CQ_SOLICITED ?
 668                                    MTHCA_ARBEL_CQ_DB_REQ_NOT_SOL :
 669                                    MTHCA_ARBEL_CQ_DB_REQ_NOT)      |
 670                                   cq->cqn);
 671         doorbell[1] = ci;
 672
 673         mthca_write64(doorbell,
 674                       to_mdev(ibcq->device)->kar + MTHCA_CQ_DOORBELL,
 675                       MTHCA_GET_DOORBELL_LOCK(&to_mdev(ibcq->device)->doorbell_lock));
 676
 677         return 0;
 678 }
 679
 680 static void mthca_free_cq_buf(struct mthca_dev *dev, struct mthca_cq *cq)
 681 {
 682         mthca_buf_free(dev, (cq->ibcq.cqe + 1) * MTHCA_CQ_ENTRY_SIZE,
 683                        &cq->queue, cq->is_direct, &cq->mr);
 684 }
 685
 686 int mthca_init_cq(struct mthca_dev *dev, int nent,
 687                   struct mthca_ucontext *ctx, u32 pdn,
 688                   struct mthca_cq *cq)
 689 {
 690         int size = nent * MTHCA_CQ_ENTRY_SIZE;
 691         struct mthca_mailbox *mailbox;
 692         struct mthca_cq_context *cq_context;
 693         int err = -ENOMEM;
 694         u8 status;
 695         int i;
 696
 697         might_sleep();
 698
 699         cq->ibcq.cqe  = nent - 1;
 700         cq->is_kernel = !ctx;
 701
 702         cq->cqn = mthca_alloc(&dev->cq_table.alloc);
 703         if (cq->cqn == -1)
 704                 return -ENOMEM;
 705
 706         if (mthca_is_memfree(dev)) {
 707                 err = mthca_table_get(dev, dev->cq_table.table, cq->cqn);
 708                 if (err)
 709                         goto err_out;
 710
 711                 if (cq->is_kernel) {
 712                         cq->arm_sn = 1;
 713
 714                         err = -ENOMEM;
 715
 716                         cq->set_ci_db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_CQ_SET_CI,
 717                                                              cq->cqn, &cq->set_ci_db);
 718                         if (cq->set_ci_db_index < 0)
 719                                 goto err_out_icm;
 720
 721                         cq->arm_db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_CQ_ARM,
 722                                                           cq->cqn, &cq->arm_db);
 723                         if (cq->arm_db_index < 0)
 724                                 goto err_out_ci;
 725                 }
 726         }
 727
 728         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 729         if (IS_ERR(mailbox))
 730                 goto err_out_arm;
 731
 732         cq_context = mailbox->buf;
 733
 734         if (cq->is_kernel) {
 735                 err = mthca_buf_alloc(dev, size, MTHCA_MAX_DIRECT_CQ_SIZE,
 736                                       &cq->queue, &cq->is_direct,
 737                                       &dev->driver_pd, 1, &cq->mr);
 738                 if (err)
 739                         goto err_out_mailbox;
 740
 741                 for (i = 0; i < nent; ++i)
 742                         set_cqe_hw(get_cqe(cq, i));
 743         }
 744
 745         spin_lock_init(&cq->lock);
 746         atomic_set(&cq->refcount, 1);
 747         init_waitqueue_head(&cq->wait);
 748
 749         memset(cq_context, 0, sizeof *cq_context);
 750         cq_context->flags           = cpu_to_be32(MTHCA_CQ_STATUS_OK      |
 751                                                   MTHCA_CQ_STATE_DISARMED |
 752                                                   MTHCA_CQ_FLAG_TR);
 753         cq_context->logsize_usrpage = cpu_to_be32((ffs(nent) - 1) << 24);
 754         if (ctx)
 755                 cq_context->logsize_usrpage |= cpu_to_be32(ctx->uar.index);
 756         else
 757                 cq_context->logsize_usrpage |= cpu_to_be32(dev->driver_uar.index);
 758         cq_context->error_eqn       = cpu_to_be32(dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn);
 759         cq_context->comp_eqn        = cpu_to_be32(dev->eq_table.eq[MTHCA_EQ_COMP].eqn);
 760         cq_context->pd              = cpu_to_be32(pdn);
 761         cq_context->lkey            = cpu_to_be32(cq->mr.ibmr.lkey);
 762         cq_context->cqn             = cpu_to_be32(cq->cqn);
 763
 764         if (mthca_is_memfree(dev)) {
 765                 cq_context->ci_db    = cpu_to_be32(cq->set_ci_db_index);
 766                 cq_context->state_db = cpu_to_be32(cq->arm_db_index);
 767         }
 768
 769         err = mthca_SW2HW_CQ(dev, mailbox, cq->cqn, &status);
 770         if (err) {
 771                 mthca_warn(dev, "SW2HW_CQ failed (%d)\n", err);
 772                 goto err_out_free_mr;
 773         }
 774
 775         if (status) {
 776                 mthca_warn(dev, "SW2HW_CQ returned status 0x%02x\n",
 777                            status);
 778                 err = -EINVAL;
 779                 goto err_out_free_mr;
 780         }
 781
 782         spin_lock_irq(&dev->cq_table.lock);
 783         if (mthca_array_set(&dev->cq_table.cq,
 784                             cq->cqn & (dev->limits.num_cqs - 1),
 785                             cq)) {
 786                 spin_unlock_irq(&dev->cq_table.lock);
 787                 goto err_out_free_mr;
 788         }
 789         spin_unlock_irq(&dev->cq_table.lock);
 790
 791         cq->cons_index = 0;
 792
 793         mthca_free_mailbox(dev, mailbox);
 794
 795         return 0;
 796
 797 err_out_free_mr:
 798         if (cq->is_kernel)
 799                 mthca_free_cq_buf(dev, cq);
 800
 801 err_out_mailbox:
 802         mthca_free_mailbox(dev, mailbox);
 803
 804 err_out_arm:
 805         if (cq->is_kernel && mthca_is_memfree(dev))
 806                 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_ARM, cq->arm_db_index);
 807
 808 err_out_ci:
 809         if (cq->is_kernel && mthca_is_memfree(dev))
 810                 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_SET_CI, cq->set_ci_db_index);
 811
 812 err_out_icm:
 813         mthca_table_put(dev, dev->cq_table.table, cq->cqn);
 814
 815 err_out:
 816         mthca_free(&dev->cq_table.alloc, cq->cqn);
 817
 818         return err;
 819 }
 820
 821 void mthca_free_cq(struct mthca_dev *dev,
 822                    struct mthca_cq *cq)
 823 {
 824         struct mthca_mailbox *mailbox;
 825         int err;
 826         u8 status;
 827
 828         might_sleep();
 829
 830         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 831         if (IS_ERR(mailbox)) {
 832                 mthca_warn(dev, "No memory for mailbox to free CQ.\n");
 833                 return;
 834         }
 835
 836         err = mthca_HW2SW_CQ(dev, mailbox, cq->cqn, &status);
 837         if (err)
 838                 mthca_warn(dev, "HW2SW_CQ failed (%d)\n", err);
 839         else if (status)
 840                 mthca_warn(dev, "HW2SW_CQ returned status 0x%02x\n", status);
 841
 842         if (0) {
 843                 __be32 *ctx = mailbox->buf;
 844                 int j;
 845
 846                 printk(KERN_ERR "context for CQN %x (cons index %x, next sw %d)\n",
 847                        cq->cqn, cq->cons_index,
 848                        cq->is_kernel ? !!next_cqe_sw(cq) : 0);
 849                 for (j = 0; j < 16; ++j)
 850                         printk(KERN_ERR "[%2x] %08x\n", j * 4, be32_to_cpu(ctx[j]));
 851         }
 852
 853         spin_lock_irq(&dev->cq_table.lock);
 854         mthca_array_clear(&dev->cq_table.cq,
 855                           cq->cqn & (dev->limits.num_cqs - 1));
 856         spin_unlock_irq(&dev->cq_table.lock);
 857
 858         if (dev->mthca_flags & MTHCA_FLAG_MSI_X)
 859                 synchronize_irq(dev->eq_table.eq[MTHCA_EQ_COMP].msi_x_vector);
 860         else
 861                 synchronize_irq(dev->pdev->irq);
 862
 863         atomic_dec(&cq->refcount);
 864         wait_event(cq->wait, !atomic_read(&cq->refcount));
 865
 866         if (cq->is_kernel) {
 867                 mthca_free_cq_buf(dev, cq);
 868                 if (mthca_is_memfree(dev)) {
 869                         mthca_free_db(dev, MTHCA_DB_TYPE_CQ_ARM,    cq->arm_db_index);
 870                         mthca_free_db(dev, MTHCA_DB_TYPE_CQ_SET_CI, cq->set_ci_db_index);
 871                 }
 872         }
 873
 874         mthca_table_put(dev, dev->cq_table.table, cq->cqn);
 875         mthca_free(&dev->cq_table.alloc, cq->cqn);
 876         mthca_free_mailbox(dev, mailbox);
 877 }
 878
 879 int __devinit mthca_init_cq_table(struct mthca_dev *dev)
 880 {
 881         int err;
 882
 883         spin_lock_init(&dev->cq_table.lock);
 884
 885         err = mthca_alloc_init(&dev->cq_table.alloc,
 886                                dev->limits.num_cqs,
 887                                (1 << 24) - 1,
 888                                dev->limits.reserved_cqs);
 889         if (err)
 890                 return err;
 891
 892         err = mthca_array_init(&dev->cq_table.cq,
 893                                dev->limits.num_cqs);
 894         if (err)
 895                 mthca_alloc_cleanup(&dev->cq_table.alloc);
 896
 897         return err;
 898 }
 899
 900 void __devexit mthca_cleanup_cq_table(struct mthca_dev *dev)
 901 {
 902         mthca_array_cleanup(&dev->cq_table.cq, dev->limits.num_cqs);
 903         mthca_alloc_cleanup(&dev->cq_table.alloc);
 904 }